drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/list_sort.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_ras.h"
  35 #include "amdgpu_atomfirmware.h"
  36 #include "amdgpu_xgmi.h"
  37 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  38 #include "nbio_v4_3.h"
  39 #include "nbio_v7_9.h"
  40 #include "atom.h"
  41 #include "amdgpu_reset.h"
  42
  43 #ifdef CONFIG_X86_MCE_AMD
  44 #include <asm/mce.h>
  45
  46 static bool notifier_registered;
  47 #endif
  48 static const char *RAS_FS_NAME = "ras";
  49
  50 const char *ras_error_string[] = {
  51         "none",
  52         "parity",
  53         "single_correctable",
  54         "multi_uncorrectable",
  55         "poison",
  56 };
  57
  58 const char *ras_block_string[] = {
  59         "umc",
  60         "sdma",
  61         "gfx",
  62         "mmhub",
  63         "athub",
  64         "pcie_bif",
  65         "hdp",
  66         "xgmi_wafl",
  67         "df",
  68         "smn",
  69         "sem",
  70         "mp0",
  71         "mp1",
  72         "fuse",
  73         "mca",
  74         "vcn",
  75         "jpeg",
  76 };
  77
  78 const char *ras_mca_block_string[] = {
  79         "mca_mp0",
  80         "mca_mp1",
  81         "mca_mpio",
  82         "mca_iohc",
  83 };
  84
  85 struct amdgpu_ras_block_list {
  86         /* ras block link */
  87         struct list_head node;
  88
  89         struct amdgpu_ras_block_object *ras_obj;
  90 };
  91
  92 const char *get_ras_block_str(struct ras_common_if *ras_block)
  93 {
  94         if (!ras_block)
  95                 return "NULL";
  96
  97         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  98                 return "OUT OF RANGE";
  99
 100         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 101                 return ras_mca_block_string[ras_block->sub_block_index];
 102
 103         return ras_block_string[ras_block->block];
 104 }
 105
 106 #define ras_block_str(_BLOCK_) \
 107         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 108
 109 #define ras_err_str(i) (ras_error_string[ffs(i)])
 110
 111 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 112
 113 /* inject address is 52 bits */
 114 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 115
 116 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 117 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 118
 119 enum amdgpu_ras_retire_page_reservation {
 120         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 121         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 122         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 123 };
 124
 125 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 126
 127 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 128                                 uint64_t addr);
 129 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 130                                 uint64_t addr);
 131 #ifdef CONFIG_X86_MCE_AMD
 132 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 133 struct mce_notifier_adev_list {
 134         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 135         int num_gpu;
 136 };
 137 static struct mce_notifier_adev_list mce_adev_list;
 138 #endif
 139
 140 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 141 {
 142         if (adev && amdgpu_ras_get_context(adev))
 143                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 144 }
 145
 146 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 147 {
 148         if (adev && amdgpu_ras_get_context(adev))
 149                 return amdgpu_ras_get_context(adev)->error_query_ready;
 150
 151         return false;
 152 }
 153
 154 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 155 {
 156         struct ras_err_data err_data;
 157         struct eeprom_table_record err_rec;
 158         int ret;
 159
 160         if ((address >= adev->gmc.mc_vram_size) ||
 161             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 162                 dev_warn(adev->dev,
 163                          "RAS WARN: input address 0x%llx is invalid.\n",
 164                          address);
 165                 return -EINVAL;
 166         }
 167
 168         if (amdgpu_ras_check_bad_page(adev, address)) {
 169                 dev_warn(adev->dev,
 170                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 171                          address);
 172                 return 0;
 173         }
 174
 175         ret = amdgpu_ras_error_data_init(&err_data);
 176         if (ret)
 177                 return ret;
 178
 179         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 180         err_data.err_addr = &err_rec;
 181         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 182
 183         if (amdgpu_bad_page_threshold != 0) {
 184                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 185                                          err_data.err_addr_cnt);
 186                 amdgpu_ras_save_bad_pages(adev, NULL);
 187         }
 188
 189         amdgpu_ras_error_data_fini(&err_data);
 190
 191         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 192         dev_warn(adev->dev, "Clear EEPROM:\n");
 193         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 194
 195         return 0;
 196 }
 197
 198 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 199                                         size_t size, loff_t *pos)
 200 {
 201         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 202         struct ras_query_if info = {
 203                 .head = obj->head,
 204         };
 205         ssize_t s;
 206         char val[128];
 207
 208         if (amdgpu_ras_query_error_status(obj->adev, &info))
 209                 return -EINVAL;
 210
 211         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 212         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 213             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 214                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 215                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 216         }
 217
 218         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 219                         "ue", info.ue_count,
 220                         "ce", info.ce_count);
 221         if (*pos >= s)
 222                 return 0;
 223
 224         s -= *pos;
 225         s = min_t(u64, s, size);
 226
 227
 228         if (copy_to_user(buf, &val[*pos], s))
 229                 return -EINVAL;
 230
 231         *pos += s;
 232
 233         return s;
 234 }
 235
 236 static const struct file_operations amdgpu_ras_debugfs_ops = {
 237         .owner = THIS_MODULE,
 238         .read = amdgpu_ras_debugfs_read,
 239         .write = NULL,
 240         .llseek = default_llseek
 241 };
 242
 243 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 244 {
 245         int i;
 246
 247         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 248                 *block_id = i;
 249                 if (strcmp(name, ras_block_string[i]) == 0)
 250                         return 0;
 251         }
 252         return -EINVAL;
 253 }
 254
 255 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 256                 const char __user *buf, size_t size,
 257                 loff_t *pos, struct ras_debug_if *data)
 258 {
 259         ssize_t s = min_t(u64, 64, size);
 260         char str[65];
 261         char block_name[33];
 262         char err[9] = "ue";
 263         int op = -1;
 264         int block_id;
 265         uint32_t sub_block;
 266         u64 address, value;
 267         /* default value is 0 if the mask is not set by user */
 268         u32 instance_mask = 0;
 269
 270         if (*pos)
 271                 return -EINVAL;
 272         *pos = size;
 273
 274         memset(str, 0, sizeof(str));
 275         memset(data, 0, sizeof(*data));
 276
 277         if (copy_from_user(str, buf, s))
 278                 return -EINVAL;
 279
 280         if (sscanf(str, "disable %32s", block_name) == 1)
 281                 op = 0;
 282         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 283                 op = 1;
 284         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 285                 op = 2;
 286         else if (strstr(str, "retire_page") != NULL)
 287                 op = 3;
 288         else if (str[0] && str[1] && str[2] && str[3])
 289                 /* ascii string, but commands are not matched. */
 290                 return -EINVAL;
 291
 292         if (op != -1) {
 293                 if (op == 3) {
 294                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 295                             sscanf(str, "%*s %llu", &address) != 1)
 296                                 return -EINVAL;
 297
 298                         data->op = op;
 299                         data->inject.address = address;
 300
 301                         return 0;
 302                 }
 303
 304                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 305                         return -EINVAL;
 306
 307                 data->head.block = block_id;
 308                 /* only ue and ce errors are supported */
 309                 if (!memcmp("ue", err, 2))
 310                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 311                 else if (!memcmp("ce", err, 2))
 312                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 313                 else
 314                         return -EINVAL;
 315
 316                 data->op = op;
 317
 318                 if (op == 2) {
 319                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 320                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 321                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 322                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 323                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 324                                    &sub_block, &address, &value) != 3 &&
 325                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 326                                    &sub_block, &address, &value) != 3)
 327                                 return -EINVAL;
 328                         data->head.sub_block_index = sub_block;
 329                         data->inject.address = address;
 330                         data->inject.value = value;
 331                         data->inject.instance_mask = instance_mask;
 332                 }
 333         } else {
 334                 if (size < sizeof(*data))
 335                         return -EINVAL;
 336
 337                 if (copy_from_user(data, buf, sizeof(*data)))
 338                         return -EINVAL;
 339         }
 340
 341         return 0;
 342 }
 343
 344 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 345                                 struct ras_debug_if *data)
 346 {
 347         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 348         uint32_t mask, inst_mask = data->inject.instance_mask;
 349
 350         /* no need to set instance mask if there is only one instance */
 351         if (num_xcc <= 1 && inst_mask) {
 352                 data->inject.instance_mask = 0;
 353                 dev_dbg(adev->dev,
 354                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 355                         inst_mask);
 356
 357                 return;
 358         }
 359
 360         switch (data->head.block) {
 361         case AMDGPU_RAS_BLOCK__GFX:
 362                 mask = GENMASK(num_xcc - 1, 0);
 363                 break;
 364         case AMDGPU_RAS_BLOCK__SDMA:
 365                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 366                 break;
 367         case AMDGPU_RAS_BLOCK__VCN:
 368         case AMDGPU_RAS_BLOCK__JPEG:
 369                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 370                 break;
 371         default:
 372                 mask = inst_mask;
 373                 break;
 374         }
 375
 376         /* remove invalid bits in instance mask */
 377         data->inject.instance_mask &= mask;
 378         if (inst_mask != data->inject.instance_mask)
 379                 dev_dbg(adev->dev,
 380                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 381                         inst_mask, data->inject.instance_mask);
 382 }
 383
 384 /**
 385  * DOC: AMDGPU RAS debugfs control interface
 386  *
 387  * The control interface accepts struct ras_debug_if which has two members.
 388  *
 389  * First member: ras_debug_if::head or ras_debug_if::inject.
 390  *
 391  * head is used to indicate which IP block will be under control.
 392  *
 393  * head has four members, they are block, type, sub_block_index, name.
 394  * block: which IP will be under control.
 395  * type: what kind of error will be enabled/disabled/injected.
 396  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 397  * name: the name of IP.
 398  *
 399  * inject has three more members than head, they are address, value and mask.
 400  * As their names indicate, inject operation will write the
 401  * value to the address.
 402  *
 403  * The second member: struct ras_debug_if::op.
 404  * It has three kinds of operations.
 405  *
 406  * - 0: disable RAS on the block. Take ::head as its data.
 407  * - 1: enable RAS on the block. Take ::head as its data.
 408  * - 2: inject errors on the block. Take ::inject as its data.
 409  *
 410  * How to use the interface?
 411  *
 412  * In a program
 413  *
 414  * Copy the struct ras_debug_if in your code and initialize it.
 415  * Write the struct to the control interface.
 416  *
 417  * From shell
 418  *
 419  * .. code-block:: bash
 420  *
 421  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 422  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 423  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 424  *
 425  * Where N, is the card which you want to affect.
 426  *
 427  * "disable" requires only the block.
 428  * "enable" requires the block and error type.
 429  * "inject" requires the block, error type, address, and value.
 430  *
 431  * The block is one of: umc, sdma, gfx, etc.
 432  *      see ras_block_string[] for details
 433  *
 434  * The error type is one of: ue, ce, where,
 435  *      ue is multi-uncorrectable
 436  *      ce is single-correctable
 437  *
 438  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 439  * The address and value are hexadecimal numbers, leading 0x is optional.
 440  * The mask means instance mask, is optional, default value is 0x1.
 441  *
 442  * For instance,
 443  *
 444  * .. code-block:: bash
 445  *
 446  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 447  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 448  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 449  *
 450  * How to check the result of the operation?
 451  *
 452  * To check disable/enable, see "ras" features at,
 453  * /sys/class/drm/card[0/1/2...]/device/ras/features
 454  *
 455  * To check inject, see the corresponding error count at,
 456  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 457  *
 458  * .. note::
 459  *      Operations are only allowed on blocks which are supported.
 460  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 461  *      to see which blocks support RAS on a particular asic.
 462  *
 463  */
 464 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 465                                              const char __user *buf,
 466                                              size_t size, loff_t *pos)
 467 {
 468         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 469         struct ras_debug_if data;
 470         int ret = 0;
 471
 472         if (!amdgpu_ras_get_error_query_ready(adev)) {
 473                 dev_warn(adev->dev, "RAS WARN: error injection "
 474                                 "currently inaccessible\n");
 475                 return size;
 476         }
 477
 478         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 479         if (ret)
 480                 return ret;
 481
 482         if (data.op == 3) {
 483                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 484                 if (!ret)
 485                         return size;
 486                 else
 487                         return ret;
 488         }
 489
 490         if (!amdgpu_ras_is_supported(adev, data.head.block))
 491                 return -EINVAL;
 492
 493         switch (data.op) {
 494         case 0:
 495                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 496                 break;
 497         case 1:
 498                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 499                 break;
 500         case 2:
 501                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 502                     adev->gmc.mc_vram_size) ||
 503                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 504                         dev_warn(adev->dev, "RAS WARN: input address "
 505                                         "0x%llx is invalid.",
 506                                         data.inject.address);
 507                         ret = -EINVAL;
 508                         break;
 509                 }
 510
 511                 /* umc ce/ue error injection for a bad page is not allowed */
 512                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 513                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 514                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 515                                  "already been marked as bad!\n",
 516                                  data.inject.address);
 517                         break;
 518                 }
 519
 520                 amdgpu_ras_instance_mask_check(adev, &data);
 521
 522                 /* data.inject.address is offset instead of absolute gpu address */
 523                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 524                 break;
 525         default:
 526                 ret = -EINVAL;
 527                 break;
 528         }
 529
 530         if (ret)
 531                 return ret;
 532
 533         return size;
 534 }
 535
 536 /**
 537  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 538  *
 539  * Some boards contain an EEPROM which is used to persistently store a list of
 540  * bad pages which experiences ECC errors in vram.  This interface provides
 541  * a way to reset the EEPROM, e.g., after testing error injection.
 542  *
 543  * Usage:
 544  *
 545  * .. code-block:: bash
 546  *
 547  *      echo 1 > ../ras/ras_eeprom_reset
 548  *
 549  * will reset EEPROM table to 0 entries.
 550  *
 551  */
 552 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 553                                                const char __user *buf,
 554                                                size_t size, loff_t *pos)
 555 {
 556         struct amdgpu_device *adev =
 557                 (struct amdgpu_device *)file_inode(f)->i_private;
 558         int ret;
 559
 560         ret = amdgpu_ras_eeprom_reset_table(
 561                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 562
 563         if (!ret) {
 564                 /* Something was written to EEPROM.
 565                  */
 566                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 567                 return size;
 568         } else {
 569                 return ret;
 570         }
 571 }
 572
 573 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 574         .owner = THIS_MODULE,
 575         .read = NULL,
 576         .write = amdgpu_ras_debugfs_ctrl_write,
 577         .llseek = default_llseek
 578 };
 579
 580 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 581         .owner = THIS_MODULE,
 582         .read = NULL,
 583         .write = amdgpu_ras_debugfs_eeprom_write,
 584         .llseek = default_llseek
 585 };
 586
 587 /**
 588  * DOC: AMDGPU RAS sysfs Error Count Interface
 589  *
 590  * It allows the user to read the error count for each IP block on the gpu through
 591  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 592  *
 593  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 594  * (ce) error counts.
 595  *
 596  * The format of one line is below,
 597  *
 598  * [ce|ue]: count
 599  *
 600  * Example:
 601  *
 602  * .. code-block:: bash
 603  *
 604  *      ue: 0
 605  *      ce: 1
 606  *
 607  */
 608 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 609                 struct device_attribute *attr, char *buf)
 610 {
 611         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 612         struct ras_query_if info = {
 613                 .head = obj->head,
 614         };
 615
 616         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 617                 return sysfs_emit(buf, "Query currently inaccessible\n");
 618
 619         if (amdgpu_ras_query_error_status(obj->adev, &info))
 620                 return -EINVAL;
 621
 622         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 623             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 624                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 625                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 626         }
 627
 628         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 629                           "ce", info.ce_count);
 630 }
 631
 632 /* obj begin */
 633
 634 #define get_obj(obj) do { (obj)->use++; } while (0)
 635 #define alive_obj(obj) ((obj)->use)
 636
 637 static inline void put_obj(struct ras_manager *obj)
 638 {
 639         if (obj && (--obj->use == 0)) {
 640                 list_del(&obj->node);
 641                 amdgpu_ras_error_data_fini(&obj->err_data);
 642         }
 643
 644         if (obj && (obj->use < 0))
 645                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 646 }
 647
 648 /* make one obj and return it. */
 649 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 650                 struct ras_common_if *head)
 651 {
 652         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 653         struct ras_manager *obj;
 654
 655         if (!adev->ras_enabled || !con)
 656                 return NULL;
 657
 658         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 659                 return NULL;
 660
 661         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 662                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 663                         return NULL;
 664
 665                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 666         } else
 667                 obj = &con->objs[head->block];
 668
 669         /* already exist. return obj? */
 670         if (alive_obj(obj))
 671                 return NULL;
 672
 673         if (amdgpu_ras_error_data_init(&obj->err_data))
 674                 return NULL;
 675
 676         obj->head = *head;
 677         obj->adev = adev;
 678         list_add(&obj->node, &con->head);
 679         get_obj(obj);
 680
 681         return obj;
 682 }
 683
 684 /* return an obj equal to head, or the first when head is NULL */
 685 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 686                 struct ras_common_if *head)
 687 {
 688         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 689         struct ras_manager *obj;
 690         int i;
 691
 692         if (!adev->ras_enabled || !con)
 693                 return NULL;
 694
 695         if (head) {
 696                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 697                         return NULL;
 698
 699                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 700                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 701                                 return NULL;
 702
 703                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 704                 } else
 705                         obj = &con->objs[head->block];
 706
 707                 if (alive_obj(obj))
 708                         return obj;
 709         } else {
 710                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 711                         obj = &con->objs[i];
 712                         if (alive_obj(obj))
 713                                 return obj;
 714                 }
 715         }
 716
 717         return NULL;
 718 }
 719 /* obj end */
 720
 721 /* feature ctl begin */
 722 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 723                                          struct ras_common_if *head)
 724 {
 725         return adev->ras_hw_enabled & BIT(head->block);
 726 }
 727
 728 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 729                 struct ras_common_if *head)
 730 {
 731         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 732
 733         return con->features & BIT(head->block);
 734 }
 735
 736 /*
 737  * if obj is not created, then create one.
 738  * set feature enable flag.
 739  */
 740 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 741                 struct ras_common_if *head, int enable)
 742 {
 743         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 744         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 745
 746         /* If hardware does not support ras, then do not create obj.
 747          * But if hardware support ras, we can create the obj.
 748          * Ras framework checks con->hw_supported to see if it need do
 749          * corresponding initialization.
 750          * IP checks con->support to see if it need disable ras.
 751          */
 752         if (!amdgpu_ras_is_feature_allowed(adev, head))
 753                 return 0;
 754
 755         if (enable) {
 756                 if (!obj) {
 757                         obj = amdgpu_ras_create_obj(adev, head);
 758                         if (!obj)
 759                                 return -EINVAL;
 760                 } else {
 761                         /* In case we create obj somewhere else */
 762                         get_obj(obj);
 763                 }
 764                 con->features |= BIT(head->block);
 765         } else {
 766                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 767                         con->features &= ~BIT(head->block);
 768                         put_obj(obj);
 769                 }
 770         }
 771
 772         return 0;
 773 }
 774
 775 /* wrapper of psp_ras_enable_features */
 776 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 777                 struct ras_common_if *head, bool enable)
 778 {
 779         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 780         union ta_ras_cmd_input *info;
 781         int ret;
 782
 783         if (!con)
 784                 return -EINVAL;
 785
 786         /* For non-gfx ip, do not enable ras feature if it is not allowed */
 787         /* For gfx ip, regardless of feature support status, */
 788         /* Force issue enable or disable ras feature commands */
 789         if (head->block != AMDGPU_RAS_BLOCK__GFX &&
 790             !amdgpu_ras_is_feature_allowed(adev, head))
 791                 return 0;
 792
 793         /* Only enable gfx ras feature from host side */
 794         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 795             !amdgpu_sriov_vf(adev) &&
 796             !amdgpu_ras_intr_triggered()) {
 797                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 798                 if (!info)
 799                         return -ENOMEM;
 800
 801                 if (!enable) {
 802                         info->disable_features = (struct ta_ras_disable_features_input) {
 803                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 804                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 805                         };
 806                 } else {
 807                         info->enable_features = (struct ta_ras_enable_features_input) {
 808                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 809                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 810                         };
 811                 }
 812
 813                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 814                 if (ret) {
 815                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 816                                 enable ? "enable":"disable",
 817                                 get_ras_block_str(head),
 818                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 819                         kfree(info);
 820                         return ret;
 821                 }
 822
 823                 kfree(info);
 824         }
 825
 826         /* setup the obj */
 827         __amdgpu_ras_feature_enable(adev, head, enable);
 828
 829         return 0;
 830 }
 831
 832 /* Only used in device probe stage and called only once. */
 833 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 834                 struct ras_common_if *head, bool enable)
 835 {
 836         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 837         int ret;
 838
 839         if (!con)
 840                 return -EINVAL;
 841
 842         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 843                 if (enable) {
 844                         /* There is no harm to issue a ras TA cmd regardless of
 845                          * the currecnt ras state.
 846                          * If current state == target state, it will do nothing
 847                          * But sometimes it requests driver to reset and repost
 848                          * with error code -EAGAIN.
 849                          */
 850                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 851                         /* With old ras TA, we might fail to enable ras.
 852                          * Log it and just setup the object.
 853                          * TODO need remove this WA in the future.
 854                          */
 855                         if (ret == -EINVAL) {
 856                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 857                                 if (!ret)
 858                                         dev_info(adev->dev,
 859                                                 "RAS INFO: %s setup object\n",
 860                                                 get_ras_block_str(head));
 861                         }
 862                 } else {
 863                         /* setup the object then issue a ras TA disable cmd.*/
 864                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 865                         if (ret)
 866                                 return ret;
 867
 868                         /* gfx block ras dsiable cmd must send to ras-ta */
 869                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 870                                 con->features |= BIT(head->block);
 871
 872                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 873
 874                         /* clean gfx block ras features flag */
 875                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 876                                 con->features &= ~BIT(head->block);
 877                 }
 878         } else
 879                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 880
 881         return ret;
 882 }
 883
 884 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 885                 bool bypass)
 886 {
 887         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 888         struct ras_manager *obj, *tmp;
 889
 890         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 891                 /* bypass psp.
 892                  * aka just release the obj and corresponding flags
 893                  */
 894                 if (bypass) {
 895                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 896                                 break;
 897                 } else {
 898                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 899                                 break;
 900                 }
 901         }
 902
 903         return con->features;
 904 }
 905
 906 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 907                 bool bypass)
 908 {
 909         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 910         int i;
 911         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 912
 913         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 914                 struct ras_common_if head = {
 915                         .block = i,
 916                         .type = default_ras_type,
 917                         .sub_block_index = 0,
 918                 };
 919
 920                 if (i == AMDGPU_RAS_BLOCK__MCA)
 921                         continue;
 922
 923                 if (bypass) {
 924                         /*
 925                          * bypass psp. vbios enable ras for us.
 926                          * so just create the obj
 927                          */
 928                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 929                                 break;
 930                 } else {
 931                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 932                                 break;
 933                 }
 934         }
 935
 936         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 937                 struct ras_common_if head = {
 938                         .block = AMDGPU_RAS_BLOCK__MCA,
 939                         .type = default_ras_type,
 940                         .sub_block_index = i,
 941                 };
 942
 943                 if (bypass) {
 944                         /*
 945                          * bypass psp. vbios enable ras for us.
 946                          * so just create the obj
 947                          */
 948                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 949                                 break;
 950                 } else {
 951                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 952                                 break;
 953                 }
 954         }
 955
 956         return con->features;
 957 }
 958 /* feature ctl end */
 959
 960 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 961                 enum amdgpu_ras_block block)
 962 {
 963         if (!block_obj)
 964                 return -EINVAL;
 965
 966         if (block_obj->ras_comm.block == block)
 967                 return 0;
 968
 969         return -EINVAL;
 970 }
 971
 972 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 973                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 974 {
 975         struct amdgpu_ras_block_list *node, *tmp;
 976         struct amdgpu_ras_block_object *obj;
 977
 978         if (block >= AMDGPU_RAS_BLOCK__LAST)
 979                 return NULL;
 980
 981         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 982                 if (!node->ras_obj) {
 983                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 984                         continue;
 985                 }
 986
 987                 obj = node->ras_obj;
 988                 if (obj->ras_block_match) {
 989                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 990                                 return obj;
 991                 } else {
 992                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 993                                 return obj;
 994                 }
 995         }
 996
 997         return NULL;
 998 }
 999
1000 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
1001 {
1002         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1003         int ret = 0;
1004
1005         /*
1006          * choosing right query method according to
1007          * whether smu support query error information
1008          */
1009         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1010         if (ret == -EOPNOTSUPP) {
1011                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1012                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1013                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1014
1015                 /* umc query_ras_error_address is also responsible for clearing
1016                  * error status
1017                  */
1018                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1019                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1020                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1021         } else if (!ret) {
1022                 if (adev->umc.ras &&
1023                         adev->umc.ras->ecc_info_query_ras_error_count)
1024                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1025
1026                 if (adev->umc.ras &&
1027                         adev->umc.ras->ecc_info_query_ras_error_address)
1028                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1029         }
1030 }
1031
1032 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1033                                               struct ras_manager *ras_mgr,
1034                                               struct ras_err_data *err_data,
1035                                               const char *blk_name,
1036                                               bool is_ue)
1037 {
1038         struct amdgpu_smuio_mcm_config_info *mcm_info;
1039         struct ras_err_node *err_node;
1040         struct ras_err_info *err_info;
1041
1042         if (is_ue) {
1043                 for_each_ras_error(err_node, err_data) {
1044                         err_info = &err_node->err_info;
1045                         mcm_info = &err_info->mcm_info;
1046                         if (err_info->ue_count) {
1047                                 dev_info(adev->dev, "socket: %d, die: %d, "
1048                                          "%lld new uncorrectable hardware errors detected in %s block\n",
1049                                          mcm_info->socket_id,
1050                                          mcm_info->die_id,
1051                                          err_info->ue_count,
1052                                          blk_name);
1053                         }
1054                 }
1055
1056                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1057                         err_info = &err_node->err_info;
1058                         mcm_info = &err_info->mcm_info;
1059                         dev_info(adev->dev, "socket: %d, die: %d, "
1060                                  "%lld uncorrectable hardware errors detected in total in %s block\n",
1061                                  mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name);
1062                 }
1063
1064         } else {
1065                 for_each_ras_error(err_node, err_data) {
1066                         err_info = &err_node->err_info;
1067                         mcm_info = &err_info->mcm_info;
1068                         if (err_info->ce_count) {
1069                                 dev_info(adev->dev, "socket: %d, die: %d, "
1070                                          "%lld new correctable hardware errors detected in %s block, "
1071                                          "no user action is needed\n",
1072                                          mcm_info->socket_id,
1073                                          mcm_info->die_id,
1074                                          err_info->ce_count,
1075                                          blk_name);
1076                         }
1077                 }
1078
1079                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1080                         err_info = &err_node->err_info;
1081                         mcm_info = &err_info->mcm_info;
1082                         dev_info(adev->dev, "socket: %d, die: %d, "
1083                                  "%lld correctable hardware errors detected in total in %s block, "
1084                                  "no user action is needed\n",
1085                                  mcm_info->socket_id, mcm_info->die_id, err_info->ce_count, blk_name);
1086                 }
1087         }
1088 }
1089
1090 static inline bool err_data_has_source_info(struct ras_err_data *data)
1091 {
1092         return !list_empty(&data->err_node_list);
1093 }
1094
1095 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1096                                              struct ras_query_if *query_if,
1097                                              struct ras_err_data *err_data)
1098 {
1099         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1100         const char *blk_name = get_ras_block_str(&query_if->head);
1101
1102         if (err_data->ce_count) {
1103                 if (err_data_has_source_info(err_data)) {
1104                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, false);
1105                 } else if (!adev->aid_mask &&
1106                            adev->smuio.funcs &&
1107                            adev->smuio.funcs->get_socket_id &&
1108                            adev->smuio.funcs->get_die_id) {
1109                         dev_info(adev->dev, "socket: %d, die: %d "
1110                                  "%ld correctable hardware errors "
1111                                  "detected in %s block, no user "
1112                                  "action is needed.\n",
1113                                  adev->smuio.funcs->get_socket_id(adev),
1114                                  adev->smuio.funcs->get_die_id(adev),
1115                                  ras_mgr->err_data.ce_count,
1116                                  blk_name);
1117                 } else {
1118                         dev_info(adev->dev, "%ld correctable hardware errors "
1119                                  "detected in %s block, no user "
1120                                  "action is needed.\n",
1121                                  ras_mgr->err_data.ce_count,
1122                                  blk_name);
1123                 }
1124         }
1125
1126         if (err_data->ue_count) {
1127                 if (err_data_has_source_info(err_data)) {
1128                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, true);
1129                 } else if (!adev->aid_mask &&
1130                            adev->smuio.funcs &&
1131                            adev->smuio.funcs->get_socket_id &&
1132                            adev->smuio.funcs->get_die_id) {
1133                         dev_info(adev->dev, "socket: %d, die: %d "
1134                                  "%ld uncorrectable hardware errors "
1135                                  "detected in %s block\n",
1136                                  adev->smuio.funcs->get_socket_id(adev),
1137                                  adev->smuio.funcs->get_die_id(adev),
1138                                  ras_mgr->err_data.ue_count,
1139                                  blk_name);
1140                 } else {
1141                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1142                                  "detected in %s block\n",
1143                                  ras_mgr->err_data.ue_count,
1144                                  blk_name);
1145                 }
1146         }
1147
1148 }
1149
1150 static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1151 {
1152         struct ras_err_node *err_node;
1153         struct ras_err_info *err_info;
1154
1155         if (err_data_has_source_info(err_data)) {
1156                 for_each_ras_error(err_node, err_data) {
1157                         err_info = &err_node->err_info;
1158
1159                         amdgpu_ras_error_statistic_ce_count(&obj->err_data,
1160                                         &err_info->mcm_info, NULL, err_info->ce_count);
1161                         amdgpu_ras_error_statistic_ue_count(&obj->err_data,
1162                                         &err_info->mcm_info, NULL, err_info->ue_count);
1163                 }
1164         } else {
1165                 /* for legacy asic path which doesn't has error source info */
1166                 obj->err_data.ue_count += err_data->ue_count;
1167                 obj->err_data.ce_count += err_data->ce_count;
1168         }
1169 }
1170
1171 static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
1172                                                 struct ras_query_if *info,
1173                                                 struct ras_err_data *err_data,
1174                                                 unsigned int error_query_mode)
1175 {
1176         enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT;
1177         struct amdgpu_ras_block_object *block_obj = NULL;
1178
1179         if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
1180                 return -EINVAL;
1181
1182         if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
1183                 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1184                         amdgpu_ras_get_ecc_info(adev, err_data);
1185                 } else {
1186                         block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1187                         if (!block_obj || !block_obj->hw_ops) {
1188                                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1189                                              get_ras_block_str(&info->head));
1190                                 return -EINVAL;
1191                         }
1192
1193                         if (block_obj->hw_ops->query_ras_error_count)
1194                                 block_obj->hw_ops->query_ras_error_count(adev, err_data);
1195
1196                         if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1197                             (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1198                             (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1199                                 if (block_obj->hw_ops->query_ras_error_status)
1200                                         block_obj->hw_ops->query_ras_error_status(adev);
1201                         }
1202                 }
1203         } else {
1204                 /* FIXME: add code to check return value later */
1205                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data);
1206                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data);
1207         }
1208
1209         return 0;
1210 }
1211
1212 /* query/inject/cure begin */
1213 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
1214 {
1215         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1216         struct ras_err_data err_data;
1217         unsigned int error_query_mode;
1218         int ret;
1219
1220         if (!obj)
1221                 return -EINVAL;
1222
1223         ret = amdgpu_ras_error_data_init(&err_data);
1224         if (ret)
1225                 return ret;
1226
1227         if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode))
1228                 return -EINVAL;
1229
1230         ret = amdgpu_ras_query_error_status_helper(adev, info,
1231                                                    &err_data,
1232                                                    error_query_mode);
1233         if (ret)
1234                 goto out_fini_err_data;
1235
1236         amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
1237
1238         info->ue_count = obj->err_data.ue_count;
1239         info->ce_count = obj->err_data.ce_count;
1240
1241         amdgpu_ras_error_generate_report(adev, info, &err_data);
1242
1243 out_fini_err_data:
1244         amdgpu_ras_error_data_fini(&err_data);
1245
1246         return ret;
1247 }
1248
1249 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
1250                 enum amdgpu_ras_block block)
1251 {
1252         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1253         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1254         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
1255         struct amdgpu_hive_info *hive;
1256         int hive_ras_recovery = 0;
1257
1258         if (!block_obj || !block_obj->hw_ops) {
1259                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1260                                 ras_block_str(block));
1261                 return -EOPNOTSUPP;
1262         }
1263
1264         if (!amdgpu_ras_is_supported(adev, block) ||
1265             !amdgpu_ras_get_mca_debug_mode(adev))
1266                 return -EOPNOTSUPP;
1267
1268         hive = amdgpu_get_xgmi_hive(adev);
1269         if (hive) {
1270                 hive_ras_recovery = atomic_read(&hive->ras_recovery);
1271                 amdgpu_put_xgmi_hive(hive);
1272         }
1273
1274         /* skip ras error reset in gpu reset */
1275         if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) ||
1276             hive_ras_recovery) &&
1277             mca_funcs && mca_funcs->mca_set_debug_mode)
1278                 return -EOPNOTSUPP;
1279
1280         if (block_obj->hw_ops->reset_ras_error_count)
1281                 block_obj->hw_ops->reset_ras_error_count(adev);
1282
1283         return 0;
1284 }
1285
1286 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1287                 enum amdgpu_ras_block block)
1288 {
1289         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1290
1291         if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1292                 return 0;
1293
1294         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1295             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1296                 if (block_obj->hw_ops->reset_ras_error_status)
1297                         block_obj->hw_ops->reset_ras_error_status(adev);
1298         }
1299
1300         return 0;
1301 }
1302
1303 /* wrapper of psp_ras_trigger_error */
1304 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1305                 struct ras_inject_if *info)
1306 {
1307         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1308         struct ta_ras_trigger_error_input block_info = {
1309                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1310                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1311                 .sub_block_index = info->head.sub_block_index,
1312                 .address = info->address,
1313                 .value = info->value,
1314         };
1315         int ret = -EINVAL;
1316         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1317                                                         info->head.block,
1318                                                         info->head.sub_block_index);
1319
1320         /* inject on guest isn't allowed, return success directly */
1321         if (amdgpu_sriov_vf(adev))
1322                 return 0;
1323
1324         if (!obj)
1325                 return -EINVAL;
1326
1327         if (!block_obj || !block_obj->hw_ops)   {
1328                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1329                              get_ras_block_str(&info->head));
1330                 return -EINVAL;
1331         }
1332
1333         /* Calculate XGMI relative offset */
1334         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1335             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1336                 block_info.address =
1337                         amdgpu_xgmi_get_relative_phy_addr(adev,
1338                                                           block_info.address);
1339         }
1340
1341         if (block_obj->hw_ops->ras_error_inject) {
1342                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1343                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1344                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1345                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1346                                                 info->instance_mask);
1347         } else {
1348                 /* default path */
1349                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1350         }
1351
1352         if (ret)
1353                 dev_err(adev->dev, "ras inject %s failed %d\n",
1354                         get_ras_block_str(&info->head), ret);
1355
1356         return ret;
1357 }
1358
1359 /**
1360  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1361  * @adev: pointer to AMD GPU device
1362  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1363  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1364  * @query_info: pointer to ras_query_if
1365  *
1366  * Return 0 for query success or do nothing, otherwise return an error
1367  * on failures
1368  */
1369 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1370                                                unsigned long *ce_count,
1371                                                unsigned long *ue_count,
1372                                                struct ras_query_if *query_info)
1373 {
1374         int ret;
1375
1376         if (!query_info)
1377                 /* do nothing if query_info is not specified */
1378                 return 0;
1379
1380         ret = amdgpu_ras_query_error_status(adev, query_info);
1381         if (ret)
1382                 return ret;
1383
1384         *ce_count += query_info->ce_count;
1385         *ue_count += query_info->ue_count;
1386
1387         /* some hardware/IP supports read to clear
1388          * no need to explictly reset the err status after the query call */
1389         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1390             amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1391                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1392                         dev_warn(adev->dev,
1393                                  "Failed to reset error counter and error status\n");
1394         }
1395
1396         return 0;
1397 }
1398
1399 /**
1400  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1401  * @adev: pointer to AMD GPU device
1402  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1403  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1404  * errors.
1405  * @query_info: pointer to ras_query_if if the query request is only for
1406  * specific ip block; if info is NULL, then the qurey request is for
1407  * all the ip blocks that support query ras error counters/status
1408  *
1409  * If set, @ce_count or @ue_count, count and return the corresponding
1410  * error counts in those integer pointers. Return 0 if the device
1411  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1412  */
1413 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1414                                  unsigned long *ce_count,
1415                                  unsigned long *ue_count,
1416                                  struct ras_query_if *query_info)
1417 {
1418         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1419         struct ras_manager *obj;
1420         unsigned long ce, ue;
1421         int ret;
1422
1423         if (!adev->ras_enabled || !con)
1424                 return -EOPNOTSUPP;
1425
1426         /* Don't count since no reporting.
1427          */
1428         if (!ce_count && !ue_count)
1429                 return 0;
1430
1431         ce = 0;
1432         ue = 0;
1433         if (!query_info) {
1434                 /* query all the ip blocks that support ras query interface */
1435                 list_for_each_entry(obj, &con->head, node) {
1436                         struct ras_query_if info = {
1437                                 .head = obj->head,
1438                         };
1439
1440                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1441                 }
1442         } else {
1443                 /* query specific ip block */
1444                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1445         }
1446
1447         if (ret)
1448                 return ret;
1449
1450         if (ce_count)
1451                 *ce_count = ce;
1452
1453         if (ue_count)
1454                 *ue_count = ue;
1455
1456         return 0;
1457 }
1458 /* query/inject/cure end */
1459
1460
1461 /* sysfs begin */
1462
1463 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1464                 struct ras_badpage **bps, unsigned int *count);
1465
1466 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1467 {
1468         switch (flags) {
1469         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1470                 return "R";
1471         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1472                 return "P";
1473         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1474         default:
1475                 return "F";
1476         }
1477 }
1478
1479 /**
1480  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1481  *
1482  * It allows user to read the bad pages of vram on the gpu through
1483  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1484  *
1485  * It outputs multiple lines, and each line stands for one gpu page.
1486  *
1487  * The format of one line is below,
1488  * gpu pfn : gpu page size : flags
1489  *
1490  * gpu pfn and gpu page size are printed in hex format.
1491  * flags can be one of below character,
1492  *
1493  * R: reserved, this gpu page is reserved and not able to use.
1494  *
1495  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1496  * in next window of page_reserve.
1497  *
1498  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1499  *
1500  * Examples:
1501  *
1502  * .. code-block:: bash
1503  *
1504  *      0x00000001 : 0x00001000 : R
1505  *      0x00000002 : 0x00001000 : P
1506  *
1507  */
1508
1509 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1510                 struct kobject *kobj, struct bin_attribute *attr,
1511                 char *buf, loff_t ppos, size_t count)
1512 {
1513         struct amdgpu_ras *con =
1514                 container_of(attr, struct amdgpu_ras, badpages_attr);
1515         struct amdgpu_device *adev = con->adev;
1516         const unsigned int element_size =
1517                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1518         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1519         unsigned int end = div64_ul(ppos + count - 1, element_size);
1520         ssize_t s = 0;
1521         struct ras_badpage *bps = NULL;
1522         unsigned int bps_count = 0;
1523
1524         memset(buf, 0, count);
1525
1526         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1527                 return 0;
1528
1529         for (; start < end && start < bps_count; start++)
1530                 s += scnprintf(&buf[s], element_size + 1,
1531                                 "0x%08x : 0x%08x : %1s\n",
1532                                 bps[start].bp,
1533                                 bps[start].size,
1534                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1535
1536         kfree(bps);
1537
1538         return s;
1539 }
1540
1541 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1542                 struct device_attribute *attr, char *buf)
1543 {
1544         struct amdgpu_ras *con =
1545                 container_of(attr, struct amdgpu_ras, features_attr);
1546
1547         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1548 }
1549
1550 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1551                 struct device_attribute *attr, char *buf)
1552 {
1553         struct amdgpu_ras *con =
1554                 container_of(attr, struct amdgpu_ras, version_attr);
1555         return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1556 }
1557
1558 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1559                 struct device_attribute *attr, char *buf)
1560 {
1561         struct amdgpu_ras *con =
1562                 container_of(attr, struct amdgpu_ras, schema_attr);
1563         return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1564 }
1565
1566 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1567 {
1568         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1569
1570         if (adev->dev->kobj.sd)
1571                 sysfs_remove_file_from_group(&adev->dev->kobj,
1572                                 &con->badpages_attr.attr,
1573                                 RAS_FS_NAME);
1574 }
1575
1576 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1577 {
1578         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1579         struct attribute *attrs[] = {
1580                 &con->features_attr.attr,
1581                 &con->version_attr.attr,
1582                 &con->schema_attr.attr,
1583                 NULL
1584         };
1585         struct attribute_group group = {
1586                 .name = RAS_FS_NAME,
1587                 .attrs = attrs,
1588         };
1589
1590         if (adev->dev->kobj.sd)
1591                 sysfs_remove_group(&adev->dev->kobj, &group);
1592
1593         return 0;
1594 }
1595
1596 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1597                 struct ras_common_if *head)
1598 {
1599         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1600
1601         if (!obj || obj->attr_inuse)
1602                 return -EINVAL;
1603
1604         get_obj(obj);
1605
1606         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1607                 "%s_err_count", head->name);
1608
1609         obj->sysfs_attr = (struct device_attribute){
1610                 .attr = {
1611                         .name = obj->fs_data.sysfs_name,
1612                         .mode = S_IRUGO,
1613                 },
1614                         .show = amdgpu_ras_sysfs_read,
1615         };
1616         sysfs_attr_init(&obj->sysfs_attr.attr);
1617
1618         if (sysfs_add_file_to_group(&adev->dev->kobj,
1619                                 &obj->sysfs_attr.attr,
1620                                 RAS_FS_NAME)) {
1621                 put_obj(obj);
1622                 return -EINVAL;
1623         }
1624
1625         obj->attr_inuse = 1;
1626
1627         return 0;
1628 }
1629
1630 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1631                 struct ras_common_if *head)
1632 {
1633         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1634
1635         if (!obj || !obj->attr_inuse)
1636                 return -EINVAL;
1637
1638         if (adev->dev->kobj.sd)
1639                 sysfs_remove_file_from_group(&adev->dev->kobj,
1640                                 &obj->sysfs_attr.attr,
1641                                 RAS_FS_NAME);
1642         obj->attr_inuse = 0;
1643         put_obj(obj);
1644
1645         return 0;
1646 }
1647
1648 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1649 {
1650         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1651         struct ras_manager *obj, *tmp;
1652
1653         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1654                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1655         }
1656
1657         if (amdgpu_bad_page_threshold != 0)
1658                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1659
1660         amdgpu_ras_sysfs_remove_dev_attr_node(adev);
1661
1662         return 0;
1663 }
1664 /* sysfs end */
1665
1666 /**
1667  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1668  *
1669  * Normally when there is an uncorrectable error, the driver will reset
1670  * the GPU to recover.  However, in the event of an unrecoverable error,
1671  * the driver provides an interface to reboot the system automatically
1672  * in that event.
1673  *
1674  * The following file in debugfs provides that interface:
1675  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1676  *
1677  * Usage:
1678  *
1679  * .. code-block:: bash
1680  *
1681  *      echo true > .../ras/auto_reboot
1682  *
1683  */
1684 /* debugfs begin */
1685 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1686 {
1687         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1688         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1689         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1690         struct dentry     *dir;
1691
1692         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1693         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1694                             &amdgpu_ras_debugfs_ctrl_ops);
1695         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1696                             &amdgpu_ras_debugfs_eeprom_ops);
1697         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1698                            &con->bad_page_cnt_threshold);
1699         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1700         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1701         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1702         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1703                             &amdgpu_ras_debugfs_eeprom_size_ops);
1704         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1705                                                        S_IRUGO, dir, adev,
1706                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1707         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1708
1709         /*
1710          * After one uncorrectable error happens, usually GPU recovery will
1711          * be scheduled. But due to the known problem in GPU recovery failing
1712          * to bring GPU back, below interface provides one direct way to
1713          * user to reboot system automatically in such case within
1714          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1715          * will never be called.
1716          */
1717         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1718
1719         /*
1720          * User could set this not to clean up hardware's error count register
1721          * of RAS IPs during ras recovery.
1722          */
1723         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1724                             &con->disable_ras_err_cnt_harvest);
1725         return dir;
1726 }
1727
1728 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1729                                       struct ras_fs_if *head,
1730                                       struct dentry *dir)
1731 {
1732         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1733
1734         if (!obj || !dir)
1735                 return;
1736
1737         get_obj(obj);
1738
1739         memcpy(obj->fs_data.debugfs_name,
1740                         head->debugfs_name,
1741                         sizeof(obj->fs_data.debugfs_name));
1742
1743         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1744                             obj, &amdgpu_ras_debugfs_ops);
1745 }
1746
1747 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1748 {
1749         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1750         struct dentry *dir;
1751         struct ras_manager *obj;
1752         struct ras_fs_if fs_info;
1753
1754         /*
1755          * it won't be called in resume path, no need to check
1756          * suspend and gpu reset status
1757          */
1758         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1759                 return;
1760
1761         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1762
1763         list_for_each_entry(obj, &con->head, node) {
1764                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1765                         (obj->attr_inuse == 1)) {
1766                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1767                                         get_ras_block_str(&obj->head));
1768                         fs_info.head = obj->head;
1769                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1770                 }
1771         }
1772
1773         amdgpu_mca_smu_debugfs_init(adev, dir);
1774 }
1775
1776 /* debugfs end */
1777
1778 /* ras fs */
1779 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1780                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1781 static DEVICE_ATTR(features, S_IRUGO,
1782                 amdgpu_ras_sysfs_features_read, NULL);
1783 static DEVICE_ATTR(version, 0444,
1784                 amdgpu_ras_sysfs_version_show, NULL);
1785 static DEVICE_ATTR(schema, 0444,
1786                 amdgpu_ras_sysfs_schema_show, NULL);
1787 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1788 {
1789         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1790         struct attribute_group group = {
1791                 .name = RAS_FS_NAME,
1792         };
1793         struct attribute *attrs[] = {
1794                 &con->features_attr.attr,
1795                 &con->version_attr.attr,
1796                 &con->schema_attr.attr,
1797                 NULL
1798         };
1799         struct bin_attribute *bin_attrs[] = {
1800                 NULL,
1801                 NULL,
1802         };
1803         int r;
1804
1805         group.attrs = attrs;
1806
1807         /* add features entry */
1808         con->features_attr = dev_attr_features;
1809         sysfs_attr_init(attrs[0]);
1810
1811         /* add version entry */
1812         con->version_attr = dev_attr_version;
1813         sysfs_attr_init(attrs[1]);
1814
1815         /* add schema entry */
1816         con->schema_attr = dev_attr_schema;
1817         sysfs_attr_init(attrs[2]);
1818
1819         if (amdgpu_bad_page_threshold != 0) {
1820                 /* add bad_page_features entry */
1821                 bin_attr_gpu_vram_bad_pages.private = NULL;
1822                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1823                 bin_attrs[0] = &con->badpages_attr;
1824                 group.bin_attrs = bin_attrs;
1825                 sysfs_bin_attr_init(bin_attrs[0]);
1826         }
1827
1828         r = sysfs_create_group(&adev->dev->kobj, &group);
1829         if (r)
1830                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1831
1832         return 0;
1833 }
1834
1835 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1836 {
1837         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1838         struct ras_manager *con_obj, *ip_obj, *tmp;
1839
1840         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1841                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1842                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1843                         if (ip_obj)
1844                                 put_obj(ip_obj);
1845                 }
1846         }
1847
1848         amdgpu_ras_sysfs_remove_all(adev);
1849         return 0;
1850 }
1851 /* ras fs end */
1852
1853 /* ih begin */
1854
1855 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1856  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1857  * register to check whether the interrupt is triggered or not, and properly
1858  * ack the interrupt if it is there
1859  */
1860 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1861 {
1862         /* Fatal error events are handled on host side */
1863         if (amdgpu_sriov_vf(adev))
1864                 return;
1865
1866         if (adev->nbio.ras &&
1867             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1868                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1869
1870         if (adev->nbio.ras &&
1871             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1872                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1873 }
1874
1875 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1876                                 struct amdgpu_iv_entry *entry)
1877 {
1878         bool poison_stat = false;
1879         struct amdgpu_device *adev = obj->adev;
1880         struct amdgpu_ras_block_object *block_obj =
1881                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1882
1883         if (!block_obj)
1884                 return;
1885
1886         /* both query_poison_status and handle_poison_consumption are optional,
1887          * but at least one of them should be implemented if we need poison
1888          * consumption handler
1889          */
1890         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1891                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1892                 if (!poison_stat) {
1893                         /* Not poison consumption interrupt, no need to handle it */
1894                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1895                                         block_obj->ras_comm.name);
1896
1897                         return;
1898                 }
1899         }
1900
1901         amdgpu_umc_poison_handler(adev, false);
1902
1903         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1904                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1905
1906         /* gpu reset is fallback for failed and default cases */
1907         if (poison_stat) {
1908                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1909                                 block_obj->ras_comm.name);
1910                 amdgpu_ras_reset_gpu(adev);
1911         } else {
1912                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1913         }
1914 }
1915
1916 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1917                                 struct amdgpu_iv_entry *entry)
1918 {
1919         dev_info(obj->adev->dev,
1920                 "Poison is created, no user action is needed.\n");
1921 }
1922
1923 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1924                                 struct amdgpu_iv_entry *entry)
1925 {
1926         struct ras_ih_data *data = &obj->ih_data;
1927         struct ras_err_data err_data;
1928         int ret;
1929
1930         if (!data->cb)
1931                 return;
1932
1933         ret = amdgpu_ras_error_data_init(&err_data);
1934         if (ret)
1935                 return;
1936
1937         /* Let IP handle its data, maybe we need get the output
1938          * from the callback to update the error type/count, etc
1939          */
1940         ret = data->cb(obj->adev, &err_data, entry);
1941         /* ue will trigger an interrupt, and in that case
1942          * we need do a reset to recovery the whole system.
1943          * But leave IP do that recovery, here we just dispatch
1944          * the error.
1945          */
1946         if (ret == AMDGPU_RAS_SUCCESS) {
1947                 /* these counts could be left as 0 if
1948                  * some blocks do not count error number
1949                  */
1950                 obj->err_data.ue_count += err_data.ue_count;
1951                 obj->err_data.ce_count += err_data.ce_count;
1952         }
1953
1954         amdgpu_ras_error_data_fini(&err_data);
1955 }
1956
1957 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1958 {
1959         struct ras_ih_data *data = &obj->ih_data;
1960         struct amdgpu_iv_entry entry;
1961
1962         while (data->rptr != data->wptr) {
1963                 rmb();
1964                 memcpy(&entry, &data->ring[data->rptr],
1965                                 data->element_size);
1966
1967                 wmb();
1968                 data->rptr = (data->aligned_element_size +
1969                                 data->rptr) % data->ring_size;
1970
1971                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1972                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1973                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1974                         else
1975                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1976                 } else {
1977                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1978                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1979                         else
1980                                 dev_warn(obj->adev->dev,
1981                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1982                 }
1983         }
1984 }
1985
1986 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1987 {
1988         struct ras_ih_data *data =
1989                 container_of(work, struct ras_ih_data, ih_work);
1990         struct ras_manager *obj =
1991                 container_of(data, struct ras_manager, ih_data);
1992
1993         amdgpu_ras_interrupt_handler(obj);
1994 }
1995
1996 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1997                 struct ras_dispatch_if *info)
1998 {
1999         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
2000         struct ras_ih_data *data = &obj->ih_data;
2001
2002         if (!obj)
2003                 return -EINVAL;
2004
2005         if (data->inuse == 0)
2006                 return 0;
2007
2008         /* Might be overflow... */
2009         memcpy(&data->ring[data->wptr], info->entry,
2010                         data->element_size);
2011
2012         wmb();
2013         data->wptr = (data->aligned_element_size +
2014                         data->wptr) % data->ring_size;
2015
2016         schedule_work(&data->ih_work);
2017
2018         return 0;
2019 }
2020
2021 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
2022                 struct ras_common_if *head)
2023 {
2024         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2025         struct ras_ih_data *data;
2026
2027         if (!obj)
2028                 return -EINVAL;
2029
2030         data = &obj->ih_data;
2031         if (data->inuse == 0)
2032                 return 0;
2033
2034         cancel_work_sync(&data->ih_work);
2035
2036         kfree(data->ring);
2037         memset(data, 0, sizeof(*data));
2038         put_obj(obj);
2039
2040         return 0;
2041 }
2042
2043 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
2044                 struct ras_common_if *head)
2045 {
2046         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2047         struct ras_ih_data *data;
2048         struct amdgpu_ras_block_object *ras_obj;
2049
2050         if (!obj) {
2051                 /* in case we registe the IH before enable ras feature */
2052                 obj = amdgpu_ras_create_obj(adev, head);
2053                 if (!obj)
2054                         return -EINVAL;
2055         } else
2056                 get_obj(obj);
2057
2058         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
2059
2060         data = &obj->ih_data;
2061         /* add the callback.etc */
2062         *data = (struct ras_ih_data) {
2063                 .inuse = 0,
2064                 .cb = ras_obj->ras_cb,
2065                 .element_size = sizeof(struct amdgpu_iv_entry),
2066                 .rptr = 0,
2067                 .wptr = 0,
2068         };
2069
2070         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
2071
2072         data->aligned_element_size = ALIGN(data->element_size, 8);
2073         /* the ring can store 64 iv entries. */
2074         data->ring_size = 64 * data->aligned_element_size;
2075         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
2076         if (!data->ring) {
2077                 put_obj(obj);
2078                 return -ENOMEM;
2079         }
2080
2081         /* IH is ready */
2082         data->inuse = 1;
2083
2084         return 0;
2085 }
2086
2087 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
2088 {
2089         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2090         struct ras_manager *obj, *tmp;
2091
2092         list_for_each_entry_safe(obj, tmp, &con->head, node) {
2093                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
2094         }
2095
2096         return 0;
2097 }
2098 /* ih end */
2099
2100 /* traversal all IPs except NBIO to query error counter */
2101 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
2102 {
2103         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2104         struct ras_manager *obj;
2105
2106         if (!adev->ras_enabled || !con)
2107                 return;
2108
2109         list_for_each_entry(obj, &con->head, node) {
2110                 struct ras_query_if info = {
2111                         .head = obj->head,
2112                 };
2113
2114                 /*
2115                  * PCIE_BIF IP has one different isr by ras controller
2116                  * interrupt, the specific ras counter query will be
2117                  * done in that isr. So skip such block from common
2118                  * sync flood interrupt isr calling.
2119                  */
2120                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2121                         continue;
2122
2123                 /*
2124                  * this is a workaround for aldebaran, skip send msg to
2125                  * smu to get ecc_info table due to smu handle get ecc
2126                  * info table failed temporarily.
2127                  * should be removed until smu fix handle ecc_info table.
2128                  */
2129                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2130                     (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2131                      IP_VERSION(13, 0, 2)))
2132                         continue;
2133
2134                 amdgpu_ras_query_error_status(adev, &info);
2135
2136                 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2137                             IP_VERSION(11, 0, 2) &&
2138                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2139                             IP_VERSION(11, 0, 4) &&
2140                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2141                             IP_VERSION(13, 0, 0)) {
2142                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
2143                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
2144                 }
2145         }
2146 }
2147
2148 /* Parse RdRspStatus and WrRspStatus */
2149 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2150                                           struct ras_query_if *info)
2151 {
2152         struct amdgpu_ras_block_object *block_obj;
2153         /*
2154          * Only two block need to query read/write
2155          * RspStatus at current state
2156          */
2157         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2158                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2159                 return;
2160
2161         block_obj = amdgpu_ras_get_ras_block(adev,
2162                                         info->head.block,
2163                                         info->head.sub_block_index);
2164
2165         if (!block_obj || !block_obj->hw_ops) {
2166                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2167                              get_ras_block_str(&info->head));
2168                 return;
2169         }
2170
2171         if (block_obj->hw_ops->query_ras_error_status)
2172                 block_obj->hw_ops->query_ras_error_status(adev);
2173
2174 }
2175
2176 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2177 {
2178         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2179         struct ras_manager *obj;
2180
2181         if (!adev->ras_enabled || !con)
2182                 return;
2183
2184         list_for_each_entry(obj, &con->head, node) {
2185                 struct ras_query_if info = {
2186                         .head = obj->head,
2187                 };
2188
2189                 amdgpu_ras_error_status_query(adev, &info);
2190         }
2191 }
2192
2193 /* recovery begin */
2194
2195 /* return 0 on success.
2196  * caller need free bps.
2197  */
2198 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2199                 struct ras_badpage **bps, unsigned int *count)
2200 {
2201         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2202         struct ras_err_handler_data *data;
2203         int i = 0;
2204         int ret = 0, status;
2205
2206         if (!con || !con->eh_data || !bps || !count)
2207                 return -EINVAL;
2208
2209         mutex_lock(&con->recovery_lock);
2210         data = con->eh_data;
2211         if (!data || data->count == 0) {
2212                 *bps = NULL;
2213                 ret = -EINVAL;
2214                 goto out;
2215         }
2216
2217         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2218         if (!*bps) {
2219                 ret = -ENOMEM;
2220                 goto out;
2221         }
2222
2223         for (; i < data->count; i++) {
2224                 (*bps)[i] = (struct ras_badpage){
2225                         .bp = data->bps[i].retired_page,
2226                         .size = AMDGPU_GPU_PAGE_SIZE,
2227                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2228                 };
2229                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2230                                 data->bps[i].retired_page);
2231                 if (status == -EBUSY)
2232                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2233                 else if (status == -ENOENT)
2234                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2235         }
2236
2237         *count = data->count;
2238 out:
2239         mutex_unlock(&con->recovery_lock);
2240         return ret;
2241 }
2242
2243 static void amdgpu_ras_do_recovery(struct work_struct *work)
2244 {
2245         struct amdgpu_ras *ras =
2246                 container_of(work, struct amdgpu_ras, recovery_work);
2247         struct amdgpu_device *remote_adev = NULL;
2248         struct amdgpu_device *adev = ras->adev;
2249         struct list_head device_list, *device_list_handle =  NULL;
2250         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2251
2252         if (hive)
2253                 atomic_set(&hive->ras_recovery, 1);
2254         if (!ras->disable_ras_err_cnt_harvest) {
2255
2256                 /* Build list of devices to query RAS related errors */
2257                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2258                         device_list_handle = &hive->device_list;
2259                 } else {
2260                         INIT_LIST_HEAD(&device_list);
2261                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2262                         device_list_handle = &device_list;
2263                 }
2264
2265                 list_for_each_entry(remote_adev,
2266                                 device_list_handle, gmc.xgmi.head) {
2267                         amdgpu_ras_query_err_status(remote_adev);
2268                         amdgpu_ras_log_on_err_counter(remote_adev);
2269                 }
2270
2271         }
2272
2273         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2274                 struct amdgpu_reset_context reset_context;
2275                 memset(&reset_context, 0, sizeof(reset_context));
2276
2277                 reset_context.method = AMD_RESET_METHOD_NONE;
2278                 reset_context.reset_req_dev = adev;
2279
2280                 /* Perform full reset in fatal error mode */
2281                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2282                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2283                 else {
2284                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2285
2286                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2287                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2288                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2289                         }
2290
2291                         /* Fatal error occurs in poison mode, mode1 reset is used to
2292                          * recover gpu.
2293                          */
2294                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2295                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2296                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2297
2298                                 psp_fatal_error_recovery_quirk(&adev->psp);
2299                         }
2300                 }
2301
2302                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2303         }
2304         atomic_set(&ras->in_recovery, 0);
2305         if (hive) {
2306                 atomic_set(&hive->ras_recovery, 0);
2307                 amdgpu_put_xgmi_hive(hive);
2308         }
2309 }
2310
2311 /* alloc/realloc bps array */
2312 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2313                 struct ras_err_handler_data *data, int pages)
2314 {
2315         unsigned int old_space = data->count + data->space_left;
2316         unsigned int new_space = old_space + pages;
2317         unsigned int align_space = ALIGN(new_space, 512);
2318         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2319
2320         if (!bps) {
2321                 return -ENOMEM;
2322         }
2323
2324         if (data->bps) {
2325                 memcpy(bps, data->bps,
2326                                 data->count * sizeof(*data->bps));
2327                 kfree(data->bps);
2328         }
2329
2330         data->bps = bps;
2331         data->space_left += align_space - old_space;
2332         return 0;
2333 }
2334
2335 /* it deal with vram only. */
2336 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2337                 struct eeprom_table_record *bps, int pages)
2338 {
2339         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2340         struct ras_err_handler_data *data;
2341         int ret = 0;
2342         uint32_t i;
2343
2344         if (!con || !con->eh_data || !bps || pages <= 0)
2345                 return 0;
2346
2347         mutex_lock(&con->recovery_lock);
2348         data = con->eh_data;
2349         if (!data)
2350                 goto out;
2351
2352         for (i = 0; i < pages; i++) {
2353                 if (amdgpu_ras_check_bad_page_unlock(con,
2354                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2355                         continue;
2356
2357                 if (!data->space_left &&
2358                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2359                         ret = -ENOMEM;
2360                         goto out;
2361                 }
2362
2363                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2364                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2365                         AMDGPU_GPU_PAGE_SIZE);
2366
2367                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2368                 data->count++;
2369                 data->space_left--;
2370         }
2371 out:
2372         mutex_unlock(&con->recovery_lock);
2373
2374         return ret;
2375 }
2376
2377 /*
2378  * write error record array to eeprom, the function should be
2379  * protected by recovery_lock
2380  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2381  */
2382 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2383                 unsigned long *new_cnt)
2384 {
2385         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2386         struct ras_err_handler_data *data;
2387         struct amdgpu_ras_eeprom_control *control;
2388         int save_count;
2389
2390         if (!con || !con->eh_data) {
2391                 if (new_cnt)
2392                         *new_cnt = 0;
2393
2394                 return 0;
2395         }
2396
2397         mutex_lock(&con->recovery_lock);
2398         control = &con->eeprom_control;
2399         data = con->eh_data;
2400         save_count = data->count - control->ras_num_recs;
2401         mutex_unlock(&con->recovery_lock);
2402
2403         if (new_cnt)
2404                 *new_cnt = save_count / adev->umc.retire_unit;
2405
2406         /* only new entries are saved */
2407         if (save_count > 0) {
2408                 if (amdgpu_ras_eeprom_append(control,
2409                                              &data->bps[control->ras_num_recs],
2410                                              save_count)) {
2411                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2412                         return -EIO;
2413                 }
2414
2415                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2416         }
2417
2418         return 0;
2419 }
2420
2421 /*
2422  * read error record array in eeprom and reserve enough space for
2423  * storing new bad pages
2424  */
2425 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2426 {
2427         struct amdgpu_ras_eeprom_control *control =
2428                 &adev->psp.ras_context.ras->eeprom_control;
2429         struct eeprom_table_record *bps;
2430         int ret;
2431
2432         /* no bad page record, skip eeprom access */
2433         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2434                 return 0;
2435
2436         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2437         if (!bps)
2438                 return -ENOMEM;
2439
2440         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2441         if (ret)
2442                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2443         else
2444                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2445
2446         kfree(bps);
2447         return ret;
2448 }
2449
2450 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2451                                 uint64_t addr)
2452 {
2453         struct ras_err_handler_data *data = con->eh_data;
2454         int i;
2455
2456         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2457         for (i = 0; i < data->count; i++)
2458                 if (addr == data->bps[i].retired_page)
2459                         return true;
2460
2461         return false;
2462 }
2463
2464 /*
2465  * check if an address belongs to bad page
2466  *
2467  * Note: this check is only for umc block
2468  */
2469 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2470                                 uint64_t addr)
2471 {
2472         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2473         bool ret = false;
2474
2475         if (!con || !con->eh_data)
2476                 return ret;
2477
2478         mutex_lock(&con->recovery_lock);
2479         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2480         mutex_unlock(&con->recovery_lock);
2481         return ret;
2482 }
2483
2484 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2485                                           uint32_t max_count)
2486 {
2487         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2488
2489         /*
2490          * Justification of value bad_page_cnt_threshold in ras structure
2491          *
2492          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2493          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2494          * scenarios accordingly.
2495          *
2496          * Bad page retirement enablement:
2497          *    - If amdgpu_bad_page_threshold = -2,
2498          *      bad_page_cnt_threshold = typical value by formula.
2499          *
2500          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2501          *      max record length in eeprom, use it directly.
2502          *
2503          * Bad page retirement disablement:
2504          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2505          *      functionality is disabled, and bad_page_cnt_threshold will
2506          *      take no effect.
2507          */
2508
2509         if (amdgpu_bad_page_threshold < 0) {
2510                 u64 val = adev->gmc.mc_vram_size;
2511
2512                 do_div(val, RAS_BAD_PAGE_COVER);
2513                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2514                                                   max_count);
2515         } else {
2516                 con->bad_page_cnt_threshold = min_t(int, max_count,
2517                                                     amdgpu_bad_page_threshold);
2518         }
2519 }
2520
2521 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2522 {
2523         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2524         struct ras_err_handler_data **data;
2525         u32  max_eeprom_records_count = 0;
2526         bool exc_err_limit = false;
2527         int ret;
2528
2529         if (!con || amdgpu_sriov_vf(adev))
2530                 return 0;
2531
2532         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2533          * supports RAS and debugfs is enabled, but when
2534          * adev->ras_enabled is unset, i.e. when "ras_enable"
2535          * module parameter is set to 0.
2536          */
2537         con->adev = adev;
2538
2539         if (!adev->ras_enabled)
2540                 return 0;
2541
2542         data = &con->eh_data;
2543         *data = kzalloc(sizeof(**data), GFP_KERNEL);
2544         if (!*data) {
2545                 ret = -ENOMEM;
2546                 goto out;
2547         }
2548
2549         mutex_init(&con->recovery_lock);
2550         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2551         atomic_set(&con->in_recovery, 0);
2552         con->eeprom_control.bad_channel_bitmap = 0;
2553
2554         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2555         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2556
2557         /* Todo: During test the SMU might fail to read the eeprom through I2C
2558          * when the GPU is pending on XGMI reset during probe time
2559          * (Mostly after second bus reset), skip it now
2560          */
2561         if (adev->gmc.xgmi.pending_reset)
2562                 return 0;
2563         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2564         /*
2565          * This calling fails when exc_err_limit is true or
2566          * ret != 0.
2567          */
2568         if (exc_err_limit || ret)
2569                 goto free;
2570
2571         if (con->eeprom_control.ras_num_recs) {
2572                 ret = amdgpu_ras_load_bad_pages(adev);
2573                 if (ret)
2574                         goto free;
2575
2576                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2577
2578                 if (con->update_channel_flag == true) {
2579                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2580                         con->update_channel_flag = false;
2581                 }
2582         }
2583
2584 #ifdef CONFIG_X86_MCE_AMD
2585         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2586             (adev->gmc.xgmi.connected_to_cpu))
2587                 amdgpu_register_bad_pages_mca_notifier(adev);
2588 #endif
2589         return 0;
2590
2591 free:
2592         kfree((*data)->bps);
2593         kfree(*data);
2594         con->eh_data = NULL;
2595 out:
2596         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2597
2598         /*
2599          * Except error threshold exceeding case, other failure cases in this
2600          * function would not fail amdgpu driver init.
2601          */
2602         if (!exc_err_limit)
2603                 ret = 0;
2604         else
2605                 ret = -EINVAL;
2606
2607         return ret;
2608 }
2609
2610 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2611 {
2612         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2613         struct ras_err_handler_data *data = con->eh_data;
2614
2615         /* recovery_init failed to init it, fini is useless */
2616         if (!data)
2617                 return 0;
2618
2619         cancel_work_sync(&con->recovery_work);
2620
2621         mutex_lock(&con->recovery_lock);
2622         con->eh_data = NULL;
2623         kfree(data->bps);
2624         kfree(data);
2625         mutex_unlock(&con->recovery_lock);
2626
2627         return 0;
2628 }
2629 /* recovery end */
2630
2631 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2632 {
2633         if (amdgpu_sriov_vf(adev)) {
2634                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2635                 case IP_VERSION(13, 0, 2):
2636                 case IP_VERSION(13, 0, 6):
2637                         return true;
2638                 default:
2639                         return false;
2640                 }
2641         }
2642
2643         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2644                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2645                 case IP_VERSION(13, 0, 0):
2646                 case IP_VERSION(13, 0, 6):
2647                 case IP_VERSION(13, 0, 10):
2648                         return true;
2649                 default:
2650                         return false;
2651                 }
2652         }
2653
2654         return adev->asic_type == CHIP_VEGA10 ||
2655                 adev->asic_type == CHIP_VEGA20 ||
2656                 adev->asic_type == CHIP_ARCTURUS ||
2657                 adev->asic_type == CHIP_ALDEBARAN ||
2658                 adev->asic_type == CHIP_SIENNA_CICHLID;
2659 }
2660
2661 /*
2662  * this is workaround for vega20 workstation sku,
2663  * force enable gfx ras, ignore vbios gfx ras flag
2664  * due to GC EDC can not write
2665  */
2666 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2667 {
2668         struct atom_context *ctx = adev->mode_info.atom_context;
2669
2670         if (!ctx)
2671                 return;
2672
2673         if (strnstr(ctx->vbios_pn, "D16406",
2674                     sizeof(ctx->vbios_pn)) ||
2675                 strnstr(ctx->vbios_pn, "D36002",
2676                         sizeof(ctx->vbios_pn)))
2677                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2678 }
2679
2680 /*
2681  * check hardware's ras ability which will be saved in hw_supported.
2682  * if hardware does not support ras, we can skip some ras initializtion and
2683  * forbid some ras operations from IP.
2684  * if software itself, say boot parameter, limit the ras ability. We still
2685  * need allow IP do some limited operations, like disable. In such case,
2686  * we have to initialize ras as normal. but need check if operation is
2687  * allowed or not in each function.
2688  */
2689 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2690 {
2691         adev->ras_hw_enabled = adev->ras_enabled = 0;
2692
2693         if (!amdgpu_ras_asic_supported(adev))
2694                 return;
2695
2696         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2697                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2698                         dev_info(adev->dev, "MEM ECC is active.\n");
2699                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2700                                                    1 << AMDGPU_RAS_BLOCK__DF);
2701                 } else {
2702                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2703                 }
2704
2705                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2706                         dev_info(adev->dev, "SRAM ECC is active.\n");
2707                         if (!amdgpu_sriov_vf(adev))
2708                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2709                                                             1 << AMDGPU_RAS_BLOCK__DF);
2710                         else
2711                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2712                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2713                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2714
2715                         /* VCN/JPEG RAS can be supported on both bare metal and
2716                          * SRIOV environment
2717                          */
2718                         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2719                                     IP_VERSION(2, 6, 0) ||
2720                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2721                                     IP_VERSION(4, 0, 0) ||
2722                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2723                                     IP_VERSION(4, 0, 3))
2724                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2725                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2726                         else
2727                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2728                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2729
2730                         /*
2731                          * XGMI RAS is not supported if xgmi num physical nodes
2732                          * is zero
2733                          */
2734                         if (!adev->gmc.xgmi.num_physical_nodes)
2735                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2736                 } else {
2737                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2738                 }
2739         } else {
2740                 /* driver only manages a few IP blocks RAS feature
2741                  * when GPU is connected cpu through XGMI */
2742                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2743                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2744                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2745         }
2746
2747         amdgpu_ras_get_quirks(adev);
2748
2749         /* hw_supported needs to be aligned with RAS block mask. */
2750         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2751
2752         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2753                 adev->ras_hw_enabled & amdgpu_ras_mask;
2754 }
2755
2756 static void amdgpu_ras_counte_dw(struct work_struct *work)
2757 {
2758         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2759                                               ras_counte_delay_work.work);
2760         struct amdgpu_device *adev = con->adev;
2761         struct drm_device *dev = adev_to_drm(adev);
2762         unsigned long ce_count, ue_count;
2763         int res;
2764
2765         res = pm_runtime_get_sync(dev->dev);
2766         if (res < 0)
2767                 goto Out;
2768
2769         /* Cache new values.
2770          */
2771         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2772                 atomic_set(&con->ras_ce_count, ce_count);
2773                 atomic_set(&con->ras_ue_count, ue_count);
2774         }
2775
2776         pm_runtime_mark_last_busy(dev->dev);
2777 Out:
2778         pm_runtime_put_autosuspend(dev->dev);
2779 }
2780
2781 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2782 {
2783         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2784         bool df_poison, umc_poison;
2785
2786         /* poison setting is useless on SRIOV guest */
2787         if (amdgpu_sriov_vf(adev) || !con)
2788                 return;
2789
2790         /* Init poison supported flag, the default value is false */
2791         if (adev->gmc.xgmi.connected_to_cpu ||
2792             adev->gmc.is_app_apu) {
2793                 /* enabled by default when GPU is connected to CPU */
2794                 con->poison_supported = true;
2795         } else if (adev->df.funcs &&
2796             adev->df.funcs->query_ras_poison_mode &&
2797             adev->umc.ras &&
2798             adev->umc.ras->query_ras_poison_mode) {
2799                 df_poison =
2800                         adev->df.funcs->query_ras_poison_mode(adev);
2801                 umc_poison =
2802                         adev->umc.ras->query_ras_poison_mode(adev);
2803
2804                 /* Only poison is set in both DF and UMC, we can support it */
2805                 if (df_poison && umc_poison)
2806                         con->poison_supported = true;
2807                 else if (df_poison != umc_poison)
2808                         dev_warn(adev->dev,
2809                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2810                                 df_poison, umc_poison);
2811         }
2812 }
2813
2814 static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
2815 {
2816         return  amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
2817                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
2818                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
2819                         AMDGPU_RAS_ERROR__PARITY;
2820 }
2821
2822 int amdgpu_ras_init(struct amdgpu_device *adev)
2823 {
2824         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2825         int r;
2826
2827         if (con)
2828                 return 0;
2829
2830         con = kzalloc(sizeof(*con) +
2831                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2832                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2833                         GFP_KERNEL);
2834         if (!con)
2835                 return -ENOMEM;
2836
2837         con->adev = adev;
2838         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2839         atomic_set(&con->ras_ce_count, 0);
2840         atomic_set(&con->ras_ue_count, 0);
2841
2842         con->objs = (struct ras_manager *)(con + 1);
2843
2844         amdgpu_ras_set_context(adev, con);
2845
2846         amdgpu_ras_check_supported(adev);
2847
2848         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2849                 /* set gfx block ras context feature for VEGA20 Gaming
2850                  * send ras disable cmd to ras ta during ras late init.
2851                  */
2852                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2853                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2854
2855                         return 0;
2856                 }
2857
2858                 r = 0;
2859                 goto release_con;
2860         }
2861
2862         con->update_channel_flag = false;
2863         con->features = 0;
2864         con->schema = 0;
2865         INIT_LIST_HEAD(&con->head);
2866         /* Might need get this flag from vbios. */
2867         con->flags = RAS_DEFAULT_FLAGS;
2868
2869         /* initialize nbio ras function ahead of any other
2870          * ras functions so hardware fatal error interrupt
2871          * can be enabled as early as possible */
2872         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2873         case IP_VERSION(7, 4, 0):
2874         case IP_VERSION(7, 4, 1):
2875         case IP_VERSION(7, 4, 4):
2876                 if (!adev->gmc.xgmi.connected_to_cpu)
2877                         adev->nbio.ras = &nbio_v7_4_ras;
2878                 break;
2879         case IP_VERSION(4, 3, 0):
2880                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2881                         /* unlike other generation of nbio ras,
2882                          * nbio v4_3 only support fatal error interrupt
2883                          * to inform software that DF is freezed due to
2884                          * system fatal error event. driver should not
2885                          * enable nbio ras in such case. Instead,
2886                          * check DF RAS */
2887                         adev->nbio.ras = &nbio_v4_3_ras;
2888                 break;
2889         case IP_VERSION(7, 9, 0):
2890                 if (!adev->gmc.is_app_apu)
2891                         adev->nbio.ras = &nbio_v7_9_ras;
2892                 break;
2893         default:
2894                 /* nbio ras is not available */
2895                 break;
2896         }
2897
2898         /* nbio ras block needs to be enabled ahead of other ras blocks
2899          * to handle fatal error */
2900         r = amdgpu_nbio_ras_sw_init(adev);
2901         if (r)
2902                 return r;
2903
2904         if (adev->nbio.ras &&
2905             adev->nbio.ras->init_ras_controller_interrupt) {
2906                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2907                 if (r)
2908                         goto release_con;
2909         }
2910
2911         if (adev->nbio.ras &&
2912             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2913                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2914                 if (r)
2915                         goto release_con;
2916         }
2917
2918         amdgpu_ras_query_poison_mode(adev);
2919
2920         /* Get RAS schema for particular SOC */
2921         con->schema = amdgpu_get_ras_schema(adev);
2922
2923         if (amdgpu_ras_fs_init(adev)) {
2924                 r = -EINVAL;
2925                 goto release_con;
2926         }
2927
2928         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2929                  "hardware ability[%x] ras_mask[%x]\n",
2930                  adev->ras_hw_enabled, adev->ras_enabled);
2931
2932         return 0;
2933 release_con:
2934         amdgpu_ras_set_context(adev, NULL);
2935         kfree(con);
2936
2937         return r;
2938 }
2939
2940 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2941 {
2942         if (adev->gmc.xgmi.connected_to_cpu ||
2943             adev->gmc.is_app_apu)
2944                 return 1;
2945         return 0;
2946 }
2947
2948 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2949                                         struct ras_common_if *ras_block)
2950 {
2951         struct ras_query_if info = {
2952                 .head = *ras_block,
2953         };
2954
2955         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2956                 return 0;
2957
2958         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2959                 DRM_WARN("RAS init harvest failure");
2960
2961         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2962                 DRM_WARN("RAS init harvest reset failure");
2963
2964         return 0;
2965 }
2966
2967 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2968 {
2969        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2970
2971        if (!con)
2972                return false;
2973
2974        return con->poison_supported;
2975 }
2976
2977 /* helper function to handle common stuff in ip late init phase */
2978 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2979                          struct ras_common_if *ras_block)
2980 {
2981         struct amdgpu_ras_block_object *ras_obj = NULL;
2982         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2983         struct ras_query_if *query_info;
2984         unsigned long ue_count, ce_count;
2985         int r;
2986
2987         /* disable RAS feature per IP block if it is not supported */
2988         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2989                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2990                 return 0;
2991         }
2992
2993         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2994         if (r) {
2995                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2996                         /* in resume phase, if fail to enable ras,
2997                          * clean up all ras fs nodes, and disable ras */
2998                         goto cleanup;
2999                 } else
3000                         return r;
3001         }
3002
3003         /* check for errors on warm reset edc persisant supported ASIC */
3004         amdgpu_persistent_edc_harvesting(adev, ras_block);
3005
3006         /* in resume phase, no need to create ras fs node */
3007         if (adev->in_suspend || amdgpu_in_reset(adev))
3008                 return 0;
3009
3010         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3011         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
3012             (ras_obj->hw_ops->query_poison_status ||
3013             ras_obj->hw_ops->handle_poison_consumption))) {
3014                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
3015                 if (r)
3016                         goto cleanup;
3017         }
3018
3019         if (ras_obj->hw_ops &&
3020             (ras_obj->hw_ops->query_ras_error_count ||
3021              ras_obj->hw_ops->query_ras_error_status)) {
3022                 r = amdgpu_ras_sysfs_create(adev, ras_block);
3023                 if (r)
3024                         goto interrupt;
3025
3026                 /* Those are the cached values at init.
3027                  */
3028                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
3029                 if (!query_info)
3030                         return -ENOMEM;
3031                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
3032
3033                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
3034                         atomic_set(&con->ras_ce_count, ce_count);
3035                         atomic_set(&con->ras_ue_count, ue_count);
3036                 }
3037
3038                 kfree(query_info);
3039         }
3040
3041         return 0;
3042
3043 interrupt:
3044         if (ras_obj->ras_cb)
3045                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3046 cleanup:
3047         amdgpu_ras_feature_enable(adev, ras_block, 0);
3048         return r;
3049 }
3050
3051 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
3052                          struct ras_common_if *ras_block)
3053 {
3054         return amdgpu_ras_block_late_init(adev, ras_block);
3055 }
3056
3057 /* helper function to remove ras fs node and interrupt handler */
3058 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
3059                           struct ras_common_if *ras_block)
3060 {
3061         struct amdgpu_ras_block_object *ras_obj;
3062         if (!ras_block)
3063                 return;
3064
3065         amdgpu_ras_sysfs_remove(adev, ras_block);
3066
3067         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3068         if (ras_obj->ras_cb)
3069                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3070 }
3071
3072 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
3073                           struct ras_common_if *ras_block)
3074 {
3075         return amdgpu_ras_block_late_fini(adev, ras_block);
3076 }
3077
3078 /* do some init work after IP late init as dependence.
3079  * and it runs in resume/gpu reset/booting up cases.
3080  */
3081 void amdgpu_ras_resume(struct amdgpu_device *adev)
3082 {
3083         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3084         struct ras_manager *obj, *tmp;
3085
3086         if (!adev->ras_enabled || !con) {
3087                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
3088                 amdgpu_release_ras_context(adev);
3089
3090                 return;
3091         }
3092
3093         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
3094                 /* Set up all other IPs which are not implemented. There is a
3095                  * tricky thing that IP's actual ras error type should be
3096                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3097                  * ERROR_NONE make sense anyway.
3098                  */
3099                 amdgpu_ras_enable_all_features(adev, 1);
3100
3101                 /* We enable ras on all hw_supported block, but as boot
3102                  * parameter might disable some of them and one or more IP has
3103                  * not implemented yet. So we disable them on behalf.
3104                  */
3105                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3106                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3107                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3108                                 /* there should be no any reference. */
3109                                 WARN_ON(alive_obj(obj));
3110                         }
3111                 }
3112         }
3113 }
3114
3115 void amdgpu_ras_suspend(struct amdgpu_device *adev)
3116 {
3117         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3118
3119         if (!adev->ras_enabled || !con)
3120                 return;
3121
3122         amdgpu_ras_disable_all_features(adev, 0);
3123         /* Make sure all ras objects are disabled. */
3124         if (con->features)
3125                 amdgpu_ras_disable_all_features(adev, 1);
3126 }
3127
3128 int amdgpu_ras_late_init(struct amdgpu_device *adev)
3129 {
3130         struct amdgpu_ras_block_list *node, *tmp;
3131         struct amdgpu_ras_block_object *obj;
3132         int r;
3133
3134         /* Guest side doesn't need init ras feature */
3135         if (amdgpu_sriov_vf(adev))
3136                 return 0;
3137
3138         /* enable MCA debug on APU device */
3139         amdgpu_ras_set_mca_debug_mode(adev, !!(adev->flags & AMD_IS_APU));
3140
3141         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3142                 if (!node->ras_obj) {
3143                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3144                         continue;
3145                 }
3146
3147                 obj = node->ras_obj;
3148                 if (obj->ras_late_init) {
3149                         r = obj->ras_late_init(adev, &obj->ras_comm);
3150                         if (r) {
3151                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3152                                         obj->ras_comm.name, r);
3153                                 return r;
3154                         }
3155                 } else
3156                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3157         }
3158
3159         return 0;
3160 }
3161
3162 /* do some fini work before IP fini as dependence */
3163 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3164 {
3165         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3166
3167         if (!adev->ras_enabled || !con)
3168                 return 0;
3169
3170
3171         /* Need disable ras on all IPs here before ip [hw/sw]fini */
3172         if (con->features)
3173                 amdgpu_ras_disable_all_features(adev, 0);
3174         amdgpu_ras_recovery_fini(adev);
3175         return 0;
3176 }
3177
3178 int amdgpu_ras_fini(struct amdgpu_device *adev)
3179 {
3180         struct amdgpu_ras_block_list *ras_node, *tmp;
3181         struct amdgpu_ras_block_object *obj = NULL;
3182         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3183
3184         if (!adev->ras_enabled || !con)
3185                 return 0;
3186
3187         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3188                 if (ras_node->ras_obj) {
3189                         obj = ras_node->ras_obj;
3190                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3191                             obj->ras_fini)
3192                                 obj->ras_fini(adev, &obj->ras_comm);
3193                         else
3194                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3195                 }
3196
3197                 /* Clear ras blocks from ras_list and free ras block list node */
3198                 list_del(&ras_node->node);
3199                 kfree(ras_node);
3200         }
3201
3202         amdgpu_ras_fs_fini(adev);
3203         amdgpu_ras_interrupt_remove_all(adev);
3204
3205         WARN(con->features, "Feature mask is not cleared");
3206
3207         if (con->features)
3208                 amdgpu_ras_disable_all_features(adev, 1);
3209
3210         cancel_delayed_work_sync(&con->ras_counte_delay_work);
3211
3212         amdgpu_ras_set_context(adev, NULL);
3213         kfree(con);
3214
3215         return 0;
3216 }
3217
3218 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3219 {
3220         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
3221                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3222
3223                 dev_info(adev->dev, "uncorrectable hardware error"
3224                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
3225
3226                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
3227                 amdgpu_ras_reset_gpu(adev);
3228         }
3229 }
3230
3231 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3232 {
3233         if (adev->asic_type == CHIP_VEGA20 &&
3234             adev->pm.fw_version <= 0x283400) {
3235                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3236                                 amdgpu_ras_intr_triggered();
3237         }
3238
3239         return false;
3240 }
3241
3242 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3243 {
3244         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3245
3246         if (!con)
3247                 return;
3248
3249         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3250                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3251                 amdgpu_ras_set_context(adev, NULL);
3252                 kfree(con);
3253         }
3254 }
3255
3256 #ifdef CONFIG_X86_MCE_AMD
3257 static struct amdgpu_device *find_adev(uint32_t node_id)
3258 {
3259         int i;
3260         struct amdgpu_device *adev = NULL;
3261
3262         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3263                 adev = mce_adev_list.devs[i];
3264
3265                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3266                     adev->gmc.xgmi.physical_node_id == node_id)
3267                         break;
3268                 adev = NULL;
3269         }
3270
3271         return adev;
3272 }
3273
3274 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3275 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3276 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3277 #define GPU_ID_OFFSET           8
3278
3279 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3280                                     unsigned long val, void *data)
3281 {
3282         struct mce *m = (struct mce *)data;
3283         struct amdgpu_device *adev = NULL;
3284         uint32_t gpu_id = 0;
3285         uint32_t umc_inst = 0, ch_inst = 0;
3286
3287         /*
3288          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3289          * and error occurred in DramECC (Extended error code = 0) then only
3290          * process the error, else bail out.
3291          */
3292         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3293                     (XEC(m->status, 0x3f) == 0x0)))
3294                 return NOTIFY_DONE;
3295
3296         /*
3297          * If it is correctable error, return.
3298          */
3299         if (mce_is_correctable(m))
3300                 return NOTIFY_OK;
3301
3302         /*
3303          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3304          */
3305         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3306
3307         adev = find_adev(gpu_id);
3308         if (!adev) {
3309                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3310                                                                 gpu_id);
3311                 return NOTIFY_DONE;
3312         }
3313
3314         /*
3315          * If it is uncorrectable error, then find out UMC instance and
3316          * channel index.
3317          */
3318         umc_inst = GET_UMC_INST(m->ipid);
3319         ch_inst = GET_CHAN_INDEX(m->ipid);
3320
3321         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3322                              umc_inst, ch_inst);
3323
3324         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3325                 return NOTIFY_OK;
3326         else
3327                 return NOTIFY_DONE;
3328 }
3329
3330 static struct notifier_block amdgpu_bad_page_nb = {
3331         .notifier_call  = amdgpu_bad_page_notifier,
3332         .priority       = MCE_PRIO_UC,
3333 };
3334
3335 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3336 {
3337         /*
3338          * Add the adev to the mce_adev_list.
3339          * During mode2 reset, amdgpu device is temporarily
3340          * removed from the mgpu_info list which can cause
3341          * page retirement to fail.
3342          * Use this list instead of mgpu_info to find the amdgpu
3343          * device on which the UMC error was reported.
3344          */
3345         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3346
3347         /*
3348          * Register the x86 notifier only once
3349          * with MCE subsystem.
3350          */
3351         if (notifier_registered == false) {
3352                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3353                 notifier_registered = true;
3354         }
3355 }
3356 #endif
3357
3358 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3359 {
3360         if (!adev)
3361                 return NULL;
3362
3363         return adev->psp.ras_context.ras;
3364 }
3365
3366 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3367 {
3368         if (!adev)
3369                 return -EINVAL;
3370
3371         adev->psp.ras_context.ras = ras_con;
3372         return 0;
3373 }
3374
3375 /* check if ras is supported on block, say, sdma, gfx */
3376 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3377                 unsigned int block)
3378 {
3379         int ret = 0;
3380         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3381
3382         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3383                 return 0;
3384
3385         ret = ras && (adev->ras_enabled & (1 << block));
3386
3387         /* For the special asic with mem ecc enabled but sram ecc
3388          * not enabled, even if the ras block is not supported on
3389          * .ras_enabled, if the asic supports poison mode and the
3390          * ras block has ras configuration, it can be considered
3391          * that the ras block supports ras function.
3392          */
3393         if (!ret &&
3394             (block == AMDGPU_RAS_BLOCK__GFX ||
3395              block == AMDGPU_RAS_BLOCK__SDMA ||
3396              block == AMDGPU_RAS_BLOCK__VCN ||
3397              block == AMDGPU_RAS_BLOCK__JPEG) &&
3398             amdgpu_ras_is_poison_mode_supported(adev) &&
3399             amdgpu_ras_get_ras_block(adev, block, 0))
3400                 ret = 1;
3401
3402         return ret;
3403 }
3404
3405 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3406 {
3407         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3408
3409         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3410                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3411         return 0;
3412 }
3413
3414 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
3415 {
3416         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3417         int ret = 0;
3418
3419         if (con) {
3420                 ret = amdgpu_mca_smu_set_debug_mode(adev, enable);
3421                 if (!ret)
3422                         con->is_mca_debug_mode = enable;
3423         }
3424
3425         return ret;
3426 }
3427
3428 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev)
3429 {
3430         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3431         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3432
3433         if (!con)
3434                 return false;
3435
3436         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3437                 return con->is_mca_debug_mode;
3438         else
3439                 return true;
3440 }
3441
3442 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
3443                                      unsigned int *error_query_mode)
3444 {
3445         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3446         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3447
3448         if (!con) {
3449                 *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY;
3450                 return false;
3451         }
3452
3453         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3454                 *error_query_mode =
3455                         (con->is_mca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY;
3456         else
3457                 *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY;
3458
3459         return true;
3460 }
3461
3462 /* Register each ip ras block into amdgpu ras */
3463 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3464                 struct amdgpu_ras_block_object *ras_block_obj)
3465 {
3466         struct amdgpu_ras_block_list *ras_node;
3467         if (!adev || !ras_block_obj)
3468                 return -EINVAL;
3469
3470         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3471         if (!ras_node)
3472                 return -ENOMEM;
3473
3474         INIT_LIST_HEAD(&ras_node->node);
3475         ras_node->ras_obj = ras_block_obj;
3476         list_add_tail(&ras_node->node, &adev->ras_list);
3477
3478         return 0;
3479 }
3480
3481 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3482 {
3483         if (!err_type_name)
3484                 return;
3485
3486         switch (err_type) {
3487         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3488                 sprintf(err_type_name, "correctable");
3489                 break;
3490         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3491                 sprintf(err_type_name, "uncorrectable");
3492                 break;
3493         default:
3494                 sprintf(err_type_name, "unknown");
3495                 break;
3496         }
3497 }
3498
3499 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3500                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3501                                          uint32_t instance,
3502                                          uint32_t *memory_id)
3503 {
3504         uint32_t err_status_lo_data, err_status_lo_offset;
3505
3506         if (!reg_entry)
3507                 return false;
3508
3509         err_status_lo_offset =
3510                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3511                                             reg_entry->seg_lo, reg_entry->reg_lo);
3512         err_status_lo_data = RREG32(err_status_lo_offset);
3513
3514         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3515             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3516                 return false;
3517
3518         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3519
3520         return true;
3521 }
3522
3523 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3524                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3525                                        uint32_t instance,
3526                                        unsigned long *err_cnt)
3527 {
3528         uint32_t err_status_hi_data, err_status_hi_offset;
3529
3530         if (!reg_entry)
3531                 return false;
3532
3533         err_status_hi_offset =
3534                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3535                                             reg_entry->seg_hi, reg_entry->reg_hi);
3536         err_status_hi_data = RREG32(err_status_hi_offset);
3537
3538         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3539             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3540                 /* keep the check here in case we need to refer to the result later */
3541                 dev_dbg(adev->dev, "Invalid err_info field\n");
3542
3543         /* read err count */
3544         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3545
3546         return true;
3547 }
3548
3549 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3550                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3551                                            uint32_t reg_list_size,
3552                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3553                                            uint32_t mem_list_size,
3554                                            uint32_t instance,
3555                                            uint32_t err_type,
3556                                            unsigned long *err_count)
3557 {
3558         uint32_t memory_id;
3559         unsigned long err_cnt;
3560         char err_type_name[16];
3561         uint32_t i, j;
3562
3563         for (i = 0; i < reg_list_size; i++) {
3564                 /* query memory_id from err_status_lo */
3565                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3566                                                          instance, &memory_id))
3567                         continue;
3568
3569                 /* query err_cnt from err_status_hi */
3570                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3571                                                        instance, &err_cnt) ||
3572                     !err_cnt)
3573                         continue;
3574
3575                 *err_count += err_cnt;
3576
3577                 /* log the errors */
3578                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3579                 if (!mem_list) {
3580                         /* memory_list is not supported */
3581                         dev_info(adev->dev,
3582                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3583                                  err_cnt, err_type_name,
3584                                  reg_list[i].block_name,
3585                                  instance, memory_id);
3586                 } else {
3587                         for (j = 0; j < mem_list_size; j++) {
3588                                 if (memory_id == mem_list[j].memory_id) {
3589                                         dev_info(adev->dev,
3590                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3591                                                  err_cnt, err_type_name,
3592                                                  reg_list[i].block_name,
3593                                                  instance, mem_list[j].name);
3594                                         break;
3595                                 }
3596                         }
3597                 }
3598         }
3599 }
3600
3601 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3602                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3603                                            uint32_t reg_list_size,
3604                                            uint32_t instance)
3605 {
3606         uint32_t err_status_lo_offset, err_status_hi_offset;
3607         uint32_t i;
3608
3609         for (i = 0; i < reg_list_size; i++) {
3610                 err_status_lo_offset =
3611                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3612                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3613                 err_status_hi_offset =
3614                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3615                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3616                 WREG32(err_status_lo_offset, 0);
3617                 WREG32(err_status_hi_offset, 0);
3618         }
3619 }
3620
3621 int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
3622 {
3623         memset(err_data, 0, sizeof(*err_data));
3624
3625         INIT_LIST_HEAD(&err_data->err_node_list);
3626
3627         return 0;
3628 }
3629
3630 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
3631 {
3632         if (!err_node)
3633                 return;
3634
3635         list_del(&err_node->node);
3636         kvfree(err_node);
3637 }
3638
3639 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
3640 {
3641         struct ras_err_node *err_node, *tmp;
3642
3643         list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
3644                 amdgpu_ras_error_node_release(err_node);
3645 }
3646
3647 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
3648                                                              struct amdgpu_smuio_mcm_config_info *mcm_info)
3649 {
3650         struct ras_err_node *err_node;
3651         struct amdgpu_smuio_mcm_config_info *ref_id;
3652
3653         if (!err_data || !mcm_info)
3654                 return NULL;
3655
3656         for_each_ras_error(err_node, err_data) {
3657                 ref_id = &err_node->err_info.mcm_info;
3658
3659                 if (mcm_info->socket_id == ref_id->socket_id &&
3660                     mcm_info->die_id == ref_id->die_id)
3661                         return err_node;
3662         }
3663
3664         return NULL;
3665 }
3666
3667 static struct ras_err_node *amdgpu_ras_error_node_new(void)
3668 {
3669         struct ras_err_node *err_node;
3670
3671         err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
3672         if (!err_node)
3673                 return NULL;
3674
3675         INIT_LIST_HEAD(&err_node->node);
3676
3677         return err_node;
3678 }
3679
3680 static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)
3681 {
3682         struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);
3683         struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);
3684         struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info;
3685         struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info;
3686
3687         if (unlikely(infoa->socket_id != infob->socket_id))
3688                 return infoa->socket_id - infob->socket_id;
3689         else
3690                 return infoa->die_id - infob->die_id;
3691
3692         return 0;
3693 }
3694
3695 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
3696                                 struct amdgpu_smuio_mcm_config_info *mcm_info,
3697                                 struct ras_err_addr *err_addr)
3698 {
3699         struct ras_err_node *err_node;
3700
3701         err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
3702         if (err_node)
3703                 return &err_node->err_info;
3704
3705         err_node = amdgpu_ras_error_node_new();
3706         if (!err_node)
3707                 return NULL;
3708
3709         memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
3710
3711         if (err_addr)
3712                 memcpy(&err_node->err_info.err_addr, err_addr, sizeof(*err_addr));
3713
3714         err_data->err_list_count++;
3715         list_add_tail(&err_node->node, &err_data->err_node_list);
3716         list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp);
3717
3718         return &err_node->err_info;
3719 }
3720
3721 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
3722                 struct amdgpu_smuio_mcm_config_info *mcm_info,
3723                 struct ras_err_addr *err_addr, u64 count)
3724 {
3725         struct ras_err_info *err_info;
3726
3727         if (!err_data || !mcm_info)
3728                 return -EINVAL;
3729
3730         if (!count)
3731                 return 0;
3732
3733         err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);
3734         if (!err_info)
3735                 return -EINVAL;
3736
3737         err_info->ue_count += count;
3738         err_data->ue_count += count;
3739
3740         return 0;
3741 }
3742
3743 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
3744                 struct amdgpu_smuio_mcm_config_info *mcm_info,
3745                 struct ras_err_addr *err_addr, u64 count)
3746 {
3747         struct ras_err_info *err_info;
3748
3749         if (!err_data || !mcm_info)
3750                 return -EINVAL;
3751
3752         if (!count)
3753                 return 0;
3754
3755         err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);
3756         if (!err_info)
3757                 return -EINVAL;
3758
3759         err_info->ce_count += count;
3760         err_data->ce_count += count;
3761
3762         return 0;
3763 }