drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/io.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include <drm/display/drm_dp_helper.h>
  20 #include <drm/display/drm_scdc_helper.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_debugfs.h>
  23 #include <drm/drm_eld.h>
  24 #include <drm/drm_file.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drm_simple_kms_helper.h>
  27
  28 #include "dc.h"
  29 #include "dp.h"
  30 #include "drm.h"
  31 #include "hda.h"
  32 #include "sor.h"
  33 #include "trace.h"
  34
  35 #define SOR_REKEY 0x38
  36
  37 struct tegra_sor_hdmi_settings {
  38         unsigned long frequency;
  39
  40         u8 vcocap;
  41         u8 filter;
  42         u8 ichpmp;
  43         u8 loadadj;
  44         u8 tmds_termadj;
  45         u8 tx_pu_value;
  46         u8 bg_temp_coef;
  47         u8 bg_vref_level;
  48         u8 avdd10_level;
  49         u8 avdd14_level;
  50         u8 sparepll;
  51
  52         u8 drive_current[4];
  53         u8 preemphasis[4];
  54 };
  55
  56 #if 1
  57 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  58         {
  59                 .frequency = 54000000,
  60                 .vcocap = 0x0,
  61                 .filter = 0x0,
  62                 .ichpmp = 0x1,
  63                 .loadadj = 0x3,
  64                 .tmds_termadj = 0x9,
  65                 .tx_pu_value = 0x10,
  66                 .bg_temp_coef = 0x3,
  67                 .bg_vref_level = 0x8,
  68                 .avdd10_level = 0x4,
  69                 .avdd14_level = 0x4,
  70                 .sparepll = 0x0,
  71                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  72                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  73         }, {
  74                 .frequency = 75000000,
  75                 .vcocap = 0x3,
  76                 .filter = 0x0,
  77                 .ichpmp = 0x1,
  78                 .loadadj = 0x3,
  79                 .tmds_termadj = 0x9,
  80                 .tx_pu_value = 0x40,
  81                 .bg_temp_coef = 0x3,
  82                 .bg_vref_level = 0x8,
  83                 .avdd10_level = 0x4,
  84                 .avdd14_level = 0x4,
  85                 .sparepll = 0x0,
  86                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  87                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  88         }, {
  89                 .frequency = 150000000,
  90                 .vcocap = 0x3,
  91                 .filter = 0x0,
  92                 .ichpmp = 0x1,
  93                 .loadadj = 0x3,
  94                 .tmds_termadj = 0x9,
  95                 .tx_pu_value = 0x66,
  96                 .bg_temp_coef = 0x3,
  97                 .bg_vref_level = 0x8,
  98                 .avdd10_level = 0x4,
  99                 .avdd14_level = 0x4,
 100                 .sparepll = 0x0,
 101                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 102                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 103         }, {
 104                 .frequency = 300000000,
 105                 .vcocap = 0x3,
 106                 .filter = 0x0,
 107                 .ichpmp = 0x1,
 108                 .loadadj = 0x3,
 109                 .tmds_termadj = 0x9,
 110                 .tx_pu_value = 0x66,
 111                 .bg_temp_coef = 0x3,
 112                 .bg_vref_level = 0xa,
 113                 .avdd10_level = 0x4,
 114                 .avdd14_level = 0x4,
 115                 .sparepll = 0x0,
 116                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 117                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 118         }, {
 119                 .frequency = 600000000,
 120                 .vcocap = 0x3,
 121                 .filter = 0x0,
 122                 .ichpmp = 0x1,
 123                 .loadadj = 0x3,
 124                 .tmds_termadj = 0x9,
 125                 .tx_pu_value = 0x66,
 126                 .bg_temp_coef = 0x3,
 127                 .bg_vref_level = 0x8,
 128                 .avdd10_level = 0x4,
 129                 .avdd14_level = 0x4,
 130                 .sparepll = 0x0,
 131                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 132                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 133         },
 134 };
 135 #else
 136 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 137         {
 138                 .frequency = 75000000,
 139                 .vcocap = 0x3,
 140                 .filter = 0x0,
 141                 .ichpmp = 0x1,
 142                 .loadadj = 0x3,
 143                 .tmds_termadj = 0x9,
 144                 .tx_pu_value = 0x40,
 145                 .bg_temp_coef = 0x3,
 146                 .bg_vref_level = 0x8,
 147                 .avdd10_level = 0x4,
 148                 .avdd14_level = 0x4,
 149                 .sparepll = 0x0,
 150                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 151                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 152         }, {
 153                 .frequency = 150000000,
 154                 .vcocap = 0x3,
 155                 .filter = 0x0,
 156                 .ichpmp = 0x1,
 157                 .loadadj = 0x3,
 158                 .tmds_termadj = 0x9,
 159                 .tx_pu_value = 0x66,
 160                 .bg_temp_coef = 0x3,
 161                 .bg_vref_level = 0x8,
 162                 .avdd10_level = 0x4,
 163                 .avdd14_level = 0x4,
 164                 .sparepll = 0x0,
 165                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 166                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 167         }, {
 168                 .frequency = 300000000,
 169                 .vcocap = 0x3,
 170                 .filter = 0x0,
 171                 .ichpmp = 0x6,
 172                 .loadadj = 0x3,
 173                 .tmds_termadj = 0x9,
 174                 .tx_pu_value = 0x66,
 175                 .bg_temp_coef = 0x3,
 176                 .bg_vref_level = 0xf,
 177                 .avdd10_level = 0x4,
 178                 .avdd14_level = 0x4,
 179                 .sparepll = 0x0,
 180                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 181                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 182         }, {
 183                 .frequency = 600000000,
 184                 .vcocap = 0x3,
 185                 .filter = 0x0,
 186                 .ichpmp = 0xa,
 187                 .loadadj = 0x3,
 188                 .tmds_termadj = 0xb,
 189                 .tx_pu_value = 0x66,
 190                 .bg_temp_coef = 0x3,
 191                 .bg_vref_level = 0xe,
 192                 .avdd10_level = 0x4,
 193                 .avdd14_level = 0x4,
 194                 .sparepll = 0x0,
 195                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 196                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 197         },
 198 };
 199 #endif
 200
 201 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 202         {
 203                 .frequency = 54000000,
 204                 .vcocap = 0,
 205                 .filter = 5,
 206                 .ichpmp = 5,
 207                 .loadadj = 3,
 208                 .tmds_termadj = 0xf,
 209                 .tx_pu_value = 0,
 210                 .bg_temp_coef = 3,
 211                 .bg_vref_level = 8,
 212                 .avdd10_level = 4,
 213                 .avdd14_level = 4,
 214                 .sparepll = 0x54,
 215                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 216                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 217         }, {
 218                 .frequency = 75000000,
 219                 .vcocap = 1,
 220                 .filter = 5,
 221                 .ichpmp = 5,
 222                 .loadadj = 3,
 223                 .tmds_termadj = 0xf,
 224                 .tx_pu_value = 0,
 225                 .bg_temp_coef = 3,
 226                 .bg_vref_level = 8,
 227                 .avdd10_level = 4,
 228                 .avdd14_level = 4,
 229                 .sparepll = 0x44,
 230                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 231                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 232         }, {
 233                 .frequency = 150000000,
 234                 .vcocap = 3,
 235                 .filter = 5,
 236                 .ichpmp = 5,
 237                 .loadadj = 3,
 238                 .tmds_termadj = 15,
 239                 .tx_pu_value = 0x66 /* 0 */,
 240                 .bg_temp_coef = 3,
 241                 .bg_vref_level = 8,
 242                 .avdd10_level = 4,
 243                 .avdd14_level = 4,
 244                 .sparepll = 0x00, /* 0x34 */
 245                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 246                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 247         }, {
 248                 .frequency = 300000000,
 249                 .vcocap = 3,
 250                 .filter = 5,
 251                 .ichpmp = 5,
 252                 .loadadj = 3,
 253                 .tmds_termadj = 15,
 254                 .tx_pu_value = 64,
 255                 .bg_temp_coef = 3,
 256                 .bg_vref_level = 8,
 257                 .avdd10_level = 4,
 258                 .avdd14_level = 4,
 259                 .sparepll = 0x34,
 260                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 261                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 262         }, {
 263                 .frequency = 600000000,
 264                 .vcocap = 3,
 265                 .filter = 5,
 266                 .ichpmp = 5,
 267                 .loadadj = 3,
 268                 .tmds_termadj = 12,
 269                 .tx_pu_value = 96,
 270                 .bg_temp_coef = 3,
 271                 .bg_vref_level = 8,
 272                 .avdd10_level = 4,
 273                 .avdd14_level = 4,
 274                 .sparepll = 0x34,
 275                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 276                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 277         }
 278 };
 279
 280 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 281         {
 282                 .frequency = 54000000,
 283                 .vcocap = 0,
 284                 .filter = 5,
 285                 .ichpmp = 5,
 286                 .loadadj = 3,
 287                 .tmds_termadj = 0xf,
 288                 .tx_pu_value = 0,
 289                 .bg_temp_coef = 3,
 290                 .bg_vref_level = 8,
 291                 .avdd10_level = 4,
 292                 .avdd14_level = 4,
 293                 .sparepll = 0x54,
 294                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 295                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 296         }, {
 297                 .frequency = 75000000,
 298                 .vcocap = 1,
 299                 .filter = 5,
 300                 .ichpmp = 5,
 301                 .loadadj = 3,
 302                 .tmds_termadj = 0xf,
 303                 .tx_pu_value = 0,
 304                 .bg_temp_coef = 3,
 305                 .bg_vref_level = 8,
 306                 .avdd10_level = 4,
 307                 .avdd14_level = 4,
 308                 .sparepll = 0x44,
 309                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 310                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 311         }, {
 312                 .frequency = 150000000,
 313                 .vcocap = 3,
 314                 .filter = 5,
 315                 .ichpmp = 5,
 316                 .loadadj = 3,
 317                 .tmds_termadj = 15,
 318                 .tx_pu_value = 0x66 /* 0 */,
 319                 .bg_temp_coef = 3,
 320                 .bg_vref_level = 8,
 321                 .avdd10_level = 4,
 322                 .avdd14_level = 4,
 323                 .sparepll = 0x00, /* 0x34 */
 324                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 325                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 326         }, {
 327                 .frequency = 300000000,
 328                 .vcocap = 3,
 329                 .filter = 5,
 330                 .ichpmp = 5,
 331                 .loadadj = 3,
 332                 .tmds_termadj = 15,
 333                 .tx_pu_value = 64,
 334                 .bg_temp_coef = 3,
 335                 .bg_vref_level = 8,
 336                 .avdd10_level = 4,
 337                 .avdd14_level = 4,
 338                 .sparepll = 0x34,
 339                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 340                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 341         }, {
 342                 .frequency = 600000000,
 343                 .vcocap = 3,
 344                 .filter = 5,
 345                 .ichpmp = 5,
 346                 .loadadj = 3,
 347                 .tmds_termadj = 12,
 348                 .tx_pu_value = 96,
 349                 .bg_temp_coef = 3,
 350                 .bg_vref_level = 8,
 351                 .avdd10_level = 4,
 352                 .avdd14_level = 4,
 353                 .sparepll = 0x34,
 354                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 355                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 356         }
 357 };
 358
 359 struct tegra_sor_regs {
 360         unsigned int head_state0;
 361         unsigned int head_state1;
 362         unsigned int head_state2;
 363         unsigned int head_state3;
 364         unsigned int head_state4;
 365         unsigned int head_state5;
 366         unsigned int pll0;
 367         unsigned int pll1;
 368         unsigned int pll2;
 369         unsigned int pll3;
 370         unsigned int dp_padctl0;
 371         unsigned int dp_padctl2;
 372 };
 373
 374 struct tegra_sor_soc {
 375         bool supports_lvds;
 376         bool supports_hdmi;
 377         bool supports_dp;
 378         bool supports_audio;
 379         bool supports_hdcp;
 380
 381         const struct tegra_sor_regs *regs;
 382         bool has_nvdisplay;
 383
 384         const struct tegra_sor_hdmi_settings *settings;
 385         unsigned int num_settings;
 386
 387         const u8 *xbar_cfg;
 388         const u8 *lane_map;
 389
 390         const u8 (*voltage_swing)[4][4];
 391         const u8 (*pre_emphasis)[4][4];
 392         const u8 (*post_cursor)[4][4];
 393         const u8 (*tx_pu)[4][4];
 394 };
 395
 396 struct tegra_sor;
 397
 398 struct tegra_sor_ops {
 399         const char *name;
 400         int (*probe)(struct tegra_sor *sor);
 401         void (*audio_enable)(struct tegra_sor *sor);
 402         void (*audio_disable)(struct tegra_sor *sor);
 403 };
 404
 405 struct tegra_sor {
 406         struct host1x_client client;
 407         struct tegra_output output;
 408         struct device *dev;
 409
 410         const struct tegra_sor_soc *soc;
 411         void __iomem *regs;
 412         unsigned int index;
 413         unsigned int irq;
 414
 415         struct reset_control *rst;
 416         struct clk *clk_parent;
 417         struct clk *clk_safe;
 418         struct clk *clk_out;
 419         struct clk *clk_pad;
 420         struct clk *clk_dp;
 421         struct clk *clk;
 422
 423         u8 xbar_cfg[5];
 424
 425         struct drm_dp_link link;
 426         struct drm_dp_aux *aux;
 427
 428         struct drm_info_list *debugfs_files;
 429
 430         const struct tegra_sor_ops *ops;
 431         enum tegra_io_pad pad;
 432
 433         /* for HDMI 2.0 */
 434         struct tegra_sor_hdmi_settings *settings;
 435         unsigned int num_settings;
 436
 437         struct regulator *avdd_io_supply;
 438         struct regulator *vdd_pll_supply;
 439         struct regulator *hdmi_supply;
 440
 441         struct delayed_work scdc;
 442         bool scdc_enabled;
 443
 444         struct tegra_hda_format format;
 445 };
 446
 447 struct tegra_sor_state {
 448         struct drm_connector_state base;
 449
 450         unsigned int link_speed;
 451         unsigned long pclk;
 452         unsigned int bpc;
 453 };
 454
 455 static inline struct tegra_sor_state *
 456 to_sor_state(struct drm_connector_state *state)
 457 {
 458         return container_of(state, struct tegra_sor_state, base);
 459 }
 460
 461 struct tegra_sor_config {
 462         u32 bits_per_pixel;
 463
 464         u32 active_polarity;
 465         u32 active_count;
 466         u32 tu_size;
 467         u32 active_frac;
 468         u32 watermark;
 469
 470         u32 hblank_symbols;
 471         u32 vblank_symbols;
 472 };
 473
 474 static inline struct tegra_sor *
 475 host1x_client_to_sor(struct host1x_client *client)
 476 {
 477         return container_of(client, struct tegra_sor, client);
 478 }
 479
 480 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 481 {
 482         return container_of(output, struct tegra_sor, output);
 483 }
 484
 485 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 486 {
 487         u32 value = readl(sor->regs + (offset << 2));
 488
 489         trace_sor_readl(sor->dev, offset, value);
 490
 491         return value;
 492 }
 493
 494 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 495                                     unsigned int offset)
 496 {
 497         trace_sor_writel(sor->dev, offset, value);
 498         writel(value, sor->regs + (offset << 2));
 499 }
 500
 501 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 502 {
 503         int err;
 504
 505         clk_disable_unprepare(sor->clk);
 506
 507         err = clk_set_parent(sor->clk_out, parent);
 508         if (err < 0)
 509                 return err;
 510
 511         err = clk_prepare_enable(sor->clk);
 512         if (err < 0)
 513                 return err;
 514
 515         return 0;
 516 }
 517
 518 struct tegra_clk_sor_pad {
 519         struct clk_hw hw;
 520         struct tegra_sor *sor;
 521 };
 522
 523 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 524 {
 525         return container_of(hw, struct tegra_clk_sor_pad, hw);
 526 }
 527
 528 static const char * const tegra_clk_sor_pad_parents[2][2] = {
 529         { "pll_d_out0", "pll_dp" },
 530         { "pll_d2_out0", "pll_dp" },
 531 };
 532
 533 /*
 534  * Implementing ->set_parent() here isn't really required because the parent
 535  * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
 536  * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
 537  * Tegra186 and later SoC generations where the BPMP implements this clock
 538  * and doesn't expose the mux via the common clock framework.
 539  */
 540
 541 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 542 {
 543         struct tegra_clk_sor_pad *pad = to_pad(hw);
 544         struct tegra_sor *sor = pad->sor;
 545         u32 value;
 546
 547         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 548         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 549
 550         switch (index) {
 551         case 0:
 552                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 553                 break;
 554
 555         case 1:
 556                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 557                 break;
 558         }
 559
 560         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 561
 562         return 0;
 563 }
 564
 565 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 566 {
 567         struct tegra_clk_sor_pad *pad = to_pad(hw);
 568         struct tegra_sor *sor = pad->sor;
 569         u8 parent = U8_MAX;
 570         u32 value;
 571
 572         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 573
 574         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 575         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 576         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 577                 parent = 0;
 578                 break;
 579
 580         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 581         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 582                 parent = 1;
 583                 break;
 584         }
 585
 586         return parent;
 587 }
 588
 589 static const struct clk_ops tegra_clk_sor_pad_ops = {
 590         .determine_rate = clk_hw_determine_rate_no_reparent,
 591         .set_parent = tegra_clk_sor_pad_set_parent,
 592         .get_parent = tegra_clk_sor_pad_get_parent,
 593 };
 594
 595 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 596                                               const char *name)
 597 {
 598         struct tegra_clk_sor_pad *pad;
 599         struct clk_init_data init;
 600         struct clk *clk;
 601
 602         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 603         if (!pad)
 604                 return ERR_PTR(-ENOMEM);
 605
 606         pad->sor = sor;
 607
 608         init.name = name;
 609         init.flags = 0;
 610         init.parent_names = tegra_clk_sor_pad_parents[sor->index];
 611         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
 612         init.ops = &tegra_clk_sor_pad_ops;
 613
 614         pad->hw.init = &init;
 615
 616         clk = devm_clk_register(sor->dev, &pad->hw);
 617
 618         return clk;
 619 }
 620
 621 static void tegra_sor_filter_rates(struct tegra_sor *sor)
 622 {
 623         struct drm_dp_link *link = &sor->link;
 624         unsigned int i;
 625
 626         /* Tegra only supports RBR, HBR and HBR2 */
 627         for (i = 0; i < link->num_rates; i++) {
 628                 switch (link->rates[i]) {
 629                 case 1620000:
 630                 case 2700000:
 631                 case 5400000:
 632                         break;
 633
 634                 default:
 635                         DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
 636                                       link->rates[i]);
 637                         link->rates[i] = 0;
 638                         break;
 639                 }
 640         }
 641
 642         drm_dp_link_update_rates(link);
 643 }
 644
 645 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
 646 {
 647         unsigned long timeout;
 648         u32 value;
 649
 650         /*
 651          * Clear or set the PD_TXD bit corresponding to each lane, depending
 652          * on whether it is used or not.
 653          */
 654         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 655
 656         if (lanes <= 2)
 657                 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 658                            SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
 659         else
 660                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 661                          SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
 662
 663         if (lanes <= 1)
 664                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 665         else
 666                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 667
 668         if (lanes == 0)
 669                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 670         else
 671                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 672
 673         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 674
 675         /* start lane sequencer */
 676         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 677                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 678         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 679
 680         timeout = jiffies + msecs_to_jiffies(250);
 681
 682         while (time_before(jiffies, timeout)) {
 683                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 684                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 685                         break;
 686
 687                 usleep_range(250, 1000);
 688         }
 689
 690         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 691                 return -ETIMEDOUT;
 692
 693         return 0;
 694 }
 695
 696 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
 697 {
 698         unsigned long timeout;
 699         u32 value;
 700
 701         /* power down all lanes */
 702         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 703         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 704                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 705         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 706
 707         /* start lane sequencer */
 708         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 709                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 710         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 711
 712         timeout = jiffies + msecs_to_jiffies(250);
 713
 714         while (time_before(jiffies, timeout)) {
 715                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 716                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 717                         break;
 718
 719                 usleep_range(25, 100);
 720         }
 721
 722         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 723                 return -ETIMEDOUT;
 724
 725         return 0;
 726 }
 727
 728 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
 729 {
 730         u32 value;
 731
 732         /* pre-charge all used lanes */
 733         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 734
 735         if (lanes <= 2)
 736                 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 737                            SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
 738         else
 739                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 740                          SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
 741
 742         if (lanes <= 1)
 743                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 744         else
 745                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 746
 747         if (lanes == 0)
 748                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 749         else
 750                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 751
 752         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 753
 754         usleep_range(15, 100);
 755
 756         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 757         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 758                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 759         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 760 }
 761
 762 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 763 {
 764         u32 mask = 0x08, adj = 0, value;
 765
 766         /* enable pad calibration logic */
 767         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 768         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 769         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 770
 771         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 772         value |= SOR_PLL1_TMDS_TERM;
 773         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 774
 775         while (mask) {
 776                 adj |= mask;
 777
 778                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 779                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 780                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 781                 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 782
 783                 usleep_range(100, 200);
 784
 785                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 786                 if (value & SOR_PLL1_TERM_COMPOUT)
 787                         adj &= ~mask;
 788
 789                 mask >>= 1;
 790         }
 791
 792         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 793         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 794         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 795         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 796
 797         /* disable pad calibration logic */
 798         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 799         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 800         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 801 }
 802
 803 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
 804 {
 805         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 806         u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
 807         const struct tegra_sor_soc *soc = sor->soc;
 808         u32 pattern = 0, tx_pu = 0, value;
 809         unsigned int i;
 810
 811         for (value = 0, i = 0; i < link->lanes; i++) {
 812                 u8 vs = link->train.request.voltage_swing[i];
 813                 u8 pe = link->train.request.pre_emphasis[i];
 814                 u8 pc = link->train.request.post_cursor[i];
 815                 u8 shift = sor->soc->lane_map[i] << 3;
 816
 817                 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
 818                 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
 819                 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
 820
 821                 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
 822                         tx_pu = sor->soc->tx_pu[pc][vs][pe];
 823
 824                 switch (link->train.pattern) {
 825                 case DP_TRAINING_PATTERN_DISABLE:
 826                         value = SOR_DP_TPG_SCRAMBLER_GALIOS |
 827                                 SOR_DP_TPG_PATTERN_NONE;
 828                         break;
 829
 830                 case DP_TRAINING_PATTERN_1:
 831                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 832                                 SOR_DP_TPG_PATTERN_TRAIN1;
 833                         break;
 834
 835                 case DP_TRAINING_PATTERN_2:
 836                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 837                                 SOR_DP_TPG_PATTERN_TRAIN2;
 838                         break;
 839
 840                 case DP_TRAINING_PATTERN_3:
 841                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 842                                 SOR_DP_TPG_PATTERN_TRAIN3;
 843                         break;
 844
 845                 default:
 846                         return -EINVAL;
 847                 }
 848
 849                 if (link->caps.channel_coding)
 850                         value |= SOR_DP_TPG_CHANNEL_CODING;
 851
 852                 pattern = pattern << 8 | value;
 853         }
 854
 855         tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
 856         tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
 857
 858         if (link->caps.tps3_supported)
 859                 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
 860
 861         tegra_sor_writel(sor, pattern, SOR_DP_TPG);
 862
 863         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 864         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 865         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 866         value |= SOR_DP_PADCTL_TX_PU(tx_pu);
 867         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 868
 869         usleep_range(20, 100);
 870
 871         return 0;
 872 }
 873
 874 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
 875 {
 876         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 877         unsigned int rate, lanes;
 878         u32 value;
 879         int err;
 880
 881         rate = drm_dp_link_rate_to_bw_code(link->rate);
 882         lanes = link->lanes;
 883
 884         /* configure link speed and lane count */
 885         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 886         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 887         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 888         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 889
 890         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 891         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 892         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 893
 894         if (link->caps.enhanced_framing)
 895                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 896
 897         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 898
 899         usleep_range(400, 1000);
 900
 901         /* configure load pulse position adjustment */
 902         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 903         value &= ~SOR_PLL1_LOADADJ_MASK;
 904
 905         switch (rate) {
 906         case DP_LINK_BW_1_62:
 907                 value |= SOR_PLL1_LOADADJ(0x3);
 908                 break;
 909
 910         case DP_LINK_BW_2_7:
 911                 value |= SOR_PLL1_LOADADJ(0x4);
 912                 break;
 913
 914         case DP_LINK_BW_5_4:
 915                 value |= SOR_PLL1_LOADADJ(0x6);
 916                 break;
 917         }
 918
 919         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 920
 921         /* use alternate scrambler reset for eDP */
 922         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 923
 924         if (link->edp == 0)
 925                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 926         else
 927                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
 928
 929         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 930
 931         err = tegra_sor_power_down_lanes(sor);
 932         if (err < 0) {
 933                 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
 934                 return err;
 935         }
 936
 937         /* power up and pre-charge lanes */
 938         err = tegra_sor_power_up_lanes(sor, lanes);
 939         if (err < 0) {
 940                 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
 941                         lanes, (lanes != 1) ? "s" : "", err);
 942                 return err;
 943         }
 944
 945         tegra_sor_dp_precharge(sor, lanes);
 946
 947         return 0;
 948 }
 949
 950 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
 951         .apply_training = tegra_sor_dp_link_apply_training,
 952         .configure = tegra_sor_dp_link_configure,
 953 };
 954
 955 static void tegra_sor_super_update(struct tegra_sor *sor)
 956 {
 957         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 958         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 959         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 960 }
 961
 962 static void tegra_sor_update(struct tegra_sor *sor)
 963 {
 964         tegra_sor_writel(sor, 0, SOR_STATE0);
 965         tegra_sor_writel(sor, 1, SOR_STATE0);
 966         tegra_sor_writel(sor, 0, SOR_STATE0);
 967 }
 968
 969 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 970 {
 971         u32 value;
 972
 973         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 974         value &= ~SOR_PWM_DIV_MASK;
 975         value |= 0x400; /* period */
 976         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 977
 978         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 979         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 980         value |= 0x400; /* duty cycle */
 981         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 982         value |= SOR_PWM_CTL_TRIGGER;
 983         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 984
 985         timeout = jiffies + msecs_to_jiffies(timeout);
 986
 987         while (time_before(jiffies, timeout)) {
 988                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 989                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 990                         return 0;
 991
 992                 usleep_range(25, 100);
 993         }
 994
 995         return -ETIMEDOUT;
 996 }
 997
 998 static int tegra_sor_attach(struct tegra_sor *sor)
 999 {
1000         unsigned long value, timeout;
1001
1002         /* wake up in normal mode */
1003         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1004         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1005         value |= SOR_SUPER_STATE_MODE_NORMAL;
1006         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1007         tegra_sor_super_update(sor);
1008
1009         /* attach */
1010         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1011         value |= SOR_SUPER_STATE_ATTACHED;
1012         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1013         tegra_sor_super_update(sor);
1014
1015         timeout = jiffies + msecs_to_jiffies(250);
1016
1017         while (time_before(jiffies, timeout)) {
1018                 value = tegra_sor_readl(sor, SOR_TEST);
1019                 if ((value & SOR_TEST_ATTACHED) != 0)
1020                         return 0;
1021
1022                 usleep_range(25, 100);
1023         }
1024
1025         return -ETIMEDOUT;
1026 }
1027
1028 static int tegra_sor_wakeup(struct tegra_sor *sor)
1029 {
1030         unsigned long value, timeout;
1031
1032         timeout = jiffies + msecs_to_jiffies(250);
1033
1034         /* wait for head to wake up */
1035         while (time_before(jiffies, timeout)) {
1036                 value = tegra_sor_readl(sor, SOR_TEST);
1037                 value &= SOR_TEST_HEAD_MODE_MASK;
1038
1039                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1040                         return 0;
1041
1042                 usleep_range(25, 100);
1043         }
1044
1045         return -ETIMEDOUT;
1046 }
1047
1048 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1049 {
1050         u32 value;
1051
1052         value = tegra_sor_readl(sor, SOR_PWR);
1053         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1054         tegra_sor_writel(sor, value, SOR_PWR);
1055
1056         timeout = jiffies + msecs_to_jiffies(timeout);
1057
1058         while (time_before(jiffies, timeout)) {
1059                 value = tegra_sor_readl(sor, SOR_PWR);
1060                 if ((value & SOR_PWR_TRIGGER) == 0)
1061                         return 0;
1062
1063                 usleep_range(25, 100);
1064         }
1065
1066         return -ETIMEDOUT;
1067 }
1068
1069 struct tegra_sor_params {
1070         /* number of link clocks per line */
1071         unsigned int num_clocks;
1072         /* ratio between input and output */
1073         u64 ratio;
1074         /* precision factor */
1075         u64 precision;
1076
1077         unsigned int active_polarity;
1078         unsigned int active_count;
1079         unsigned int active_frac;
1080         unsigned int tu_size;
1081         unsigned int error;
1082 };
1083
1084 static int tegra_sor_compute_params(struct tegra_sor *sor,
1085                                     struct tegra_sor_params *params,
1086                                     unsigned int tu_size)
1087 {
1088         u64 active_sym, active_count, frac, approx;
1089         u32 active_polarity, active_frac = 0;
1090         const u64 f = params->precision;
1091         s64 error;
1092
1093         active_sym = params->ratio * tu_size;
1094         active_count = div_u64(active_sym, f) * f;
1095         frac = active_sym - active_count;
1096
1097         /* fraction < 0.5 */
1098         if (frac >= (f / 2)) {
1099                 active_polarity = 1;
1100                 frac = f - frac;
1101         } else {
1102                 active_polarity = 0;
1103         }
1104
1105         if (frac != 0) {
1106                 frac = div_u64(f * f,  frac); /* 1/fraction */
1107                 if (frac <= (15 * f)) {
1108                         active_frac = div_u64(frac, f);
1109
1110                         /* round up */
1111                         if (active_polarity)
1112                                 active_frac++;
1113                 } else {
1114                         active_frac = active_polarity ? 1 : 15;
1115                 }
1116         }
1117
1118         if (active_frac == 1)
1119                 active_polarity = 0;
1120
1121         if (active_polarity == 1) {
1122                 if (active_frac) {
1123                         approx = active_count + (active_frac * (f - 1)) * f;
1124                         approx = div_u64(approx, active_frac * f);
1125                 } else {
1126                         approx = active_count + f;
1127                 }
1128         } else {
1129                 if (active_frac)
1130                         approx = active_count + div_u64(f, active_frac);
1131                 else
1132                         approx = active_count;
1133         }
1134
1135         error = div_s64(active_sym - approx, tu_size);
1136         error *= params->num_clocks;
1137
1138         if (error <= 0 && abs(error) < params->error) {
1139                 params->active_count = div_u64(active_count, f);
1140                 params->active_polarity = active_polarity;
1141                 params->active_frac = active_frac;
1142                 params->error = abs(error);
1143                 params->tu_size = tu_size;
1144
1145                 if (error == 0)
1146                         return true;
1147         }
1148
1149         return false;
1150 }
1151
1152 static int tegra_sor_compute_config(struct tegra_sor *sor,
1153                                     const struct drm_display_mode *mode,
1154                                     struct tegra_sor_config *config,
1155                                     struct drm_dp_link *link)
1156 {
1157         const u64 f = 100000, link_rate = link->rate * 1000;
1158         const u64 pclk = (u64)mode->clock * 1000;
1159         u64 input, output, watermark, num;
1160         struct tegra_sor_params params;
1161         u32 num_syms_per_line;
1162         unsigned int i;
1163
1164         if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1165                 return -EINVAL;
1166
1167         input = pclk * config->bits_per_pixel;
1168         output = link_rate * 8 * link->lanes;
1169
1170         if (input >= output)
1171                 return -ERANGE;
1172
1173         memset(&params, 0, sizeof(params));
1174         params.ratio = div64_u64(input * f, output);
1175         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1176         params.precision = f;
1177         params.error = 64 * f;
1178         params.tu_size = 64;
1179
1180         for (i = params.tu_size; i >= 32; i--)
1181                 if (tegra_sor_compute_params(sor, &params, i))
1182                         break;
1183
1184         if (params.active_frac == 0) {
1185                 config->active_polarity = 0;
1186                 config->active_count = params.active_count;
1187
1188                 if (!params.active_polarity)
1189                         config->active_count--;
1190
1191                 config->tu_size = params.tu_size;
1192                 config->active_frac = 1;
1193         } else {
1194                 config->active_polarity = params.active_polarity;
1195                 config->active_count = params.active_count;
1196                 config->active_frac = params.active_frac;
1197                 config->tu_size = params.tu_size;
1198         }
1199
1200         dev_dbg(sor->dev,
1201                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1202                 config->active_polarity, config->active_count,
1203                 config->tu_size, config->active_frac);
1204
1205         watermark = params.ratio * config->tu_size * (f - params.ratio);
1206         watermark = div_u64(watermark, f);
1207
1208         watermark = div_u64(watermark + params.error, f);
1209         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1210         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1211                             (link->lanes * 8);
1212
1213         if (config->watermark > 30) {
1214                 config->watermark = 30;
1215                 dev_err(sor->dev,
1216                         "unable to compute TU size, forcing watermark to %u\n",
1217                         config->watermark);
1218         } else if (config->watermark > num_syms_per_line) {
1219                 config->watermark = num_syms_per_line;
1220                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1221                         config->watermark);
1222         }
1223
1224         /* compute the number of symbols per horizontal blanking interval */
1225         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1226         config->hblank_symbols = div_u64(num, pclk);
1227
1228         if (link->caps.enhanced_framing)
1229                 config->hblank_symbols -= 3;
1230
1231         config->hblank_symbols -= 12 / link->lanes;
1232
1233         /* compute the number of symbols per vertical blanking interval */
1234         num = (mode->hdisplay - 25) * link_rate;
1235         config->vblank_symbols = div_u64(num, pclk);
1236         config->vblank_symbols -= 36 / link->lanes + 4;
1237
1238         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1239                 config->vblank_symbols);
1240
1241         return 0;
1242 }
1243
1244 static void tegra_sor_apply_config(struct tegra_sor *sor,
1245                                    const struct tegra_sor_config *config)
1246 {
1247         u32 value;
1248
1249         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1250         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1251         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1252         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1253
1254         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1255         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1256         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1257
1258         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1259         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1260
1261         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1262         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1263
1264         if (config->active_polarity)
1265                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1266         else
1267                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1268
1269         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1270         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1271         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1272
1273         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1274         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1275         value |= config->hblank_symbols & 0xffff;
1276         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1277
1278         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1279         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1280         value |= config->vblank_symbols & 0xffff;
1281         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1282 }
1283
1284 static void tegra_sor_mode_set(struct tegra_sor *sor,
1285                                const struct drm_display_mode *mode,
1286                                struct tegra_sor_state *state)
1287 {
1288         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1289         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1290         u32 value;
1291
1292         value = tegra_sor_readl(sor, SOR_STATE1);
1293         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1294         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1295         value &= ~SOR_STATE_ASY_OWNER_MASK;
1296
1297         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1298                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1299
1300         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1301                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1302
1303         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1304                 value |= SOR_STATE_ASY_HSYNCPOL;
1305
1306         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1307                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1308
1309         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1310                 value |= SOR_STATE_ASY_VSYNCPOL;
1311
1312         switch (state->bpc) {
1313         case 16:
1314                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1315                 break;
1316
1317         case 12:
1318                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1319                 break;
1320
1321         case 10:
1322                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1323                 break;
1324
1325         case 8:
1326                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1327                 break;
1328
1329         case 6:
1330                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1331                 break;
1332
1333         default:
1334                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1335                 break;
1336         }
1337
1338         tegra_sor_writel(sor, value, SOR_STATE1);
1339
1340         /*
1341          * TODO: The video timing programming below doesn't seem to match the
1342          * register definitions.
1343          */
1344
1345         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1346         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1347
1348         /* sync end = sync width - 1 */
1349         vse = mode->vsync_end - mode->vsync_start - 1;
1350         hse = mode->hsync_end - mode->hsync_start - 1;
1351
1352         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1353         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1354
1355         /* blank end = sync end + back porch */
1356         vbe = vse + (mode->vtotal - mode->vsync_end);
1357         hbe = hse + (mode->htotal - mode->hsync_end);
1358
1359         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1360         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1361
1362         /* blank start = blank end + active */
1363         vbs = vbe + mode->vdisplay;
1364         hbs = hbe + mode->hdisplay;
1365
1366         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1367         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1368
1369         /* XXX interlacing support */
1370         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1371 }
1372
1373 static int tegra_sor_detach(struct tegra_sor *sor)
1374 {
1375         unsigned long value, timeout;
1376
1377         /* switch to safe mode */
1378         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1379         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1380         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1381         tegra_sor_super_update(sor);
1382
1383         timeout = jiffies + msecs_to_jiffies(250);
1384
1385         while (time_before(jiffies, timeout)) {
1386                 value = tegra_sor_readl(sor, SOR_PWR);
1387                 if (value & SOR_PWR_MODE_SAFE)
1388                         break;
1389         }
1390
1391         if ((value & SOR_PWR_MODE_SAFE) == 0)
1392                 return -ETIMEDOUT;
1393
1394         /* go to sleep */
1395         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1396         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1397         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1398         tegra_sor_super_update(sor);
1399
1400         /* detach */
1401         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1402         value &= ~SOR_SUPER_STATE_ATTACHED;
1403         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1404         tegra_sor_super_update(sor);
1405
1406         timeout = jiffies + msecs_to_jiffies(250);
1407
1408         while (time_before(jiffies, timeout)) {
1409                 value = tegra_sor_readl(sor, SOR_TEST);
1410                 if ((value & SOR_TEST_ATTACHED) == 0)
1411                         break;
1412
1413                 usleep_range(25, 100);
1414         }
1415
1416         if ((value & SOR_TEST_ATTACHED) != 0)
1417                 return -ETIMEDOUT;
1418
1419         return 0;
1420 }
1421
1422 static int tegra_sor_power_down(struct tegra_sor *sor)
1423 {
1424         unsigned long value, timeout;
1425         int err;
1426
1427         value = tegra_sor_readl(sor, SOR_PWR);
1428         value &= ~SOR_PWR_NORMAL_STATE_PU;
1429         value |= SOR_PWR_TRIGGER;
1430         tegra_sor_writel(sor, value, SOR_PWR);
1431
1432         timeout = jiffies + msecs_to_jiffies(250);
1433
1434         while (time_before(jiffies, timeout)) {
1435                 value = tegra_sor_readl(sor, SOR_PWR);
1436                 if ((value & SOR_PWR_TRIGGER) == 0)
1437                         return 0;
1438
1439                 usleep_range(25, 100);
1440         }
1441
1442         if ((value & SOR_PWR_TRIGGER) != 0)
1443                 return -ETIMEDOUT;
1444
1445         /* switch to safe parent clock */
1446         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1447         if (err < 0) {
1448                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1449                 return err;
1450         }
1451
1452         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1453         value |= SOR_PLL2_PORT_POWERDOWN;
1454         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1455
1456         usleep_range(20, 100);
1457
1458         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1459         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1460         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1461
1462         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1463         value |= SOR_PLL2_SEQ_PLLCAPPD;
1464         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1465         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1466
1467         usleep_range(20, 100);
1468
1469         return 0;
1470 }
1471
1472 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1473 {
1474         u32 value;
1475
1476         timeout = jiffies + msecs_to_jiffies(timeout);
1477
1478         while (time_before(jiffies, timeout)) {
1479                 value = tegra_sor_readl(sor, SOR_CRCA);
1480                 if (value & SOR_CRCA_VALID)
1481                         return 0;
1482
1483                 usleep_range(100, 200);
1484         }
1485
1486         return -ETIMEDOUT;
1487 }
1488
1489 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1490 {
1491         struct drm_info_node *node = s->private;
1492         struct tegra_sor *sor = node->info_ent->data;
1493         struct drm_crtc *crtc = sor->output.encoder.crtc;
1494         struct drm_device *drm = node->minor->dev;
1495         int err = 0;
1496         u32 value;
1497
1498         drm_modeset_lock_all(drm);
1499
1500         if (!crtc || !crtc->state->active) {
1501                 err = -EBUSY;
1502                 goto unlock;
1503         }
1504
1505         value = tegra_sor_readl(sor, SOR_STATE1);
1506         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1507         tegra_sor_writel(sor, value, SOR_STATE1);
1508
1509         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1510         value |= SOR_CRC_CNTRL_ENABLE;
1511         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1512
1513         value = tegra_sor_readl(sor, SOR_TEST);
1514         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1515         tegra_sor_writel(sor, value, SOR_TEST);
1516
1517         err = tegra_sor_crc_wait(sor, 100);
1518         if (err < 0)
1519                 goto unlock;
1520
1521         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1522         value = tegra_sor_readl(sor, SOR_CRCB);
1523
1524         seq_printf(s, "%08x\n", value);
1525
1526 unlock:
1527         drm_modeset_unlock_all(drm);
1528         return err;
1529 }
1530
1531 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1532
1533 static const struct debugfs_reg32 tegra_sor_regs[] = {
1534         DEBUGFS_REG32(SOR_CTXSW),
1535         DEBUGFS_REG32(SOR_SUPER_STATE0),
1536         DEBUGFS_REG32(SOR_SUPER_STATE1),
1537         DEBUGFS_REG32(SOR_STATE0),
1538         DEBUGFS_REG32(SOR_STATE1),
1539         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1540         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1541         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1542         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1543         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1544         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1545         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1546         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1547         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1548         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1549         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1550         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1551         DEBUGFS_REG32(SOR_CRC_CNTRL),
1552         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1553         DEBUGFS_REG32(SOR_CLK_CNTRL),
1554         DEBUGFS_REG32(SOR_CAP),
1555         DEBUGFS_REG32(SOR_PWR),
1556         DEBUGFS_REG32(SOR_TEST),
1557         DEBUGFS_REG32(SOR_PLL0),
1558         DEBUGFS_REG32(SOR_PLL1),
1559         DEBUGFS_REG32(SOR_PLL2),
1560         DEBUGFS_REG32(SOR_PLL3),
1561         DEBUGFS_REG32(SOR_CSTM),
1562         DEBUGFS_REG32(SOR_LVDS),
1563         DEBUGFS_REG32(SOR_CRCA),
1564         DEBUGFS_REG32(SOR_CRCB),
1565         DEBUGFS_REG32(SOR_BLANK),
1566         DEBUGFS_REG32(SOR_SEQ_CTL),
1567         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1568         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1569         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1570         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1571         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1572         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1573         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1574         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1575         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1576         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1577         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1578         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1579         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1580         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1581         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1582         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1583         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1584         DEBUGFS_REG32(SOR_PWM_DIV),
1585         DEBUGFS_REG32(SOR_PWM_CTL),
1586         DEBUGFS_REG32(SOR_VCRC_A0),
1587         DEBUGFS_REG32(SOR_VCRC_A1),
1588         DEBUGFS_REG32(SOR_VCRC_B0),
1589         DEBUGFS_REG32(SOR_VCRC_B1),
1590         DEBUGFS_REG32(SOR_CCRC_A0),
1591         DEBUGFS_REG32(SOR_CCRC_A1),
1592         DEBUGFS_REG32(SOR_CCRC_B0),
1593         DEBUGFS_REG32(SOR_CCRC_B1),
1594         DEBUGFS_REG32(SOR_EDATA_A0),
1595         DEBUGFS_REG32(SOR_EDATA_A1),
1596         DEBUGFS_REG32(SOR_EDATA_B0),
1597         DEBUGFS_REG32(SOR_EDATA_B1),
1598         DEBUGFS_REG32(SOR_COUNT_A0),
1599         DEBUGFS_REG32(SOR_COUNT_A1),
1600         DEBUGFS_REG32(SOR_COUNT_B0),
1601         DEBUGFS_REG32(SOR_COUNT_B1),
1602         DEBUGFS_REG32(SOR_DEBUG_A0),
1603         DEBUGFS_REG32(SOR_DEBUG_A1),
1604         DEBUGFS_REG32(SOR_DEBUG_B0),
1605         DEBUGFS_REG32(SOR_DEBUG_B1),
1606         DEBUGFS_REG32(SOR_TRIG),
1607         DEBUGFS_REG32(SOR_MSCHECK),
1608         DEBUGFS_REG32(SOR_XBAR_CTRL),
1609         DEBUGFS_REG32(SOR_XBAR_POL),
1610         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1611         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1612         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1613         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1614         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1615         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1616         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1617         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1618         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1619         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1620         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1621         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1622         DEBUGFS_REG32(SOR_DP_CONFIG0),
1623         DEBUGFS_REG32(SOR_DP_CONFIG1),
1624         DEBUGFS_REG32(SOR_DP_MN0),
1625         DEBUGFS_REG32(SOR_DP_MN1),
1626         DEBUGFS_REG32(SOR_DP_PADCTL0),
1627         DEBUGFS_REG32(SOR_DP_PADCTL1),
1628         DEBUGFS_REG32(SOR_DP_PADCTL2),
1629         DEBUGFS_REG32(SOR_DP_DEBUG0),
1630         DEBUGFS_REG32(SOR_DP_DEBUG1),
1631         DEBUGFS_REG32(SOR_DP_SPARE0),
1632         DEBUGFS_REG32(SOR_DP_SPARE1),
1633         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1634         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1635         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1636         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1637         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1638         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1639         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1640         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1641         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1642         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1643         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1644         DEBUGFS_REG32(SOR_DP_TPG),
1645         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1646         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1647         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1648         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1649 };
1650
1651 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1652 {
1653         struct drm_info_node *node = s->private;
1654         struct tegra_sor *sor = node->info_ent->data;
1655         struct drm_crtc *crtc = sor->output.encoder.crtc;
1656         struct drm_device *drm = node->minor->dev;
1657         unsigned int i;
1658         int err = 0;
1659
1660         drm_modeset_lock_all(drm);
1661
1662         if (!crtc || !crtc->state->active) {
1663                 err = -EBUSY;
1664                 goto unlock;
1665         }
1666
1667         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1668                 unsigned int offset = tegra_sor_regs[i].offset;
1669
1670                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1671                            offset, tegra_sor_readl(sor, offset));
1672         }
1673
1674 unlock:
1675         drm_modeset_unlock_all(drm);
1676         return err;
1677 }
1678
1679 static const struct drm_info_list debugfs_files[] = {
1680         { "crc", tegra_sor_show_crc, 0, NULL },
1681         { "regs", tegra_sor_show_regs, 0, NULL },
1682 };
1683
1684 static int tegra_sor_late_register(struct drm_connector *connector)
1685 {
1686         struct tegra_output *output = connector_to_output(connector);
1687         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1688         struct drm_minor *minor = connector->dev->primary;
1689         struct dentry *root = connector->debugfs_entry;
1690         struct tegra_sor *sor = to_sor(output);
1691
1692         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1693                                      GFP_KERNEL);
1694         if (!sor->debugfs_files)
1695                 return -ENOMEM;
1696
1697         for (i = 0; i < count; i++)
1698                 sor->debugfs_files[i].data = sor;
1699
1700         drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1701
1702         return 0;
1703 }
1704
1705 static void tegra_sor_early_unregister(struct drm_connector *connector)
1706 {
1707         struct tegra_output *output = connector_to_output(connector);
1708         unsigned int count = ARRAY_SIZE(debugfs_files);
1709         struct tegra_sor *sor = to_sor(output);
1710
1711         drm_debugfs_remove_files(sor->debugfs_files, count,
1712                                  connector->debugfs_entry,
1713                                  connector->dev->primary);
1714         kfree(sor->debugfs_files);
1715         sor->debugfs_files = NULL;
1716 }
1717
1718 static void tegra_sor_connector_reset(struct drm_connector *connector)
1719 {
1720         struct tegra_sor_state *state;
1721
1722         state = kzalloc(sizeof(*state), GFP_KERNEL);
1723         if (!state)
1724                 return;
1725
1726         if (connector->state) {
1727                 __drm_atomic_helper_connector_destroy_state(connector->state);
1728                 kfree(connector->state);
1729         }
1730
1731         __drm_atomic_helper_connector_reset(connector, &state->base);
1732 }
1733
1734 static enum drm_connector_status
1735 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1736 {
1737         struct tegra_output *output = connector_to_output(connector);
1738         struct tegra_sor *sor = to_sor(output);
1739
1740         if (sor->aux)
1741                 return drm_dp_aux_detect(sor->aux);
1742
1743         return tegra_output_connector_detect(connector, force);
1744 }
1745
1746 static struct drm_connector_state *
1747 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1748 {
1749         struct tegra_sor_state *state = to_sor_state(connector->state);
1750         struct tegra_sor_state *copy;
1751
1752         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1753         if (!copy)
1754                 return NULL;
1755
1756         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1757
1758         return &copy->base;
1759 }
1760
1761 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1762         .reset = tegra_sor_connector_reset,
1763         .detect = tegra_sor_connector_detect,
1764         .fill_modes = drm_helper_probe_single_connector_modes,
1765         .destroy = tegra_output_connector_destroy,
1766         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1767         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1768         .late_register = tegra_sor_late_register,
1769         .early_unregister = tegra_sor_early_unregister,
1770 };
1771
1772 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1773 {
1774         struct tegra_output *output = connector_to_output(connector);
1775         struct tegra_sor *sor = to_sor(output);
1776         int err;
1777
1778         if (sor->aux)
1779                 drm_dp_aux_enable(sor->aux);
1780
1781         err = tegra_output_connector_get_modes(connector);
1782
1783         if (sor->aux)
1784                 drm_dp_aux_disable(sor->aux);
1785
1786         return err;
1787 }
1788
1789 static enum drm_mode_status
1790 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1791                                struct drm_display_mode *mode)
1792 {
1793         return MODE_OK;
1794 }
1795
1796 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1797         .get_modes = tegra_sor_connector_get_modes,
1798         .mode_valid = tegra_sor_connector_mode_valid,
1799 };
1800
1801 static int
1802 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1803                                struct drm_crtc_state *crtc_state,
1804                                struct drm_connector_state *conn_state)
1805 {
1806         struct tegra_output *output = encoder_to_output(encoder);
1807         struct tegra_sor_state *state = to_sor_state(conn_state);
1808         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1809         unsigned long pclk = crtc_state->mode.clock * 1000;
1810         struct tegra_sor *sor = to_sor(output);
1811         struct drm_display_info *info;
1812         int err;
1813
1814         info = &output->connector.display_info;
1815
1816         /*
1817          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1818          * the pixel clock must be corrected accordingly.
1819          */
1820         if (pclk >= 340000000) {
1821                 state->link_speed = 20;
1822                 state->pclk = pclk / 2;
1823         } else {
1824                 state->link_speed = 10;
1825                 state->pclk = pclk;
1826         }
1827
1828         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1829                                          pclk, 0);
1830         if (err < 0) {
1831                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1832                 return err;
1833         }
1834
1835         switch (info->bpc) {
1836         case 8:
1837         case 6:
1838                 state->bpc = info->bpc;
1839                 break;
1840
1841         default:
1842                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1843                 state->bpc = 8;
1844                 break;
1845         }
1846
1847         return 0;
1848 }
1849
1850 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1851 {
1852         u32 value = 0;
1853         size_t i;
1854
1855         for (i = size; i > 0; i--)
1856                 value = (value << 8) | ptr[i - 1];
1857
1858         return value;
1859 }
1860
1861 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1862                                           const void *data, size_t size)
1863 {
1864         const u8 *ptr = data;
1865         unsigned long offset;
1866         size_t i, j;
1867         u32 value;
1868
1869         switch (ptr[0]) {
1870         case HDMI_INFOFRAME_TYPE_AVI:
1871                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1872                 break;
1873
1874         case HDMI_INFOFRAME_TYPE_AUDIO:
1875                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1876                 break;
1877
1878         case HDMI_INFOFRAME_TYPE_VENDOR:
1879                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1880                 break;
1881
1882         default:
1883                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1884                         ptr[0]);
1885                 return;
1886         }
1887
1888         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1889                 INFOFRAME_HEADER_VERSION(ptr[1]) |
1890                 INFOFRAME_HEADER_LEN(ptr[2]);
1891         tegra_sor_writel(sor, value, offset);
1892         offset++;
1893
1894         /*
1895          * Each subpack contains 7 bytes, divided into:
1896          * - subpack_low: bytes 0 - 3
1897          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1898          */
1899         for (i = 3, j = 0; i < size; i += 7, j += 8) {
1900                 size_t rem = size - i, num = min_t(size_t, rem, 4);
1901
1902                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1903                 tegra_sor_writel(sor, value, offset++);
1904
1905                 num = min_t(size_t, rem - num, 3);
1906
1907                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1908                 tegra_sor_writel(sor, value, offset++);
1909         }
1910 }
1911
1912 static int
1913 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1914                                    const struct drm_display_mode *mode)
1915 {
1916         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1917         struct hdmi_avi_infoframe frame;
1918         u32 value;
1919         int err;
1920
1921         /* disable AVI infoframe */
1922         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1923         value &= ~INFOFRAME_CTRL_SINGLE;
1924         value &= ~INFOFRAME_CTRL_OTHER;
1925         value &= ~INFOFRAME_CTRL_ENABLE;
1926         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1927
1928         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1929                                                        &sor->output.connector, mode);
1930         if (err < 0) {
1931                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1932                 return err;
1933         }
1934
1935         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1936         if (err < 0) {
1937                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1938                 return err;
1939         }
1940
1941         tegra_sor_hdmi_write_infopack(sor, buffer, err);
1942
1943         /* enable AVI infoframe */
1944         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1945         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1946         value |= INFOFRAME_CTRL_ENABLE;
1947         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1948
1949         return 0;
1950 }
1951
1952 static void tegra_sor_write_eld(struct tegra_sor *sor)
1953 {
1954         size_t length = drm_eld_size(sor->output.connector.eld), i;
1955
1956         for (i = 0; i < length; i++)
1957                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1958                                  SOR_AUDIO_HDA_ELD_BUFWR);
1959
1960         /*
1961          * The HDA codec will always report an ELD buffer size of 96 bytes and
1962          * the HDA codec driver will check that each byte read from the buffer
1963          * is valid. Therefore every byte must be written, even if no 96 bytes
1964          * were parsed from EDID.
1965          */
1966         for (i = length; i < 96; i++)
1967                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1968 }
1969
1970 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1971 {
1972         u32 value;
1973
1974         /*
1975          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1976          * is used for interoperability between the HDA codec driver and the
1977          * HDMI/DP driver.
1978          */
1979         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1980         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1981         tegra_sor_writel(sor, value, SOR_INT_MASK);
1982
1983         tegra_sor_write_eld(sor);
1984
1985         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1986         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1987 }
1988
1989 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1990 {
1991         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1992         tegra_sor_writel(sor, 0, SOR_INT_MASK);
1993         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
1994 }
1995
1996 static void tegra_sor_audio_enable(struct tegra_sor *sor)
1997 {
1998         u32 value;
1999
2000         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2001
2002         /* select HDA audio input */
2003         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2004         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2005
2006         /* inject null samples */
2007         if (sor->format.channels != 2)
2008                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2009         else
2010                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2011
2012         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2013
2014         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2015
2016         /* enable advertising HBR capability */
2017         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2018 }
2019
2020 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2021 {
2022         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2023         struct hdmi_audio_infoframe frame;
2024         u32 value;
2025         int err;
2026
2027         err = hdmi_audio_infoframe_init(&frame);
2028         if (err < 0) {
2029                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2030                 return err;
2031         }
2032
2033         frame.channels = sor->format.channels;
2034
2035         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2036         if (err < 0) {
2037                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2038                 return err;
2039         }
2040
2041         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2042
2043         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2044         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2045         value |= INFOFRAME_CTRL_ENABLE;
2046         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2047
2048         return 0;
2049 }
2050
2051 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2052 {
2053         u32 value;
2054
2055         tegra_sor_audio_enable(sor);
2056
2057         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2058
2059         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2060                 SOR_HDMI_SPARE_CTS_RESET(1) |
2061                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2062         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2063
2064         /* enable HW CTS */
2065         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2066         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2067
2068         /* allow packet to be sent */
2069         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2070         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2071
2072         /* reset N counter and enable lookup */
2073         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2074         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2075
2076         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2077         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2078         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2079
2080         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2081         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2082
2083         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2084         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2085
2086         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2087         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2088
2089         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2090         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2091         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2092
2093         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2094         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2095         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2096
2097         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2098         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2099         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2100
2101         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2102         value &= ~SOR_HDMI_AUDIO_N_RESET;
2103         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2104
2105         tegra_sor_hdmi_enable_audio_infoframe(sor);
2106 }
2107
2108 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2109 {
2110         u32 value;
2111
2112         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2113         value &= ~INFOFRAME_CTRL_ENABLE;
2114         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2115 }
2116
2117 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2118 {
2119         tegra_sor_hdmi_disable_audio_infoframe(sor);
2120 }
2121
2122 static struct tegra_sor_hdmi_settings *
2123 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2124 {
2125         unsigned int i;
2126
2127         for (i = 0; i < sor->num_settings; i++)
2128                 if (frequency <= sor->settings[i].frequency)
2129                         return &sor->settings[i];
2130
2131         return NULL;
2132 }
2133
2134 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2135 {
2136         u32 value;
2137
2138         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2139         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2140         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2141         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2142 }
2143
2144 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2145 {
2146         drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false);
2147         drm_scdc_set_scrambling(&sor->output.connector, false);
2148
2149         tegra_sor_hdmi_disable_scrambling(sor);
2150 }
2151
2152 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2153 {
2154         if (sor->scdc_enabled) {
2155                 cancel_delayed_work_sync(&sor->scdc);
2156                 tegra_sor_hdmi_scdc_disable(sor);
2157         }
2158 }
2159
2160 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2161 {
2162         u32 value;
2163
2164         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2165         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2166         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2167         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2168 }
2169
2170 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2171 {
2172         drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true);
2173         drm_scdc_set_scrambling(&sor->output.connector, true);
2174
2175         tegra_sor_hdmi_enable_scrambling(sor);
2176 }
2177
2178 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2179 {
2180         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2181
2182         if (!drm_scdc_get_scrambling_status(&sor->output.connector)) {
2183                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2184                 tegra_sor_hdmi_scdc_enable(sor);
2185         }
2186
2187         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2188 }
2189
2190 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2191 {
2192         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2193         struct drm_display_mode *mode;
2194
2195         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2196
2197         if (mode->clock >= 340000 && scdc->supported) {
2198                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2199                 tegra_sor_hdmi_scdc_enable(sor);
2200                 sor->scdc_enabled = true;
2201         }
2202 }
2203
2204 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2205 {
2206         struct tegra_output *output = encoder_to_output(encoder);
2207         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2208         struct tegra_sor *sor = to_sor(output);
2209         u32 value;
2210         int err;
2211
2212         tegra_sor_audio_unprepare(sor);
2213         tegra_sor_hdmi_scdc_stop(sor);
2214
2215         err = tegra_sor_detach(sor);
2216         if (err < 0)
2217                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2218
2219         tegra_sor_writel(sor, 0, SOR_STATE1);
2220         tegra_sor_update(sor);
2221
2222         /* disable display to SOR clock */
2223         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2224
2225         if (!sor->soc->has_nvdisplay)
2226                 value &= ~SOR1_TIMING_CYA;
2227
2228         value &= ~SOR_ENABLE(sor->index);
2229
2230         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2231
2232         tegra_dc_commit(dc);
2233
2234         err = tegra_sor_power_down(sor);
2235         if (err < 0)
2236                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2237
2238         err = tegra_io_pad_power_disable(sor->pad);
2239         if (err < 0)
2240                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2241
2242         host1x_client_suspend(&sor->client);
2243 }
2244
2245 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2246 {
2247         struct tegra_output *output = encoder_to_output(encoder);
2248         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2249         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2250         struct tegra_sor_hdmi_settings *settings;
2251         struct tegra_sor *sor = to_sor(output);
2252         struct tegra_sor_state *state;
2253         struct drm_display_mode *mode;
2254         unsigned long rate, pclk;
2255         unsigned int div, i;
2256         u32 value;
2257         int err;
2258
2259         state = to_sor_state(output->connector.state);
2260         mode = &encoder->crtc->state->adjusted_mode;
2261         pclk = mode->clock * 1000;
2262
2263         err = host1x_client_resume(&sor->client);
2264         if (err < 0) {
2265                 dev_err(sor->dev, "failed to resume: %d\n", err);
2266                 return;
2267         }
2268
2269         /* switch to safe parent clock */
2270         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2271         if (err < 0) {
2272                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2273                 return;
2274         }
2275
2276         div = clk_get_rate(sor->clk) / 1000000 * 4;
2277
2278         err = tegra_io_pad_power_enable(sor->pad);
2279         if (err < 0)
2280                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2281
2282         usleep_range(20, 100);
2283
2284         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2285         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2286         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2287
2288         usleep_range(20, 100);
2289
2290         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2291         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2292         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2293
2294         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2295         value &= ~SOR_PLL0_VCOPD;
2296         value &= ~SOR_PLL0_PWR;
2297         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2298
2299         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2300         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2301         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2302
2303         usleep_range(200, 400);
2304
2305         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2306         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2307         value &= ~SOR_PLL2_PORT_POWERDOWN;
2308         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2309
2310         usleep_range(20, 100);
2311
2312         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2313         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2314                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2315         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2316
2317         while (true) {
2318                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2319                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2320                         break;
2321
2322                 usleep_range(250, 1000);
2323         }
2324
2325         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2326                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2327         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2328
2329         while (true) {
2330                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2331                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2332                         break;
2333
2334                 usleep_range(250, 1000);
2335         }
2336
2337         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2338         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2339         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2340
2341         if (mode->clock < 340000) {
2342                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2343                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2344         } else {
2345                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2346                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2347         }
2348
2349         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2350         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2351
2352         /* SOR pad PLL stabilization time */
2353         usleep_range(250, 1000);
2354
2355         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2356         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2357         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2358         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2359
2360         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2361         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2362         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2363         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2364         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2365         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2366
2367         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2368                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2369         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2370
2371         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2372                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2373         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2374         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2375
2376         if (!sor->soc->has_nvdisplay) {
2377                 /* program the reference clock */
2378                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2379                 tegra_sor_writel(sor, value, SOR_REFCLK);
2380         }
2381
2382         /* XXX not in TRM */
2383         for (value = 0, i = 0; i < 5; i++)
2384                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2385                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2386
2387         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2388         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2389
2390         /*
2391          * Switch the pad clock to the DP clock. Note that we cannot actually
2392          * do this because Tegra186 and later don't support clk_set_parent()
2393          * on the sorX_pad_clkout clocks. We already do the equivalent above
2394          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2395          */
2396 #if 0
2397         err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2398         if (err < 0) {
2399                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2400                         err);
2401                 return;
2402         }
2403 #endif
2404
2405         /* switch the SOR clock to the pad clock */
2406         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2407         if (err < 0) {
2408                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2409                         err);
2410                 return;
2411         }
2412
2413         /* switch the output clock to the parent pixel clock */
2414         err = clk_set_parent(sor->clk, sor->clk_parent);
2415         if (err < 0) {
2416                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2417                         err);
2418                 return;
2419         }
2420
2421         /* adjust clock rate for HDMI 2.0 modes */
2422         rate = clk_get_rate(sor->clk_parent);
2423
2424         if (mode->clock >= 340000)
2425                 rate /= 2;
2426
2427         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2428
2429         clk_set_rate(sor->clk, rate);
2430
2431         if (!sor->soc->has_nvdisplay) {
2432                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2433
2434                 /* XXX is this the proper check? */
2435                 if (mode->clock < 75000)
2436                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2437
2438                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2439         }
2440
2441         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2442
2443         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2444                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2445         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2446
2447         if (!dc->soc->has_nvdisplay) {
2448                 /* H_PULSE2 setup */
2449                 pulse_start = h_ref_to_sync +
2450                               (mode->hsync_end - mode->hsync_start) +
2451                               (mode->htotal - mode->hsync_end) - 10;
2452
2453                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2454                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2455                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2456
2457                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2458                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2459
2460                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2461                 value |= H_PULSE2_ENABLE;
2462                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2463         }
2464
2465         /* infoframe setup */
2466         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2467         if (err < 0)
2468                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2469
2470         /* XXX HDMI audio support not implemented yet */
2471         tegra_sor_hdmi_disable_audio_infoframe(sor);
2472
2473         /* use single TMDS protocol */
2474         value = tegra_sor_readl(sor, SOR_STATE1);
2475         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2476         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2477         tegra_sor_writel(sor, value, SOR_STATE1);
2478
2479         /* power up pad calibration */
2480         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2481         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2482         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2483
2484         /* production settings */
2485         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2486         if (!settings) {
2487                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2488                         mode->clock * 1000);
2489                 return;
2490         }
2491
2492         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2493         value &= ~SOR_PLL0_ICHPMP_MASK;
2494         value &= ~SOR_PLL0_FILTER_MASK;
2495         value &= ~SOR_PLL0_VCOCAP_MASK;
2496         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2497         value |= SOR_PLL0_FILTER(settings->filter);
2498         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2499         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2500
2501         /* XXX not in TRM */
2502         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2503         value &= ~SOR_PLL1_LOADADJ_MASK;
2504         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2505         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2506         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2507         value |= SOR_PLL1_TMDS_TERM;
2508         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2509
2510         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2511         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2512         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2513         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2514         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2515         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2516         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2517         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2518         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2519         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2520
2521         value = settings->drive_current[3] << 24 |
2522                 settings->drive_current[2] << 16 |
2523                 settings->drive_current[1] <<  8 |
2524                 settings->drive_current[0] <<  0;
2525         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2526
2527         value = settings->preemphasis[3] << 24 |
2528                 settings->preemphasis[2] << 16 |
2529                 settings->preemphasis[1] <<  8 |
2530                 settings->preemphasis[0] <<  0;
2531         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2532
2533         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2534         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2535         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2536         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2537         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2538
2539         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2540         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2541         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2542         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2543
2544         /* power down pad calibration */
2545         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2546         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2547         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2548
2549         if (!dc->soc->has_nvdisplay) {
2550                 /* miscellaneous display controller settings */
2551                 value = VSYNC_H_POSITION(1);
2552                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2553         }
2554
2555         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2556         value &= ~DITHER_CONTROL_MASK;
2557         value &= ~BASE_COLOR_SIZE_MASK;
2558
2559         switch (state->bpc) {
2560         case 6:
2561                 value |= BASE_COLOR_SIZE_666;
2562                 break;
2563
2564         case 8:
2565                 value |= BASE_COLOR_SIZE_888;
2566                 break;
2567
2568         case 10:
2569                 value |= BASE_COLOR_SIZE_101010;
2570                 break;
2571
2572         case 12:
2573                 value |= BASE_COLOR_SIZE_121212;
2574                 break;
2575
2576         default:
2577                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2578                 value |= BASE_COLOR_SIZE_888;
2579                 break;
2580         }
2581
2582         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2583
2584         /* XXX set display head owner */
2585         value = tegra_sor_readl(sor, SOR_STATE1);
2586         value &= ~SOR_STATE_ASY_OWNER_MASK;
2587         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2588         tegra_sor_writel(sor, value, SOR_STATE1);
2589
2590         err = tegra_sor_power_up(sor, 250);
2591         if (err < 0)
2592                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2593
2594         /* configure dynamic range of output */
2595         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2596         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2597         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2598         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2599
2600         /* configure colorspace */
2601         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2602         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2603         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2604         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2605
2606         tegra_sor_mode_set(sor, mode, state);
2607
2608         tegra_sor_update(sor);
2609
2610         /* program preamble timing in SOR (XXX) */
2611         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2612         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2613         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2614
2615         err = tegra_sor_attach(sor);
2616         if (err < 0)
2617                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2618
2619         /* enable display to SOR clock and generate HDMI preamble */
2620         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2621
2622         if (!sor->soc->has_nvdisplay)
2623                 value |= SOR1_TIMING_CYA;
2624
2625         value |= SOR_ENABLE(sor->index);
2626
2627         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2628
2629         if (dc->soc->has_nvdisplay) {
2630                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2631                 value &= ~PROTOCOL_MASK;
2632                 value |= PROTOCOL_SINGLE_TMDS_A;
2633                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2634         }
2635
2636         tegra_dc_commit(dc);
2637
2638         err = tegra_sor_wakeup(sor);
2639         if (err < 0)
2640                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2641
2642         tegra_sor_hdmi_scdc_start(sor);
2643         tegra_sor_audio_prepare(sor);
2644 }
2645
2646 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2647         .disable = tegra_sor_hdmi_disable,
2648         .enable = tegra_sor_hdmi_enable,
2649         .atomic_check = tegra_sor_encoder_atomic_check,
2650 };
2651
2652 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2653 {
2654         struct tegra_output *output = encoder_to_output(encoder);
2655         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2656         struct tegra_sor *sor = to_sor(output);
2657         u32 value;
2658         int err;
2659
2660         if (output->panel)
2661                 drm_panel_disable(output->panel);
2662
2663         /*
2664          * Do not attempt to power down a DP link if we're not connected since
2665          * the AUX transactions would just be timing out.
2666          */
2667         if (output->connector.status != connector_status_disconnected) {
2668                 err = drm_dp_link_power_down(sor->aux, &sor->link);
2669                 if (err < 0)
2670                         dev_err(sor->dev, "failed to power down link: %d\n",
2671                                 err);
2672         }
2673
2674         err = tegra_sor_detach(sor);
2675         if (err < 0)
2676                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2677
2678         tegra_sor_writel(sor, 0, SOR_STATE1);
2679         tegra_sor_update(sor);
2680
2681         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2682         value &= ~SOR_ENABLE(sor->index);
2683         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2684         tegra_dc_commit(dc);
2685
2686         value = tegra_sor_readl(sor, SOR_STATE1);
2687         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2688         value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2689         value &= ~SOR_STATE_ASY_OWNER_MASK;
2690         tegra_sor_writel(sor, value, SOR_STATE1);
2691         tegra_sor_update(sor);
2692
2693         /* switch to safe parent clock */
2694         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2695         if (err < 0)
2696                 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2697
2698         err = tegra_sor_power_down(sor);
2699         if (err < 0)
2700                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2701
2702         err = tegra_io_pad_power_disable(sor->pad);
2703         if (err < 0)
2704                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2705
2706         err = drm_dp_aux_disable(sor->aux);
2707         if (err < 0)
2708                 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2709
2710         if (output->panel)
2711                 drm_panel_unprepare(output->panel);
2712
2713         host1x_client_suspend(&sor->client);
2714 }
2715
2716 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2717 {
2718         struct tegra_output *output = encoder_to_output(encoder);
2719         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2720         struct tegra_sor *sor = to_sor(output);
2721         struct tegra_sor_config config;
2722         struct tegra_sor_state *state;
2723         struct drm_display_mode *mode;
2724         struct drm_display_info *info;
2725         unsigned int i;
2726         u32 value;
2727         int err;
2728
2729         state = to_sor_state(output->connector.state);
2730         mode = &encoder->crtc->state->adjusted_mode;
2731         info = &output->connector.display_info;
2732
2733         err = host1x_client_resume(&sor->client);
2734         if (err < 0) {
2735                 dev_err(sor->dev, "failed to resume: %d\n", err);
2736                 return;
2737         }
2738
2739         /* switch to safe parent clock */
2740         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2741         if (err < 0)
2742                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2743
2744         err = tegra_io_pad_power_enable(sor->pad);
2745         if (err < 0)
2746                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2747
2748         usleep_range(20, 100);
2749
2750         err = drm_dp_aux_enable(sor->aux);
2751         if (err < 0)
2752                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2753
2754         err = drm_dp_link_probe(sor->aux, &sor->link);
2755         if (err < 0)
2756                 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2757
2758         tegra_sor_filter_rates(sor);
2759
2760         err = drm_dp_link_choose(&sor->link, mode, info);
2761         if (err < 0)
2762                 dev_err(sor->dev, "failed to choose link: %d\n", err);
2763
2764         if (output->panel)
2765                 drm_panel_prepare(output->panel);
2766
2767         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2768         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2769         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2770
2771         usleep_range(20, 40);
2772
2773         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2774         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2775         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2776
2777         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2778         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2779         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2780
2781         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2782         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2783         value |= SOR_PLL2_SEQ_PLLCAPPD;
2784         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2785
2786         usleep_range(200, 400);
2787
2788         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2789         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2790         value &= ~SOR_PLL2_PORT_POWERDOWN;
2791         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2792
2793         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2794         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2795
2796         if (output->panel)
2797                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2798         else
2799                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2800
2801         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2802
2803         usleep_range(200, 400);
2804
2805         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2806         /* XXX not in TRM */
2807         if (output->panel)
2808                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2809         else
2810                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2811
2812         value |= SOR_DP_SPARE_SEQ_ENABLE;
2813         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2814
2815         /* XXX not in TRM */
2816         tegra_sor_writel(sor, 0, SOR_LVDS);
2817
2818         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2819         value &= ~SOR_PLL0_ICHPMP_MASK;
2820         value &= ~SOR_PLL0_VCOCAP_MASK;
2821         value |= SOR_PLL0_ICHPMP(0x1);
2822         value |= SOR_PLL0_VCOCAP(0x3);
2823         value |= SOR_PLL0_RESISTOR_EXT;
2824         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2825
2826         /* XXX not in TRM */
2827         for (value = 0, i = 0; i < 5; i++)
2828                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2829                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2830
2831         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2832         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2833
2834         /*
2835          * Switch the pad clock to the DP clock. Note that we cannot actually
2836          * do this because Tegra186 and later don't support clk_set_parent()
2837          * on the sorX_pad_clkout clocks. We already do the equivalent above
2838          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2839          */
2840 #if 0
2841         err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2842         if (err < 0) {
2843                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2844                         err);
2845                 return;
2846         }
2847 #endif
2848
2849         /* switch the SOR clock to the pad clock */
2850         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2851         if (err < 0) {
2852                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2853                         err);
2854                 return;
2855         }
2856
2857         /* switch the output clock to the parent pixel clock */
2858         err = clk_set_parent(sor->clk, sor->clk_parent);
2859         if (err < 0) {
2860                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2861                         err);
2862                 return;
2863         }
2864
2865         /* use DP-A protocol */
2866         value = tegra_sor_readl(sor, SOR_STATE1);
2867         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2868         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2869         tegra_sor_writel(sor, value, SOR_STATE1);
2870
2871         /* enable port */
2872         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2873         value |= SOR_DP_LINKCTL_ENABLE;
2874         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2875
2876         tegra_sor_dp_term_calibrate(sor);
2877
2878         err = drm_dp_link_train(&sor->link);
2879         if (err < 0)
2880                 dev_err(sor->dev, "link training failed: %d\n", err);
2881         else
2882                 dev_dbg(sor->dev, "link training succeeded\n");
2883
2884         err = drm_dp_link_power_up(sor->aux, &sor->link);
2885         if (err < 0)
2886                 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2887
2888         /* compute configuration */
2889         memset(&config, 0, sizeof(config));
2890         config.bits_per_pixel = state->bpc * 3;
2891
2892         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2893         if (err < 0)
2894                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2895
2896         tegra_sor_apply_config(sor, &config);
2897         tegra_sor_mode_set(sor, mode, state);
2898
2899         if (output->panel) {
2900                 /* CSTM (LVDS, link A/B, upper) */
2901                 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2902                         SOR_CSTM_UPPER;
2903                 tegra_sor_writel(sor, value, SOR_CSTM);
2904
2905                 /* PWM setup */
2906                 err = tegra_sor_setup_pwm(sor, 250);
2907                 if (err < 0)
2908                         dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2909         }
2910
2911         tegra_sor_update(sor);
2912
2913         err = tegra_sor_power_up(sor, 250);
2914         if (err < 0)
2915                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2916
2917         /* attach and wake up */
2918         err = tegra_sor_attach(sor);
2919         if (err < 0)
2920                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2921
2922         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2923         value |= SOR_ENABLE(sor->index);
2924         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2925
2926         tegra_dc_commit(dc);
2927
2928         err = tegra_sor_wakeup(sor);
2929         if (err < 0)
2930                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2931
2932         if (output->panel)
2933                 drm_panel_enable(output->panel);
2934 }
2935
2936 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2937         .disable = tegra_sor_dp_disable,
2938         .enable = tegra_sor_dp_enable,
2939         .atomic_check = tegra_sor_encoder_atomic_check,
2940 };
2941
2942 static void tegra_sor_disable_regulator(void *data)
2943 {
2944         struct regulator *reg = data;
2945
2946         regulator_disable(reg);
2947 }
2948
2949 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
2950 {
2951         int err;
2952
2953         err = regulator_enable(reg);
2954         if (err)
2955                 return err;
2956
2957         return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2958 }
2959
2960 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2961 {
2962         int err;
2963
2964         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2965         if (IS_ERR(sor->avdd_io_supply))
2966                 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply),
2967                                      "cannot get AVDD I/O supply\n");
2968
2969         err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
2970         if (err < 0) {
2971                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2972                         err);
2973                 return err;
2974         }
2975
2976         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2977         if (IS_ERR(sor->vdd_pll_supply))
2978                 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply),
2979                                      "cannot get VDD PLL supply\n");
2980
2981         err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
2982         if (err < 0) {
2983                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2984                         err);
2985                 return err;
2986         }
2987
2988         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2989         if (IS_ERR(sor->hdmi_supply))
2990                 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply),
2991                                      "cannot get HDMI supply\n");
2992
2993         err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
2994         if (err < 0) {
2995                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2996                 return err;
2997         }
2998
2999         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3000
3001         return 0;
3002 }
3003
3004 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3005         .name = "HDMI",
3006         .probe = tegra_sor_hdmi_probe,
3007         .audio_enable = tegra_sor_hdmi_audio_enable,
3008         .audio_disable = tegra_sor_hdmi_audio_disable,
3009 };
3010
3011 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3012 {
3013         int err;
3014
3015         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3016         if (IS_ERR(sor->avdd_io_supply))
3017                 return PTR_ERR(sor->avdd_io_supply);
3018
3019         err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
3020         if (err < 0)
3021                 return err;
3022
3023         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3024         if (IS_ERR(sor->vdd_pll_supply))
3025                 return PTR_ERR(sor->vdd_pll_supply);
3026
3027         err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
3028         if (err < 0)
3029                 return err;
3030
3031         return 0;
3032 }
3033
3034 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3035         .name = "DP",
3036         .probe = tegra_sor_dp_probe,
3037 };
3038
3039 static int tegra_sor_init(struct host1x_client *client)
3040 {
3041         struct drm_device *drm = dev_get_drvdata(client->host);
3042         const struct drm_encoder_helper_funcs *helpers = NULL;
3043         struct tegra_sor *sor = host1x_client_to_sor(client);
3044         int connector = DRM_MODE_CONNECTOR_Unknown;
3045         int encoder = DRM_MODE_ENCODER_NONE;
3046         int err;
3047
3048         if (!sor->aux) {
3049                 if (sor->ops == &tegra_sor_hdmi_ops) {
3050                         connector = DRM_MODE_CONNECTOR_HDMIA;
3051                         encoder = DRM_MODE_ENCODER_TMDS;
3052                         helpers = &tegra_sor_hdmi_helpers;
3053                 } else if (sor->soc->supports_lvds) {
3054                         connector = DRM_MODE_CONNECTOR_LVDS;
3055                         encoder = DRM_MODE_ENCODER_LVDS;
3056                 }
3057         } else {
3058                 if (sor->output.panel) {
3059                         connector = DRM_MODE_CONNECTOR_eDP;
3060                         encoder = DRM_MODE_ENCODER_TMDS;
3061                         helpers = &tegra_sor_dp_helpers;
3062                 } else {
3063                         connector = DRM_MODE_CONNECTOR_DisplayPort;
3064                         encoder = DRM_MODE_ENCODER_TMDS;
3065                         helpers = &tegra_sor_dp_helpers;
3066                 }
3067
3068                 sor->link.ops = &tegra_sor_dp_link_ops;
3069                 sor->link.aux = sor->aux;
3070         }
3071
3072         sor->output.dev = sor->dev;
3073
3074         drm_connector_init_with_ddc(drm, &sor->output.connector,
3075                                     &tegra_sor_connector_funcs,
3076                                     connector,
3077                                     sor->output.ddc);
3078         drm_connector_helper_add(&sor->output.connector,
3079                                  &tegra_sor_connector_helper_funcs);
3080         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3081
3082         drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3083         drm_encoder_helper_add(&sor->output.encoder, helpers);
3084
3085         drm_connector_attach_encoder(&sor->output.connector,
3086                                           &sor->output.encoder);
3087         drm_connector_register(&sor->output.connector);
3088
3089         err = tegra_output_init(drm, &sor->output);
3090         if (err < 0) {
3091                 dev_err(client->dev, "failed to initialize output: %d\n", err);
3092                 return err;
3093         }
3094
3095         tegra_output_find_possible_crtcs(&sor->output, drm);
3096
3097         if (sor->aux) {
3098                 err = drm_dp_aux_attach(sor->aux, &sor->output);
3099                 if (err < 0) {
3100                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
3101                         return err;
3102                 }
3103         }
3104
3105         /*
3106          * XXX: Remove this reset once proper hand-over from firmware to
3107          * kernel is possible.
3108          */
3109         if (sor->rst) {
3110                 err = pm_runtime_resume_and_get(sor->dev);
3111                 if (err < 0) {
3112                         dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3113                         return err;
3114                 }
3115
3116                 err = reset_control_acquire(sor->rst);
3117                 if (err < 0) {
3118                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3119                                 err);
3120                         goto rpm_put;
3121                 }
3122
3123                 err = reset_control_assert(sor->rst);
3124                 if (err < 0) {
3125                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3126                                 err);
3127                         goto rpm_put;
3128                 }
3129         }
3130
3131         err = clk_prepare_enable(sor->clk);
3132         if (err < 0) {
3133                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3134                 goto rpm_put;
3135         }
3136
3137         usleep_range(1000, 3000);
3138
3139         if (sor->rst) {
3140                 err = reset_control_deassert(sor->rst);
3141                 if (err < 0) {
3142                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3143                                 err);
3144                         clk_disable_unprepare(sor->clk);
3145                         goto rpm_put;
3146                 }
3147
3148                 reset_control_release(sor->rst);
3149                 pm_runtime_put(sor->dev);
3150         }
3151
3152         err = clk_prepare_enable(sor->clk_safe);
3153         if (err < 0) {
3154                 clk_disable_unprepare(sor->clk);
3155                 return err;
3156         }
3157
3158         err = clk_prepare_enable(sor->clk_dp);
3159         if (err < 0) {
3160                 clk_disable_unprepare(sor->clk_safe);
3161                 clk_disable_unprepare(sor->clk);
3162                 return err;
3163         }
3164
3165         return 0;
3166
3167 rpm_put:
3168         if (sor->rst)
3169                 pm_runtime_put(sor->dev);
3170
3171         return err;
3172 }
3173
3174 static int tegra_sor_exit(struct host1x_client *client)
3175 {
3176         struct tegra_sor *sor = host1x_client_to_sor(client);
3177         int err;
3178
3179         tegra_output_exit(&sor->output);
3180
3181         if (sor->aux) {
3182                 err = drm_dp_aux_detach(sor->aux);
3183                 if (err < 0) {
3184                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
3185                         return err;
3186                 }
3187         }
3188
3189         clk_disable_unprepare(sor->clk_safe);
3190         clk_disable_unprepare(sor->clk_dp);
3191         clk_disable_unprepare(sor->clk);
3192
3193         return 0;
3194 }
3195
3196 static int tegra_sor_runtime_suspend(struct host1x_client *client)
3197 {
3198         struct tegra_sor *sor = host1x_client_to_sor(client);
3199         struct device *dev = client->dev;
3200         int err;
3201
3202         if (sor->rst) {
3203                 err = reset_control_assert(sor->rst);
3204                 if (err < 0) {
3205                         dev_err(dev, "failed to assert reset: %d\n", err);
3206                         return err;
3207                 }
3208
3209                 reset_control_release(sor->rst);
3210         }
3211
3212         usleep_range(1000, 2000);
3213
3214         clk_disable_unprepare(sor->clk);
3215         pm_runtime_put_sync(dev);
3216
3217         return 0;
3218 }
3219
3220 static int tegra_sor_runtime_resume(struct host1x_client *client)
3221 {
3222         struct tegra_sor *sor = host1x_client_to_sor(client);
3223         struct device *dev = client->dev;
3224         int err;
3225
3226         err = pm_runtime_resume_and_get(dev);
3227         if (err < 0) {
3228                 dev_err(dev, "failed to get runtime PM: %d\n", err);
3229                 return err;
3230         }
3231
3232         err = clk_prepare_enable(sor->clk);
3233         if (err < 0) {
3234                 dev_err(dev, "failed to enable clock: %d\n", err);
3235                 goto put_rpm;
3236         }
3237
3238         usleep_range(1000, 2000);
3239
3240         if (sor->rst) {
3241                 err = reset_control_acquire(sor->rst);
3242                 if (err < 0) {
3243                         dev_err(dev, "failed to acquire reset: %d\n", err);
3244                         goto disable_clk;
3245                 }
3246
3247                 err = reset_control_deassert(sor->rst);
3248                 if (err < 0) {
3249                         dev_err(dev, "failed to deassert reset: %d\n", err);
3250                         goto release_reset;
3251                 }
3252         }
3253
3254         return 0;
3255
3256 release_reset:
3257         reset_control_release(sor->rst);
3258 disable_clk:
3259         clk_disable_unprepare(sor->clk);
3260 put_rpm:
3261         pm_runtime_put_sync(dev);
3262         return err;
3263 }
3264
3265 static const struct host1x_client_ops sor_client_ops = {
3266         .init = tegra_sor_init,
3267         .exit = tegra_sor_exit,
3268         .suspend = tegra_sor_runtime_suspend,
3269         .resume = tegra_sor_runtime_resume,
3270 };
3271
3272 static const u8 tegra124_sor_xbar_cfg[5] = {
3273         0, 1, 2, 3, 4
3274 };
3275
3276 static const struct tegra_sor_regs tegra124_sor_regs = {
3277         .head_state0 = 0x05,
3278         .head_state1 = 0x07,
3279         .head_state2 = 0x09,
3280         .head_state3 = 0x0b,
3281         .head_state4 = 0x0d,
3282         .head_state5 = 0x0f,
3283         .pll0 = 0x17,
3284         .pll1 = 0x18,
3285         .pll2 = 0x19,
3286         .pll3 = 0x1a,
3287         .dp_padctl0 = 0x5c,
3288         .dp_padctl2 = 0x73,
3289 };
3290
3291 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3292 static const u8 tegra124_sor_lane_map[4] = {
3293         2, 1, 0, 3,
3294 };
3295
3296 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3297         {
3298                 { 0x13, 0x19, 0x1e, 0x28 },
3299                 { 0x1e, 0x25, 0x2d, },
3300                 { 0x28, 0x32, },
3301                 { 0x3c, },
3302         }, {
3303                 { 0x12, 0x17, 0x1b, 0x25 },
3304                 { 0x1c, 0x23, 0x2a, },
3305                 { 0x25, 0x2f, },
3306                 { 0x39, }
3307         }, {
3308                 { 0x12, 0x16, 0x1a, 0x22 },
3309                 { 0x1b, 0x20, 0x27, },
3310                 { 0x24, 0x2d, },
3311                 { 0x36, },
3312         }, {
3313                 { 0x11, 0x14, 0x17, 0x1f },
3314                 { 0x19, 0x1e, 0x24, },
3315                 { 0x22, 0x2a, },
3316                 { 0x32, },
3317         },
3318 };
3319
3320 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3321         {
3322                 { 0x00, 0x09, 0x13, 0x25 },
3323                 { 0x00, 0x0f, 0x1e, },
3324                 { 0x00, 0x14, },
3325                 { 0x00, },
3326         }, {
3327                 { 0x00, 0x0a, 0x14, 0x28 },
3328                 { 0x00, 0x0f, 0x1e, },
3329                 { 0x00, 0x14, },
3330                 { 0x00 },
3331         }, {
3332                 { 0x00, 0x0a, 0x14, 0x28 },
3333                 { 0x00, 0x0f, 0x1e, },
3334                 { 0x00, 0x14, },
3335                 { 0x00, },
3336         }, {
3337                 { 0x00, 0x0a, 0x14, 0x28 },
3338                 { 0x00, 0x0f, 0x1e, },
3339                 { 0x00, 0x14, },
3340                 { 0x00, },
3341         },
3342 };
3343
3344 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3345         {
3346                 { 0x00, 0x00, 0x00, 0x00 },
3347                 { 0x00, 0x00, 0x00, },
3348                 { 0x00, 0x00, },
3349                 { 0x00, },
3350         }, {
3351                 { 0x02, 0x02, 0x04, 0x05 },
3352                 { 0x02, 0x04, 0x05, },
3353                 { 0x04, 0x05, },
3354                 { 0x05, },
3355         }, {
3356                 { 0x04, 0x05, 0x08, 0x0b },
3357                 { 0x05, 0x09, 0x0b, },
3358                 { 0x08, 0x0a, },
3359                 { 0x0b, },
3360         }, {
3361                 { 0x05, 0x09, 0x0b, 0x12 },
3362                 { 0x09, 0x0d, 0x12, },
3363                 { 0x0b, 0x0f, },
3364                 { 0x12, },
3365         },
3366 };
3367
3368 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3369         {
3370                 { 0x20, 0x30, 0x40, 0x60 },
3371                 { 0x30, 0x40, 0x60, },
3372                 { 0x40, 0x60, },
3373                 { 0x60, },
3374         }, {
3375                 { 0x20, 0x20, 0x30, 0x50 },
3376                 { 0x30, 0x40, 0x50, },
3377                 { 0x40, 0x50, },
3378                 { 0x60, },
3379         }, {
3380                 { 0x20, 0x20, 0x30, 0x40, },
3381                 { 0x30, 0x30, 0x40, },
3382                 { 0x40, 0x50, },
3383                 { 0x60, },
3384         }, {
3385                 { 0x20, 0x20, 0x20, 0x40, },
3386                 { 0x30, 0x30, 0x40, },
3387                 { 0x40, 0x40, },
3388                 { 0x60, },
3389         },
3390 };
3391
3392 static const struct tegra_sor_soc tegra124_sor = {
3393         .supports_lvds = true,
3394         .supports_hdmi = false,
3395         .supports_dp = true,
3396         .supports_audio = false,
3397         .supports_hdcp = false,
3398         .regs = &tegra124_sor_regs,
3399         .has_nvdisplay = false,
3400         .xbar_cfg = tegra124_sor_xbar_cfg,
3401         .lane_map = tegra124_sor_lane_map,
3402         .voltage_swing = tegra124_sor_voltage_swing,
3403         .pre_emphasis = tegra124_sor_pre_emphasis,
3404         .post_cursor = tegra124_sor_post_cursor,
3405         .tx_pu = tegra124_sor_tx_pu,
3406 };
3407
3408 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3409         {
3410                 { 0x00, 0x08, 0x12, 0x24 },
3411                 { 0x01, 0x0e, 0x1d, },
3412                 { 0x01, 0x13, },
3413                 { 0x00, },
3414         }, {
3415                 { 0x00, 0x08, 0x12, 0x24 },
3416                 { 0x00, 0x0e, 0x1d, },
3417                 { 0x00, 0x13, },
3418                 { 0x00 },
3419         }, {
3420                 { 0x00, 0x08, 0x12, 0x24 },
3421                 { 0x00, 0x0e, 0x1d, },
3422                 { 0x00, 0x13, },
3423                 { 0x00, },
3424         }, {
3425                 { 0x00, 0x08, 0x12, 0x24 },
3426                 { 0x00, 0x0e, 0x1d, },
3427                 { 0x00, 0x13, },
3428                 { 0x00, },
3429         },
3430 };
3431
3432 static const struct tegra_sor_soc tegra132_sor = {
3433         .supports_lvds = true,
3434         .supports_hdmi = false,
3435         .supports_dp = true,
3436         .supports_audio = false,
3437         .supports_hdcp = false,
3438         .regs = &tegra124_sor_regs,
3439         .has_nvdisplay = false,
3440         .xbar_cfg = tegra124_sor_xbar_cfg,
3441         .lane_map = tegra124_sor_lane_map,
3442         .voltage_swing = tegra124_sor_voltage_swing,
3443         .pre_emphasis = tegra132_sor_pre_emphasis,
3444         .post_cursor = tegra124_sor_post_cursor,
3445         .tx_pu = tegra124_sor_tx_pu,
3446 };
3447
3448 static const struct tegra_sor_regs tegra210_sor_regs = {
3449         .head_state0 = 0x05,
3450         .head_state1 = 0x07,
3451         .head_state2 = 0x09,
3452         .head_state3 = 0x0b,
3453         .head_state4 = 0x0d,
3454         .head_state5 = 0x0f,
3455         .pll0 = 0x17,
3456         .pll1 = 0x18,
3457         .pll2 = 0x19,
3458         .pll3 = 0x1a,
3459         .dp_padctl0 = 0x5c,
3460         .dp_padctl2 = 0x73,
3461 };
3462
3463 static const u8 tegra210_sor_xbar_cfg[5] = {
3464         2, 1, 0, 3, 4
3465 };
3466
3467 static const u8 tegra210_sor_lane_map[4] = {
3468         0, 1, 2, 3,
3469 };
3470
3471 static const struct tegra_sor_soc tegra210_sor = {
3472         .supports_lvds = false,
3473         .supports_hdmi = false,
3474         .supports_dp = true,
3475         .supports_audio = false,
3476         .supports_hdcp = false,
3477
3478         .regs = &tegra210_sor_regs,
3479         .has_nvdisplay = false,
3480
3481         .xbar_cfg = tegra210_sor_xbar_cfg,
3482         .lane_map = tegra210_sor_lane_map,
3483         .voltage_swing = tegra124_sor_voltage_swing,
3484         .pre_emphasis = tegra124_sor_pre_emphasis,
3485         .post_cursor = tegra124_sor_post_cursor,
3486         .tx_pu = tegra124_sor_tx_pu,
3487 };
3488
3489 static const struct tegra_sor_soc tegra210_sor1 = {
3490         .supports_lvds = false,
3491         .supports_hdmi = true,
3492         .supports_dp = true,
3493         .supports_audio = true,
3494         .supports_hdcp = true,
3495
3496         .regs = &tegra210_sor_regs,
3497         .has_nvdisplay = false,
3498
3499         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3500         .settings = tegra210_sor_hdmi_defaults,
3501         .xbar_cfg = tegra210_sor_xbar_cfg,
3502         .lane_map = tegra210_sor_lane_map,
3503         .voltage_swing = tegra124_sor_voltage_swing,
3504         .pre_emphasis = tegra124_sor_pre_emphasis,
3505         .post_cursor = tegra124_sor_post_cursor,
3506         .tx_pu = tegra124_sor_tx_pu,
3507 };
3508
3509 static const struct tegra_sor_regs tegra186_sor_regs = {
3510         .head_state0 = 0x151,
3511         .head_state1 = 0x154,
3512         .head_state2 = 0x157,
3513         .head_state3 = 0x15a,
3514         .head_state4 = 0x15d,
3515         .head_state5 = 0x160,
3516         .pll0 = 0x163,
3517         .pll1 = 0x164,
3518         .pll2 = 0x165,
3519         .pll3 = 0x166,
3520         .dp_padctl0 = 0x168,
3521         .dp_padctl2 = 0x16a,
3522 };
3523
3524 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3525         {
3526                 { 0x13, 0x19, 0x1e, 0x28 },
3527                 { 0x1e, 0x25, 0x2d, },
3528                 { 0x28, 0x32, },
3529                 { 0x39, },
3530         }, {
3531                 { 0x12, 0x16, 0x1b, 0x25 },
3532                 { 0x1c, 0x23, 0x2a, },
3533                 { 0x25, 0x2f, },
3534                 { 0x37, }
3535         }, {
3536                 { 0x12, 0x16, 0x1a, 0x22 },
3537                 { 0x1b, 0x20, 0x27, },
3538                 { 0x24, 0x2d, },
3539                 { 0x35, },
3540         }, {
3541                 { 0x11, 0x14, 0x17, 0x1f },
3542                 { 0x19, 0x1e, 0x24, },
3543                 { 0x22, 0x2a, },
3544                 { 0x32, },
3545         },
3546 };
3547
3548 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3549         {
3550                 { 0x00, 0x08, 0x12, 0x24 },
3551                 { 0x01, 0x0e, 0x1d, },
3552                 { 0x01, 0x13, },
3553                 { 0x00, },
3554         }, {
3555                 { 0x00, 0x08, 0x12, 0x24 },
3556                 { 0x00, 0x0e, 0x1d, },
3557                 { 0x00, 0x13, },
3558                 { 0x00 },
3559         }, {
3560                 { 0x00, 0x08, 0x14, 0x24 },
3561                 { 0x00, 0x0e, 0x1d, },
3562                 { 0x00, 0x13, },
3563                 { 0x00, },
3564         }, {
3565                 { 0x00, 0x08, 0x12, 0x24 },
3566                 { 0x00, 0x0e, 0x1d, },
3567                 { 0x00, 0x13, },
3568                 { 0x00, },
3569         },
3570 };
3571
3572 static const struct tegra_sor_soc tegra186_sor = {
3573         .supports_lvds = false,
3574         .supports_hdmi = true,
3575         .supports_dp = true,
3576         .supports_audio = true,
3577         .supports_hdcp = true,
3578
3579         .regs = &tegra186_sor_regs,
3580         .has_nvdisplay = true,
3581
3582         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3583         .settings = tegra186_sor_hdmi_defaults,
3584         .xbar_cfg = tegra124_sor_xbar_cfg,
3585         .lane_map = tegra124_sor_lane_map,
3586         .voltage_swing = tegra186_sor_voltage_swing,
3587         .pre_emphasis = tegra186_sor_pre_emphasis,
3588         .post_cursor = tegra124_sor_post_cursor,
3589         .tx_pu = tegra124_sor_tx_pu,
3590 };
3591
3592 static const struct tegra_sor_regs tegra194_sor_regs = {
3593         .head_state0 = 0x151,
3594         .head_state1 = 0x155,
3595         .head_state2 = 0x159,
3596         .head_state3 = 0x15d,
3597         .head_state4 = 0x161,
3598         .head_state5 = 0x165,
3599         .pll0 = 0x169,
3600         .pll1 = 0x16a,
3601         .pll2 = 0x16b,
3602         .pll3 = 0x16c,
3603         .dp_padctl0 = 0x16e,
3604         .dp_padctl2 = 0x16f,
3605 };
3606
3607 static const struct tegra_sor_soc tegra194_sor = {
3608         .supports_lvds = false,
3609         .supports_hdmi = true,
3610         .supports_dp = true,
3611         .supports_audio = true,
3612         .supports_hdcp = true,
3613
3614         .regs = &tegra194_sor_regs,
3615         .has_nvdisplay = true,
3616
3617         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3618         .settings = tegra194_sor_hdmi_defaults,
3619
3620         .xbar_cfg = tegra210_sor_xbar_cfg,
3621         .lane_map = tegra124_sor_lane_map,
3622         .voltage_swing = tegra186_sor_voltage_swing,
3623         .pre_emphasis = tegra186_sor_pre_emphasis,
3624         .post_cursor = tegra124_sor_post_cursor,
3625         .tx_pu = tegra124_sor_tx_pu,
3626 };
3627
3628 static const struct of_device_id tegra_sor_of_match[] = {
3629         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3630         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3631         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3632         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3633         { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3634         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3635         { },
3636 };
3637 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3638
3639 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3640 {
3641         struct device_node *np = sor->dev->of_node;
3642         u32 xbar_cfg[5];
3643         unsigned int i;
3644         u32 value;
3645         int err;
3646
3647         if (sor->soc->has_nvdisplay) {
3648                 err = of_property_read_u32(np, "nvidia,interface", &value);
3649                 if (err < 0)
3650                         return err;
3651
3652                 sor->index = value;
3653
3654                 /*
3655                  * override the default that we already set for Tegra210 and
3656                  * earlier
3657                  */
3658                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3659         } else {
3660                 if (!sor->soc->supports_audio)
3661                         sor->index = 0;
3662                 else
3663                         sor->index = 1;
3664         }
3665
3666         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3667         if (err < 0) {
3668                 /* fall back to default per-SoC XBAR configuration */
3669                 for (i = 0; i < 5; i++)
3670                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3671         } else {
3672                 /* copy cells to SOR XBAR configuration */
3673                 for (i = 0; i < 5; i++)
3674                         sor->xbar_cfg[i] = xbar_cfg[i];
3675         }
3676
3677         return 0;
3678 }
3679
3680 static irqreturn_t tegra_sor_irq(int irq, void *data)
3681 {
3682         struct tegra_sor *sor = data;
3683         u32 value;
3684
3685         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3686         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3687
3688         if (value & SOR_INT_CODEC_SCRATCH0) {
3689                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3690
3691                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3692                         unsigned int format;
3693
3694                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3695
3696                         tegra_hda_parse_format(format, &sor->format);
3697
3698                         if (sor->ops->audio_enable)
3699                                 sor->ops->audio_enable(sor);
3700                 } else {
3701                         if (sor->ops->audio_disable)
3702                                 sor->ops->audio_disable(sor);
3703                 }
3704         }
3705
3706         return IRQ_HANDLED;
3707 }
3708
3709 static int tegra_sor_probe(struct platform_device *pdev)
3710 {
3711         struct device_node *np;
3712         struct tegra_sor *sor;
3713         int err;
3714
3715         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3716         if (!sor)
3717                 return -ENOMEM;
3718
3719         sor->soc = of_device_get_match_data(&pdev->dev);
3720         sor->output.dev = sor->dev = &pdev->dev;
3721
3722         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3723                                      sor->soc->num_settings *
3724                                         sizeof(*sor->settings),
3725                                      GFP_KERNEL);
3726         if (!sor->settings)
3727                 return -ENOMEM;
3728
3729         sor->num_settings = sor->soc->num_settings;
3730
3731         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3732         if (np) {
3733                 sor->aux = drm_dp_aux_find_by_of_node(np);
3734                 of_node_put(np);
3735
3736                 if (!sor->aux)
3737                         return -EPROBE_DEFER;
3738
3739                 if (get_device(sor->aux->dev))
3740                         sor->output.ddc = &sor->aux->ddc;
3741         }
3742
3743         if (!sor->aux) {
3744                 if (sor->soc->supports_hdmi) {
3745                         sor->ops = &tegra_sor_hdmi_ops;
3746                         sor->pad = TEGRA_IO_PAD_HDMI;
3747                 } else if (sor->soc->supports_lvds) {
3748                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3749                         return -ENODEV;
3750                 } else {
3751                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3752                         return -ENODEV;
3753                 }
3754         } else {
3755                 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3756                 /*
3757                  * No need to keep this around since we only use it as a check
3758                  * to see if a panel is connected (eDP) or not (DP).
3759                  */
3760                 of_node_put(np);
3761
3762                 sor->ops = &tegra_sor_dp_ops;
3763                 sor->pad = TEGRA_IO_PAD_LVDS;
3764         }
3765
3766         err = tegra_sor_parse_dt(sor);
3767         if (err < 0)
3768                 goto put_aux;
3769
3770         err = tegra_output_probe(&sor->output);
3771         if (err < 0) {
3772                 dev_err_probe(&pdev->dev, err, "failed to probe output\n");
3773                 goto put_aux;
3774         }
3775
3776         if (sor->ops && sor->ops->probe) {
3777                 err = sor->ops->probe(sor);
3778                 if (err < 0) {
3779                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3780                                 sor->ops->name, err);
3781                         goto remove;
3782                 }
3783         }
3784
3785         sor->regs = devm_platform_ioremap_resource(pdev, 0);
3786         if (IS_ERR(sor->regs)) {
3787                 err = PTR_ERR(sor->regs);
3788                 goto remove;
3789         }
3790
3791         err = platform_get_irq(pdev, 0);
3792         if (err < 0)
3793                 goto remove;
3794
3795         sor->irq = err;
3796
3797         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3798                                dev_name(sor->dev), sor);
3799         if (err < 0) {
3800                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3801                 goto remove;
3802         }
3803
3804         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3805         if (IS_ERR(sor->rst)) {
3806                 err = PTR_ERR(sor->rst);
3807
3808                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3809                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3810                                 err);
3811                         goto remove;
3812                 }
3813
3814                 /*
3815                  * At this point, the reset control is most likely being used
3816                  * by the generic power domain implementation. With any luck
3817                  * the power domain will have taken care of resetting the SOR
3818                  * and we don't have to do anything.
3819                  */
3820                 sor->rst = NULL;
3821         }
3822
3823         sor->clk = devm_clk_get(&pdev->dev, NULL);
3824         if (IS_ERR(sor->clk)) {
3825                 err = PTR_ERR(sor->clk);
3826                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3827                 goto remove;
3828         }
3829
3830         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3831                 struct device_node *np = pdev->dev.of_node;
3832                 const char *name;
3833
3834                 /*
3835                  * For backwards compatibility with Tegra210 device trees,
3836                  * fall back to the old clock name "source" if the new "out"
3837                  * clock is not available.
3838                  */
3839                 if (of_property_match_string(np, "clock-names", "out") < 0)
3840                         name = "source";
3841                 else
3842                         name = "out";
3843
3844                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3845                 if (IS_ERR(sor->clk_out)) {
3846                         err = PTR_ERR(sor->clk_out);
3847                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3848                                 name, err);
3849                         goto remove;
3850                 }
3851         } else {
3852                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3853                 sor->clk_out = sor->clk;
3854         }
3855
3856         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3857         if (IS_ERR(sor->clk_parent)) {
3858                 err = PTR_ERR(sor->clk_parent);
3859                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3860                 goto remove;
3861         }
3862
3863         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3864         if (IS_ERR(sor->clk_safe)) {
3865                 err = PTR_ERR(sor->clk_safe);
3866                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3867                 goto remove;
3868         }
3869
3870         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3871         if (IS_ERR(sor->clk_dp)) {
3872                 err = PTR_ERR(sor->clk_dp);
3873                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3874                 goto remove;
3875         }
3876
3877         /*
3878          * Starting with Tegra186, the BPMP provides an implementation for
3879          * the pad output clock, so we have to look it up from device tree.
3880          */
3881         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3882         if (IS_ERR(sor->clk_pad)) {
3883                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3884                         err = PTR_ERR(sor->clk_pad);
3885                         goto remove;
3886                 }
3887
3888                 /*
3889                  * If the pad output clock is not available, then we assume
3890                  * we're on Tegra210 or earlier and have to provide our own
3891                  * implementation.
3892                  */
3893                 sor->clk_pad = NULL;
3894         }
3895
3896         /*
3897          * The bootloader may have set up the SOR such that it's module clock
3898          * is sourced by one of the display PLLs. However, that doesn't work
3899          * without properly having set up other bits of the SOR.
3900          */
3901         err = clk_set_parent(sor->clk_out, sor->clk_safe);
3902         if (err < 0) {
3903                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3904                 goto remove;
3905         }
3906
3907         platform_set_drvdata(pdev, sor);
3908         pm_runtime_enable(&pdev->dev);
3909
3910         host1x_client_init(&sor->client);
3911         sor->client.ops = &sor_client_ops;
3912         sor->client.dev = &pdev->dev;
3913
3914         /*
3915          * On Tegra210 and earlier, provide our own implementation for the
3916          * pad output clock.
3917          */
3918         if (!sor->clk_pad) {
3919                 char *name;
3920
3921                 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3922                                       sor->index);
3923                 if (!name) {
3924                         err = -ENOMEM;
3925                         goto uninit;
3926                 }
3927
3928                 err = host1x_client_resume(&sor->client);
3929                 if (err < 0) {
3930                         dev_err(sor->dev, "failed to resume: %d\n", err);
3931                         goto uninit;
3932                 }
3933
3934                 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3935                 host1x_client_suspend(&sor->client);
3936         }
3937
3938         if (IS_ERR(sor->clk_pad)) {
3939                 err = PTR_ERR(sor->clk_pad);
3940                 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3941                         err);
3942                 goto uninit;
3943         }
3944
3945         err = __host1x_client_register(&sor->client);
3946         if (err < 0) {
3947                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3948                         err);
3949                 goto uninit;
3950         }
3951
3952         return 0;
3953
3954 uninit:
3955         host1x_client_exit(&sor->client);
3956         pm_runtime_disable(&pdev->dev);
3957 remove:
3958         if (sor->aux)
3959                 sor->output.ddc = NULL;
3960
3961         tegra_output_remove(&sor->output);
3962 put_aux:
3963         if (sor->aux)
3964                 put_device(sor->aux->dev);
3965
3966         return err;
3967 }
3968
3969 static void tegra_sor_remove(struct platform_device *pdev)
3970 {
3971         struct tegra_sor *sor = platform_get_drvdata(pdev);
3972
3973         host1x_client_unregister(&sor->client);
3974
3975         pm_runtime_disable(&pdev->dev);
3976
3977         if (sor->aux) {
3978                 put_device(sor->aux->dev);
3979                 sor->output.ddc = NULL;
3980         }
3981
3982         tegra_output_remove(&sor->output);
3983 }
3984
3985 static int __maybe_unused tegra_sor_suspend(struct device *dev)
3986 {
3987         struct tegra_sor *sor = dev_get_drvdata(dev);
3988         int err;
3989
3990         err = tegra_output_suspend(&sor->output);
3991         if (err < 0) {
3992                 dev_err(dev, "failed to suspend output: %d\n", err);
3993                 return err;
3994         }
3995
3996         if (sor->hdmi_supply) {
3997                 err = regulator_disable(sor->hdmi_supply);
3998                 if (err < 0) {
3999                         tegra_output_resume(&sor->output);
4000                         return err;
4001                 }
4002         }
4003
4004         return 0;
4005 }
4006
4007 static int __maybe_unused tegra_sor_resume(struct device *dev)
4008 {
4009         struct tegra_sor *sor = dev_get_drvdata(dev);
4010         int err;
4011
4012         if (sor->hdmi_supply) {
4013                 err = regulator_enable(sor->hdmi_supply);
4014                 if (err < 0)
4015                         return err;
4016         }
4017
4018         err = tegra_output_resume(&sor->output);
4019         if (err < 0) {
4020                 dev_err(dev, "failed to resume output: %d\n", err);
4021
4022                 if (sor->hdmi_supply)
4023                         regulator_disable(sor->hdmi_supply);
4024
4025                 return err;
4026         }
4027
4028         return 0;
4029 }
4030
4031 static const struct dev_pm_ops tegra_sor_pm_ops = {
4032         SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4033 };
4034
4035 struct platform_driver tegra_sor_driver = {
4036         .driver = {
4037                 .name = "tegra-sor",
4038                 .of_match_table = tegra_sor_of_match,
4039                 .pm = &tegra_sor_pm_ops,
4040         },
4041         .probe = tegra_sor_probe,
4042         .remove_new = tegra_sor_remove,
4043 };