drivers/gpu/drm/amd/include/mes_v11_api_def.h

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __MES_API_DEF_H__
  25 #define __MES_API_DEF_H__
  26
  27 #pragma pack(push, 4)
  28
  29 #define MES_API_VERSION 1
  30
  31 /* Driver submits one API(cmd) as a single Frame and this command size is same
  32  * for all API to ease the debugging and parsing of ring buffer.
  33  */
  34 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
  35
  36 /* To avoid command in scheduler context to be overwritten whenenver mutilple
  37  * interrupts come in, this creates another queue.
  38  */
  39 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
  40
  41 enum MES_API_TYPE {
  42         MES_API_TYPE_SCHEDULER = 1,
  43         MES_API_TYPE_MAX
  44 };
  45
  46 enum MES_SCH_API_OPCODE {
  47         MES_SCH_API_SET_HW_RSRC                 = 0,
  48         MES_SCH_API_SET_SCHEDULING_CONFIG       = 1, /* agreegated db, quantums, etc */
  49         MES_SCH_API_ADD_QUEUE                   = 2,
  50         MES_SCH_API_REMOVE_QUEUE                = 3,
  51         MES_SCH_API_PERFORM_YIELD               = 4,
  52         MES_SCH_API_SET_GANG_PRIORITY_LEVEL     = 5,
  53         MES_SCH_API_SUSPEND                     = 6,
  54         MES_SCH_API_RESUME                      = 7,
  55         MES_SCH_API_RESET                       = 8,
  56         MES_SCH_API_SET_LOG_BUFFER              = 9,
  57         MES_SCH_API_CHANGE_GANG_PRORITY         = 10,
  58         MES_SCH_API_QUERY_SCHEDULER_STATUS      = 11,
  59         MES_SCH_API_PROGRAM_GDS                 = 12,
  60         MES_SCH_API_SET_DEBUG_VMID              = 13,
  61         MES_SCH_API_MISC                        = 14,
  62         MES_SCH_API_UPDATE_ROOT_PAGE_TABLE      = 15,
  63         MES_SCH_API_AMD_LOG                     = 16,
  64         MES_SCH_API_MAX                         = 0xFF
  65 };
  66
  67 union MES_API_HEADER {
  68         struct {
  69                 uint32_t type           : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
  70                 uint32_t opcode         : 8;
  71                 uint32_t dwsize         : 8; /* including header */
  72                 uint32_t reserved       : 12;
  73         };
  74
  75         uint32_t        u32All;
  76 };
  77
  78 enum MES_AMD_PRIORITY_LEVEL {
  79         AMD_PRIORITY_LEVEL_LOW          = 0,
  80         AMD_PRIORITY_LEVEL_NORMAL       = 1,
  81         AMD_PRIORITY_LEVEL_MEDIUM       = 2,
  82         AMD_PRIORITY_LEVEL_HIGH         = 3,
  83         AMD_PRIORITY_LEVEL_REALTIME     = 4,
  84         AMD_PRIORITY_NUM_LEVELS
  85 };
  86
  87 enum MES_QUEUE_TYPE {
  88         MES_QUEUE_TYPE_GFX,
  89         MES_QUEUE_TYPE_COMPUTE,
  90         MES_QUEUE_TYPE_SDMA,
  91         MES_QUEUE_TYPE_MAX,
  92 };
  93
  94 struct MES_API_STATUS {
  95         uint64_t        api_completion_fence_addr;
  96         uint64_t        api_completion_fence_value;
  97 };
  98
  99 enum { MAX_COMPUTE_PIPES = 8 };
 100 enum { MAX_GFX_PIPES = 2 };
 101 enum { MAX_SDMA_PIPES = 2 };
 102
 103 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
 104 enum { MAX_GFX_HQD_PER_PIPE = 8 };
 105 enum { MAX_SDMA_HQD_PER_PIPE = 10 };
 106 enum { MAX_SDMA_HQD_PER_PIPE_11_0   = 8 };
 107
 108 enum { MAX_QUEUES_IN_A_GANG = 8 };
 109
 110 enum VM_HUB_TYPE {
 111         VM_HUB_TYPE_GC = 0,
 112         VM_HUB_TYPE_MM = 1,
 113         VM_HUB_TYPE_MAX,
 114 };
 115
 116 enum { VMID_INVALID = 0xffff };
 117
 118 enum { MAX_VMID_GCHUB = 16 };
 119 enum { MAX_VMID_MMHUB = 16 };
 120
 121 enum SET_DEBUG_VMID_OPERATIONS {
 122         DEBUG_VMID_OP_PROGRAM = 0,
 123         DEBUG_VMID_OP_ALLOCATE = 1,
 124         DEBUG_VMID_OP_RELEASE = 2
 125 };
 126
 127 enum MES_LOG_OPERATION {
 128         MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
 129         MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
 130         MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
 131         MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
 132         MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
 133         MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
 134 };
 135
 136 enum MES_LOG_CONTEXT_STATE {
 137         MES_LOG_CONTEXT_STATE_IDLE              = 0,
 138         MES_LOG_CONTEXT_STATE_RUNNING           = 1,
 139         MES_LOG_CONTEXT_STATE_READY             = 2,
 140         MES_LOG_CONTEXT_STATE_READY_STANDBY     = 3,
 141         MES_LOG_CONTEXT_STATE_INVALID           = 0xF,
 142 };
 143
 144 struct MES_LOG_CONTEXT_STATE_CHANGE {
 145         void                            *h_context;
 146         enum MES_LOG_CONTEXT_STATE      new_context_state;
 147 };
 148
 149 struct MES_LOG_QUEUE_NEW_WORK {
 150         uint64_t                   h_queue;
 151         uint64_t                   reserved;
 152 };
 153
 154 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
 155         uint64_t                   h_queue;
 156         uint64_t                   h_sync_object;
 157 };
 158
 159 struct MES_LOG_QUEUE_NO_MORE_WORK {
 160         uint64_t                   h_queue;
 161         uint64_t                   reserved;
 162 };
 163
 164 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
 165         uint64_t                   h_queue;
 166         uint64_t                   h_sync_object;
 167 };
 168
 169 struct MES_LOG_ENTRY_HEADER {
 170         uint32_t        first_free_entry_index;
 171         uint32_t        wraparound_count;
 172         uint64_t        number_of_entries;
 173         uint64_t        reserved[2];
 174 };
 175
 176 struct MES_LOG_ENTRY_DATA {
 177         uint64_t        gpu_time_stamp;
 178         uint32_t        operation_type; /* operation_type is of MES_LOG_OPERATION type */
 179         uint32_t        reserved_operation_type_bits;
 180         union {
 181                 struct MES_LOG_CONTEXT_STATE_CHANGE     context_state_change;
 182                 struct MES_LOG_QUEUE_NEW_WORK           queue_new_work;
 183                 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
 184                 struct MES_LOG_QUEUE_NO_MORE_WORK       queue_no_more_work;
 185                 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT   queue_wait_sync_object;
 186                 uint64_t                                all[2];
 187         };
 188 };
 189
 190 struct MES_LOG_BUFFER {
 191         struct MES_LOG_ENTRY_HEADER     header;
 192         struct MES_LOG_ENTRY_DATA       entries[1];
 193 };
 194
 195 enum MES_SWIP_TO_HWIP_DEF {
 196         MES_MAX_HWIP_SEGMENT = 8,
 197 };
 198
 199 union MESAPI_SET_HW_RESOURCES {
 200         struct {
 201                 union MES_API_HEADER    header;
 202                 uint32_t                vmid_mask_mmhub;
 203                 uint32_t                vmid_mask_gfxhub;
 204                 uint32_t                gds_size;
 205                 uint32_t                paging_vmid;
 206                 uint32_t                compute_hqd_mask[MAX_COMPUTE_PIPES];
 207                 uint32_t                gfx_hqd_mask[MAX_GFX_PIPES];
 208                 uint32_t                sdma_hqd_mask[MAX_SDMA_PIPES];
 209                 uint32_t                aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
 210                 uint64_t                g_sch_ctx_gpu_mc_ptr;
 211                 uint64_t                query_status_fence_gpu_mc_ptr;
 212                 uint32_t                gc_base[MES_MAX_HWIP_SEGMENT];
 213                 uint32_t                mmhub_base[MES_MAX_HWIP_SEGMENT];
 214                 uint32_t                osssys_base[MES_MAX_HWIP_SEGMENT];
 215                 struct MES_API_STATUS   api_status;
 216                 union {
 217                         struct {
 218                                 uint32_t disable_reset  : 1;
 219                                 uint32_t use_different_vmid_compute : 1;
 220                                 uint32_t disable_mes_log   : 1;
 221                                 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
 222                                 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
 223                                 uint32_t second_gfx_pipe_enabled : 1;
 224                                 uint32_t enable_level_process_quantum_check : 1;
 225                                 uint32_t legacy_sch_mode : 1;
 226                                 uint32_t disable_add_queue_wptr_mc_addr : 1;
 227                                 uint32_t enable_mes_event_int_logging : 1;
 228                                 uint32_t enable_reg_active_poll : 1;
 229                                 uint32_t reserved       : 21;
 230                         };
 231                         uint32_t        uint32_t_all;
 232                 };
 233                 uint32_t        oversubscription_timer;
 234                 uint64_t        doorbell_info;
 235         };
 236
 237         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 238 };
 239
 240 union MESAPI__ADD_QUEUE {
 241         struct {
 242                 union MES_API_HEADER            header;
 243                 uint32_t                        process_id;
 244                 uint64_t                        page_table_base_addr;
 245                 uint64_t                        process_va_start;
 246                 uint64_t                        process_va_end;
 247                 uint64_t                        process_quantum;
 248                 uint64_t                        process_context_addr;
 249                 uint64_t                        gang_quantum;
 250                 uint64_t                        gang_context_addr;
 251                 uint32_t                        inprocess_gang_priority;
 252                 enum MES_AMD_PRIORITY_LEVEL     gang_global_priority_level;
 253                 uint32_t                        doorbell_offset;
 254                 uint64_t                        mqd_addr;
 255                 uint64_t                        wptr_addr;
 256                 uint64_t                        h_context;
 257                 uint64_t                        h_queue;
 258                 enum MES_QUEUE_TYPE             queue_type;
 259                 uint32_t                        gds_base;
 260                 uint32_t                        gds_size;
 261                 uint32_t                        gws_base;
 262                 uint32_t                        gws_size;
 263                 uint32_t                        oa_mask;
 264                 uint64_t                        trap_handler_addr;
 265                 uint32_t                        vm_context_cntl;
 266
 267                 struct {
 268                         uint32_t paging                 : 1;
 269                         uint32_t debug_vmid             : 4;
 270                         uint32_t program_gds            : 1;
 271                         uint32_t is_gang_suspended      : 1;
 272                         uint32_t is_tmz_queue           : 1;
 273                         uint32_t map_kiq_utility_queue  : 1;
 274                         uint32_t is_kfd_process         : 1;
 275                         uint32_t trap_en                : 1;
 276                         uint32_t is_aql_queue           : 1;
 277                         uint32_t reserved               : 20;
 278                 };
 279                 struct MES_API_STATUS           api_status;
 280                 uint64_t                        tma_addr;
 281         };
 282
 283         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 284 };
 285
 286 union MESAPI__REMOVE_QUEUE {
 287         struct {
 288                 union MES_API_HEADER    header;
 289                 uint32_t                doorbell_offset;
 290                 uint64_t                gang_context_addr;
 291
 292                 struct {
 293                         uint32_t unmap_legacy_gfx_queue   : 1;
 294                         uint32_t unmap_kiq_utility_queue  : 1;
 295                         uint32_t preempt_legacy_gfx_queue : 1;
 296                         uint32_t unmap_legacy_queue       : 1;
 297                         uint32_t reserved                 : 28;
 298                 };
 299                 struct MES_API_STATUS       api_status;
 300
 301                 uint32_t                    pipe_id;
 302                 uint32_t                    queue_id;
 303
 304                 uint64_t                    tf_addr;
 305                 uint32_t                    tf_data;
 306
 307                 enum MES_QUEUE_TYPE         queue_type;
 308         };
 309
 310         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 311 };
 312
 313 union MESAPI__SET_SCHEDULING_CONFIG {
 314         struct {
 315                 union MES_API_HEADER    header;
 316                 /* Grace period when preempting another priority band for this
 317                  * priority band. The value for idle priority band is ignored,
 318                  * as it never preempts other bands.
 319                  */
 320                 uint64_t                grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
 321                 /* Default quantum for scheduling across processes within
 322                  * a priority band.
 323                  */
 324                 uint64_t                process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
 325                 /* Default grace period for processes that preempt each other
 326                  * within a priority band.
 327                  */
 328                 uint64_t                process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
 329                 /* For normal level this field specifies the target GPU
 330                  * percentage in situations when it's starved by the high level.
 331                  * Valid values are between 0 and 50, with the default being 10.
 332                  */
 333                 uint32_t                normal_yield_percent;
 334                 struct MES_API_STATUS   api_status;
 335         };
 336
 337         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 338 };
 339
 340 union MESAPI__PERFORM_YIELD {
 341         struct {
 342                 union MES_API_HEADER    header;
 343                 uint32_t                dummy;
 344                 struct MES_API_STATUS   api_status;
 345         };
 346
 347         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 348 };
 349
 350 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
 351         struct {
 352                 union MES_API_HEADER            header;
 353                 uint32_t                        inprocess_gang_priority;
 354                 enum MES_AMD_PRIORITY_LEVEL     gang_global_priority_level;
 355                 uint64_t                        gang_quantum;
 356                 uint64_t                        gang_context_addr;
 357                 struct MES_API_STATUS           api_status;
 358         };
 359
 360         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 361 };
 362
 363 union MESAPI__SUSPEND {
 364         struct {
 365                 union MES_API_HEADER    header;
 366                 /* false - suspend all gangs; true - specific gang */
 367                 struct {
 368                         uint32_t suspend_all_gangs      : 1;
 369                         uint32_t reserved               : 31;
 370                 };
 371                 /* gang_context_addr is valid only if suspend_all = false */
 372                 uint64_t                gang_context_addr;
 373
 374                 uint64_t                suspend_fence_addr;
 375                 uint32_t                suspend_fence_value;
 376
 377                 struct MES_API_STATUS   api_status;
 378         };
 379
 380         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 381 };
 382
 383 union MESAPI__RESUME {
 384         struct {
 385                 union MES_API_HEADER    header;
 386                 /* false - resume all gangs; true - specified gang */
 387                 struct {
 388                         uint32_t resume_all_gangs       : 1;
 389                         uint32_t reserved               : 31;
 390                 };
 391                 /* valid only if resume_all_gangs = false */
 392                 uint64_t                gang_context_addr;
 393
 394                 struct MES_API_STATUS   api_status;
 395         };
 396
 397         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 398 };
 399
 400 union MESAPI__RESET {
 401         struct {
 402                 union MES_API_HEADER            header;
 403
 404                 struct {
 405                         /* Only reset the queue given by doorbell_offset (not entire gang) */
 406                         uint32_t                reset_queue_only : 1;
 407                         /* Hang detection first then reset any queues that are hung */
 408                         uint32_t                hang_detect_then_reset : 1;
 409                         /* Only do hang detection (no reset) */
 410                         uint32_t                hang_detect_only : 1;
 411                         /* Rest HP and LP kernel queues not managed by MES */
 412                         uint32_t                reset_legacy_gfx : 1;
 413                         uint32_t                reserved : 28;
 414                 };
 415
 416                 uint64_t                        gang_context_addr;
 417
 418                 /* valid only if reset_queue_only = true */
 419                 uint32_t                        doorbell_offset;
 420
 421                 /* valid only if hang_detect_then_reset = true */
 422                 uint64_t                        doorbell_offset_addr;
 423                 enum MES_QUEUE_TYPE             queue_type;
 424
 425                 /* valid only if reset_legacy_gfx = true */
 426                 uint32_t                        pipe_id_lp;
 427                 uint32_t                        queue_id_lp;
 428                 uint32_t                        vmid_id_lp;
 429                 uint64_t                        mqd_mc_addr_lp;
 430                 uint32_t                        doorbell_offset_lp;
 431                 uint64_t                        wptr_addr_lp;
 432
 433                 uint32_t                        pipe_id_hp;
 434                 uint32_t                        queue_id_hp;
 435                 uint32_t                        vmid_id_hp;
 436                 uint64_t                        mqd_mc_addr_hp;
 437                 uint32_t                        doorbell_offset_hp;
 438                 uint64_t                        wptr_addr_hp;
 439
 440                 struct MES_API_STATUS           api_status;
 441         };
 442
 443         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 444 };
 445
 446 union MESAPI__SET_LOGGING_BUFFER {
 447         struct {
 448                 union MES_API_HEADER    header;
 449                 /* There are separate log buffers for each queue type */
 450                 enum MES_QUEUE_TYPE     log_type;
 451                 /* Log buffer GPU Address */
 452                 uint64_t                logging_buffer_addr;
 453                 /* number of entries in the log buffer */
 454                 uint32_t                number_of_entries;
 455                 /* Entry index at which CPU interrupt needs to be signalled */
 456                 uint32_t                interrupt_entry;
 457
 458                 struct MES_API_STATUS   api_status;
 459         };
 460
 461         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 462 };
 463
 464 union MESAPI__QUERY_MES_STATUS {
 465         struct {
 466                 union MES_API_HEADER    header;
 467                 bool                    mes_healthy; /* 0 - not healthy, 1 - healthy */
 468                 struct MES_API_STATUS   api_status;
 469         };
 470
 471         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 472 };
 473
 474 union MESAPI__PROGRAM_GDS {
 475         struct {
 476                 union MES_API_HEADER    header;
 477                 uint64_t                process_context_addr;
 478                 uint32_t                gds_base;
 479                 uint32_t                gds_size;
 480                 uint32_t                gws_base;
 481                 uint32_t                gws_size;
 482                 uint32_t                oa_mask;
 483                 struct MES_API_STATUS   api_status;
 484         };
 485
 486         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 487 };
 488
 489 union MESAPI__SET_DEBUG_VMID {
 490         struct {
 491                 union MES_API_HEADER    header;
 492                 struct MES_API_STATUS   api_status;
 493                 union {
 494                         struct {
 495                                 uint32_t use_gds        : 1;
 496                                 uint32_t operation      : 2;
 497                                 uint32_t reserved       : 29;
 498                         } flags;
 499                         uint32_t        u32All;
 500                 };
 501                 uint32_t                reserved;
 502                 uint32_t                debug_vmid;
 503                 uint64_t                process_context_addr;
 504                 uint64_t                page_table_base_addr;
 505                 uint64_t                process_va_start;
 506                 uint64_t                process_va_end;
 507                 uint32_t                gds_base;
 508                 uint32_t                gds_size;
 509                 uint32_t                gws_base;
 510                 uint32_t                gws_size;
 511                 uint32_t                oa_mask;
 512
 513                 /* output addr of the acquired vmid value */
 514                 uint64_t                output_addr;
 515         };
 516
 517         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 518 };
 519
 520 enum MESAPI_MISC_OPCODE {
 521         MESAPI_MISC__WRITE_REG,
 522         MESAPI_MISC__INV_GART,
 523         MESAPI_MISC__QUERY_STATUS,
 524         MESAPI_MISC__READ_REG,
 525         MESAPI_MISC__WAIT_REG_MEM,
 526         MESAPI_MISC__MAX,
 527 };
 528
 529 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
 530
 531 struct WRITE_REG {
 532         uint32_t                  reg_offset;
 533         uint32_t                  reg_value;
 534 };
 535
 536 struct READ_REG {
 537         uint32_t                  reg_offset;
 538         uint64_t                  buffer_addr;
 539 };
 540
 541 enum WRM_OPERATION {
 542         WRM_OPERATION__WAIT_REG_MEM,
 543         WRM_OPERATION__WR_WAIT_WR_REG,
 544         WRM_OPERATION__MAX,
 545 };
 546
 547 struct WAIT_REG_MEM {
 548         enum WRM_OPERATION         op;
 549         uint32_t                   reference;
 550         uint32_t                   mask;
 551         uint32_t                   reg_offset1;
 552         uint32_t                   reg_offset2;
 553 };
 554
 555 struct INV_GART {
 556         uint64_t                  inv_range_va_start;
 557         uint64_t                  inv_range_size;
 558 };
 559
 560 struct QUERY_STATUS {
 561         uint32_t context_id;
 562 };
 563
 564 union MESAPI__MISC {
 565         struct {
 566                 union MES_API_HEADER    header;
 567                 enum MESAPI_MISC_OPCODE opcode;
 568                 struct MES_API_STATUS   api_status;
 569
 570                 union {
 571                         struct          WRITE_REG write_reg;
 572                         struct          INV_GART inv_gart;
 573                         struct          QUERY_STATUS query_status;
 574                         struct          READ_REG read_reg;
 575                         struct          WAIT_REG_MEM wait_reg_mem;
 576                         uint32_t        data[MISC_DATA_MAX_SIZE_IN_DWORDS];
 577                 };
 578         };
 579
 580         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 581 };
 582
 583 union MESAPI__UPDATE_ROOT_PAGE_TABLE {
 584         struct {
 585                 union MES_API_HEADER        header;
 586                 uint64_t                    page_table_base_addr;
 587                 uint64_t                    process_context_addr;
 588                 struct MES_API_STATUS       api_status;
 589         };
 590
 591         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 592 };
 593
 594 union MESAPI_AMD_LOG {
 595         struct {
 596                 union MES_API_HEADER        header;
 597                 uint64_t                    p_buffer_memory;
 598                 uint64_t                    p_buffer_size_used;
 599                 struct MES_API_STATUS       api_status;
 600         };
 601
 602         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 603 };
 604
 605 #pragma pack(pop)
 606 #endif