drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_GEN(dev_priv) < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_GEN(dev_priv) <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  73 {
  74         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         if (width)
  86                 *width = cache->plane.src_w;
  87         if (height)
  88                 *height = cache->plane.src_h;
  89 }
  90
  91 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  92                                         struct intel_fbc_state_cache *cache)
  93 {
  94         int lines;
  95
  96         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  97         if (INTEL_GEN(dev_priv) == 7)
  98                 lines = min(lines, 2048);
  99         else if (INTEL_GEN(dev_priv) >= 8)
 100                 lines = min(lines, 2560);
 101
 102         /* Hardware needs the full buffer stride, not just the active area. */
 103         return lines * cache->fb.stride;
 104 }
 105
 106 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 107 {
 108         u32 fbc_ctl;
 109
 110         /* Disable compression */
 111         fbc_ctl = I915_READ(FBC_CONTROL);
 112         if ((fbc_ctl & FBC_CTL_EN) == 0)
 113                 return;
 114
 115         fbc_ctl &= ~FBC_CTL_EN;
 116         I915_WRITE(FBC_CONTROL, fbc_ctl);
 117
 118         /* Wait for compressing bit to clear */
 119         if (intel_wait_for_register(dev_priv,
 120                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 121                                     10)) {
 122                 DRM_DEBUG_KMS("FBC idle timed out\n");
 123                 return;
 124         }
 125 }
 126
 127 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 128 {
 129         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 130         int cfb_pitch;
 131         int i;
 132         u32 fbc_ctl;
 133
 134         /* Note: fbc.threshold == 1 for i8xx */
 135         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 136         if (params->fb.stride < cfb_pitch)
 137                 cfb_pitch = params->fb.stride;
 138
 139         /* FBC_CTL wants 32B or 64B units */
 140         if (IS_GEN2(dev_priv))
 141                 cfb_pitch = (cfb_pitch / 32) - 1;
 142         else
 143                 cfb_pitch = (cfb_pitch / 64) - 1;
 144
 145         /* Clear old tags */
 146         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 147                 I915_WRITE(FBC_TAG(i), 0);
 148
 149         if (IS_GEN4(dev_priv)) {
 150                 u32 fbc_ctl2;
 151
 152                 /* Set it up... */
 153                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 154                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
 155                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 156                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 157         }
 158
 159         /* enable it... */
 160         fbc_ctl = I915_READ(FBC_CONTROL);
 161         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 162         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 163         if (IS_I945GM(dev_priv))
 164                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 165         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 166         fbc_ctl |= params->vma->fence->id;
 167         I915_WRITE(FBC_CONTROL, fbc_ctl);
 168 }
 169
 170 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 171 {
 172         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 173 }
 174
 175 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 176 {
 177         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 178         u32 dpfc_ctl;
 179
 180         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
 181         if (params->fb.format->cpp[0] == 2)
 182                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 183         else
 184                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 185
 186         if (params->vma->fence) {
 187                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 188                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 189         } else {
 190                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 191         }
 192
 193         /* enable it... */
 194         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 195 }
 196
 197 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 198 {
 199         u32 dpfc_ctl;
 200
 201         /* Disable compression */
 202         dpfc_ctl = I915_READ(DPFC_CONTROL);
 203         if (dpfc_ctl & DPFC_CTL_EN) {
 204                 dpfc_ctl &= ~DPFC_CTL_EN;
 205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 206         }
 207 }
 208
 209 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 210 {
 211         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 212 }
 213
 214 /* This function forces a CFB recompression through the nuke operation. */
 215 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 216 {
 217         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 218         POSTING_READ(MSG_FBC_REND_STATE);
 219 }
 220
 221 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 222 {
 223         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 224         u32 dpfc_ctl;
 225         int threshold = dev_priv->fbc.threshold;
 226
 227         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
 228         if (params->fb.format->cpp[0] == 2)
 229                 threshold++;
 230
 231         switch (threshold) {
 232         case 4:
 233         case 3:
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 235                 break;
 236         case 2:
 237                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 238                 break;
 239         case 1:
 240                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 241                 break;
 242         }
 243
 244         if (params->vma->fence) {
 245                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 246                 if (IS_GEN5(dev_priv))
 247                         dpfc_ctl |= params->vma->fence->id;
 248                 if (IS_GEN6(dev_priv)) {
 249                         I915_WRITE(SNB_DPFC_CTL_SA,
 250                                    SNB_CPU_FENCE_ENABLE |
 251                                    params->vma->fence->id);
 252                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 253                                    params->crtc.fence_y_offset);
 254                 }
 255         } else {
 256                 if (IS_GEN6(dev_priv)) {
 257                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 258                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 259                 }
 260         }
 261
 262         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 263         I915_WRITE(ILK_FBC_RT_BASE,
 264                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 265         /* enable it... */
 266         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 267
 268         intel_fbc_recompress(dev_priv);
 269 }
 270
 271 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 272 {
 273         u32 dpfc_ctl;
 274
 275         /* Disable compression */
 276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 277         if (dpfc_ctl & DPFC_CTL_EN) {
 278                 dpfc_ctl &= ~DPFC_CTL_EN;
 279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 280         }
 281 }
 282
 283 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 284 {
 285         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 286 }
 287
 288 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 289 {
 290         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 291         u32 dpfc_ctl;
 292         int threshold = dev_priv->fbc.threshold;
 293
 294         /* Display WA #0529: skl, kbl, bxt. */
 295         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
 296                 u32 val = I915_READ(CHICKEN_MISC_4);
 297
 298                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 299
 300                 if (i915_gem_object_get_tiling(params->vma->obj) !=
 301                     I915_TILING_X)
 302                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 303
 304                 I915_WRITE(CHICKEN_MISC_4, val);
 305         }
 306
 307         dpfc_ctl = 0;
 308         if (IS_IVYBRIDGE(dev_priv))
 309                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
 310
 311         if (params->fb.format->cpp[0] == 2)
 312                 threshold++;
 313
 314         switch (threshold) {
 315         case 4:
 316         case 3:
 317                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 318                 break;
 319         case 2:
 320                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 321                 break;
 322         case 1:
 323                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 324                 break;
 325         }
 326
 327         if (params->vma->fence) {
 328                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 329                 I915_WRITE(SNB_DPFC_CTL_SA,
 330                            SNB_CPU_FENCE_ENABLE |
 331                            params->vma->fence->id);
 332                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 333         } else {
 334                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 335                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 336         }
 337
 338         if (dev_priv->fbc.false_color)
 339                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 340
 341         if (IS_IVYBRIDGE(dev_priv)) {
 342                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 343                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 344                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 345                            ILK_FBCQ_DIS);
 346         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 347                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 348                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 349                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 350                            HSW_FBCQ_DIS);
 351         }
 352
 353         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 354
 355         intel_fbc_recompress(dev_priv);
 356 }
 357
 358 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 359 {
 360         if (INTEL_GEN(dev_priv) >= 5)
 361                 return ilk_fbc_is_active(dev_priv);
 362         else if (IS_GM45(dev_priv))
 363                 return g4x_fbc_is_active(dev_priv);
 364         else
 365                 return i8xx_fbc_is_active(dev_priv);
 366 }
 367
 368 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 369 {
 370         struct intel_fbc *fbc = &dev_priv->fbc;
 371
 372         fbc->active = true;
 373
 374         if (INTEL_GEN(dev_priv) >= 7)
 375                 gen7_fbc_activate(dev_priv);
 376         else if (INTEL_GEN(dev_priv) >= 5)
 377                 ilk_fbc_activate(dev_priv);
 378         else if (IS_GM45(dev_priv))
 379                 g4x_fbc_activate(dev_priv);
 380         else
 381                 i8xx_fbc_activate(dev_priv);
 382 }
 383
 384 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 385 {
 386         struct intel_fbc *fbc = &dev_priv->fbc;
 387
 388         fbc->active = false;
 389
 390         if (INTEL_GEN(dev_priv) >= 5)
 391                 ilk_fbc_deactivate(dev_priv);
 392         else if (IS_GM45(dev_priv))
 393                 g4x_fbc_deactivate(dev_priv);
 394         else
 395                 i8xx_fbc_deactivate(dev_priv);
 396 }
 397
 398 /**
 399  * intel_fbc_is_active - Is FBC active?
 400  * @dev_priv: i915 device instance
 401  *
 402  * This function is used to verify the current state of FBC.
 403  *
 404  * FIXME: This should be tracked in the plane config eventually
 405  * instead of queried at runtime for most callers.
 406  */
 407 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 408 {
 409         return dev_priv->fbc.active;
 410 }
 411
 412 static void intel_fbc_work_fn(struct work_struct *__work)
 413 {
 414         struct drm_i915_private *dev_priv =
 415                 container_of(__work, struct drm_i915_private, fbc.work.work);
 416         struct intel_fbc *fbc = &dev_priv->fbc;
 417         struct intel_fbc_work *work = &fbc->work;
 418         struct intel_crtc *crtc = fbc->crtc;
 419         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 420
 421         if (drm_crtc_vblank_get(&crtc->base)) {
 422                 /* CRTC is now off, leave FBC deactivated */
 423                 mutex_lock(&fbc->lock);
 424                 work->scheduled = false;
 425                 mutex_unlock(&fbc->lock);
 426                 return;
 427         }
 428
 429 retry:
 430         /* Delay the actual enabling to let pageflipping cease and the
 431          * display to settle before starting the compression. Note that
 432          * this delay also serves a second purpose: it allows for a
 433          * vblank to pass after disabling the FBC before we attempt
 434          * to modify the control registers.
 435          *
 436          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 437          *
 438          * It is also worth mentioning that since work->scheduled_vblank can be
 439          * updated multiple times by the other threads, hitting the timeout is
 440          * not an error condition. We'll just end up hitting the "goto retry"
 441          * case below.
 442          */
 443         wait_event_timeout(vblank->queue,
 444                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 445                 msecs_to_jiffies(50));
 446
 447         mutex_lock(&fbc->lock);
 448
 449         /* Were we cancelled? */
 450         if (!work->scheduled)
 451                 goto out;
 452
 453         /* Were we delayed again while this function was sleeping? */
 454         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 455                 mutex_unlock(&fbc->lock);
 456                 goto retry;
 457         }
 458
 459         intel_fbc_hw_activate(dev_priv);
 460
 461         work->scheduled = false;
 462
 463 out:
 464         mutex_unlock(&fbc->lock);
 465         drm_crtc_vblank_put(&crtc->base);
 466 }
 467
 468 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 471         struct intel_fbc *fbc = &dev_priv->fbc;
 472         struct intel_fbc_work *work = &fbc->work;
 473
 474         WARN_ON(!mutex_is_locked(&fbc->lock));
 475         if (WARN_ON(!fbc->enabled))
 476                 return;
 477
 478         if (drm_crtc_vblank_get(&crtc->base)) {
 479                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 480                           pipe_name(crtc->pipe));
 481                 return;
 482         }
 483
 484         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 485          * this function since we're not releasing fbc.lock, so it won't have an
 486          * opportunity to grab it to discover that it was cancelled. So we just
 487          * update the expected jiffy count. */
 488         work->scheduled = true;
 489         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 490         drm_crtc_vblank_put(&crtc->base);
 491
 492         schedule_work(&work->work);
 493 }
 494
 495 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 496 {
 497         struct intel_fbc *fbc = &dev_priv->fbc;
 498
 499         WARN_ON(!mutex_is_locked(&fbc->lock));
 500
 501         /* Calling cancel_work() here won't help due to the fact that the work
 502          * function grabs fbc->lock. Just set scheduled to false so the work
 503          * function can know it was cancelled. */
 504         fbc->work.scheduled = false;
 505
 506         if (fbc->active)
 507                 intel_fbc_hw_deactivate(dev_priv);
 508 }
 509
 510 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 511                               struct intel_plane_state *plane_state)
 512 {
 513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 514         struct intel_fbc *fbc = &dev_priv->fbc;
 515         enum pipe pipe = crtc->pipe;
 516
 517         /* Don't even bother tracking anything we don't need. */
 518         if (!no_fbc_on_multiple_pipes(dev_priv))
 519                 return true;
 520
 521         if (plane_state->base.visible)
 522                 fbc->visible_pipes_mask |= (1 << pipe);
 523         else
 524                 fbc->visible_pipes_mask &= ~(1 << pipe);
 525
 526         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 527 }
 528
 529 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 530                                       struct drm_mm_node *node,
 531                                       int size,
 532                                       int fb_cpp)
 533 {
 534         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 535         int compression_threshold = 1;
 536         int ret;
 537         u64 end;
 538
 539         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 540          * reserved range size, so it always assumes the maximum (8mb) is used.
 541          * If we enable FBC using a CFB on that memory range we'll get FIFO
 542          * underruns, even if that range is not reserved by the BIOS. */
 543         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 544                 end = ggtt->stolen_size - 8 * 1024 * 1024;
 545         else
 546                 end = U64_MAX;
 547
 548         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 549          * code changes, this code needs to change as well.
 550          *
 551          * The enable_fbc code will attempt to use one of our 2 compression
 552          * thresholds, therefore, in that case, we only have 1 resort.
 553          */
 554
 555         /* Try to over-allocate to reduce reallocations and fragmentation. */
 556         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 557                                                    4096, 0, end);
 558         if (ret == 0)
 559                 return compression_threshold;
 560
 561 again:
 562         /* HW's ability to limit the CFB is 1:4 */
 563         if (compression_threshold > 4 ||
 564             (fb_cpp == 2 && compression_threshold == 2))
 565                 return 0;
 566
 567         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 568                                                    4096, 0, end);
 569         if (ret && INTEL_GEN(dev_priv) <= 4) {
 570                 return 0;
 571         } else if (ret) {
 572                 compression_threshold <<= 1;
 573                 goto again;
 574         } else {
 575                 return compression_threshold;
 576         }
 577 }
 578
 579 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 580 {
 581         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 582         struct intel_fbc *fbc = &dev_priv->fbc;
 583         struct drm_mm_node *uninitialized_var(compressed_llb);
 584         int size, fb_cpp, ret;
 585
 586         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 587
 588         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 589         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 590
 591         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 592                                          size, fb_cpp);
 593         if (!ret)
 594                 goto err_llb;
 595         else if (ret > 1) {
 596                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 597
 598         }
 599
 600         fbc->threshold = ret;
 601
 602         if (INTEL_GEN(dev_priv) >= 5)
 603                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 604         else if (IS_GM45(dev_priv)) {
 605                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 606         } else {
 607                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 608                 if (!compressed_llb)
 609                         goto err_fb;
 610
 611                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 612                                                   4096, 4096);
 613                 if (ret)
 614                         goto err_fb;
 615
 616                 fbc->compressed_llb = compressed_llb;
 617
 618                 I915_WRITE(FBC_CFB_BASE,
 619                            dev_priv->mm.stolen_base + fbc->compressed_fb.start);
 620                 I915_WRITE(FBC_LL_BASE,
 621                            dev_priv->mm.stolen_base + compressed_llb->start);
 622         }
 623
 624         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 625                       fbc->compressed_fb.size, fbc->threshold);
 626
 627         return 0;
 628
 629 err_fb:
 630         kfree(compressed_llb);
 631         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 632 err_llb:
 633         if (drm_mm_initialized(&dev_priv->mm.stolen))
 634                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 635         return -ENOSPC;
 636 }
 637
 638 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 639 {
 640         struct intel_fbc *fbc = &dev_priv->fbc;
 641
 642         if (drm_mm_node_allocated(&fbc->compressed_fb))
 643                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 644
 645         if (fbc->compressed_llb) {
 646                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 647                 kfree(fbc->compressed_llb);
 648         }
 649 }
 650
 651 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 652 {
 653         struct intel_fbc *fbc = &dev_priv->fbc;
 654
 655         if (!fbc_supported(dev_priv))
 656                 return;
 657
 658         mutex_lock(&fbc->lock);
 659         __intel_fbc_cleanup_cfb(dev_priv);
 660         mutex_unlock(&fbc->lock);
 661 }
 662
 663 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 664                             unsigned int stride)
 665 {
 666         /* These should have been caught earlier. */
 667         WARN_ON(stride < 512);
 668         WARN_ON((stride & (64 - 1)) != 0);
 669
 670         /* Below are the additional FBC restrictions. */
 671
 672         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 673                 return stride == 4096 || stride == 8192;
 674
 675         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 676                 return false;
 677
 678         if (stride > 16384)
 679                 return false;
 680
 681         return true;
 682 }
 683
 684 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 685                                   uint32_t pixel_format)
 686 {
 687         switch (pixel_format) {
 688         case DRM_FORMAT_XRGB8888:
 689         case DRM_FORMAT_XBGR8888:
 690                 return true;
 691         case DRM_FORMAT_XRGB1555:
 692         case DRM_FORMAT_RGB565:
 693                 /* 16bpp not supported on gen2 */
 694                 if (IS_GEN2(dev_priv))
 695                         return false;
 696                 /* WaFbcOnly1to1Ratio:ctg */
 697                 if (IS_G4X(dev_priv))
 698                         return false;
 699                 return true;
 700         default:
 701                 return false;
 702         }
 703 }
 704
 705 /*
 706  * For some reason, the hardware tracking starts looking at whatever we
 707  * programmed as the display plane base address register. It does not look at
 708  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 709  * variables instead of just looking at the pipe/plane size.
 710  */
 711 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 712 {
 713         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 714         struct intel_fbc *fbc = &dev_priv->fbc;
 715         unsigned int effective_w, effective_h, max_w, max_h;
 716
 717         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 718                 max_w = 4096;
 719                 max_h = 4096;
 720         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 721                 max_w = 4096;
 722                 max_h = 2048;
 723         } else {
 724                 max_w = 2048;
 725                 max_h = 1536;
 726         }
 727
 728         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 729                                         &effective_h);
 730         effective_w += fbc->state_cache.plane.adjusted_x;
 731         effective_h += fbc->state_cache.plane.adjusted_y;
 732
 733         return effective_w <= max_w && effective_h <= max_h;
 734 }
 735
 736 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 737                                          struct intel_crtc_state *crtc_state,
 738                                          struct intel_plane_state *plane_state)
 739 {
 740         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 741         struct intel_fbc *fbc = &dev_priv->fbc;
 742         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 743         struct drm_framebuffer *fb = plane_state->base.fb;
 744
 745         cache->vma = NULL;
 746
 747         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 748         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 749                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 750
 751         cache->plane.rotation = plane_state->base.rotation;
 752         /*
 753          * Src coordinates are already rotated by 270 degrees for
 754          * the 90/270 degree plane rotation cases (to match the
 755          * GTT mapping), hence no need to account for rotation here.
 756          */
 757         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 758         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 759         cache->plane.visible = plane_state->base.visible;
 760         cache->plane.adjusted_x = plane_state->main.x;
 761         cache->plane.adjusted_y = plane_state->main.y;
 762         cache->plane.y = plane_state->base.src.y1 >> 16;
 763
 764         if (!cache->plane.visible)
 765                 return;
 766
 767         cache->fb.format = fb->format;
 768         cache->fb.stride = fb->pitches[0];
 769
 770         cache->vma = plane_state->vma;
 771 }
 772
 773 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 774 {
 775         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 776         struct intel_fbc *fbc = &dev_priv->fbc;
 777         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 778
 779         /* We don't need to use a state cache here since this information is
 780          * global for all CRTC.
 781          */
 782         if (fbc->underrun_detected) {
 783                 fbc->no_fbc_reason = "underrun detected";
 784                 return false;
 785         }
 786
 787         if (!cache->vma) {
 788                 fbc->no_fbc_reason = "primary plane not visible";
 789                 return false;
 790         }
 791
 792         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 793             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 794                 fbc->no_fbc_reason = "incompatible mode";
 795                 return false;
 796         }
 797
 798         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 799                 fbc->no_fbc_reason = "mode too large for compression";
 800                 return false;
 801         }
 802
 803         /* The use of a CPU fence is mandatory in order to detect writes
 804          * by the CPU to the scanout and trigger updates to the FBC.
 805          *
 806          * Note that is possible for a tiled surface to be unmappable (and
 807          * so have no fence associated with it) due to aperture constaints
 808          * at the time of pinning.
 809          */
 810         if (!cache->vma->fence) {
 811                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 812                 return false;
 813         }
 814         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 815             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 816                 fbc->no_fbc_reason = "rotation unsupported";
 817                 return false;
 818         }
 819
 820         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 821                 fbc->no_fbc_reason = "framebuffer stride not supported";
 822                 return false;
 823         }
 824
 825         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 826                 fbc->no_fbc_reason = "pixel format is invalid";
 827                 return false;
 828         }
 829
 830         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 831         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 832             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 833                 fbc->no_fbc_reason = "pixel rate is too big";
 834                 return false;
 835         }
 836
 837         /* It is possible for the required CFB size change without a
 838          * crtc->disable + crtc->enable since it is possible to change the
 839          * stride without triggering a full modeset. Since we try to
 840          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 841          * if this happens, but if we exceed the current CFB size we'll have to
 842          * disable FBC. Notice that it would be possible to disable FBC, wait
 843          * for a frame, free the stolen node, then try to reenable FBC in case
 844          * we didn't get any invalidate/deactivate calls, but this would require
 845          * a lot of tracking just for a specific case. If we conclude it's an
 846          * important case, we can implement it later. */
 847         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 848             fbc->compressed_fb.size * fbc->threshold) {
 849                 fbc->no_fbc_reason = "CFB requirements changed";
 850                 return false;
 851         }
 852
 853         return true;
 854 }
 855
 856 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 857 {
 858         struct intel_fbc *fbc = &dev_priv->fbc;
 859
 860         if (intel_vgpu_active(dev_priv)) {
 861                 fbc->no_fbc_reason = "VGPU is active";
 862                 return false;
 863         }
 864
 865         if (!i915_modparams.enable_fbc) {
 866                 fbc->no_fbc_reason = "disabled per module param or by default";
 867                 return false;
 868         }
 869
 870         if (fbc->underrun_detected) {
 871                 fbc->no_fbc_reason = "underrun detected";
 872                 return false;
 873         }
 874
 875         return true;
 876 }
 877
 878 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 879                                      struct intel_fbc_reg_params *params)
 880 {
 881         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 882         struct intel_fbc *fbc = &dev_priv->fbc;
 883         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 884
 885         /* Since all our fields are integer types, use memset here so the
 886          * comparison function can rely on memcmp because the padding will be
 887          * zero. */
 888         memset(params, 0, sizeof(*params));
 889
 890         params->vma = cache->vma;
 891
 892         params->crtc.pipe = crtc->pipe;
 893         params->crtc.plane = crtc->plane;
 894         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 895
 896         params->fb.format = cache->fb.format;
 897         params->fb.stride = cache->fb.stride;
 898
 899         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 900
 901         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
 902                 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
 903                                                 32 * fbc->threshold) * 8;
 904 }
 905
 906 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 907                                        struct intel_fbc_reg_params *params2)
 908 {
 909         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 910         return memcmp(params1, params2, sizeof(*params1)) == 0;
 911 }
 912
 913 void intel_fbc_pre_update(struct intel_crtc *crtc,
 914                           struct intel_crtc_state *crtc_state,
 915                           struct intel_plane_state *plane_state)
 916 {
 917         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 918         struct intel_fbc *fbc = &dev_priv->fbc;
 919
 920         if (!fbc_supported(dev_priv))
 921                 return;
 922
 923         mutex_lock(&fbc->lock);
 924
 925         if (!multiple_pipes_ok(crtc, plane_state)) {
 926                 fbc->no_fbc_reason = "more than one pipe active";
 927                 goto deactivate;
 928         }
 929
 930         if (!fbc->enabled || fbc->crtc != crtc)
 931                 goto unlock;
 932
 933         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 934
 935 deactivate:
 936         intel_fbc_deactivate(dev_priv);
 937 unlock:
 938         mutex_unlock(&fbc->lock);
 939 }
 940
 941 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 944         struct intel_fbc *fbc = &dev_priv->fbc;
 945         struct intel_fbc_reg_params old_params;
 946
 947         WARN_ON(!mutex_is_locked(&fbc->lock));
 948
 949         if (!fbc->enabled || fbc->crtc != crtc)
 950                 return;
 951
 952         if (!intel_fbc_can_activate(crtc)) {
 953                 WARN_ON(fbc->active);
 954                 return;
 955         }
 956
 957         old_params = fbc->params;
 958         intel_fbc_get_reg_params(crtc, &fbc->params);
 959
 960         /* If the scanout has not changed, don't modify the FBC settings.
 961          * Note that we make the fundamental assumption that the fb->obj
 962          * cannot be unpinned (and have its GTT offset and fence revoked)
 963          * without first being decoupled from the scanout and FBC disabled.
 964          */
 965         if (fbc->active &&
 966             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 967                 return;
 968
 969         intel_fbc_deactivate(dev_priv);
 970         intel_fbc_schedule_activation(crtc);
 971         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 972 }
 973
 974 void intel_fbc_post_update(struct intel_crtc *crtc)
 975 {
 976         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 977         struct intel_fbc *fbc = &dev_priv->fbc;
 978
 979         if (!fbc_supported(dev_priv))
 980                 return;
 981
 982         mutex_lock(&fbc->lock);
 983         __intel_fbc_post_update(crtc);
 984         mutex_unlock(&fbc->lock);
 985 }
 986
 987 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 988 {
 989         if (fbc->enabled)
 990                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 991         else
 992                 return fbc->possible_framebuffer_bits;
 993 }
 994
 995 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 996                           unsigned int frontbuffer_bits,
 997                           enum fb_op_origin origin)
 998 {
 999         struct intel_fbc *fbc = &dev_priv->fbc;
1000
1001         if (!fbc_supported(dev_priv))
1002                 return;
1003
1004         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1005                 return;
1006
1007         mutex_lock(&fbc->lock);
1008
1009         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1010
1011         if (fbc->enabled && fbc->busy_bits)
1012                 intel_fbc_deactivate(dev_priv);
1013
1014         mutex_unlock(&fbc->lock);
1015 }
1016
1017 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1018                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1019 {
1020         struct intel_fbc *fbc = &dev_priv->fbc;
1021
1022         if (!fbc_supported(dev_priv))
1023                 return;
1024
1025         mutex_lock(&fbc->lock);
1026
1027         fbc->busy_bits &= ~frontbuffer_bits;
1028
1029         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1030                 goto out;
1031
1032         if (!fbc->busy_bits && fbc->enabled &&
1033             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1034                 if (fbc->active)
1035                         intel_fbc_recompress(dev_priv);
1036                 else
1037                         __intel_fbc_post_update(fbc->crtc);
1038         }
1039
1040 out:
1041         mutex_unlock(&fbc->lock);
1042 }
1043
1044 /**
1045  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1046  * @dev_priv: i915 device instance
1047  * @state: the atomic state structure
1048  *
1049  * This function looks at the proposed state for CRTCs and planes, then chooses
1050  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1051  * true.
1052  *
1053  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1054  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1055  */
1056 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1057                            struct drm_atomic_state *state)
1058 {
1059         struct intel_fbc *fbc = &dev_priv->fbc;
1060         struct drm_plane *plane;
1061         struct drm_plane_state *plane_state;
1062         bool crtc_chosen = false;
1063         int i;
1064
1065         mutex_lock(&fbc->lock);
1066
1067         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1068         if (fbc->crtc &&
1069             !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
1070                 goto out;
1071
1072         if (!intel_fbc_can_enable(dev_priv))
1073                 goto out;
1074
1075         /* Simply choose the first CRTC that is compatible and has a visible
1076          * plane. We could go for fancier schemes such as checking the plane
1077          * size, but this would just affect the few platforms that don't tie FBC
1078          * to pipe or plane A. */
1079         for_each_new_plane_in_state(state, plane, plane_state, i) {
1080                 struct intel_plane_state *intel_plane_state =
1081                         to_intel_plane_state(plane_state);
1082                 struct intel_crtc_state *intel_crtc_state;
1083                 struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
1084
1085                 if (!intel_plane_state->base.visible)
1086                         continue;
1087
1088                 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1089                         continue;
1090
1091                 if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
1092                         continue;
1093
1094                 intel_crtc_state = to_intel_crtc_state(
1095                         drm_atomic_get_existing_crtc_state(state, &crtc->base));
1096
1097                 intel_crtc_state->enable_fbc = true;
1098                 crtc_chosen = true;
1099                 break;
1100         }
1101
1102         if (!crtc_chosen)
1103                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1104
1105 out:
1106         mutex_unlock(&fbc->lock);
1107 }
1108
1109 /**
1110  * intel_fbc_enable: tries to enable FBC on the CRTC
1111  * @crtc: the CRTC
1112  * @crtc_state: corresponding &drm_crtc_state for @crtc
1113  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1114  *
1115  * This function checks if the given CRTC was chosen for FBC, then enables it if
1116  * possible. Notice that it doesn't activate FBC. It is valid to call
1117  * intel_fbc_enable multiple times for the same pipe without an
1118  * intel_fbc_disable in the middle, as long as it is deactivated.
1119  */
1120 void intel_fbc_enable(struct intel_crtc *crtc,
1121                       struct intel_crtc_state *crtc_state,
1122                       struct intel_plane_state *plane_state)
1123 {
1124         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1125         struct intel_fbc *fbc = &dev_priv->fbc;
1126
1127         if (!fbc_supported(dev_priv))
1128                 return;
1129
1130         mutex_lock(&fbc->lock);
1131
1132         if (fbc->enabled) {
1133                 WARN_ON(fbc->crtc == NULL);
1134                 if (fbc->crtc == crtc) {
1135                         WARN_ON(!crtc_state->enable_fbc);
1136                         WARN_ON(fbc->active);
1137                 }
1138                 goto out;
1139         }
1140
1141         if (!crtc_state->enable_fbc)
1142                 goto out;
1143
1144         WARN_ON(fbc->active);
1145         WARN_ON(fbc->crtc != NULL);
1146
1147         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1148         if (intel_fbc_alloc_cfb(crtc)) {
1149                 fbc->no_fbc_reason = "not enough stolen memory";
1150                 goto out;
1151         }
1152
1153         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1154         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1155
1156         fbc->enabled = true;
1157         fbc->crtc = crtc;
1158 out:
1159         mutex_unlock(&fbc->lock);
1160 }
1161
1162 /**
1163  * __intel_fbc_disable - disable FBC
1164  * @dev_priv: i915 device instance
1165  *
1166  * This is the low level function that actually disables FBC. Callers should
1167  * grab the FBC lock.
1168  */
1169 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1170 {
1171         struct intel_fbc *fbc = &dev_priv->fbc;
1172         struct intel_crtc *crtc = fbc->crtc;
1173
1174         WARN_ON(!mutex_is_locked(&fbc->lock));
1175         WARN_ON(!fbc->enabled);
1176         WARN_ON(fbc->active);
1177         WARN_ON(crtc->active);
1178
1179         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1180
1181         __intel_fbc_cleanup_cfb(dev_priv);
1182
1183         fbc->enabled = false;
1184         fbc->crtc = NULL;
1185 }
1186
1187 /**
1188  * intel_fbc_disable - disable FBC if it's associated with crtc
1189  * @crtc: the CRTC
1190  *
1191  * This function disables FBC if it's associated with the provided CRTC.
1192  */
1193 void intel_fbc_disable(struct intel_crtc *crtc)
1194 {
1195         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1196         struct intel_fbc *fbc = &dev_priv->fbc;
1197
1198         if (!fbc_supported(dev_priv))
1199                 return;
1200
1201         mutex_lock(&fbc->lock);
1202         if (fbc->crtc == crtc)
1203                 __intel_fbc_disable(dev_priv);
1204         mutex_unlock(&fbc->lock);
1205
1206         cancel_work_sync(&fbc->work.work);
1207 }
1208
1209 /**
1210  * intel_fbc_global_disable - globally disable FBC
1211  * @dev_priv: i915 device instance
1212  *
1213  * This function disables FBC regardless of which CRTC is associated with it.
1214  */
1215 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1216 {
1217         struct intel_fbc *fbc = &dev_priv->fbc;
1218
1219         if (!fbc_supported(dev_priv))
1220                 return;
1221
1222         mutex_lock(&fbc->lock);
1223         if (fbc->enabled)
1224                 __intel_fbc_disable(dev_priv);
1225         mutex_unlock(&fbc->lock);
1226
1227         cancel_work_sync(&fbc->work.work);
1228 }
1229
1230 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1231 {
1232         struct drm_i915_private *dev_priv =
1233                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1234         struct intel_fbc *fbc = &dev_priv->fbc;
1235
1236         mutex_lock(&fbc->lock);
1237
1238         /* Maybe we were scheduled twice. */
1239         if (fbc->underrun_detected || !fbc->enabled)
1240                 goto out;
1241
1242         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1243         fbc->underrun_detected = true;
1244
1245         intel_fbc_deactivate(dev_priv);
1246 out:
1247         mutex_unlock(&fbc->lock);
1248 }
1249
1250 /**
1251  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1252  * @dev_priv: i915 device instance
1253  *
1254  * Without FBC, most underruns are harmless and don't really cause too many
1255  * problems, except for an annoying message on dmesg. With FBC, underruns can
1256  * become black screens or even worse, especially when paired with bad
1257  * watermarks. So in order for us to be on the safe side, completely disable FBC
1258  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1259  * already suggests that watermarks may be bad, so try to be as safe as
1260  * possible.
1261  *
1262  * This function is called from the IRQ handler.
1263  */
1264 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1265 {
1266         struct intel_fbc *fbc = &dev_priv->fbc;
1267
1268         if (!fbc_supported(dev_priv))
1269                 return;
1270
1271         /* There's no guarantee that underrun_detected won't be set to true
1272          * right after this check and before the work is scheduled, but that's
1273          * not a problem since we'll check it again under the work function
1274          * while FBC is locked. This check here is just to prevent us from
1275          * unnecessarily scheduling the work, and it relies on the fact that we
1276          * never switch underrun_detect back to false after it's true. */
1277         if (READ_ONCE(fbc->underrun_detected))
1278                 return;
1279
1280         schedule_work(&fbc->underrun_work);
1281 }
1282
1283 /**
1284  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1285  * @dev_priv: i915 device instance
1286  *
1287  * The FBC code needs to track CRTC visibility since the older platforms can't
1288  * have FBC enabled while multiple pipes are used. This function does the
1289  * initial setup at driver load to make sure FBC is matching the real hardware.
1290  */
1291 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1292 {
1293         struct intel_crtc *crtc;
1294
1295         /* Don't even bother tracking anything if we don't need. */
1296         if (!no_fbc_on_multiple_pipes(dev_priv))
1297                 return;
1298
1299         for_each_intel_crtc(&dev_priv->drm, crtc)
1300                 if (intel_crtc_active(crtc) &&
1301                     crtc->base.primary->state->visible)
1302                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1303 }
1304
1305 /*
1306  * The DDX driver changes its behavior depending on the value it reads from
1307  * i915.enable_fbc, so sanitize it by translating the default value into either
1308  * 0 or 1 in order to allow it to know what's going on.
1309  *
1310  * Notice that this is done at driver initialization and we still allow user
1311  * space to change the value during runtime without sanitizing it again. IGT
1312  * relies on being able to change i915.enable_fbc at runtime.
1313  */
1314 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1315 {
1316         if (i915_modparams.enable_fbc >= 0)
1317                 return !!i915_modparams.enable_fbc;
1318
1319         if (!HAS_FBC(dev_priv))
1320                 return 0;
1321
1322         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1323                 return 1;
1324
1325         return 0;
1326 }
1327
1328 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1329 {
1330         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1331         if (intel_vtd_active() &&
1332             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1333                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1334                 return true;
1335         }
1336
1337         return false;
1338 }
1339
1340 /**
1341  * intel_fbc_init - Initialize FBC
1342  * @dev_priv: the i915 device
1343  *
1344  * This function might be called during PM init process.
1345  */
1346 void intel_fbc_init(struct drm_i915_private *dev_priv)
1347 {
1348         struct intel_fbc *fbc = &dev_priv->fbc;
1349         enum pipe pipe;
1350
1351         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1352         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1353         mutex_init(&fbc->lock);
1354         fbc->enabled = false;
1355         fbc->active = false;
1356         fbc->work.scheduled = false;
1357
1358         if (need_fbc_vtd_wa(dev_priv))
1359                 mkwrite_device_info(dev_priv)->has_fbc = false;
1360
1361         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1362         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1363                       i915_modparams.enable_fbc);
1364
1365         if (!HAS_FBC(dev_priv)) {
1366                 fbc->no_fbc_reason = "unsupported by this chipset";
1367                 return;
1368         }
1369
1370         for_each_pipe(dev_priv, pipe) {
1371                 fbc->possible_framebuffer_bits |=
1372                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1373
1374                 if (fbc_on_pipe_a_only(dev_priv))
1375                         break;
1376         }
1377
1378         /* This value was pulled out of someone's hat */
1379         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1380                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1381
1382         /* We still don't have any sort of hardware state readout for FBC, so
1383          * deactivate it in case the BIOS activated it to make sure software
1384          * matches the hardware state. */
1385         if (intel_fbc_hw_is_active(dev_priv))
1386                 intel_fbc_hw_deactivate(dev_priv);
1387 }