drivers/gpu/drm/bridge/samsung-dsim.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Samsung MIPI DSIM bridge driver.
   4  *
   5  * Copyright (C) 2021 Amarula Solutions(India)
   6  * Copyright (c) 2014 Samsung Electronics Co., Ltd
   7  * Author: Jagan Teki <[email protected]>
   8  *
   9  * Based on exynos_drm_dsi from
  10  * Tomasz Figa <[email protected]>
  11  */
  12
  13 #include <asm/unaligned.h>
  14
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/irq.h>
  18 #include <linux/media-bus-format.h>
  19 #include <linux/of_device.h>
  20 #include <linux/phy/phy.h>
  21
  22 #include <video/mipi_display.h>
  23
  24 #include <drm/bridge/samsung-dsim.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drm_print.h>
  27
  28 /* returns true iff both arguments logically differs */
  29 #define NEQV(a, b) (!(a) ^ !(b))
  30
  31 /* DSIM_STATUS */
  32 #define DSIM_STOP_STATE_DAT(x)          (((x) & 0xf) << 0)
  33 #define DSIM_STOP_STATE_CLK             BIT(8)
  34 #define DSIM_TX_READY_HS_CLK            BIT(10)
  35 #define DSIM_PLL_STABLE                 BIT(31)
  36
  37 /* DSIM_SWRST */
  38 #define DSIM_FUNCRST                    BIT(16)
  39 #define DSIM_SWRST                      BIT(0)
  40
  41 /* DSIM_TIMEOUT */
  42 #define DSIM_LPDR_TIMEOUT(x)            ((x) << 0)
  43 #define DSIM_BTA_TIMEOUT(x)             ((x) << 16)
  44
  45 /* DSIM_CLKCTRL */
  46 #define DSIM_ESC_PRESCALER(x)           (((x) & 0xffff) << 0)
  47 #define DSIM_ESC_PRESCALER_MASK         (0xffff << 0)
  48 #define DSIM_LANE_ESC_CLK_EN_CLK        BIT(19)
  49 #define DSIM_LANE_ESC_CLK_EN_DATA(x)    (((x) & 0xf) << 20)
  50 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK  (0xf << 20)
  51 #define DSIM_BYTE_CLKEN                 BIT(24)
  52 #define DSIM_BYTE_CLK_SRC(x)            (((x) & 0x3) << 25)
  53 #define DSIM_BYTE_CLK_SRC_MASK          (0x3 << 25)
  54 #define DSIM_PLL_BYPASS                 BIT(27)
  55 #define DSIM_ESC_CLKEN                  BIT(28)
  56 #define DSIM_TX_REQUEST_HSCLK           BIT(31)
  57
  58 /* DSIM_CONFIG */
  59 #define DSIM_LANE_EN_CLK                BIT(0)
  60 #define DSIM_LANE_EN(x)                 (((x) & 0xf) << 1)
  61 #define DSIM_NUM_OF_DATA_LANE(x)        (((x) & 0x3) << 5)
  62 #define DSIM_SUB_PIX_FORMAT(x)          (((x) & 0x7) << 8)
  63 #define DSIM_MAIN_PIX_FORMAT_MASK       (0x7 << 12)
  64 #define DSIM_MAIN_PIX_FORMAT_RGB888     (0x7 << 12)
  65 #define DSIM_MAIN_PIX_FORMAT_RGB666     (0x6 << 12)
  66 #define DSIM_MAIN_PIX_FORMAT_RGB666_P   (0x5 << 12)
  67 #define DSIM_MAIN_PIX_FORMAT_RGB565     (0x4 << 12)
  68 #define DSIM_SUB_VC                     (((x) & 0x3) << 16)
  69 #define DSIM_MAIN_VC                    (((x) & 0x3) << 18)
  70 #define DSIM_HSA_DISABLE_MODE           BIT(20)
  71 #define DSIM_HBP_DISABLE_MODE           BIT(21)
  72 #define DSIM_HFP_DISABLE_MODE           BIT(22)
  73 /*
  74  * The i.MX 8M Mini Applications Processor Reference Manual,
  75  * Rev. 3, 11/2020 Page 4091
  76  * The i.MX 8M Nano Applications Processor Reference Manual,
  77  * Rev. 2, 07/2022 Page 3058
  78  * The i.MX 8M Plus Applications Processor Reference Manual,
  79  * Rev. 1, 06/2021 Page 5436
  80  * all claims this bit is 'HseDisableMode' with the definition
  81  * 0 = Disables transfer
  82  * 1 = Enables transfer
  83  *
  84  * This clearly states that HSE is not a disabled bit.
  85  *
  86  * The naming convention follows as per the manual and the
  87  * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag.
  88  */
  89 #define DSIM_HSE_DISABLE_MODE           BIT(23)
  90 #define DSIM_AUTO_MODE                  BIT(24)
  91 #define DSIM_VIDEO_MODE                 BIT(25)
  92 #define DSIM_BURST_MODE                 BIT(26)
  93 #define DSIM_SYNC_INFORM                BIT(27)
  94 #define DSIM_EOT_DISABLE                BIT(28)
  95 #define DSIM_MFLUSH_VS                  BIT(29)
  96 /* This flag is valid only for exynos3250/3472/5260/5430 */
  97 #define DSIM_CLKLANE_STOP               BIT(30)
  98
  99 /* DSIM_ESCMODE */
 100 #define DSIM_TX_TRIGGER_RST             BIT(4)
 101 #define DSIM_TX_LPDT_LP                 BIT(6)
 102 #define DSIM_CMD_LPDT_LP                BIT(7)
 103 #define DSIM_FORCE_BTA                  BIT(16)
 104 #define DSIM_FORCE_STOP_STATE           BIT(20)
 105 #define DSIM_STOP_STATE_CNT(x)          (((x) & 0x7ff) << 21)
 106 #define DSIM_STOP_STATE_CNT_MASK        (0x7ff << 21)
 107
 108 /* DSIM_MDRESOL */
 109 #define DSIM_MAIN_STAND_BY              BIT(31)
 110 #define DSIM_MAIN_VRESOL(x, num_bits)   (((x) & ((1 << (num_bits)) - 1)) << 16)
 111 #define DSIM_MAIN_HRESOL(x, num_bits)   (((x) & ((1 << (num_bits)) - 1)) << 0)
 112
 113 /* DSIM_MVPORCH */
 114 #define DSIM_CMD_ALLOW(x)               ((x) << 28)
 115 #define DSIM_STABLE_VFP(x)              ((x) << 16)
 116 #define DSIM_MAIN_VBP(x)                ((x) << 0)
 117 #define DSIM_CMD_ALLOW_MASK             (0xf << 28)
 118 #define DSIM_STABLE_VFP_MASK            (0x7ff << 16)
 119 #define DSIM_MAIN_VBP_MASK              (0x7ff << 0)
 120
 121 /* DSIM_MHPORCH */
 122 #define DSIM_MAIN_HFP(x)                ((x) << 16)
 123 #define DSIM_MAIN_HBP(x)                ((x) << 0)
 124 #define DSIM_MAIN_HFP_MASK              ((0xffff) << 16)
 125 #define DSIM_MAIN_HBP_MASK              ((0xffff) << 0)
 126
 127 /* DSIM_MSYNC */
 128 #define DSIM_MAIN_VSA(x)                ((x) << 22)
 129 #define DSIM_MAIN_HSA(x)                ((x) << 0)
 130 #define DSIM_MAIN_VSA_MASK              ((0x3ff) << 22)
 131 #define DSIM_MAIN_HSA_MASK              ((0xffff) << 0)
 132
 133 /* DSIM_SDRESOL */
 134 #define DSIM_SUB_STANDY(x)              ((x) << 31)
 135 #define DSIM_SUB_VRESOL(x)              ((x) << 16)
 136 #define DSIM_SUB_HRESOL(x)              ((x) << 0)
 137 #define DSIM_SUB_STANDY_MASK            ((0x1) << 31)
 138 #define DSIM_SUB_VRESOL_MASK            ((0x7ff) << 16)
 139 #define DSIM_SUB_HRESOL_MASK            ((0x7ff) << 0)
 140
 141 /* DSIM_INTSRC */
 142 #define DSIM_INT_PLL_STABLE             BIT(31)
 143 #define DSIM_INT_SW_RST_RELEASE         BIT(30)
 144 #define DSIM_INT_SFR_FIFO_EMPTY         BIT(29)
 145 #define DSIM_INT_SFR_HDR_FIFO_EMPTY     BIT(28)
 146 #define DSIM_INT_BTA                    BIT(25)
 147 #define DSIM_INT_FRAME_DONE             BIT(24)
 148 #define DSIM_INT_RX_TIMEOUT             BIT(21)
 149 #define DSIM_INT_BTA_TIMEOUT            BIT(20)
 150 #define DSIM_INT_RX_DONE                BIT(18)
 151 #define DSIM_INT_RX_TE                  BIT(17)
 152 #define DSIM_INT_RX_ACK                 BIT(16)
 153 #define DSIM_INT_RX_ECC_ERR             BIT(15)
 154 #define DSIM_INT_RX_CRC_ERR             BIT(14)
 155
 156 /* DSIM_FIFOCTRL */
 157 #define DSIM_RX_DATA_FULL               BIT(25)
 158 #define DSIM_RX_DATA_EMPTY              BIT(24)
 159 #define DSIM_SFR_HEADER_FULL            BIT(23)
 160 #define DSIM_SFR_HEADER_EMPTY           BIT(22)
 161 #define DSIM_SFR_PAYLOAD_FULL           BIT(21)
 162 #define DSIM_SFR_PAYLOAD_EMPTY          BIT(20)
 163 #define DSIM_I80_HEADER_FULL            BIT(19)
 164 #define DSIM_I80_HEADER_EMPTY           BIT(18)
 165 #define DSIM_I80_PAYLOAD_FULL           BIT(17)
 166 #define DSIM_I80_PAYLOAD_EMPTY          BIT(16)
 167 #define DSIM_SD_HEADER_FULL             BIT(15)
 168 #define DSIM_SD_HEADER_EMPTY            BIT(14)
 169 #define DSIM_SD_PAYLOAD_FULL            BIT(13)
 170 #define DSIM_SD_PAYLOAD_EMPTY           BIT(12)
 171 #define DSIM_MD_HEADER_FULL             BIT(11)
 172 #define DSIM_MD_HEADER_EMPTY            BIT(10)
 173 #define DSIM_MD_PAYLOAD_FULL            BIT(9)
 174 #define DSIM_MD_PAYLOAD_EMPTY           BIT(8)
 175 #define DSIM_RX_FIFO                    BIT(4)
 176 #define DSIM_SFR_FIFO                   BIT(3)
 177 #define DSIM_I80_FIFO                   BIT(2)
 178 #define DSIM_SD_FIFO                    BIT(1)
 179 #define DSIM_MD_FIFO                    BIT(0)
 180
 181 /* DSIM_PHYACCHR */
 182 #define DSIM_AFC_EN                     BIT(14)
 183 #define DSIM_AFC_CTL(x)                 (((x) & 0x7) << 5)
 184
 185 /* DSIM_PLLCTRL */
 186 #define DSIM_PLL_DPDNSWAP_CLK           (1 << 25)
 187 #define DSIM_PLL_DPDNSWAP_DAT           (1 << 24)
 188 #define DSIM_FREQ_BAND(x)               ((x) << 24)
 189 #define DSIM_PLL_EN                     BIT(23)
 190 #define DSIM_PLL_P(x, offset)           ((x) << (offset))
 191 #define DSIM_PLL_M(x)                   ((x) << 4)
 192 #define DSIM_PLL_S(x)                   ((x) << 1)
 193
 194 /* DSIM_PHYCTRL */
 195 #define DSIM_PHYCTRL_ULPS_EXIT(x)       (((x) & 0x1ff) << 0)
 196 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP  BIT(30)
 197 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP  BIT(14)
 198
 199 /* DSIM_PHYTIMING */
 200 #define DSIM_PHYTIMING_LPX(x)           ((x) << 8)
 201 #define DSIM_PHYTIMING_HS_EXIT(x)       ((x) << 0)
 202
 203 /* DSIM_PHYTIMING1 */
 204 #define DSIM_PHYTIMING1_CLK_PREPARE(x)  ((x) << 24)
 205 #define DSIM_PHYTIMING1_CLK_ZERO(x)     ((x) << 16)
 206 #define DSIM_PHYTIMING1_CLK_POST(x)     ((x) << 8)
 207 #define DSIM_PHYTIMING1_CLK_TRAIL(x)    ((x) << 0)
 208
 209 /* DSIM_PHYTIMING2 */
 210 #define DSIM_PHYTIMING2_HS_PREPARE(x)   ((x) << 16)
 211 #define DSIM_PHYTIMING2_HS_ZERO(x)      ((x) << 8)
 212 #define DSIM_PHYTIMING2_HS_TRAIL(x)     ((x) << 0)
 213
 214 #define DSI_MAX_BUS_WIDTH               4
 215 #define DSI_NUM_VIRTUAL_CHANNELS        4
 216 #define DSI_TX_FIFO_SIZE                2048
 217 #define DSI_RX_FIFO_SIZE                256
 218 #define DSI_XFER_TIMEOUT_MS             100
 219 #define DSI_RX_FIFO_EMPTY               0x30800002
 220
 221 #define OLD_SCLK_MIPI_CLK_NAME          "pll_clk"
 222
 223 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)
 224
 225 static const char *const clk_names[5] = {
 226         "bus_clk",
 227         "sclk_mipi",
 228         "phyclk_mipidphy0_bitclkdiv8",
 229         "phyclk_mipidphy0_rxclkesc0",
 230         "sclk_rgb_vclk_to_dsim0"
 231 };
 232
 233 enum samsung_dsim_transfer_type {
 234         EXYNOS_DSI_TX,
 235         EXYNOS_DSI_RX,
 236 };
 237
 238 enum reg_idx {
 239         DSIM_STATUS_REG,        /* Status register */
 240         DSIM_SWRST_REG,         /* Software reset register */
 241         DSIM_CLKCTRL_REG,       /* Clock control register */
 242         DSIM_TIMEOUT_REG,       /* Time out register */
 243         DSIM_CONFIG_REG,        /* Configuration register */
 244         DSIM_ESCMODE_REG,       /* Escape mode register */
 245         DSIM_MDRESOL_REG,
 246         DSIM_MVPORCH_REG,       /* Main display Vporch register */
 247         DSIM_MHPORCH_REG,       /* Main display Hporch register */
 248         DSIM_MSYNC_REG,         /* Main display sync area register */
 249         DSIM_INTSRC_REG,        /* Interrupt source register */
 250         DSIM_INTMSK_REG,        /* Interrupt mask register */
 251         DSIM_PKTHDR_REG,        /* Packet Header FIFO register */
 252         DSIM_PAYLOAD_REG,       /* Payload FIFO register */
 253         DSIM_RXFIFO_REG,        /* Read FIFO register */
 254         DSIM_FIFOCTRL_REG,      /* FIFO status and control register */
 255         DSIM_PLLCTRL_REG,       /* PLL control register */
 256         DSIM_PHYCTRL_REG,
 257         DSIM_PHYTIMING_REG,
 258         DSIM_PHYTIMING1_REG,
 259         DSIM_PHYTIMING2_REG,
 260         NUM_REGS
 261 };
 262
 263 static const unsigned int exynos_reg_ofs[] = {
 264         [DSIM_STATUS_REG] =  0x00,
 265         [DSIM_SWRST_REG] =  0x04,
 266         [DSIM_CLKCTRL_REG] =  0x08,
 267         [DSIM_TIMEOUT_REG] =  0x0c,
 268         [DSIM_CONFIG_REG] =  0x10,
 269         [DSIM_ESCMODE_REG] =  0x14,
 270         [DSIM_MDRESOL_REG] =  0x18,
 271         [DSIM_MVPORCH_REG] =  0x1c,
 272         [DSIM_MHPORCH_REG] =  0x20,
 273         [DSIM_MSYNC_REG] =  0x24,
 274         [DSIM_INTSRC_REG] =  0x2c,
 275         [DSIM_INTMSK_REG] =  0x30,
 276         [DSIM_PKTHDR_REG] =  0x34,
 277         [DSIM_PAYLOAD_REG] =  0x38,
 278         [DSIM_RXFIFO_REG] =  0x3c,
 279         [DSIM_FIFOCTRL_REG] =  0x44,
 280         [DSIM_PLLCTRL_REG] =  0x4c,
 281         [DSIM_PHYCTRL_REG] =  0x5c,
 282         [DSIM_PHYTIMING_REG] =  0x64,
 283         [DSIM_PHYTIMING1_REG] =  0x68,
 284         [DSIM_PHYTIMING2_REG] =  0x6c,
 285 };
 286
 287 static const unsigned int exynos5433_reg_ofs[] = {
 288         [DSIM_STATUS_REG] = 0x04,
 289         [DSIM_SWRST_REG] = 0x0C,
 290         [DSIM_CLKCTRL_REG] = 0x10,
 291         [DSIM_TIMEOUT_REG] = 0x14,
 292         [DSIM_CONFIG_REG] = 0x18,
 293         [DSIM_ESCMODE_REG] = 0x1C,
 294         [DSIM_MDRESOL_REG] = 0x20,
 295         [DSIM_MVPORCH_REG] = 0x24,
 296         [DSIM_MHPORCH_REG] = 0x28,
 297         [DSIM_MSYNC_REG] = 0x2C,
 298         [DSIM_INTSRC_REG] = 0x34,
 299         [DSIM_INTMSK_REG] = 0x38,
 300         [DSIM_PKTHDR_REG] = 0x3C,
 301         [DSIM_PAYLOAD_REG] = 0x40,
 302         [DSIM_RXFIFO_REG] = 0x44,
 303         [DSIM_FIFOCTRL_REG] = 0x4C,
 304         [DSIM_PLLCTRL_REG] = 0x94,
 305         [DSIM_PHYCTRL_REG] = 0xA4,
 306         [DSIM_PHYTIMING_REG] = 0xB4,
 307         [DSIM_PHYTIMING1_REG] = 0xB8,
 308         [DSIM_PHYTIMING2_REG] = 0xBC,
 309 };
 310
 311 enum reg_value_idx {
 312         RESET_TYPE,
 313         PLL_TIMER,
 314         STOP_STATE_CNT,
 315         PHYCTRL_ULPS_EXIT,
 316         PHYCTRL_VREG_LP,
 317         PHYCTRL_SLEW_UP,
 318         PHYTIMING_LPX,
 319         PHYTIMING_HS_EXIT,
 320         PHYTIMING_CLK_PREPARE,
 321         PHYTIMING_CLK_ZERO,
 322         PHYTIMING_CLK_POST,
 323         PHYTIMING_CLK_TRAIL,
 324         PHYTIMING_HS_PREPARE,
 325         PHYTIMING_HS_ZERO,
 326         PHYTIMING_HS_TRAIL
 327 };
 328
 329 static const unsigned int reg_values[] = {
 330         [RESET_TYPE] = DSIM_SWRST,
 331         [PLL_TIMER] = 500,
 332         [STOP_STATE_CNT] = 0xf,
 333         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
 334         [PHYCTRL_VREG_LP] = 0,
 335         [PHYCTRL_SLEW_UP] = 0,
 336         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
 337         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
 338         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
 339         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
 340         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
 341         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
 342         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
 343         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
 344         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
 345 };
 346
 347 static const unsigned int exynos5422_reg_values[] = {
 348         [RESET_TYPE] = DSIM_SWRST,
 349         [PLL_TIMER] = 500,
 350         [STOP_STATE_CNT] = 0xf,
 351         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
 352         [PHYCTRL_VREG_LP] = 0,
 353         [PHYCTRL_SLEW_UP] = 0,
 354         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
 355         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
 356         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 357         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
 358         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 359         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
 360         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
 361         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
 362         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
 363 };
 364
 365 static const unsigned int exynos5433_reg_values[] = {
 366         [RESET_TYPE] = DSIM_FUNCRST,
 367         [PLL_TIMER] = 22200,
 368         [STOP_STATE_CNT] = 0xa,
 369         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
 370         [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
 371         [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
 372         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
 373         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
 374         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 375         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
 376         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 377         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
 378         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
 379         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
 380         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
 381 };
 382
 383 static const unsigned int imx8mm_dsim_reg_values[] = {
 384         [RESET_TYPE] = DSIM_SWRST,
 385         [PLL_TIMER] = 500,
 386         [STOP_STATE_CNT] = 0xf,
 387         [PHYCTRL_ULPS_EXIT] = 0,
 388         [PHYCTRL_VREG_LP] = 0,
 389         [PHYCTRL_SLEW_UP] = 0,
 390         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
 391         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
 392         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
 393         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
 394         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
 395         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
 396         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
 397         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
 398         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
 399 };
 400
 401 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
 402         .reg_ofs = exynos_reg_ofs,
 403         .plltmr_reg = 0x50,
 404         .has_freqband = 1,
 405         .has_clklane_stop = 1,
 406         .num_clks = 2,
 407         .max_freq = 1000,
 408         .wait_for_reset = 1,
 409         .num_bits_resol = 11,
 410         .pll_p_offset = 13,
 411         .reg_values = reg_values,
 412         .m_min = 41,
 413         .m_max = 125,
 414         .min_freq = 500,
 415 };
 416
 417 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
 418         .reg_ofs = exynos_reg_ofs,
 419         .plltmr_reg = 0x50,
 420         .has_freqband = 1,
 421         .has_clklane_stop = 1,
 422         .num_clks = 2,
 423         .max_freq = 1000,
 424         .wait_for_reset = 1,
 425         .num_bits_resol = 11,
 426         .pll_p_offset = 13,
 427         .reg_values = reg_values,
 428         .m_min = 41,
 429         .m_max = 125,
 430         .min_freq = 500,
 431 };
 432
 433 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
 434         .reg_ofs = exynos_reg_ofs,
 435         .plltmr_reg = 0x58,
 436         .num_clks = 2,
 437         .max_freq = 1000,
 438         .wait_for_reset = 1,
 439         .num_bits_resol = 11,
 440         .pll_p_offset = 13,
 441         .reg_values = reg_values,
 442         .m_min = 41,
 443         .m_max = 125,
 444         .min_freq = 500,
 445 };
 446
 447 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
 448         .reg_ofs = exynos5433_reg_ofs,
 449         .plltmr_reg = 0xa0,
 450         .has_clklane_stop = 1,
 451         .num_clks = 5,
 452         .max_freq = 1500,
 453         .wait_for_reset = 0,
 454         .num_bits_resol = 12,
 455         .pll_p_offset = 13,
 456         .reg_values = exynos5433_reg_values,
 457         .m_min = 41,
 458         .m_max = 125,
 459         .min_freq = 500,
 460 };
 461
 462 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
 463         .reg_ofs = exynos5433_reg_ofs,
 464         .plltmr_reg = 0xa0,
 465         .has_clklane_stop = 1,
 466         .num_clks = 2,
 467         .max_freq = 1500,
 468         .wait_for_reset = 1,
 469         .num_bits_resol = 12,
 470         .pll_p_offset = 13,
 471         .reg_values = exynos5422_reg_values,
 472         .m_min = 41,
 473         .m_max = 125,
 474         .min_freq = 500,
 475 };
 476
 477 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
 478         .reg_ofs = exynos5433_reg_ofs,
 479         .plltmr_reg = 0xa0,
 480         .has_clklane_stop = 1,
 481         .num_clks = 2,
 482         .max_freq = 2100,
 483         .wait_for_reset = 0,
 484         .num_bits_resol = 12,
 485         /*
 486          * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
 487          * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
 488          */
 489         .pll_p_offset = 14,
 490         .reg_values = imx8mm_dsim_reg_values,
 491         .m_min = 64,
 492         .m_max = 1023,
 493         .min_freq = 1050,
 494 };
 495
 496 static const struct samsung_dsim_driver_data *
 497 samsung_dsim_types[DSIM_TYPE_COUNT] = {
 498         [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
 499         [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data,
 500         [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
 501         [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
 502         [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
 503         [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
 504         [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
 505 };
 506
 507 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
 508 {
 509         return container_of(h, struct samsung_dsim, dsi_host);
 510 }
 511
 512 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
 513 {
 514         return container_of(b, struct samsung_dsim, bridge);
 515 }
 516
 517 static inline void samsung_dsim_write(struct samsung_dsim *dsi,
 518                                       enum reg_idx idx, u32 val)
 519 {
 520         writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 521 }
 522
 523 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
 524 {
 525         return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 526 }
 527
 528 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
 529 {
 530         if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
 531                 return;
 532
 533         dev_err(dsi->dev, "timeout waiting for reset\n");
 534 }
 535
 536 static void samsung_dsim_reset(struct samsung_dsim *dsi)
 537 {
 538         u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
 539
 540         reinit_completion(&dsi->completed);
 541         samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
 542 }
 543
 544 #ifndef MHZ
 545 #define MHZ     (1000 * 1000)
 546 #endif
 547
 548 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
 549                                                unsigned long fin,
 550                                                unsigned long fout,
 551                                                u8 *p, u16 *m, u8 *s)
 552 {
 553         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 554         unsigned long best_freq = 0;
 555         u32 min_delta = 0xffffffff;
 556         u8 p_min, p_max;
 557         u8 _p, best_p;
 558         u16 _m, best_m;
 559         u8 _s, best_s;
 560
 561         p_min = DIV_ROUND_UP(fin, (12 * MHZ));
 562         p_max = fin / (6 * MHZ);
 563
 564         for (_p = p_min; _p <= p_max; ++_p) {
 565                 for (_s = 0; _s <= 5; ++_s) {
 566                         u64 tmp;
 567                         u32 delta;
 568
 569                         tmp = (u64)fout * (_p << _s);
 570                         do_div(tmp, fin);
 571                         _m = tmp;
 572                         if (_m < driver_data->m_min || _m > driver_data->m_max)
 573                                 continue;
 574
 575                         tmp = (u64)_m * fin;
 576                         do_div(tmp, _p);
 577                         if (tmp < driver_data->min_freq  * MHZ ||
 578                             tmp > driver_data->max_freq * MHZ)
 579                                 continue;
 580
 581                         tmp = (u64)_m * fin;
 582                         do_div(tmp, _p << _s);
 583
 584                         delta = abs(fout - tmp);
 585                         if (delta < min_delta) {
 586                                 best_p = _p;
 587                                 best_m = _m;
 588                                 best_s = _s;
 589                                 min_delta = delta;
 590                                 best_freq = tmp;
 591                         }
 592                 }
 593         }
 594
 595         if (best_freq) {
 596                 *p = best_p;
 597                 *m = best_m;
 598                 *s = best_s;
 599         }
 600
 601         return best_freq;
 602 }
 603
 604 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 605                                           unsigned long freq)
 606 {
 607         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 608         unsigned long fin, fout;
 609         int timeout;
 610         u8 p, s;
 611         u16 m;
 612         u32 reg;
 613
 614         fin = dsi->pll_clk_rate;
 615         fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
 616         if (!fout) {
 617                 dev_err(dsi->dev,
 618                         "failed to find PLL PMS for requested frequency\n");
 619                 return 0;
 620         }
 621         dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
 622
 623         writel(driver_data->reg_values[PLL_TIMER],
 624                dsi->reg_base + driver_data->plltmr_reg);
 625
 626         reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
 627               DSIM_PLL_M(m) | DSIM_PLL_S(s);
 628
 629         if (driver_data->has_freqband) {
 630                 static const unsigned long freq_bands[] = {
 631                         100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
 632                         270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
 633                         510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
 634                         770 * MHZ, 870 * MHZ, 950 * MHZ,
 635                 };
 636                 int band;
 637
 638                 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
 639                         if (fout < freq_bands[band])
 640                                 break;
 641
 642                 dev_dbg(dsi->dev, "band %d\n", band);
 643
 644                 reg |= DSIM_FREQ_BAND(band);
 645         }
 646
 647         if (dsi->swap_dn_dp_clk)
 648                 reg |= DSIM_PLL_DPDNSWAP_CLK;
 649         if (dsi->swap_dn_dp_data)
 650                 reg |= DSIM_PLL_DPDNSWAP_DAT;
 651
 652         samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 653
 654         timeout = 1000;
 655         do {
 656                 if (timeout-- == 0) {
 657                         dev_err(dsi->dev, "PLL failed to stabilize\n");
 658                         return 0;
 659                 }
 660                 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
 661         } while ((reg & DSIM_PLL_STABLE) == 0);
 662
 663         dsi->hs_clock = fout;
 664
 665         return fout;
 666 }
 667
 668 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
 669 {
 670         unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
 671         unsigned long esc_div;
 672         u32 reg;
 673         struct drm_display_mode *m = &dsi->mode;
 674         int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 675
 676         /* m->clock is in KHz */
 677         pix_clk = m->clock * 1000;
 678
 679         /* Use burst_clk_rate if available, otherwise use the pix_clk */
 680         if (dsi->burst_clk_rate)
 681                 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
 682         else
 683                 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));
 684
 685         if (!hs_clk) {
 686                 dev_err(dsi->dev, "failed to configure DSI PLL\n");
 687                 return -EFAULT;
 688         }
 689
 690         byte_clk = hs_clk / 8;
 691         esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
 692         esc_clk = byte_clk / esc_div;
 693
 694         if (esc_clk > 20 * MHZ) {
 695                 ++esc_div;
 696                 esc_clk = byte_clk / esc_div;
 697         }
 698
 699         dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
 700                 hs_clk, byte_clk, esc_clk);
 701
 702         reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
 703         reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
 704                         | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
 705                         | DSIM_BYTE_CLK_SRC_MASK);
 706         reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
 707                         | DSIM_ESC_PRESCALER(esc_div)
 708                         | DSIM_LANE_ESC_CLK_EN_CLK
 709                         | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
 710                         | DSIM_BYTE_CLK_SRC(0)
 711                         | DSIM_TX_REQUEST_HSCLK;
 712         samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
 713
 714         return 0;
 715 }
 716
 717 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
 718 {
 719         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 720         const unsigned int *reg_values = driver_data->reg_values;
 721         u32 reg;
 722         struct phy_configure_opts_mipi_dphy cfg;
 723         int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
 724         int hs_exit, hs_prepare, hs_zero, hs_trail;
 725         unsigned long long byte_clock = dsi->hs_clock / 8;
 726
 727         if (driver_data->has_freqband)
 728                 return;
 729
 730         phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
 731                                                    dsi->lanes, &cfg);
 732
 733         /*
 734          * TODO:
 735          * The tech Applications Processor manuals for i.MX8M Mini, Nano,
 736          * and Plus don't state what the definition of the PHYTIMING
 737          * bits are beyond their address and bit position.
 738          * After reviewing NXP's downstream code, it appears
 739          * that the various PHYTIMING registers take the number
 740          * of cycles and use various dividers on them.  This
 741          * calculation does not result in an exact match to the
 742          * downstream code, but it is very close to the values
 743          * generated by their lookup table, and it appears
 744          * to sync at a variety of resolutions. If someone
 745          * can get a more accurate mathematical equation needed
 746          * for these registers, this should be updated.
 747          */
 748
 749         lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
 750         hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
 751         clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
 752         clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
 753         clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
 754         clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
 755         hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
 756         hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
 757         hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);
 758
 759         /* B D-PHY: D-PHY Master & Slave Analog Block control */
 760         reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
 761                 reg_values[PHYCTRL_SLEW_UP];
 762
 763         samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
 764
 765         /*
 766          * T LPX: Transmitted length of any Low-Power state period
 767          * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
 768          *      burst
 769          */
 770
 771         reg  = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit);
 772
 773         samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
 774
 775         /*
 776          * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
 777          *      Line state immediately before the HS-0 Line state starting the
 778          *      HS transmission
 779          * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
 780          *      transmitting the Clock.
 781          * T CLK_POST: Time that the transmitter continues to send HS clock
 782          *      after the last associated Data Lane has transitioned to LP Mode
 783          *      Interval is defined as the period from the end of T HS-TRAIL to
 784          *      the beginning of T CLK-TRAIL
 785          * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
 786          *      the last payload clock bit of a HS transmission burst
 787          */
 788
 789         reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare)  |
 790               DSIM_PHYTIMING1_CLK_ZERO(clk_zero)        |
 791               DSIM_PHYTIMING1_CLK_POST(clk_post)        |
 792               DSIM_PHYTIMING1_CLK_TRAIL(clk_trail);
 793
 794         samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
 795
 796         /*
 797          * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
 798          *      Line state immediately before the HS-0 Line state starting the
 799          *      HS transmission
 800          * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
 801          *      transmitting the Sync sequence.
 802          * T HS-TRAIL: Time that the transmitter drives the flipped differential
 803          *      state after last payload data bit of a HS transmission burst
 804          */
 805
 806         reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) |
 807               DSIM_PHYTIMING2_HS_ZERO(hs_zero) |
 808               DSIM_PHYTIMING2_HS_TRAIL(hs_trail);
 809
 810         samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
 811 }
 812
 813 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
 814 {
 815         u32 reg;
 816
 817         reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
 818         reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
 819                         | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
 820         samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
 821
 822         reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
 823         reg &= ~DSIM_PLL_EN;
 824         samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 825 }
 826
 827 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
 828 {
 829         u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);
 830
 831         reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
 832                         DSIM_LANE_EN(lane));
 833         samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
 834 }
 835
 836 static int samsung_dsim_init_link(struct samsung_dsim *dsi)
 837 {
 838         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 839         int timeout;
 840         u32 reg;
 841         u32 lanes_mask;
 842
 843         /* Initialize FIFO pointers */
 844         reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
 845         reg &= ~0x1f;
 846         samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
 847
 848         usleep_range(9000, 11000);
 849
 850         reg |= 0x1f;
 851         samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
 852         usleep_range(9000, 11000);
 853
 854         /* DSI configuration */
 855         reg = 0;
 856
 857         /*
 858          * The first bit of mode_flags specifies display configuration.
 859          * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
 860          * mode, otherwise it will support command mode.
 861          */
 862         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 863                 reg |= DSIM_VIDEO_MODE;
 864
 865                 /*
 866                  * The user manual describes that following bits are ignored in
 867                  * command mode.
 868                  */
 869                 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
 870                         reg |= DSIM_MFLUSH_VS;
 871                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 872                         reg |= DSIM_SYNC_INFORM;
 873                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 874                         reg |= DSIM_BURST_MODE;
 875                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
 876                         reg |= DSIM_AUTO_MODE;
 877                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
 878                         reg |= DSIM_HSE_DISABLE_MODE;
 879                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
 880                         reg |= DSIM_HFP_DISABLE_MODE;
 881                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
 882                         reg |= DSIM_HBP_DISABLE_MODE;
 883                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
 884                         reg |= DSIM_HSA_DISABLE_MODE;
 885         }
 886
 887         if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
 888                 reg |= DSIM_EOT_DISABLE;
 889
 890         switch (dsi->format) {
 891         case MIPI_DSI_FMT_RGB888:
 892                 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
 893                 break;
 894         case MIPI_DSI_FMT_RGB666:
 895                 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
 896                 break;
 897         case MIPI_DSI_FMT_RGB666_PACKED:
 898                 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
 899                 break;
 900         case MIPI_DSI_FMT_RGB565:
 901                 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
 902                 break;
 903         default:
 904                 dev_err(dsi->dev, "invalid pixel format\n");
 905                 return -EINVAL;
 906         }
 907
 908         /*
 909          * Use non-continuous clock mode if the periparal wants and
 910          * host controller supports
 911          *
 912          * In non-continous clock mode, host controller will turn off
 913          * the HS clock between high-speed transmissions to reduce
 914          * power consumption.
 915          */
 916         if (driver_data->has_clklane_stop &&
 917             dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
 918                 reg |= DSIM_CLKLANE_STOP;
 919         samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
 920
 921         lanes_mask = BIT(dsi->lanes) - 1;
 922         samsung_dsim_enable_lane(dsi, lanes_mask);
 923
 924         /* Check clock and data lane state are stop state */
 925         timeout = 100;
 926         do {
 927                 if (timeout-- == 0) {
 928                         dev_err(dsi->dev, "waiting for bus lanes timed out\n");
 929                         return -EFAULT;
 930                 }
 931
 932                 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
 933                 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
 934                     != DSIM_STOP_STATE_DAT(lanes_mask))
 935                         continue;
 936         } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
 937
 938         reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
 939         reg &= ~DSIM_STOP_STATE_CNT_MASK;
 940         reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
 941
 942         if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type))
 943                 reg |= DSIM_FORCE_STOP_STATE;
 944
 945         samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
 946
 947         reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
 948         samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);
 949
 950         return 0;
 951 }
 952
 953 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
 954 {
 955         struct drm_display_mode *m = &dsi->mode;
 956         unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
 957         u32 reg;
 958
 959         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 960                 int byte_clk_khz = dsi->hs_clock / 1000 / 8;
 961                 int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
 962                 int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
 963                 int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock;
 964
 965                 /* remove packet overhead when possible */
 966                 hfp = max(hfp - 6, 0);
 967                 hbp = max(hbp - 6, 0);
 968                 hsa = max(hsa - 6, 0);
 969
 970                 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
 971                         hfp, hbp, hsa);
 972
 973                 reg = DSIM_CMD_ALLOW(0xf)
 974                         | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
 975                         | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
 976                 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
 977
 978                 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
 979                 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
 980
 981                 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
 982                         | DSIM_MAIN_HSA(hsa);
 983                 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
 984         }
 985         reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
 986                 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
 987
 988         samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
 989
 990         dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
 991 }
 992
 993 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
 994 {
 995         u32 reg;
 996
 997         reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
 998         if (enable)
 999                 reg |= DSIM_MAIN_STAND_BY;
1000         else
1001                 reg &= ~DSIM_MAIN_STAND_BY;
1002         samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
1003 }
1004
1005 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
1006 {
1007         int timeout = 2000;
1008
1009         do {
1010                 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
1011
1012                 if (!(reg & DSIM_SFR_HEADER_FULL))
1013                         return 0;
1014
1015                 if (!cond_resched())
1016                         usleep_range(950, 1050);
1017         } while (--timeout);
1018
1019         return -ETIMEDOUT;
1020 }
1021
1022 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
1023 {
1024         u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1025
1026         if (lpm)
1027                 v |= DSIM_CMD_LPDT_LP;
1028         else
1029                 v &= ~DSIM_CMD_LPDT_LP;
1030
1031         samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1032 }
1033
1034 static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
1035 {
1036         u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1037
1038         v |= DSIM_FORCE_BTA;
1039         samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1040 }
1041
1042 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
1043                                       struct samsung_dsim_transfer *xfer)
1044 {
1045         struct device *dev = dsi->dev;
1046         struct mipi_dsi_packet *pkt = &xfer->packet;
1047         const u8 *payload = pkt->payload + xfer->tx_done;
1048         u16 length = pkt->payload_length - xfer->tx_done;
1049         bool first = !xfer->tx_done;
1050         u32 reg;
1051
1052         dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
1053                 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1054
1055         if (length > DSI_TX_FIFO_SIZE)
1056                 length = DSI_TX_FIFO_SIZE;
1057
1058         xfer->tx_done += length;
1059
1060         /* Send payload */
1061         while (length >= 4) {
1062                 reg = get_unaligned_le32(payload);
1063                 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1064                 payload += 4;
1065                 length -= 4;
1066         }
1067
1068         reg = 0;
1069         switch (length) {
1070         case 3:
1071                 reg |= payload[2] << 16;
1072                 fallthrough;
1073         case 2:
1074                 reg |= payload[1] << 8;
1075                 fallthrough;
1076         case 1:
1077                 reg |= payload[0];
1078                 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1079                 break;
1080         }
1081
1082         /* Send packet header */
1083         if (!first)
1084                 return;
1085
1086         reg = get_unaligned_le32(pkt->header);
1087         if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
1088                 dev_err(dev, "waiting for header FIFO timed out\n");
1089                 return;
1090         }
1091
1092         if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1093                  dsi->state & DSIM_STATE_CMD_LPM)) {
1094                 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1095                 dsi->state ^= DSIM_STATE_CMD_LPM;
1096         }
1097
1098         samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);
1099
1100         if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1101                 samsung_dsim_force_bta(dsi);
1102 }
1103
1104 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
1105                                         struct samsung_dsim_transfer *xfer)
1106 {
1107         u8 *payload = xfer->rx_payload + xfer->rx_done;
1108         bool first = !xfer->rx_done;
1109         struct device *dev = dsi->dev;
1110         u16 length;
1111         u32 reg;
1112
1113         if (first) {
1114                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1115
1116                 switch (reg & 0x3f) {
1117                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1118                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1119                         if (xfer->rx_len >= 2) {
1120                                 payload[1] = reg >> 16;
1121                                 ++xfer->rx_done;
1122                         }
1123                         fallthrough;
1124                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1125                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1126                         payload[0] = reg >> 8;
1127                         ++xfer->rx_done;
1128                         xfer->rx_len = xfer->rx_done;
1129                         xfer->result = 0;
1130                         goto clear_fifo;
1131                 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1132                         dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
1133                         xfer->result = 0;
1134                         goto clear_fifo;
1135                 }
1136
1137                 length = (reg >> 8) & 0xffff;
1138                 if (length > xfer->rx_len) {
1139                         dev_err(dev,
1140                                 "response too long (%u > %u bytes), stripping\n",
1141                                 xfer->rx_len, length);
1142                         length = xfer->rx_len;
1143                 } else if (length < xfer->rx_len) {
1144                         xfer->rx_len = length;
1145                 }
1146         }
1147
1148         length = xfer->rx_len - xfer->rx_done;
1149         xfer->rx_done += length;
1150
1151         /* Receive payload */
1152         while (length >= 4) {
1153                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1154                 payload[0] = (reg >>  0) & 0xff;
1155                 payload[1] = (reg >>  8) & 0xff;
1156                 payload[2] = (reg >> 16) & 0xff;
1157                 payload[3] = (reg >> 24) & 0xff;
1158                 payload += 4;
1159                 length -= 4;
1160         }
1161
1162         if (length) {
1163                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1164                 switch (length) {
1165                 case 3:
1166                         payload[2] = (reg >> 16) & 0xff;
1167                         fallthrough;
1168                 case 2:
1169                         payload[1] = (reg >> 8) & 0xff;
1170                         fallthrough;
1171                 case 1:
1172                         payload[0] = reg & 0xff;
1173                 }
1174         }
1175
1176         if (xfer->rx_done == xfer->rx_len)
1177                 xfer->result = 0;
1178
1179 clear_fifo:
1180         length = DSI_RX_FIFO_SIZE / 4;
1181         do {
1182                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1183                 if (reg == DSI_RX_FIFO_EMPTY)
1184                         break;
1185         } while (--length);
1186 }
1187
1188 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
1189 {
1190         unsigned long flags;
1191         struct samsung_dsim_transfer *xfer;
1192         bool start = false;
1193
1194 again:
1195         spin_lock_irqsave(&dsi->transfer_lock, flags);
1196
1197         if (list_empty(&dsi->transfer_list)) {
1198                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1199                 return;
1200         }
1201
1202         xfer = list_first_entry(&dsi->transfer_list,
1203                                 struct samsung_dsim_transfer, list);
1204
1205         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1206
1207         if (xfer->packet.payload_length &&
1208             xfer->tx_done == xfer->packet.payload_length)
1209                 /* waiting for RX */
1210                 return;
1211
1212         samsung_dsim_send_to_fifo(dsi, xfer);
1213
1214         if (xfer->packet.payload_length || xfer->rx_len)
1215                 return;
1216
1217         xfer->result = 0;
1218         complete(&xfer->completed);
1219
1220         spin_lock_irqsave(&dsi->transfer_lock, flags);
1221
1222         list_del_init(&xfer->list);
1223         start = !list_empty(&dsi->transfer_list);
1224
1225         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1226
1227         if (start)
1228                 goto again;
1229 }
1230
1231 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
1232 {
1233         struct samsung_dsim_transfer *xfer;
1234         unsigned long flags;
1235         bool start = true;
1236
1237         spin_lock_irqsave(&dsi->transfer_lock, flags);
1238
1239         if (list_empty(&dsi->transfer_list)) {
1240                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1241                 return false;
1242         }
1243
1244         xfer = list_first_entry(&dsi->transfer_list,
1245                                 struct samsung_dsim_transfer, list);
1246
1247         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1248
1249         dev_dbg(dsi->dev,
1250                 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1251                 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1252                 xfer->rx_done);
1253
1254         if (xfer->tx_done != xfer->packet.payload_length)
1255                 return true;
1256
1257         if (xfer->rx_done != xfer->rx_len)
1258                 samsung_dsim_read_from_fifo(dsi, xfer);
1259
1260         if (xfer->rx_done != xfer->rx_len)
1261                 return true;
1262
1263         spin_lock_irqsave(&dsi->transfer_lock, flags);
1264
1265         list_del_init(&xfer->list);
1266         start = !list_empty(&dsi->transfer_list);
1267
1268         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1269
1270         if (!xfer->rx_len)
1271                 xfer->result = 0;
1272         complete(&xfer->completed);
1273
1274         return start;
1275 }
1276
1277 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
1278                                          struct samsung_dsim_transfer *xfer)
1279 {
1280         unsigned long flags;
1281         bool start;
1282
1283         spin_lock_irqsave(&dsi->transfer_lock, flags);
1284
1285         if (!list_empty(&dsi->transfer_list) &&
1286             xfer == list_first_entry(&dsi->transfer_list,
1287                                      struct samsung_dsim_transfer, list)) {
1288                 list_del_init(&xfer->list);
1289                 start = !list_empty(&dsi->transfer_list);
1290                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1291                 if (start)
1292                         samsung_dsim_transfer_start(dsi);
1293                 return;
1294         }
1295
1296         list_del_init(&xfer->list);
1297
1298         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1299 }
1300
1301 static int samsung_dsim_transfer(struct samsung_dsim *dsi,
1302                                  struct samsung_dsim_transfer *xfer)
1303 {
1304         unsigned long flags;
1305         bool stopped;
1306
1307         xfer->tx_done = 0;
1308         xfer->rx_done = 0;
1309         xfer->result = -ETIMEDOUT;
1310         init_completion(&xfer->completed);
1311
1312         spin_lock_irqsave(&dsi->transfer_lock, flags);
1313
1314         stopped = list_empty(&dsi->transfer_list);
1315         list_add_tail(&xfer->list, &dsi->transfer_list);
1316
1317         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1318
1319         if (stopped)
1320                 samsung_dsim_transfer_start(dsi);
1321
1322         wait_for_completion_timeout(&xfer->completed,
1323                                     msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1324         if (xfer->result == -ETIMEDOUT) {
1325                 struct mipi_dsi_packet *pkt = &xfer->packet;
1326
1327                 samsung_dsim_remove_transfer(dsi, xfer);
1328                 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1329                         (int)pkt->payload_length, pkt->payload);
1330                 return -ETIMEDOUT;
1331         }
1332
1333         /* Also covers hardware timeout condition */
1334         return xfer->result;
1335 }
1336
1337 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
1338 {
1339         struct samsung_dsim *dsi = dev_id;
1340         u32 status;
1341
1342         status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
1343         if (!status) {
1344                 static unsigned long j;
1345
1346                 if (printk_timed_ratelimit(&j, 500))
1347                         dev_warn(dsi->dev, "spurious interrupt\n");
1348                 return IRQ_HANDLED;
1349         }
1350         samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);
1351
1352         if (status & DSIM_INT_SW_RST_RELEASE) {
1353                 unsigned long mask = ~(DSIM_INT_RX_DONE |
1354                                        DSIM_INT_SFR_FIFO_EMPTY |
1355                                        DSIM_INT_SFR_HDR_FIFO_EMPTY |
1356                                        DSIM_INT_RX_ECC_ERR |
1357                                        DSIM_INT_SW_RST_RELEASE);
1358                 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
1359                 complete(&dsi->completed);
1360                 return IRQ_HANDLED;
1361         }
1362
1363         if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1364                         DSIM_INT_PLL_STABLE)))
1365                 return IRQ_HANDLED;
1366
1367         if (samsung_dsim_transfer_finish(dsi))
1368                 samsung_dsim_transfer_start(dsi);
1369
1370         return IRQ_HANDLED;
1371 }
1372
1373 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
1374 {
1375         enable_irq(dsi->irq);
1376
1377         if (dsi->te_gpio)
1378                 enable_irq(gpiod_to_irq(dsi->te_gpio));
1379 }
1380
1381 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
1382 {
1383         if (dsi->te_gpio)
1384                 disable_irq(gpiod_to_irq(dsi->te_gpio));
1385
1386         disable_irq(dsi->irq);
1387 }
1388
1389 static int samsung_dsim_init(struct samsung_dsim *dsi)
1390 {
1391         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1392
1393         if (dsi->state & DSIM_STATE_INITIALIZED)
1394                 return 0;
1395
1396         samsung_dsim_reset(dsi);
1397         samsung_dsim_enable_irq(dsi);
1398
1399         if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1400                 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
1401
1402         samsung_dsim_enable_clock(dsi);
1403         if (driver_data->wait_for_reset)
1404                 samsung_dsim_wait_for_reset(dsi);
1405         samsung_dsim_set_phy_ctrl(dsi);
1406         samsung_dsim_init_link(dsi);
1407
1408         dsi->state |= DSIM_STATE_INITIALIZED;
1409
1410         return 0;
1411 }
1412
1413 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
1414                                            struct drm_bridge_state *old_bridge_state)
1415 {
1416         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1417         int ret;
1418
1419         if (dsi->state & DSIM_STATE_ENABLED)
1420                 return;
1421
1422         ret = pm_runtime_resume_and_get(dsi->dev);
1423         if (ret < 0) {
1424                 dev_err(dsi->dev, "failed to enable DSI device.\n");
1425                 return;
1426         }
1427
1428         dsi->state |= DSIM_STATE_ENABLED;
1429
1430         /*
1431          * For Exynos-DSIM the downstream bridge, or panel are expecting
1432          * the host initialization during DSI transfer.
1433          */
1434         if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1435                 ret = samsung_dsim_init(dsi);
1436                 if (ret)
1437                         return;
1438
1439                 samsung_dsim_set_display_mode(dsi);
1440                 samsung_dsim_set_display_enable(dsi, true);
1441         }
1442 }
1443
1444 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
1445                                        struct drm_bridge_state *old_bridge_state)
1446 {
1447         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1448         u32 reg;
1449
1450         if (samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1451                 samsung_dsim_set_display_mode(dsi);
1452                 samsung_dsim_set_display_enable(dsi, true);
1453         } else {
1454                 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1455                 reg &= ~DSIM_FORCE_STOP_STATE;
1456                 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
1457         }
1458
1459         dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1460 }
1461
1462 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
1463                                         struct drm_bridge_state *old_bridge_state)
1464 {
1465         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1466         u32 reg;
1467
1468         if (!(dsi->state & DSIM_STATE_ENABLED))
1469                 return;
1470
1471         if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1472                 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1473                 reg |= DSIM_FORCE_STOP_STATE;
1474                 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
1475         }
1476
1477         dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1478 }
1479
1480 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
1481                                              struct drm_bridge_state *old_bridge_state)
1482 {
1483         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1484
1485         samsung_dsim_set_display_enable(dsi, false);
1486
1487         dsi->state &= ~DSIM_STATE_ENABLED;
1488         pm_runtime_put_sync(dsi->dev);
1489 }
1490
1491 /*
1492  * This pixel output formats list referenced from,
1493  * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
1494  * 3.7.4 Pixel formats
1495  * Table 14. DSI pixel packing formats
1496  */
1497 static const u32 samsung_dsim_pixel_output_fmts[] = {
1498         MEDIA_BUS_FMT_YUYV10_1X20,
1499         MEDIA_BUS_FMT_YUYV12_1X24,
1500         MEDIA_BUS_FMT_UYVY8_1X16,
1501         MEDIA_BUS_FMT_RGB101010_1X30,
1502         MEDIA_BUS_FMT_RGB121212_1X36,
1503         MEDIA_BUS_FMT_RGB565_1X16,
1504         MEDIA_BUS_FMT_RGB666_1X18,
1505         MEDIA_BUS_FMT_RGB888_1X24,
1506 };
1507
1508 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt)
1509 {
1510         int i;
1511
1512         if (fmt == MEDIA_BUS_FMT_FIXED)
1513                 return false;
1514
1515         for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) {
1516                 if (samsung_dsim_pixel_output_fmts[i] == fmt)
1517                         return true;
1518         }
1519
1520         return false;
1521 }
1522
1523 static u32 *
1524 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1525                                        struct drm_bridge_state *bridge_state,
1526                                        struct drm_crtc_state *crtc_state,
1527                                        struct drm_connector_state *conn_state,
1528                                        u32 output_fmt,
1529                                        unsigned int *num_input_fmts)
1530 {
1531         u32 *input_fmts;
1532
1533         input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
1534         if (!input_fmts)
1535                 return NULL;
1536
1537         if (!samsung_dsim_pixel_output_fmt_supported(output_fmt))
1538                 /*
1539                  * Some bridge/display drivers are still not able to pass the
1540                  * correct format, so handle those pipelines by falling back
1541                  * to the default format till the supported formats finalized.
1542                  */
1543                 output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
1544
1545         input_fmts[0] = output_fmt;
1546         *num_input_fmts = 1;
1547
1548         return input_fmts;
1549 }
1550
1551 static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
1552                                      struct drm_bridge_state *bridge_state,
1553                                      struct drm_crtc_state *crtc_state,
1554                                      struct drm_connector_state *conn_state)
1555 {
1556         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1557         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1558
1559         /*
1560          * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
1561          * inverts HS/VS/DE sync signals polarity, therefore, while
1562          * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
1563          * 13.6.3.5.2 RGB interface
1564          * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
1565          * 13.6.2.7.2 RGB interface
1566          * both claim "Vsync, Hsync, and VDEN are active high signals.", the
1567          * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
1568          *
1569          * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not
1570          * implement the same behavior, therefore LCDIFv3 must generate
1571          * HS/VS/DE signals active HIGH.
1572          */
1573         if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
1574                 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1575                 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1576         } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
1577                 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1578                 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1579         }
1580
1581         return 0;
1582 }
1583
1584 static void samsung_dsim_mode_set(struct drm_bridge *bridge,
1585                                   const struct drm_display_mode *mode,
1586                                   const struct drm_display_mode *adjusted_mode)
1587 {
1588         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1589
1590         drm_mode_copy(&dsi->mode, adjusted_mode);
1591 }
1592
1593 static int samsung_dsim_attach(struct drm_bridge *bridge,
1594                                enum drm_bridge_attach_flags flags)
1595 {
1596         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1597
1598         return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
1599                                  flags);
1600 }
1601
1602 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
1603         .atomic_duplicate_state         = drm_atomic_helper_bridge_duplicate_state,
1604         .atomic_destroy_state           = drm_atomic_helper_bridge_destroy_state,
1605         .atomic_reset                   = drm_atomic_helper_bridge_reset,
1606         .atomic_get_input_bus_fmts      = samsung_dsim_atomic_get_input_bus_fmts,
1607         .atomic_check                   = samsung_dsim_atomic_check,
1608         .atomic_pre_enable              = samsung_dsim_atomic_pre_enable,
1609         .atomic_enable                  = samsung_dsim_atomic_enable,
1610         .atomic_disable                 = samsung_dsim_atomic_disable,
1611         .atomic_post_disable            = samsung_dsim_atomic_post_disable,
1612         .mode_set                       = samsung_dsim_mode_set,
1613         .attach                         = samsung_dsim_attach,
1614 };
1615
1616 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id)
1617 {
1618         struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id;
1619         const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1620
1621         if (pdata->host_ops && pdata->host_ops->te_irq_handler)
1622                 return pdata->host_ops->te_irq_handler(dsi);
1623
1624         return IRQ_HANDLED;
1625 }
1626
1627 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev)
1628 {
1629         int te_gpio_irq;
1630         int ret;
1631
1632         dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
1633         if (!dsi->te_gpio)
1634                 return 0;
1635         else if (IS_ERR(dsi->te_gpio))
1636                 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");
1637
1638         te_gpio_irq = gpiod_to_irq(dsi->te_gpio);
1639
1640         ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL,
1641                                    IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1642         if (ret) {
1643                 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1644                 gpiod_put(dsi->te_gpio);
1645                 return ret;
1646         }
1647
1648         return 0;
1649 }
1650
1651 static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
1652                                     struct mipi_dsi_device *device)
1653 {
1654         struct samsung_dsim *dsi = host_to_dsi(host);
1655         const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1656         struct device *dev = dsi->dev;
1657         struct device_node *np = dev->of_node;
1658         struct device_node *remote;
1659         struct drm_panel *panel;
1660         int ret;
1661
1662         /*
1663          * Devices can also be child nodes when we also control that device
1664          * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
1665          *
1666          * Lookup for a child node of the given parent that isn't either port
1667          * or ports.
1668          */
1669         for_each_available_child_of_node(np, remote) {
1670                 if (of_node_name_eq(remote, "port") ||
1671                     of_node_name_eq(remote, "ports"))
1672                         continue;
1673
1674                 goto of_find_panel_or_bridge;
1675         }
1676
1677         /*
1678          * of_graph_get_remote_node() produces a noisy error message if port
1679          * node isn't found and the absence of the port is a legit case here,
1680          * so at first we silently check whether graph presents in the
1681          * device-tree node.
1682          */
1683         if (!of_graph_is_present(np))
1684                 return -ENODEV;
1685
1686         remote = of_graph_get_remote_node(np, 1, 0);
1687
1688 of_find_panel_or_bridge:
1689         if (!remote)
1690                 return -ENODEV;
1691
1692         panel = of_drm_find_panel(remote);
1693         if (!IS_ERR(panel)) {
1694                 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
1695         } else {
1696                 dsi->out_bridge = of_drm_find_bridge(remote);
1697                 if (!dsi->out_bridge)
1698                         dsi->out_bridge = ERR_PTR(-EINVAL);
1699         }
1700
1701         of_node_put(remote);
1702
1703         if (IS_ERR(dsi->out_bridge)) {
1704                 ret = PTR_ERR(dsi->out_bridge);
1705                 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
1706                 return ret;
1707         }
1708
1709         DRM_DEV_INFO(dev, "Attached %s device\n", device->name);
1710
1711         drm_bridge_add(&dsi->bridge);
1712
1713         /*
1714          * This is a temporary solution and should be made by more generic way.
1715          *
1716          * If attached panel device is for command mode one, dsi should register
1717          * TE interrupt handler.
1718          */
1719         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1720                 ret = samsung_dsim_register_te_irq(dsi, &device->dev);
1721                 if (ret)
1722                         return ret;
1723         }
1724
1725         if (pdata->host_ops && pdata->host_ops->attach) {
1726                 ret = pdata->host_ops->attach(dsi, device);
1727                 if (ret)
1728                         return ret;
1729         }
1730
1731         dsi->lanes = device->lanes;
1732         dsi->format = device->format;
1733         dsi->mode_flags = device->mode_flags;
1734
1735         return 0;
1736 }
1737
1738 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi)
1739 {
1740         if (dsi->te_gpio) {
1741                 free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
1742                 gpiod_put(dsi->te_gpio);
1743         }
1744 }
1745
1746 static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
1747                                     struct mipi_dsi_device *device)
1748 {
1749         struct samsung_dsim *dsi = host_to_dsi(host);
1750         const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1751
1752         dsi->out_bridge = NULL;
1753
1754         if (pdata->host_ops && pdata->host_ops->detach)
1755                 pdata->host_ops->detach(dsi, device);
1756
1757         samsung_dsim_unregister_te_irq(dsi);
1758
1759         drm_bridge_remove(&dsi->bridge);
1760
1761         return 0;
1762 }
1763
1764 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
1765                                           const struct mipi_dsi_msg *msg)
1766 {
1767         struct samsung_dsim *dsi = host_to_dsi(host);
1768         struct samsung_dsim_transfer xfer;
1769         int ret;
1770
1771         if (!(dsi->state & DSIM_STATE_ENABLED))
1772                 return -EINVAL;
1773
1774         ret = samsung_dsim_init(dsi);
1775         if (ret)
1776                 return ret;
1777
1778         ret = mipi_dsi_create_packet(&xfer.packet, msg);
1779         if (ret < 0)
1780                 return ret;
1781
1782         xfer.rx_len = msg->rx_len;
1783         xfer.rx_payload = msg->rx_buf;
1784         xfer.flags = msg->flags;
1785
1786         ret = samsung_dsim_transfer(dsi, &xfer);
1787         return (ret < 0) ? ret : xfer.rx_done;
1788 }
1789
1790 static const struct mipi_dsi_host_ops samsung_dsim_ops = {
1791         .attach = samsung_dsim_host_attach,
1792         .detach = samsung_dsim_host_detach,
1793         .transfer = samsung_dsim_host_transfer,
1794 };
1795
1796 static int samsung_dsim_of_read_u32(const struct device_node *np,
1797                                     const char *propname, u32 *out_value, bool optional)
1798 {
1799         int ret = of_property_read_u32(np, propname, out_value);
1800
1801         if (ret < 0 && !optional)
1802                 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1803
1804         return ret;
1805 }
1806
1807 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
1808 {
1809         struct device *dev = dsi->dev;
1810         struct device_node *node = dev->of_node;
1811         u32 lane_polarities[5] = { 0 };
1812         struct device_node *endpoint;
1813         int i, nr_lanes, ret;
1814         struct clk *pll_clk;
1815
1816         ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
1817                                        &dsi->pll_clk_rate, 1);
1818         /* If it doesn't exist, read it from the clock instead of failing */
1819         if (ret < 0) {
1820                 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
1821                 pll_clk = devm_clk_get(dev, "sclk_mipi");
1822                 if (!IS_ERR(pll_clk))
1823                         dsi->pll_clk_rate = clk_get_rate(pll_clk);
1824                 else
1825                         return PTR_ERR(pll_clk);
1826         }
1827
1828         /* If it doesn't exist, use pixel clock instead of failing */
1829         ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
1830                                        &dsi->burst_clk_rate, 1);
1831         if (ret < 0) {
1832                 dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
1833                 dsi->burst_clk_rate = 0;
1834         }
1835
1836         ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
1837                                        &dsi->esc_clk_rate, 0);
1838         if (ret < 0)
1839                 return ret;
1840
1841         endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1842         nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1843         if (nr_lanes > 0 && nr_lanes <= 4) {
1844                 /* Polarity 0 is clock lane, 1..4 are data lanes. */
1845                 of_property_read_u32_array(endpoint, "lane-polarities",
1846                                            lane_polarities, nr_lanes + 1);
1847                 for (i = 1; i <= nr_lanes; i++) {
1848                         if (lane_polarities[1] != lane_polarities[i])
1849                                 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1850                 }
1851                 if (lane_polarities[0])
1852                         dsi->swap_dn_dp_clk = true;
1853                 if (lane_polarities[1])
1854                         dsi->swap_dn_dp_data = true;
1855         }
1856
1857         return 0;
1858 }
1859
1860 static int generic_dsim_register_host(struct samsung_dsim *dsi)
1861 {
1862         return mipi_dsi_host_register(&dsi->dsi_host);
1863 }
1864
1865 static void generic_dsim_unregister_host(struct samsung_dsim *dsi)
1866 {
1867         mipi_dsi_host_unregister(&dsi->dsi_host);
1868 }
1869
1870 static const struct samsung_dsim_host_ops generic_dsim_host_ops = {
1871         .register_host = generic_dsim_register_host,
1872         .unregister_host = generic_dsim_unregister_host,
1873 };
1874
1875 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = {
1876         .input_bus_flags = DRM_BUS_FLAG_DE_HIGH,
1877 };
1878
1879 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = {
1880         .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1881 };
1882
1883 int samsung_dsim_probe(struct platform_device *pdev)
1884 {
1885         struct device *dev = &pdev->dev;
1886         struct samsung_dsim *dsi;
1887         int ret, i;
1888
1889         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1890         if (!dsi)
1891                 return -ENOMEM;
1892
1893         init_completion(&dsi->completed);
1894         spin_lock_init(&dsi->transfer_lock);
1895         INIT_LIST_HEAD(&dsi->transfer_list);
1896
1897         dsi->dsi_host.ops = &samsung_dsim_ops;
1898         dsi->dsi_host.dev = dev;
1899
1900         dsi->dev = dev;
1901         dsi->plat_data = of_device_get_match_data(dev);
1902         dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];
1903
1904         dsi->supplies[0].supply = "vddcore";
1905         dsi->supplies[1].supply = "vddio";
1906         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1907                                       dsi->supplies);
1908         if (ret)
1909                 return dev_err_probe(dev, ret, "failed to get regulators\n");
1910
1911         dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
1912                                  sizeof(*dsi->clks), GFP_KERNEL);
1913         if (!dsi->clks)
1914                 return -ENOMEM;
1915
1916         for (i = 0; i < dsi->driver_data->num_clks; i++) {
1917                 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1918                 if (IS_ERR(dsi->clks[i])) {
1919                         if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1920                                 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1921                                 if (!IS_ERR(dsi->clks[i]))
1922                                         continue;
1923                         }
1924
1925                         dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
1926                         return PTR_ERR(dsi->clks[i]);
1927                 }
1928         }
1929
1930         dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1931         if (IS_ERR(dsi->reg_base))
1932                 return PTR_ERR(dsi->reg_base);
1933
1934         dsi->phy = devm_phy_optional_get(dev, "dsim");
1935         if (IS_ERR(dsi->phy)) {
1936                 dev_info(dev, "failed to get dsim phy\n");
1937                 return PTR_ERR(dsi->phy);
1938         }
1939
1940         dsi->irq = platform_get_irq(pdev, 0);
1941         if (dsi->irq < 0)
1942                 return dsi->irq;
1943
1944         ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1945                                         samsung_dsim_irq,
1946                                         IRQF_ONESHOT | IRQF_NO_AUTOEN,
1947                                         dev_name(dev), dsi);
1948         if (ret) {
1949                 dev_err(dev, "failed to request dsi irq\n");
1950                 return ret;
1951         }
1952
1953         ret = samsung_dsim_parse_dt(dsi);
1954         if (ret)
1955                 return ret;
1956
1957         platform_set_drvdata(pdev, dsi);
1958
1959         pm_runtime_enable(dev);
1960
1961         dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
1962         dsi->bridge.of_node = dev->of_node;
1963         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1964
1965         /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
1966         if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)
1967                 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
1968         else
1969                 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;
1970
1971         if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
1972                 ret = dsi->plat_data->host_ops->register_host(dsi);
1973
1974         if (ret)
1975                 goto err_disable_runtime;
1976
1977         return 0;
1978
1979 err_disable_runtime:
1980         pm_runtime_disable(dev);
1981
1982         return ret;
1983 }
1984 EXPORT_SYMBOL_GPL(samsung_dsim_probe);
1985
1986 int samsung_dsim_remove(struct platform_device *pdev)
1987 {
1988         struct samsung_dsim *dsi = platform_get_drvdata(pdev);
1989
1990         pm_runtime_disable(&pdev->dev);
1991
1992         if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
1993                 dsi->plat_data->host_ops->unregister_host(dsi);
1994
1995         return 0;
1996 }
1997 EXPORT_SYMBOL_GPL(samsung_dsim_remove);
1998
1999 static int __maybe_unused samsung_dsim_suspend(struct device *dev)
2000 {
2001         struct samsung_dsim *dsi = dev_get_drvdata(dev);
2002         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2003         int ret, i;
2004
2005         usleep_range(10000, 20000);
2006
2007         if (dsi->state & DSIM_STATE_INITIALIZED) {
2008                 dsi->state &= ~DSIM_STATE_INITIALIZED;
2009
2010                 samsung_dsim_disable_clock(dsi);
2011
2012                 samsung_dsim_disable_irq(dsi);
2013         }
2014
2015         dsi->state &= ~DSIM_STATE_CMD_LPM;
2016
2017         phy_power_off(dsi->phy);
2018
2019         for (i = driver_data->num_clks - 1; i > -1; i--)
2020                 clk_disable_unprepare(dsi->clks[i]);
2021
2022         ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2023         if (ret < 0)
2024                 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
2025
2026         return 0;
2027 }
2028
2029 static int __maybe_unused samsung_dsim_resume(struct device *dev)
2030 {
2031         struct samsung_dsim *dsi = dev_get_drvdata(dev);
2032         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2033         int ret, i;
2034
2035         ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2036         if (ret < 0) {
2037                 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
2038                 return ret;
2039         }
2040
2041         for (i = 0; i < driver_data->num_clks; i++) {
2042                 ret = clk_prepare_enable(dsi->clks[i]);
2043                 if (ret < 0)
2044                         goto err_clk;
2045         }
2046
2047         ret = phy_power_on(dsi->phy);
2048         if (ret < 0) {
2049                 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
2050                 goto err_clk;
2051         }
2052
2053         return 0;
2054
2055 err_clk:
2056         while (--i > -1)
2057                 clk_disable_unprepare(dsi->clks[i]);
2058         regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2059
2060         return ret;
2061 }
2062
2063 const struct dev_pm_ops samsung_dsim_pm_ops = {
2064         SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
2065         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2066                                 pm_runtime_force_resume)
2067 };
2068 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);
2069
2070 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
2071         .hw_type = DSIM_TYPE_IMX8MM,
2072         .host_ops = &generic_dsim_host_ops,
2073 };
2074
2075 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = {
2076         .hw_type = DSIM_TYPE_IMX8MP,
2077         .host_ops = &generic_dsim_host_ops,
2078 };
2079
2080 static const struct of_device_id samsung_dsim_of_match[] = {
2081         {
2082                 .compatible = "fsl,imx8mm-mipi-dsim",
2083                 .data = &samsung_dsim_imx8mm_pdata,
2084         },
2085         {
2086                 .compatible = "fsl,imx8mp-mipi-dsim",
2087                 .data = &samsung_dsim_imx8mp_pdata,
2088         },
2089         { /* sentinel. */ }
2090 };
2091 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
2092
2093 static struct platform_driver samsung_dsim_driver = {
2094         .probe = samsung_dsim_probe,
2095         .remove = samsung_dsim_remove,
2096         .driver = {
2097                    .name = "samsung-dsim",
2098                    .pm = &samsung_dsim_pm_ops,
2099                    .of_match_table = samsung_dsim_of_match,
2100         },
2101 };
2102
2103 module_platform_driver(samsung_dsim_driver);
2104
2105 MODULE_AUTHOR("Jagan Teki <[email protected]>");
2106 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
2107 MODULE_LICENSE("GPL");