1 // SPDX-License-Identifier: GPL-2.0
2 /* pci.c: UltraSparc PCI controller support.
8 * OF tree based PCI bus probing taken from the PowerPC port
9 * with minor modifications, see there for credits.
12 #include <linux/export.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/capability.h>
17 #include <linux/errno.h>
18 #include <linux/pci.h>
19 #include <linux/msi.h>
20 #include <linux/irq.h>
21 #include <linux/init.h>
23 #include <linux/of_device.h>
24 #include <linux/pgtable.h>
26 #include <linux/uaccess.h>
34 /* List of all PCI controllers found in the system. */
35 struct pci_pbm_info *pci_pbm_root = NULL;
37 /* Each PBM found gets a unique index. */
40 volatile int pci_poke_in_progress;
41 volatile int pci_poke_cpu = -1;
42 volatile int pci_poke_faulted;
44 static DEFINE_SPINLOCK(pci_poke_lock);
46 void pci_config_read8(u8 *addr, u8 *ret)
51 spin_lock_irqsave(&pci_poke_lock, flags);
52 pci_poke_cpu = smp_processor_id();
53 pci_poke_in_progress = 1;
55 __asm__ __volatile__("membar #Sync\n\t"
56 "lduba [%1] %2, %0\n\t"
59 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
61 pci_poke_in_progress = 0;
63 if (!pci_poke_faulted)
65 spin_unlock_irqrestore(&pci_poke_lock, flags);
68 void pci_config_read16(u16 *addr, u16 *ret)
73 spin_lock_irqsave(&pci_poke_lock, flags);
74 pci_poke_cpu = smp_processor_id();
75 pci_poke_in_progress = 1;
77 __asm__ __volatile__("membar #Sync\n\t"
78 "lduha [%1] %2, %0\n\t"
81 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
83 pci_poke_in_progress = 0;
85 if (!pci_poke_faulted)
87 spin_unlock_irqrestore(&pci_poke_lock, flags);
90 void pci_config_read32(u32 *addr, u32 *ret)
95 spin_lock_irqsave(&pci_poke_lock, flags);
96 pci_poke_cpu = smp_processor_id();
97 pci_poke_in_progress = 1;
99 __asm__ __volatile__("membar #Sync\n\t"
100 "lduwa [%1] %2, %0\n\t"
103 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
105 pci_poke_in_progress = 0;
107 if (!pci_poke_faulted)
109 spin_unlock_irqrestore(&pci_poke_lock, flags);
112 void pci_config_write8(u8 *addr, u8 val)
116 spin_lock_irqsave(&pci_poke_lock, flags);
117 pci_poke_cpu = smp_processor_id();
118 pci_poke_in_progress = 1;
119 pci_poke_faulted = 0;
120 __asm__ __volatile__("membar #Sync\n\t"
121 "stba %0, [%1] %2\n\t"
124 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
126 pci_poke_in_progress = 0;
128 spin_unlock_irqrestore(&pci_poke_lock, flags);
131 void pci_config_write16(u16 *addr, u16 val)
135 spin_lock_irqsave(&pci_poke_lock, flags);
136 pci_poke_cpu = smp_processor_id();
137 pci_poke_in_progress = 1;
138 pci_poke_faulted = 0;
139 __asm__ __volatile__("membar #Sync\n\t"
140 "stha %0, [%1] %2\n\t"
143 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
145 pci_poke_in_progress = 0;
147 spin_unlock_irqrestore(&pci_poke_lock, flags);
150 void pci_config_write32(u32 *addr, u32 val)
154 spin_lock_irqsave(&pci_poke_lock, flags);
155 pci_poke_cpu = smp_processor_id();
156 pci_poke_in_progress = 1;
157 pci_poke_faulted = 0;
158 __asm__ __volatile__("membar #Sync\n\t"
159 "stwa %0, [%1] %2\n\t"
162 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
164 pci_poke_in_progress = 0;
166 spin_unlock_irqrestore(&pci_poke_lock, flags);
169 static int ofpci_verbose;
171 static int __init ofpci_debug(char *str)
175 get_option(&str, &val);
181 __setup("ofpci_debug=", ofpci_debug);
183 static unsigned long pci_parse_of_flags(u32 addr0)
185 unsigned long flags = 0;
187 if (addr0 & 0x02000000) {
188 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
189 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
190 if (addr0 & 0x01000000)
191 flags |= IORESOURCE_MEM_64
192 | PCI_BASE_ADDRESS_MEM_TYPE_64;
193 if (addr0 & 0x40000000)
194 flags |= IORESOURCE_PREFETCH
195 | PCI_BASE_ADDRESS_MEM_PREFETCH;
196 } else if (addr0 & 0x01000000)
197 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
201 /* The of_device layer has translated all of the assigned-address properties
202 * into physical address resources, we only have to figure out the register
205 static void pci_parse_of_addrs(struct platform_device *op,
206 struct device_node *node,
209 struct resource *op_res;
213 addrs = of_get_property(node, "assigned-addresses", &proplen);
217 pci_info(dev, " parse addresses (%d bytes) @ %p\n",
219 op_res = &op->resource[0];
220 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
221 struct resource *res;
225 flags = pci_parse_of_flags(addrs[0]);
230 pci_info(dev, " start: %llx, end: %llx, i: %x\n",
231 op_res->start, op_res->end, i);
233 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
234 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
235 } else if (i == dev->rom_base_reg) {
236 res = &dev->resource[PCI_ROM_RESOURCE];
237 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
239 pci_err(dev, "bad cfg reg num 0x%x\n", i);
242 res->start = op_res->start;
243 res->end = op_res->end;
245 res->name = pci_name(dev);
247 pci_info(dev, "reg 0x%x: %pR\n", i, res);
251 static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
252 void *stc, void *host_controller,
253 struct platform_device *op,
258 sd->host_controller = host_controller;
260 sd->numa_node = numa_node;
263 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
264 struct device_node *node,
265 struct pci_bus *bus, int devfn)
267 struct dev_archdata *sd;
268 struct platform_device *op;
272 dev = pci_alloc_dev(bus);
276 op = of_find_device_by_node(node);
277 sd = &dev->dev.archdata;
278 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
280 sd = &op->dev.archdata;
281 sd->iommu = pbm->iommu;
283 sd->numa_node = pbm->numa_node;
285 if (of_node_name_eq(node, "ebus"))
286 of_propagate_archdata(op);
289 pci_info(bus," create device, devfn: %x, type: %s\n",
290 devfn, of_node_get_device_type(node));
293 dev->dev.parent = bus->bridge;
294 dev->dev.bus = &pci_bus_type;
295 dev->dev.of_node = of_node_get(node);
297 dev->multifunction = 0; /* maybe a lie? */
298 set_pcie_port_type(dev);
300 pci_dev_assign_slot(dev);
301 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
302 dev->device = of_getintprop_default(node, "device-id", 0xffff);
303 dev->subsystem_vendor =
304 of_getintprop_default(node, "subsystem-vendor-id", 0);
305 dev->subsystem_device =
306 of_getintprop_default(node, "subsystem-id", 0);
308 dev->cfg_size = pci_cfg_space_size(dev);
310 /* We can't actually use the firmware value, we have
311 * to read what is in the register right now. One
312 * reason is that in the case of IDE interfaces the
313 * firmware can sample the value before the the IDE
314 * interface is programmed into native mode.
316 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
317 dev->class = class >> 8;
318 dev->revision = class & 0xff;
320 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
321 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
323 /* I have seen IDE devices which will not respond to
324 * the bmdma simplex check reads if bus mastering is
327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
330 dev->current_state = PCI_UNKNOWN; /* unknown power state */
331 dev->error_state = pci_channel_io_normal;
332 dev->dma_mask = 0xffffffff;
334 if (of_node_name_eq(node, "pci")) {
335 /* a PCI-PCI bridge */
336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 } else if (of_node_is_type(node, "cardbus")) {
339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 dev->rom_base_reg = PCI_ROM_ADDRESS;
344 dev->irq = sd->op->archdata.irqs[0];
345 if (dev->irq == 0xffffffff)
346 dev->irq = PCI_IRQ_NONE;
349 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
350 dev->vendor, dev->device, dev->hdr_type, dev->class);
352 pci_parse_of_addrs(sd->op, node, dev);
355 pci_info(dev, " adding to system ...\n");
357 pci_device_add(dev, bus);
362 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
364 u32 idx, first, last;
368 for (idx = 0; idx < 8; idx++) {
369 if ((map & (1 << idx)) != 0) {
381 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
382 * a proper 'ranges' property.
384 static void apb_fake_ranges(struct pci_dev *dev,
386 struct pci_pbm_info *pbm)
388 struct pci_bus_region region;
389 struct resource *res;
393 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
394 apb_calc_first_last(map, &first, &last);
395 res = bus->resource[0];
396 res->flags = IORESOURCE_IO;
397 region.start = (first << 21);
398 region.end = (last << 21) + ((1 << 21) - 1);
399 pcibios_bus_to_resource(dev->bus, res, ®ion);
401 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
402 apb_calc_first_last(map, &first, &last);
403 res = bus->resource[1];
404 res->flags = IORESOURCE_MEM;
405 region.start = (first << 29);
406 region.end = (last << 29) + ((1 << 29) - 1);
407 pcibios_bus_to_resource(dev->bus, res, ®ion);
410 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
411 struct device_node *node,
412 struct pci_bus *bus);
414 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
416 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
417 struct device_node *node,
421 const u32 *busrange, *ranges;
423 struct pci_bus_region region;
424 struct resource *res;
429 pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
431 /* parse bus-range property */
432 busrange = of_get_property(node, "bus-range", &len);
433 if (busrange == NULL || len != 8) {
434 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
440 pci_info(dev, " Bridge bus range [%u --> %u]\n",
441 busrange[0], busrange[1]);
443 ranges = of_get_property(node, "ranges", &len);
445 if (ranges == NULL) {
446 const char *model = of_get_property(node, "model", NULL);
447 if (model && !strcmp(model, "SUNW,simba"))
451 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
453 pci_err(dev, "Failed to create pci bus for %pOF\n",
458 bus->primary = dev->bus->number;
459 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
463 pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
466 /* parse ranges property, or cook one up by hand for Simba */
467 /* PCI #address-cells == 3 and #size-cells == 2 always */
468 res = &dev->resource[PCI_BRIDGE_RESOURCES];
469 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
471 bus->resource[i] = res;
475 apb_fake_ranges(dev, bus, pbm);
477 } else if (ranges == NULL) {
478 pci_read_bridge_bases(bus);
482 for (; len >= 32; len -= 32, ranges += 8) {
486 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
488 ranges[0], ranges[1], ranges[2], ranges[3],
489 ranges[4], ranges[5], ranges[6], ranges[7]);
491 flags = pci_parse_of_flags(ranges[0]);
492 size = GET_64BIT(ranges, 6);
493 if (flags == 0 || size == 0)
496 /* On PCI-Express systems, PCI bridges that have no devices downstream
497 * have a bogus size value where the first 32-bit cell is 0xffffffff.
498 * This results in a bogus range where start + size overflows.
500 * Just skip these otherwise the kernel will complain when the resource
501 * tries to be claimed.
503 if (size >> 32 == 0xffffffff)
506 if (flags & IORESOURCE_IO) {
507 res = bus->resource[0];
509 pci_err(dev, "ignoring extra I/O range"
510 " for bridge %pOF\n", node);
514 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
515 pci_err(dev, "too many memory ranges"
516 " for bridge %pOF\n", node);
519 res = bus->resource[i];
524 region.start = start = GET_64BIT(ranges, 1);
525 region.end = region.start + size - 1;
528 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
531 pcibios_bus_to_resource(dev->bus, res, ®ion);
534 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
537 pci_info(dev, " bus name: %s\n", bus->name);
539 pci_of_scan_bus(pbm, node, bus);
542 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
543 struct device_node *node,
546 struct device_node *child;
548 int reglen, devfn, prev_devfn;
552 pci_info(bus, "scan_bus[%pOF] bus no %d\n",
556 for_each_child_of_node(node, child) {
558 pci_info(bus, " * %pOF\n", child);
559 reg = of_get_property(child, "reg", ®len);
560 if (reg == NULL || reglen < 20)
563 devfn = (reg[0] >> 8) & 0xff;
565 /* This is a workaround for some device trees
566 * which list PCI devices twice. On the V100
567 * for example, device number 3 is listed twice.
568 * Once as "pm" and once again as "lomp".
570 if (devfn == prev_devfn)
574 /* create a new pci_dev for this device */
575 dev = of_create_pci_dev(pbm, child, bus, devfn);
579 pci_info(dev, "dev header type: %x\n", dev->hdr_type);
581 if (pci_is_bridge(dev))
582 of_scan_pci_bridge(pbm, child, dev);
587 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
589 struct pci_dev *pdev;
590 struct device_node *dp;
592 pdev = to_pci_dev(dev);
593 dp = pdev->dev.of_node;
595 return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
598 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
600 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
603 struct pci_bus *child_bus;
606 list_for_each_entry(dev, &bus->devices, bus_list) {
607 /* we don't really care if we can create this file or
608 * not, but we need to assign the result of the call
609 * or the world will fall under alien invasion and
610 * everybody will be frozen on a spaceship ready to be
611 * eaten on alpha centauri by some green and jelly
614 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
617 list_for_each_entry(child_bus, &bus->children, node)
618 pci_bus_register_of_sysfs(child_bus);
621 static void pci_claim_legacy_resources(struct pci_dev *dev)
623 struct pci_bus_region region;
624 struct resource *p, *root, *conflict;
626 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
629 p = kzalloc(sizeof(*p), GFP_KERNEL);
633 p->name = "Video RAM area";
634 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
636 region.start = 0xa0000UL;
637 region.end = region.start + 0x1ffffUL;
638 pcibios_bus_to_resource(dev->bus, p, ®ion);
640 root = pci_find_parent_resource(dev, p);
642 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
646 conflict = request_resource_conflict(root, p);
648 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
649 p, conflict->name, conflict);
653 pci_info(dev, "VGA legacy framebuffer %pR\n", p);
660 static void pci_claim_bus_resources(struct pci_bus *bus)
662 struct pci_bus *child_bus;
665 list_for_each_entry(dev, &bus->devices, bus_list) {
669 pci_dev_for_each_resource(dev, r, i) {
670 if (r->parent || !r->start || !r->flags)
674 pci_info(dev, "Claiming Resource %d: %pR\n",
677 pci_claim_resource(dev, i);
680 pci_claim_legacy_resources(dev);
683 list_for_each_entry(child_bus, &bus->children, node)
684 pci_claim_bus_resources(child_bus);
687 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
688 struct device *parent)
690 LIST_HEAD(resources);
691 struct device_node *node = pbm->op->dev.of_node;
694 printk("PCI: Scanning PBM %pOF\n", node);
696 pci_add_resource_offset(&resources, &pbm->io_space,
698 pci_add_resource_offset(&resources, &pbm->mem_space,
700 if (pbm->mem64_space.flags)
701 pci_add_resource_offset(&resources, &pbm->mem64_space,
703 pbm->busn.start = pbm->pci_first_busno;
704 pbm->busn.end = pbm->pci_last_busno;
705 pbm->busn.flags = IORESOURCE_BUS;
706 pci_add_resource(&resources, &pbm->busn);
707 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
710 printk(KERN_ERR "Failed to create bus for %pOF\n", node);
711 pci_free_resource_list(&resources);
715 pci_of_scan_bus(pbm, node, bus);
716 pci_bus_register_of_sysfs(bus);
718 pci_claim_bus_resources(bus);
720 pci_bus_add_devices(bus);
724 int pcibios_enable_device(struct pci_dev *dev, int mask)
726 struct resource *res;
730 pci_read_config_word(dev, PCI_COMMAND, &cmd);
733 pci_dev_for_each_resource(dev, res, i) {
734 /* Only set up the requested stuff */
735 if (!(mask & (1<<i)))
738 if (res->flags & IORESOURCE_IO)
739 cmd |= PCI_COMMAND_IO;
740 if (res->flags & IORESOURCE_MEM)
741 cmd |= PCI_COMMAND_MEMORY;
745 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
746 pci_write_config_word(dev, PCI_COMMAND, cmd);
751 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
752 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
754 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
755 resource_size_t ioaddr = pci_resource_start(pdev, bar);
760 vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT;
766 int pcibus_to_node(struct pci_bus *pbus)
768 struct pci_pbm_info *pbm = pbus->sysdata;
770 return pbm->numa_node;
772 EXPORT_SYMBOL(pcibus_to_node);
775 /* Return the domain number for this pci bus */
777 int pci_domain_nr(struct pci_bus *pbus)
779 struct pci_pbm_info *pbm = pbus->sysdata;
790 EXPORT_SYMBOL(pci_domain_nr);
792 #ifdef CONFIG_PCI_MSI
793 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
795 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
798 if (!pbm->setup_msi_irq)
801 return pbm->setup_msi_irq(&irq, pdev, desc);
804 void arch_teardown_msi_irq(unsigned int irq)
806 struct msi_desc *entry = irq_get_msi_desc(irq);
807 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
808 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
810 if (pbm->teardown_msi_irq)
811 pbm->teardown_msi_irq(irq, pdev);
813 #endif /* !(CONFIG_PCI_MSI) */
815 /* ALI sound chips generate 31-bits of DMA, a special register
816 * determines what bit 31 is emitted as.
818 int ali_sound_dma_hack(struct device *dev, u64 device_mask)
820 struct iommu *iommu = dev->archdata.iommu;
821 struct pci_dev *ali_isa_bridge;
824 if (!dev_is_pci(dev))
827 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
828 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
829 device_mask != 0x7fffffff)
832 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
833 PCI_DEVICE_ID_AL_M1533,
836 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
837 if (iommu->dma_addr_mask & 0x80000000)
841 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
842 pci_dev_put(ali_isa_bridge);
846 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
847 const struct resource *rp, resource_size_t *start,
848 resource_size_t *end)
850 struct pci_bus_region region;
853 * "User" addresses are shown in /sys/devices/pci.../.../resource
854 * and /proc/bus/pci/devices and used as mmap offsets for
855 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
857 * On sparc, these are PCI bus addresses, i.e., raw BAR values.
859 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
860 *start = region.start;
864 void pcibios_set_master(struct pci_dev *dev)
866 /* No special bus mastering setup handling */
869 #ifdef CONFIG_PCI_IOV
870 int pcibios_device_add(struct pci_dev *dev)
872 struct pci_dev *pdev;
874 /* Add sriov arch specific initialization here.
875 * Copy dev_archdata from PF to VF
877 if (dev->is_virtfn) {
878 struct dev_archdata *psd;
881 psd = &pdev->dev.archdata;
882 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
883 psd->stc, psd->host_controller, NULL,
888 #endif /* CONFIG_PCI_IOV */
890 static int __init pcibios_init(void)
892 pci_dfl_cache_line_size = 64 >> 2;
895 subsys_initcall(pcibios_init);
899 #define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
901 static void pcie_bus_slot_names(struct pci_bus *pbus)
903 struct pci_dev *pdev;
906 list_for_each_entry(pdev, &pbus->devices, bus_list) {
907 char name[SLOT_NAME_SIZE];
908 struct pci_slot *pci_slot;
912 slot_num = of_get_property(pdev->dev.of_node,
913 "physical-slot#", &len);
915 if (slot_num == NULL || len != 4)
918 snprintf(name, sizeof(name), "%u", slot_num[0]);
919 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
921 if (IS_ERR(pci_slot))
922 pr_err("PCI: pci_create_slot returned %ld.\n",
926 list_for_each_entry(bus, &pbus->children, node)
927 pcie_bus_slot_names(bus);
930 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
932 const struct pci_slot_names {
940 prop = of_get_property(node, "slot-names", &len);
944 mask = prop->slot_mask;
948 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
953 struct pci_slot *pci_slot;
954 u32 this_bit = 1 << i;
956 if (!(mask & this_bit)) {
962 pci_info(bus, "Making slot [%s]\n", sp);
964 pci_slot = pci_create_slot(bus, i, sp, NULL);
965 if (IS_ERR(pci_slot))
966 pci_err(bus, "pci_create_slot returned %ld\n",
969 sp += strlen(sp) + 1;
975 static int __init of_pci_slot_init(void)
977 struct pci_bus *pbus = NULL;
979 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
980 struct device_node *node;
981 struct pci_dev *pdev;
983 pdev = list_first_entry(&pbus->devices, struct pci_dev,
986 if (pdev && pci_is_pcie(pdev)) {
987 pcie_bus_slot_names(pbus);
992 /* PCI->PCI bridge */
993 node = pbus->self->dev.of_node;
996 struct pci_pbm_info *pbm = pbus->sysdata;
998 /* Host PCI controller */
999 node = pbm->op->dev.of_node;
1002 pci_bus_slot_names(node, pbus);
1008 device_initcall(of_pci_slot_init);