drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30
  31 #include "soc15ip.h"
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #define GFX9_NUM_GFX_RINGS     1
  42 #define GFX9_MEC_HPD_SIZE 2048
  43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  44 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  45 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
  46
  47 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  48 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  49 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  52 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  53
  54 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  55 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  59 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  60
  61 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  62 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  63 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  64 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  65 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  66 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  67
  68 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  69 {
  70         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
  71           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
  72           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
  73           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
  74         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
  75           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
  76           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
  77           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
  78         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
  79           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
  80           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
  81           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
  82         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
  83           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
  84           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
  85           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
  86         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
  87           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
  88           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
  89           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
  90         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
  91           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
  92           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
  93           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
  94         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
  95           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
  96           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
  97           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
  98         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
  99           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
 100           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
 101           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
 102         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
 103           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
 104           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
 105           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
 106         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
 107           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
 108           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
 109           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
 110         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
 111           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
 112           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
 113           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
 114         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
 115           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
 116           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
 117           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
 118         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
 119           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
 120           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
 121           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
 122         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
 123           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
 124           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
 125           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
 126         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
 127           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
 128           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
 129           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
 130         { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
 131           SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
 132           SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
 133           SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
 134 };
 135
 136 static const u32 golden_settings_gc_9_0[] =
 137 {
 138         SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
 139         SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
 140         SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
 141         SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
 142         SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
 143         SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
 144         SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
 145         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
 146         SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
 147         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
 148         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
 149         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
 150         SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
 151         SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
 152         SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
 153         SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
 154         SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
 155         SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
 156         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
 157         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
 158         SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
 159         SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
 160         SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
 161 };
 162
 163 static const u32 golden_settings_gc_9_0_vg10[] =
 164 {
 165         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
 166         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
 167         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
 168         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
 169         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
 170         SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
 171         SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
 172 };
 173
 174 static const u32 golden_settings_gc_9_1[] =
 175 {
 176         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
 177         SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
 178         SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
 179         SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
 180         SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
 181         SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
 182         SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
 183         SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
 184         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
 185         SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
 186         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
 187         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
 188         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
 189         SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
 190         SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
 191         SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
 192         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
 193         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
 194         SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
 195         SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
 196         SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
 197 };
 198
 199 static const u32 golden_settings_gc_9_1_rv1[] =
 200 {
 201         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
 202         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
 203         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
 204         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
 205         SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
 206         SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
 207         SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
 208 };
 209
 210 static const u32 golden_settings_gc_9_x_common[] =
 211 {
 212         SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
 213         SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
 214 };
 215
 216 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 217 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 218
 219 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 220 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 221 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 222 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 223 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 224                                  struct amdgpu_cu_info *cu_info);
 225 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 226 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 227 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 228
 229 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 230 {
 231         switch (adev->asic_type) {
 232         case CHIP_VEGA10:
 233                 amdgpu_program_register_sequence(adev,
 234                                                  golden_settings_gc_9_0,
 235                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 236                 amdgpu_program_register_sequence(adev,
 237                                                  golden_settings_gc_9_0_vg10,
 238                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 239                 break;
 240         case CHIP_RAVEN:
 241                 amdgpu_program_register_sequence(adev,
 242                                                  golden_settings_gc_9_1,
 243                                                  ARRAY_SIZE(golden_settings_gc_9_1));
 244                 amdgpu_program_register_sequence(adev,
 245                                                  golden_settings_gc_9_1_rv1,
 246                                                  ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 247                 break;
 248         default:
 249                 break;
 250         }
 251
 252         amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
 253                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 254 }
 255
 256 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 257 {
 258         adev->gfx.scratch.num_reg = 8;
 259         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 260         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 261 }
 262
 263 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 264                                        bool wc, uint32_t reg, uint32_t val)
 265 {
 266         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 267         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 268                                 WRITE_DATA_DST_SEL(0) |
 269                                 (wc ? WR_CONFIRM : 0));
 270         amdgpu_ring_write(ring, reg);
 271         amdgpu_ring_write(ring, 0);
 272         amdgpu_ring_write(ring, val);
 273 }
 274
 275 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 276                                   int mem_space, int opt, uint32_t addr0,
 277                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 278                                   uint32_t inv)
 279 {
 280         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 281         amdgpu_ring_write(ring,
 282                                  /* memory (1) or register (0) */
 283                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 284                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 285                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 286                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 287
 288         if (mem_space)
 289                 BUG_ON(addr0 & 0x3); /* Dword align */
 290         amdgpu_ring_write(ring, addr0);
 291         amdgpu_ring_write(ring, addr1);
 292         amdgpu_ring_write(ring, ref);
 293         amdgpu_ring_write(ring, mask);
 294         amdgpu_ring_write(ring, inv); /* poll interval */
 295 }
 296
 297 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 298 {
 299         struct amdgpu_device *adev = ring->adev;
 300         uint32_t scratch;
 301         uint32_t tmp = 0;
 302         unsigned i;
 303         int r;
 304
 305         r = amdgpu_gfx_scratch_get(adev, &scratch);
 306         if (r) {
 307                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 308                 return r;
 309         }
 310         WREG32(scratch, 0xCAFEDEAD);
 311         r = amdgpu_ring_alloc(ring, 3);
 312         if (r) {
 313                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 314                           ring->idx, r);
 315                 amdgpu_gfx_scratch_free(adev, scratch);
 316                 return r;
 317         }
 318         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 319         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 320         amdgpu_ring_write(ring, 0xDEADBEEF);
 321         amdgpu_ring_commit(ring);
 322
 323         for (i = 0; i < adev->usec_timeout; i++) {
 324                 tmp = RREG32(scratch);
 325                 if (tmp == 0xDEADBEEF)
 326                         break;
 327                 DRM_UDELAY(1);
 328         }
 329         if (i < adev->usec_timeout) {
 330                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 331                          ring->idx, i);
 332         } else {
 333                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 334                           ring->idx, scratch, tmp);
 335                 r = -EINVAL;
 336         }
 337         amdgpu_gfx_scratch_free(adev, scratch);
 338         return r;
 339 }
 340
 341 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 342 {
 343         struct amdgpu_device *adev = ring->adev;
 344         struct amdgpu_ib ib;
 345         struct dma_fence *f = NULL;
 346         uint32_t scratch;
 347         uint32_t tmp = 0;
 348         long r;
 349
 350         r = amdgpu_gfx_scratch_get(adev, &scratch);
 351         if (r) {
 352                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
 353                 return r;
 354         }
 355         WREG32(scratch, 0xCAFEDEAD);
 356         memset(&ib, 0, sizeof(ib));
 357         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 358         if (r) {
 359                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 360                 goto err1;
 361         }
 362         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 363         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 364         ib.ptr[2] = 0xDEADBEEF;
 365         ib.length_dw = 3;
 366
 367         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 368         if (r)
 369                 goto err2;
 370
 371         r = dma_fence_wait_timeout(f, false, timeout);
 372         if (r == 0) {
 373                 DRM_ERROR("amdgpu: IB test timed out.\n");
 374                 r = -ETIMEDOUT;
 375                 goto err2;
 376         } else if (r < 0) {
 377                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 378                 goto err2;
 379         }
 380         tmp = RREG32(scratch);
 381         if (tmp == 0xDEADBEEF) {
 382                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 383                 r = 0;
 384         } else {
 385                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 386                           scratch, tmp);
 387                 r = -EINVAL;
 388         }
 389 err2:
 390         amdgpu_ib_free(adev, &ib, NULL);
 391         dma_fence_put(f);
 392 err1:
 393         amdgpu_gfx_scratch_free(adev, scratch);
 394         return r;
 395 }
 396
 397
 398 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 399 {
 400         release_firmware(adev->gfx.pfp_fw);
 401         adev->gfx.pfp_fw = NULL;
 402         release_firmware(adev->gfx.me_fw);
 403         adev->gfx.me_fw = NULL;
 404         release_firmware(adev->gfx.ce_fw);
 405         adev->gfx.ce_fw = NULL;
 406         release_firmware(adev->gfx.rlc_fw);
 407         adev->gfx.rlc_fw = NULL;
 408         release_firmware(adev->gfx.mec_fw);
 409         adev->gfx.mec_fw = NULL;
 410         release_firmware(adev->gfx.mec2_fw);
 411         adev->gfx.mec2_fw = NULL;
 412
 413         kfree(adev->gfx.rlc.register_list_format);
 414 }
 415
 416 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 417 {
 418         const char *chip_name;
 419         char fw_name[30];
 420         int err;
 421         struct amdgpu_firmware_info *info = NULL;
 422         const struct common_firmware_header *header = NULL;
 423         const struct gfx_firmware_header_v1_0 *cp_hdr;
 424         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 425         unsigned int *tmp = NULL;
 426         unsigned int i = 0;
 427
 428         DRM_DEBUG("\n");
 429
 430         switch (adev->asic_type) {
 431         case CHIP_VEGA10:
 432                 chip_name = "vega10";
 433                 break;
 434         case CHIP_RAVEN:
 435                 chip_name = "raven";
 436                 break;
 437         default:
 438                 BUG();
 439         }
 440
 441         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 442         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 443         if (err)
 444                 goto out;
 445         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 446         if (err)
 447                 goto out;
 448         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 449         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 450         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 451
 452         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 453         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 454         if (err)
 455                 goto out;
 456         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 457         if (err)
 458                 goto out;
 459         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 460         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 461         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 462
 463         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 464         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 465         if (err)
 466                 goto out;
 467         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 468         if (err)
 469                 goto out;
 470         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 471         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 472         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 473
 474         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 475         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 476         if (err)
 477                 goto out;
 478         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 479         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 480         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 481         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 482         adev->gfx.rlc.save_and_restore_offset =
 483                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 484         adev->gfx.rlc.clear_state_descriptor_offset =
 485                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 486         adev->gfx.rlc.avail_scratch_ram_locations =
 487                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 488         adev->gfx.rlc.reg_restore_list_size =
 489                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 490         adev->gfx.rlc.reg_list_format_start =
 491                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 492         adev->gfx.rlc.reg_list_format_separate_start =
 493                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 494         adev->gfx.rlc.starting_offsets_start =
 495                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 496         adev->gfx.rlc.reg_list_format_size_bytes =
 497                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 498         adev->gfx.rlc.reg_list_size_bytes =
 499                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 500         adev->gfx.rlc.register_list_format =
 501                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 502                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 503         if (!adev->gfx.rlc.register_list_format) {
 504                 err = -ENOMEM;
 505                 goto out;
 506         }
 507
 508         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 509                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 510         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 511                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 512
 513         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 514
 515         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 516                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 517         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 518                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 519
 520         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 521         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 522         if (err)
 523                 goto out;
 524         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 525         if (err)
 526                 goto out;
 527         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 528         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 529         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 530
 531
 532         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 533         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 534         if (!err) {
 535                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 536                 if (err)
 537                         goto out;
 538                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 539                 adev->gfx.mec2_fw->data;
 540                 adev->gfx.mec2_fw_version =
 541                 le32_to_cpu(cp_hdr->header.ucode_version);
 542                 adev->gfx.mec2_feature_version =
 543                 le32_to_cpu(cp_hdr->ucode_feature_version);
 544         } else {
 545                 err = 0;
 546                 adev->gfx.mec2_fw = NULL;
 547         }
 548
 549         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 550                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 551                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 552                 info->fw = adev->gfx.pfp_fw;
 553                 header = (const struct common_firmware_header *)info->fw->data;
 554                 adev->firmware.fw_size +=
 555                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 556
 557                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 558                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 559                 info->fw = adev->gfx.me_fw;
 560                 header = (const struct common_firmware_header *)info->fw->data;
 561                 adev->firmware.fw_size +=
 562                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 563
 564                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 565                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 566                 info->fw = adev->gfx.ce_fw;
 567                 header = (const struct common_firmware_header *)info->fw->data;
 568                 adev->firmware.fw_size +=
 569                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 570
 571                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 572                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 573                 info->fw = adev->gfx.rlc_fw;
 574                 header = (const struct common_firmware_header *)info->fw->data;
 575                 adev->firmware.fw_size +=
 576                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 577
 578                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 579                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 580                 info->fw = adev->gfx.mec_fw;
 581                 header = (const struct common_firmware_header *)info->fw->data;
 582                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 583                 adev->firmware.fw_size +=
 584                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 585
 586                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 587                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 588                 info->fw = adev->gfx.mec_fw;
 589                 adev->firmware.fw_size +=
 590                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 591
 592                 if (adev->gfx.mec2_fw) {
 593                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 594                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 595                         info->fw = adev->gfx.mec2_fw;
 596                         header = (const struct common_firmware_header *)info->fw->data;
 597                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 598                         adev->firmware.fw_size +=
 599                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 600                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 601                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 602                         info->fw = adev->gfx.mec2_fw;
 603                         adev->firmware.fw_size +=
 604                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 605                 }
 606
 607         }
 608
 609 out:
 610         if (err) {
 611                 dev_err(adev->dev,
 612                         "gfx9: Failed to load firmware \"%s\"\n",
 613                         fw_name);
 614                 release_firmware(adev->gfx.pfp_fw);
 615                 adev->gfx.pfp_fw = NULL;
 616                 release_firmware(adev->gfx.me_fw);
 617                 adev->gfx.me_fw = NULL;
 618                 release_firmware(adev->gfx.ce_fw);
 619                 adev->gfx.ce_fw = NULL;
 620                 release_firmware(adev->gfx.rlc_fw);
 621                 adev->gfx.rlc_fw = NULL;
 622                 release_firmware(adev->gfx.mec_fw);
 623                 adev->gfx.mec_fw = NULL;
 624                 release_firmware(adev->gfx.mec2_fw);
 625                 adev->gfx.mec2_fw = NULL;
 626         }
 627         return err;
 628 }
 629
 630 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 631 {
 632         u32 count = 0;
 633         const struct cs_section_def *sect = NULL;
 634         const struct cs_extent_def *ext = NULL;
 635
 636         /* begin clear state */
 637         count += 2;
 638         /* context control state */
 639         count += 3;
 640
 641         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 642                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 643                         if (sect->id == SECT_CONTEXT)
 644                                 count += 2 + ext->reg_count;
 645                         else
 646                                 return 0;
 647                 }
 648         }
 649
 650         /* end clear state */
 651         count += 2;
 652         /* clear state */
 653         count += 2;
 654
 655         return count;
 656 }
 657
 658 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 659                                     volatile u32 *buffer)
 660 {
 661         u32 count = 0, i;
 662         const struct cs_section_def *sect = NULL;
 663         const struct cs_extent_def *ext = NULL;
 664
 665         if (adev->gfx.rlc.cs_data == NULL)
 666                 return;
 667         if (buffer == NULL)
 668                 return;
 669
 670         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 671         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 672
 673         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 674         buffer[count++] = cpu_to_le32(0x80000000);
 675         buffer[count++] = cpu_to_le32(0x80000000);
 676
 677         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 678                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 679                         if (sect->id == SECT_CONTEXT) {
 680                                 buffer[count++] =
 681                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 682                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 683                                                 PACKET3_SET_CONTEXT_REG_START);
 684                                 for (i = 0; i < ext->reg_count; i++)
 685                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 686                         } else {
 687                                 return;
 688                         }
 689                 }
 690         }
 691
 692         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 693         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 694
 695         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 696         buffer[count++] = cpu_to_le32(0);
 697 }
 698
 699 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 700 {
 701         uint32_t data;
 702
 703         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 704         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 705         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 706         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 707         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 708
 709         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 710         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 711
 712         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 713         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 714
 715         mutex_lock(&adev->grbm_idx_mutex);
 716         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 717         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 718         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 719
 720         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 721         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 722         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 723         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 724         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 725
 726         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 727         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 728         data &= 0x0000FFFF;
 729         data |= 0x00C00000;
 730         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 731
 732         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 733         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 734
 735         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 736          * but used for RLC_LB_CNTL configuration */
 737         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 738         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
 739         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
 740         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 741         mutex_unlock(&adev->grbm_idx_mutex);
 742 }
 743
 744 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 745 {
 746         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
 747 }
 748
 749 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 750 {
 751         const __le32 *fw_data;
 752         volatile u32 *dst_ptr;
 753         int me, i, max_me = 5;
 754         u32 bo_offset = 0;
 755         u32 table_offset, table_size;
 756
 757         /* write the cp table buffer */
 758         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 759         for (me = 0; me < max_me; me++) {
 760                 if (me == 0) {
 761                         const struct gfx_firmware_header_v1_0 *hdr =
 762                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 763                         fw_data = (const __le32 *)
 764                                 (adev->gfx.ce_fw->data +
 765                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 766                         table_offset = le32_to_cpu(hdr->jt_offset);
 767                         table_size = le32_to_cpu(hdr->jt_size);
 768                 } else if (me == 1) {
 769                         const struct gfx_firmware_header_v1_0 *hdr =
 770                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 771                         fw_data = (const __le32 *)
 772                                 (adev->gfx.pfp_fw->data +
 773                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 774                         table_offset = le32_to_cpu(hdr->jt_offset);
 775                         table_size = le32_to_cpu(hdr->jt_size);
 776                 } else if (me == 2) {
 777                         const struct gfx_firmware_header_v1_0 *hdr =
 778                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 779                         fw_data = (const __le32 *)
 780                                 (adev->gfx.me_fw->data +
 781                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 782                         table_offset = le32_to_cpu(hdr->jt_offset);
 783                         table_size = le32_to_cpu(hdr->jt_size);
 784                 } else if (me == 3) {
 785                         const struct gfx_firmware_header_v1_0 *hdr =
 786                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 787                         fw_data = (const __le32 *)
 788                                 (adev->gfx.mec_fw->data +
 789                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 790                         table_offset = le32_to_cpu(hdr->jt_offset);
 791                         table_size = le32_to_cpu(hdr->jt_size);
 792                 } else  if (me == 4) {
 793                         const struct gfx_firmware_header_v1_0 *hdr =
 794                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 795                         fw_data = (const __le32 *)
 796                                 (adev->gfx.mec2_fw->data +
 797                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 798                         table_offset = le32_to_cpu(hdr->jt_offset);
 799                         table_size = le32_to_cpu(hdr->jt_size);
 800                 }
 801
 802                 for (i = 0; i < table_size; i ++) {
 803                         dst_ptr[bo_offset + i] =
 804                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
 805                 }
 806
 807                 bo_offset += table_size;
 808         }
 809 }
 810
 811 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
 812 {
 813         /* clear state block */
 814         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 815                         &adev->gfx.rlc.clear_state_gpu_addr,
 816                         (void **)&adev->gfx.rlc.cs_ptr);
 817
 818         /* jump table block */
 819         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 820                         &adev->gfx.rlc.cp_table_gpu_addr,
 821                         (void **)&adev->gfx.rlc.cp_table_ptr);
 822 }
 823
 824 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 825 {
 826         volatile u32 *dst_ptr;
 827         u32 dws;
 828         const struct cs_section_def *cs_data;
 829         int r;
 830
 831         adev->gfx.rlc.cs_data = gfx9_cs_data;
 832
 833         cs_data = adev->gfx.rlc.cs_data;
 834
 835         if (cs_data) {
 836                 /* clear state block */
 837                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
 838                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
 839                                               AMDGPU_GEM_DOMAIN_VRAM,
 840                                               &adev->gfx.rlc.clear_state_obj,
 841                                               &adev->gfx.rlc.clear_state_gpu_addr,
 842                                               (void **)&adev->gfx.rlc.cs_ptr);
 843                 if (r) {
 844                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
 845                                 r);
 846                         gfx_v9_0_rlc_fini(adev);
 847                         return r;
 848                 }
 849                 /* set up the cs buffer */
 850                 dst_ptr = adev->gfx.rlc.cs_ptr;
 851                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 852                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
 853                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 854         }
 855
 856         if (adev->asic_type == CHIP_RAVEN) {
 857                 /* TODO: double check the cp_table_size for RV */
 858                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 859                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
 860                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 861                                               &adev->gfx.rlc.cp_table_obj,
 862                                               &adev->gfx.rlc.cp_table_gpu_addr,
 863                                               (void **)&adev->gfx.rlc.cp_table_ptr);
 864                 if (r) {
 865                         dev_err(adev->dev,
 866                                 "(%d) failed to create cp table bo\n", r);
 867                         gfx_v9_0_rlc_fini(adev);
 868                         return r;
 869                 }
 870
 871                 rv_init_cp_jump_table(adev);
 872                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
 873                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
 874
 875                 gfx_v9_0_init_lbpw(adev);
 876         }
 877
 878         return 0;
 879 }
 880
 881 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
 882 {
 883         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 884         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 885 }
 886
 887 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 888 {
 889         int r;
 890         u32 *hpd;
 891         const __le32 *fw_data;
 892         unsigned fw_size;
 893         u32 *fw;
 894         size_t mec_hpd_size;
 895
 896         const struct gfx_firmware_header_v1_0 *mec_hdr;
 897
 898         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 899
 900         /* take ownership of the relevant compute queues */
 901         amdgpu_gfx_compute_queue_acquire(adev);
 902         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
 903
 904         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 905                                       AMDGPU_GEM_DOMAIN_GTT,
 906                                       &adev->gfx.mec.hpd_eop_obj,
 907                                       &adev->gfx.mec.hpd_eop_gpu_addr,
 908                                       (void **)&hpd);
 909         if (r) {
 910                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 911                 gfx_v9_0_mec_fini(adev);
 912                 return r;
 913         }
 914
 915         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
 916
 917         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 918         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 919
 920         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 921
 922         fw_data = (const __le32 *)
 923                 (adev->gfx.mec_fw->data +
 924                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 925         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
 926
 927         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
 928                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 929                                       &adev->gfx.mec.mec_fw_obj,
 930                                       &adev->gfx.mec.mec_fw_gpu_addr,
 931                                       (void **)&fw);
 932         if (r) {
 933                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
 934                 gfx_v9_0_mec_fini(adev);
 935                 return r;
 936         }
 937
 938         memcpy(fw, fw_data, fw_size);
 939
 940         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
 941         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 942
 943         return 0;
 944 }
 945
 946 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
 947 {
 948         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
 949                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 950                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 951                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
 952                 (SQ_IND_INDEX__FORCE_READ_MASK));
 953         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
 954 }
 955
 956 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
 957                            uint32_t wave, uint32_t thread,
 958                            uint32_t regno, uint32_t num, uint32_t *out)
 959 {
 960         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
 961                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 962                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 963                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 964                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
 965                 (SQ_IND_INDEX__FORCE_READ_MASK) |
 966                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 967         while (num--)
 968                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
 969 }
 970
 971 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 972 {
 973         /* type 1 wave data */
 974         dst[(*no_fields)++] = 1;
 975         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
 976         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
 977         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
 978         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
 979         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
 980         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
 981         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
 982         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
 983         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
 984         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
 985         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
 986         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
 987         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
 988         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
 989 }
 990
 991 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
 992                                      uint32_t wave, uint32_t start,
 993                                      uint32_t size, uint32_t *dst)
 994 {
 995         wave_read_regs(
 996                 adev, simd, wave, 0,
 997                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
 998 }
 999
1000 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1001                                      uint32_t wave, uint32_t thread,
1002                                      uint32_t start, uint32_t size,
1003                                      uint32_t *dst)
1004 {
1005         wave_read_regs(
1006                 adev, simd, wave, thread,
1007                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1008 }
1009
1010 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1011         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1012         .select_se_sh = &gfx_v9_0_select_se_sh,
1013         .read_wave_data = &gfx_v9_0_read_wave_data,
1014         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1015         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1016 };
1017
1018 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1019 {
1020         u32 gb_addr_config;
1021
1022         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1023
1024         switch (adev->asic_type) {
1025         case CHIP_VEGA10:
1026                 adev->gfx.config.max_hw_contexts = 8;
1027                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1028                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1029                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1030                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1031                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1032                 break;
1033         case CHIP_RAVEN:
1034                 adev->gfx.config.max_hw_contexts = 8;
1035                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1036                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1037                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1038                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1039                 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1040                 break;
1041         default:
1042                 BUG();
1043                 break;
1044         }
1045
1046         adev->gfx.config.gb_addr_config = gb_addr_config;
1047
1048         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1049                         REG_GET_FIELD(
1050                                         adev->gfx.config.gb_addr_config,
1051                                         GB_ADDR_CONFIG,
1052                                         NUM_PIPES);
1053
1054         adev->gfx.config.max_tile_pipes =
1055                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1056
1057         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1058                         REG_GET_FIELD(
1059                                         adev->gfx.config.gb_addr_config,
1060                                         GB_ADDR_CONFIG,
1061                                         NUM_BANKS);
1062         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1063                         REG_GET_FIELD(
1064                                         adev->gfx.config.gb_addr_config,
1065                                         GB_ADDR_CONFIG,
1066                                         MAX_COMPRESSED_FRAGS);
1067         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1068                         REG_GET_FIELD(
1069                                         adev->gfx.config.gb_addr_config,
1070                                         GB_ADDR_CONFIG,
1071                                         NUM_RB_PER_SE);
1072         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1073                         REG_GET_FIELD(
1074                                         adev->gfx.config.gb_addr_config,
1075                                         GB_ADDR_CONFIG,
1076                                         NUM_SHADER_ENGINES);
1077         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1078                         REG_GET_FIELD(
1079                                         adev->gfx.config.gb_addr_config,
1080                                         GB_ADDR_CONFIG,
1081                                         PIPE_INTERLEAVE_SIZE));
1082 }
1083
1084 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1085                                    struct amdgpu_ngg_buf *ngg_buf,
1086                                    int size_se,
1087                                    int default_size_se)
1088 {
1089         int r;
1090
1091         if (size_se < 0) {
1092                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1093                 return -EINVAL;
1094         }
1095         size_se = size_se ? size_se : default_size_se;
1096
1097         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1098         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1099                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1100                                     &ngg_buf->bo,
1101                                     &ngg_buf->gpu_addr,
1102                                     NULL);
1103         if (r) {
1104                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1105                 return r;
1106         }
1107         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1108
1109         return r;
1110 }
1111
1112 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1113 {
1114         int i;
1115
1116         for (i = 0; i < NGG_BUF_MAX; i++)
1117                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1118                                       &adev->gfx.ngg.buf[i].gpu_addr,
1119                                       NULL);
1120
1121         memset(&adev->gfx.ngg.buf[0], 0,
1122                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1123
1124         adev->gfx.ngg.init = false;
1125
1126         return 0;
1127 }
1128
1129 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1130 {
1131         int r;
1132
1133         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1134                 return 0;
1135
1136         /* GDS reserve memory: 64 bytes alignment */
1137         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1138         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1139         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1140         adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1141         adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1142
1143         /* Primitive Buffer */
1144         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1145                                     amdgpu_prim_buf_per_se,
1146                                     64 * 1024);
1147         if (r) {
1148                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1149                 goto err;
1150         }
1151
1152         /* Position Buffer */
1153         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1154                                     amdgpu_pos_buf_per_se,
1155                                     256 * 1024);
1156         if (r) {
1157                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1158                 goto err;
1159         }
1160
1161         /* Control Sideband */
1162         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1163                                     amdgpu_cntl_sb_buf_per_se,
1164                                     256);
1165         if (r) {
1166                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1167                 goto err;
1168         }
1169
1170         /* Parameter Cache, not created by default */
1171         if (amdgpu_param_buf_per_se <= 0)
1172                 goto out;
1173
1174         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1175                                     amdgpu_param_buf_per_se,
1176                                     512 * 1024);
1177         if (r) {
1178                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1179                 goto err;
1180         }
1181
1182 out:
1183         adev->gfx.ngg.init = true;
1184         return 0;
1185 err:
1186         gfx_v9_0_ngg_fini(adev);
1187         return r;
1188 }
1189
1190 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1191 {
1192         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1193         int r;
1194         u32 data, base;
1195
1196         if (!amdgpu_ngg)
1197                 return 0;
1198
1199         /* Program buffer size */
1200         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1201                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1202         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1203                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1204         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1205
1206         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1207                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1208         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1209                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1210         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1211
1212         /* Program buffer base address */
1213         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1214         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1215         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1216
1217         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1218         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1219         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1220
1221         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1222         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1223         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1224
1225         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1226         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1227         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1228
1229         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1230         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1231         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1232
1233         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1234         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1235         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1236
1237         /* Clear GDS reserved memory */
1238         r = amdgpu_ring_alloc(ring, 17);
1239         if (r) {
1240                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1241                           ring->idx, r);
1242                 return r;
1243         }
1244
1245         gfx_v9_0_write_data_to_reg(ring, 0, false,
1246                                    amdgpu_gds_reg_offset[0].mem_size,
1247                                    (adev->gds.mem.total_size +
1248                                     adev->gfx.ngg.gds_reserve_size) >>
1249                                    AMDGPU_GDS_SHIFT);
1250
1251         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1252         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1253                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1254         amdgpu_ring_write(ring, 0);
1255         amdgpu_ring_write(ring, 0);
1256         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1257         amdgpu_ring_write(ring, 0);
1258         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1259
1260
1261         gfx_v9_0_write_data_to_reg(ring, 0, false,
1262                                    amdgpu_gds_reg_offset[0].mem_size, 0);
1263
1264         amdgpu_ring_commit(ring);
1265
1266         return 0;
1267 }
1268
1269 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1270                                       int mec, int pipe, int queue)
1271 {
1272         int r;
1273         unsigned irq_type;
1274         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1275
1276         ring = &adev->gfx.compute_ring[ring_id];
1277
1278         /* mec0 is me1 */
1279         ring->me = mec + 1;
1280         ring->pipe = pipe;
1281         ring->queue = queue;
1282
1283         ring->ring_obj = NULL;
1284         ring->use_doorbell = true;
1285         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1286         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1287                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1288         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1289
1290         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1291                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1292                 + ring->pipe;
1293
1294         /* type-2 packets are deprecated on MEC, use type-3 instead */
1295         r = amdgpu_ring_init(adev, ring, 1024,
1296                              &adev->gfx.eop_irq, irq_type);
1297         if (r)
1298                 return r;
1299
1300
1301         return 0;
1302 }
1303
1304 static int gfx_v9_0_sw_init(void *handle)
1305 {
1306         int i, j, k, r, ring_id;
1307         struct amdgpu_ring *ring;
1308         struct amdgpu_kiq *kiq;
1309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310
1311         switch (adev->asic_type) {
1312         case CHIP_VEGA10:
1313         case CHIP_RAVEN:
1314                 adev->gfx.mec.num_mec = 2;
1315                 break;
1316         default:
1317                 adev->gfx.mec.num_mec = 1;
1318                 break;
1319         }
1320
1321         adev->gfx.mec.num_pipe_per_mec = 4;
1322         adev->gfx.mec.num_queue_per_pipe = 8;
1323
1324         /* KIQ event */
1325         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1326         if (r)
1327                 return r;
1328
1329         /* EOP Event */
1330         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1331         if (r)
1332                 return r;
1333
1334         /* Privileged reg */
1335         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1336                               &adev->gfx.priv_reg_irq);
1337         if (r)
1338                 return r;
1339
1340         /* Privileged inst */
1341         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1342                               &adev->gfx.priv_inst_irq);
1343         if (r)
1344                 return r;
1345
1346         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1347
1348         gfx_v9_0_scratch_init(adev);
1349
1350         r = gfx_v9_0_init_microcode(adev);
1351         if (r) {
1352                 DRM_ERROR("Failed to load gfx firmware!\n");
1353                 return r;
1354         }
1355
1356         r = gfx_v9_0_rlc_init(adev);
1357         if (r) {
1358                 DRM_ERROR("Failed to init rlc BOs!\n");
1359                 return r;
1360         }
1361
1362         r = gfx_v9_0_mec_init(adev);
1363         if (r) {
1364                 DRM_ERROR("Failed to init MEC BOs!\n");
1365                 return r;
1366         }
1367
1368         /* set up the gfx ring */
1369         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1370                 ring = &adev->gfx.gfx_ring[i];
1371                 ring->ring_obj = NULL;
1372                 if (!i)
1373                         sprintf(ring->name, "gfx");
1374                 else
1375                         sprintf(ring->name, "gfx_%d", i);
1376                 ring->use_doorbell = true;
1377                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1378                 r = amdgpu_ring_init(adev, ring, 1024,
1379                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1380                 if (r)
1381                         return r;
1382         }
1383
1384         /* set up the compute queues - allocate horizontally across pipes */
1385         ring_id = 0;
1386         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1387                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1388                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1389                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1390                                         continue;
1391
1392                                 r = gfx_v9_0_compute_ring_init(adev,
1393                                                                ring_id,
1394                                                                i, k, j);
1395                                 if (r)
1396                                         return r;
1397
1398                                 ring_id++;
1399                         }
1400                 }
1401         }
1402
1403         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1404         if (r) {
1405                 DRM_ERROR("Failed to init KIQ BOs!\n");
1406                 return r;
1407         }
1408
1409         kiq = &adev->gfx.kiq;
1410         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1411         if (r)
1412                 return r;
1413
1414         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1415         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1416         if (r)
1417                 return r;
1418
1419         /* reserve GDS, GWS and OA resource for gfx */
1420         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1421                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1422                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1423         if (r)
1424                 return r;
1425
1426         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1427                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1428                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1429         if (r)
1430                 return r;
1431
1432         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1433                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1434                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1435         if (r)
1436                 return r;
1437
1438         adev->gfx.ce_ram_size = 0x8000;
1439
1440         gfx_v9_0_gpu_early_init(adev);
1441
1442         r = gfx_v9_0_ngg_init(adev);
1443         if (r)
1444                 return r;
1445
1446         return 0;
1447 }
1448
1449
1450 static int gfx_v9_0_sw_fini(void *handle)
1451 {
1452         int i;
1453         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1454
1455         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1456         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1457         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1458
1459         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1460                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1461         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1462                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1463
1464         amdgpu_gfx_compute_mqd_sw_fini(adev);
1465         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1466         amdgpu_gfx_kiq_fini(adev);
1467
1468         gfx_v9_0_mec_fini(adev);
1469         gfx_v9_0_ngg_fini(adev);
1470         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1471                                 &adev->gfx.rlc.clear_state_gpu_addr,
1472                                 (void **)&adev->gfx.rlc.cs_ptr);
1473         if (adev->asic_type == CHIP_RAVEN) {
1474                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1475                                 &adev->gfx.rlc.cp_table_gpu_addr,
1476                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1477         }
1478         gfx_v9_0_free_microcode(adev);
1479
1480         return 0;
1481 }
1482
1483
1484 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1485 {
1486         /* TODO */
1487 }
1488
1489 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1490 {
1491         u32 data;
1492
1493         if (instance == 0xffffffff)
1494                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1495         else
1496                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1497
1498         if (se_num == 0xffffffff)
1499                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1500         else
1501                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1502
1503         if (sh_num == 0xffffffff)
1504                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1505         else
1506                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1507
1508         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1509 }
1510
1511 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1512 {
1513         u32 data, mask;
1514
1515         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1516         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1517
1518         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1519         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1520
1521         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1522                                          adev->gfx.config.max_sh_per_se);
1523
1524         return (~data) & mask;
1525 }
1526
1527 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1528 {
1529         int i, j;
1530         u32 data;
1531         u32 active_rbs = 0;
1532         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1533                                         adev->gfx.config.max_sh_per_se;
1534
1535         mutex_lock(&adev->grbm_idx_mutex);
1536         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1537                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1538                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1539                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1540                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1541                                                rb_bitmap_width_per_sh);
1542                 }
1543         }
1544         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1545         mutex_unlock(&adev->grbm_idx_mutex);
1546
1547         adev->gfx.config.backend_enable_mask = active_rbs;
1548         adev->gfx.config.num_rbs = hweight32(active_rbs);
1549 }
1550
1551 #define DEFAULT_SH_MEM_BASES    (0x6000)
1552 #define FIRST_COMPUTE_VMID      (8)
1553 #define LAST_COMPUTE_VMID       (16)
1554 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1555 {
1556         int i;
1557         uint32_t sh_mem_config;
1558         uint32_t sh_mem_bases;
1559
1560         /*
1561          * Configure apertures:
1562          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1563          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1564          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1565          */
1566         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1567
1568         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1569                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1570                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1571
1572         mutex_lock(&adev->srbm_mutex);
1573         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1574                 soc15_grbm_select(adev, 0, 0, 0, i);
1575                 /* CP and shaders */
1576                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1577                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1578         }
1579         soc15_grbm_select(adev, 0, 0, 0, 0);
1580         mutex_unlock(&adev->srbm_mutex);
1581 }
1582
1583 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1584 {
1585         u32 tmp;
1586         int i;
1587
1588         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1589
1590         gfx_v9_0_tiling_mode_table_init(adev);
1591
1592         gfx_v9_0_setup_rb(adev);
1593         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1594
1595         /* XXX SH_MEM regs */
1596         /* where to put LDS, scratch, GPUVM in FSA64 space */
1597         mutex_lock(&adev->srbm_mutex);
1598         for (i = 0; i < 16; i++) {
1599                 soc15_grbm_select(adev, 0, 0, 0, i);
1600                 /* CP and shaders */
1601                 tmp = 0;
1602                 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1603                                     SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1604                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1605                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1606         }
1607         soc15_grbm_select(adev, 0, 0, 0, 0);
1608
1609         mutex_unlock(&adev->srbm_mutex);
1610
1611         gfx_v9_0_init_compute_vmid(adev);
1612
1613         mutex_lock(&adev->grbm_idx_mutex);
1614         /*
1615          * making sure that the following register writes will be broadcasted
1616          * to all the shaders
1617          */
1618         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1619
1620         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1621                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1622                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1623                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1624                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1625                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1626                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1627                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1628                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1629         mutex_unlock(&adev->grbm_idx_mutex);
1630
1631 }
1632
1633 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1634 {
1635         u32 i, j, k;
1636         u32 mask;
1637
1638         mutex_lock(&adev->grbm_idx_mutex);
1639         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1640                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1641                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1642                         for (k = 0; k < adev->usec_timeout; k++) {
1643                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1644                                         break;
1645                                 udelay(1);
1646                         }
1647                         if (k == adev->usec_timeout) {
1648                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1649                                                       0xffffffff, 0xffffffff);
1650                                 mutex_unlock(&adev->grbm_idx_mutex);
1651                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1652                                          i, j);
1653                                 return;
1654                         }
1655                 }
1656         }
1657         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1658         mutex_unlock(&adev->grbm_idx_mutex);
1659
1660         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1661                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1662                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1663                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1664         for (k = 0; k < adev->usec_timeout; k++) {
1665                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1666                         break;
1667                 udelay(1);
1668         }
1669 }
1670
1671 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1672                                                bool enable)
1673 {
1674         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1675
1676         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1677         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1678         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1679         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1680
1681         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1682 }
1683
1684 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1685 {
1686         /* csib */
1687         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1688                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1689         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1690                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1691         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1692                         adev->gfx.rlc.clear_state_size);
1693 }
1694
1695 static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1696                                 int indirect_offset,
1697                                 int list_size,
1698                                 int *unique_indirect_regs,
1699                                 int *unique_indirect_reg_count,
1700                                 int max_indirect_reg_count,
1701                                 int *indirect_start_offsets,
1702                                 int *indirect_start_offsets_count,
1703                                 int max_indirect_start_offsets_count)
1704 {
1705         int idx;
1706         bool new_entry = true;
1707
1708         for (; indirect_offset < list_size; indirect_offset++) {
1709
1710                 if (new_entry) {
1711                         new_entry = false;
1712                         indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1713                         *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1714                         BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1715                 }
1716
1717                 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1718                         new_entry = true;
1719                         continue;
1720                 }
1721
1722                 indirect_offset += 2;
1723
1724                 /* look for the matching indice */
1725                 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1726                         if (unique_indirect_regs[idx] ==
1727                                 register_list_format[indirect_offset])
1728                                 break;
1729                 }
1730
1731                 if (idx >= *unique_indirect_reg_count) {
1732                         unique_indirect_regs[*unique_indirect_reg_count] =
1733                                 register_list_format[indirect_offset];
1734                         idx = *unique_indirect_reg_count;
1735                         *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1736                         BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1737                 }
1738
1739                 register_list_format[indirect_offset] = idx;
1740         }
1741 }
1742
1743 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1744 {
1745         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1746         int unique_indirect_reg_count = 0;
1747
1748         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1749         int indirect_start_offsets_count = 0;
1750
1751         int list_size = 0;
1752         int i = 0;
1753         u32 tmp = 0;
1754
1755         u32 *register_list_format =
1756                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1757         if (!register_list_format)
1758                 return -ENOMEM;
1759         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1760                 adev->gfx.rlc.reg_list_format_size_bytes);
1761
1762         /* setup unique_indirect_regs array and indirect_start_offsets array */
1763         gfx_v9_0_parse_ind_reg_list(register_list_format,
1764                                 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1765                                 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1766                                 unique_indirect_regs,
1767                                 &unique_indirect_reg_count,
1768                                 ARRAY_SIZE(unique_indirect_regs),
1769                                 indirect_start_offsets,
1770                                 &indirect_start_offsets_count,
1771                                 ARRAY_SIZE(indirect_start_offsets));
1772
1773         /* enable auto inc in case it is disabled */
1774         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1775         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1776         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1777
1778         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1779         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1780                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1781         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1782                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1783                         adev->gfx.rlc.register_restore[i]);
1784
1785         /* load direct register */
1786         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1787         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1788                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1789                         adev->gfx.rlc.register_restore[i]);
1790
1791         /* load indirect register */
1792         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1793                 adev->gfx.rlc.reg_list_format_start);
1794         for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1795                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1796                         register_list_format[i]);
1797
1798         /* set save/restore list size */
1799         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1800         list_size = list_size >> 1;
1801         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1802                 adev->gfx.rlc.reg_restore_list_size);
1803         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1804
1805         /* write the starting offsets to RLC scratch ram */
1806         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1807                 adev->gfx.rlc.starting_offsets_start);
1808         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
1809                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1810                         indirect_start_offsets[i]);
1811
1812         /* load unique indirect regs*/
1813         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
1814                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1815                         unique_indirect_regs[i] & 0x3FFFF);
1816                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1817                         unique_indirect_regs[i] >> 20);
1818         }
1819
1820         kfree(register_list_format);
1821         return 0;
1822 }
1823
1824 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1825 {
1826         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
1827 }
1828
1829 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1830                                              bool enable)
1831 {
1832         uint32_t data = 0;
1833         uint32_t default_data = 0;
1834
1835         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1836         if (enable == true) {
1837                 /* enable GFXIP control over CGPG */
1838                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1839                 if(default_data != data)
1840                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1841
1842                 /* update status */
1843                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1844                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1845                 if(default_data != data)
1846                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1847         } else {
1848                 /* restore GFXIP control over GCPG */
1849                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1850                 if(default_data != data)
1851                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1852         }
1853 }
1854
1855 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1856 {
1857         uint32_t data = 0;
1858
1859         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1860                               AMD_PG_SUPPORT_GFX_SMG |
1861                               AMD_PG_SUPPORT_GFX_DMG)) {
1862                 /* init IDLE_POLL_COUNT = 60 */
1863                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1864                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1865                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1866                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1867
1868                 /* init RLC PG Delay */
1869                 data = 0;
1870                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1871                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1872                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1873                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1874                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1875
1876                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1877                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1878                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1879                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1880
1881                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1882                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1883                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1884                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1885
1886                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1887                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1888
1889                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1890                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1891                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1892
1893                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1894         }
1895 }
1896
1897 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1898                                                 bool enable)
1899 {
1900         uint32_t data = 0;
1901         uint32_t default_data = 0;
1902
1903         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1904         data = REG_SET_FIELD(data, RLC_PG_CNTL,
1905                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
1906                              enable ? 1 : 0);
1907         if (default_data != data)
1908                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1909 }
1910
1911 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1912                                                 bool enable)
1913 {
1914         uint32_t data = 0;
1915         uint32_t default_data = 0;
1916
1917         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1918         data = REG_SET_FIELD(data, RLC_PG_CNTL,
1919                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
1920                              enable ? 1 : 0);
1921         if(default_data != data)
1922                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1923 }
1924
1925 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1926                                         bool enable)
1927 {
1928         uint32_t data = 0;
1929         uint32_t default_data = 0;
1930
1931         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1932         data = REG_SET_FIELD(data, RLC_PG_CNTL,
1933                              CP_PG_DISABLE,
1934                              enable ? 0 : 1);
1935         if(default_data != data)
1936                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1937 }
1938
1939 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1940                                                 bool enable)
1941 {
1942         uint32_t data, default_data;
1943
1944         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1945         data = REG_SET_FIELD(data, RLC_PG_CNTL,
1946                              GFX_POWER_GATING_ENABLE,
1947                              enable ? 1 : 0);
1948         if(default_data != data)
1949                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1950 }
1951
1952 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1953                                                 bool enable)
1954 {
1955         uint32_t data, default_data;
1956
1957         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1958         data = REG_SET_FIELD(data, RLC_PG_CNTL,
1959                              GFX_PIPELINE_PG_ENABLE,
1960                              enable ? 1 : 0);
1961         if(default_data != data)
1962                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1963
1964         if (!enable)
1965                 /* read any GFX register to wake up GFX */
1966                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1967 }
1968
1969 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1970                                                        bool enable)
1971 {
1972         uint32_t data, default_data;
1973
1974         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1975         data = REG_SET_FIELD(data, RLC_PG_CNTL,
1976                              STATIC_PER_CU_PG_ENABLE,
1977                              enable ? 1 : 0);
1978         if(default_data != data)
1979                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1980 }
1981
1982 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
1983                                                 bool enable)
1984 {
1985         uint32_t data, default_data;
1986
1987         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1988         data = REG_SET_FIELD(data, RLC_PG_CNTL,
1989                              DYN_PER_CU_PG_ENABLE,
1990                              enable ? 1 : 0);
1991         if(default_data != data)
1992                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1993 }
1994
1995 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1996 {
1997         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1998                               AMD_PG_SUPPORT_GFX_SMG |
1999                               AMD_PG_SUPPORT_GFX_DMG |
2000                               AMD_PG_SUPPORT_CP |
2001                               AMD_PG_SUPPORT_GDS |
2002                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2003                 gfx_v9_0_init_csb(adev);
2004                 gfx_v9_0_init_rlc_save_restore_list(adev);
2005                 gfx_v9_0_enable_save_restore_machine(adev);
2006
2007                 if (adev->asic_type == CHIP_RAVEN) {
2008                         WREG32(mmRLC_JUMP_TABLE_RESTORE,
2009                                 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2010                         gfx_v9_0_init_gfx_power_gating(adev);
2011
2012                         if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2013                                 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2014                                 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2015                         } else {
2016                                 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2017                                 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2018                         }
2019
2020                         if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2021                                 gfx_v9_0_enable_cp_power_gating(adev, true);
2022                         else
2023                                 gfx_v9_0_enable_cp_power_gating(adev, false);
2024                 }
2025         }
2026 }
2027
2028 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2029 {
2030         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2031         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2032         gfx_v9_0_wait_for_rlc_serdes(adev);
2033 }
2034
2035 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2036 {
2037         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2038         udelay(50);
2039         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2040         udelay(50);
2041 }
2042
2043 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2044 {
2045 #ifdef AMDGPU_RLC_DEBUG_RETRY
2046         u32 rlc_ucode_ver;
2047 #endif
2048
2049         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2050
2051         /* carrizo do enable cp interrupt after cp inited */
2052         if (!(adev->flags & AMD_IS_APU))
2053                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2054
2055         udelay(50);
2056
2057 #ifdef AMDGPU_RLC_DEBUG_RETRY
2058         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2059         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2060         if(rlc_ucode_ver == 0x108) {
2061                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2062                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2063                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2064                  * default is 0x9C4 to create a 100us interval */
2065                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2066                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2067                  * to disable the page fault retry interrupts, default is
2068                  * 0x100 (256) */
2069                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2070         }
2071 #endif
2072 }
2073
2074 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2075 {
2076         const struct rlc_firmware_header_v2_0 *hdr;
2077         const __le32 *fw_data;
2078         unsigned i, fw_size;
2079
2080         if (!adev->gfx.rlc_fw)
2081                 return -EINVAL;
2082
2083         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2084         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2085
2086         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2087                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2088         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2089
2090         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2091                         RLCG_UCODE_LOADING_START_ADDRESS);
2092         for (i = 0; i < fw_size; i++)
2093                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2094         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2095
2096         return 0;
2097 }
2098
2099 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2100 {
2101         int r;
2102
2103         if (amdgpu_sriov_vf(adev)) {
2104                 gfx_v9_0_init_csb(adev);
2105                 return 0;
2106         }
2107
2108         gfx_v9_0_rlc_stop(adev);
2109
2110         /* disable CG */
2111         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2112
2113         /* disable PG */
2114         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2115
2116         gfx_v9_0_rlc_reset(adev);
2117
2118         gfx_v9_0_init_pg(adev);
2119
2120         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2121                 /* legacy rlc firmware loading */
2122                 r = gfx_v9_0_rlc_load_microcode(adev);
2123                 if (r)
2124                         return r;
2125         }
2126
2127         if (adev->asic_type == CHIP_RAVEN) {
2128                 if (amdgpu_lbpw != 0)
2129                         gfx_v9_0_enable_lbpw(adev, true);
2130                 else
2131                         gfx_v9_0_enable_lbpw(adev, false);
2132         }
2133
2134         gfx_v9_0_rlc_start(adev);
2135
2136         return 0;
2137 }
2138
2139 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2140 {
2141         int i;
2142         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2143
2144         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2145         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2146         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2147         if (!enable) {
2148                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2149                         adev->gfx.gfx_ring[i].ready = false;
2150         }
2151         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2152         udelay(50);
2153 }
2154
2155 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2156 {
2157         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2158         const struct gfx_firmware_header_v1_0 *ce_hdr;
2159         const struct gfx_firmware_header_v1_0 *me_hdr;
2160         const __le32 *fw_data;
2161         unsigned i, fw_size;
2162
2163         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2164                 return -EINVAL;
2165
2166         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2167                 adev->gfx.pfp_fw->data;
2168         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2169                 adev->gfx.ce_fw->data;
2170         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2171                 adev->gfx.me_fw->data;
2172
2173         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2174         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2175         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2176
2177         gfx_v9_0_cp_gfx_enable(adev, false);
2178
2179         /* PFP */
2180         fw_data = (const __le32 *)
2181                 (adev->gfx.pfp_fw->data +
2182                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2183         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2184         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2185         for (i = 0; i < fw_size; i++)
2186                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2187         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2188
2189         /* CE */
2190         fw_data = (const __le32 *)
2191                 (adev->gfx.ce_fw->data +
2192                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2193         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2194         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2195         for (i = 0; i < fw_size; i++)
2196                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2197         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2198
2199         /* ME */
2200         fw_data = (const __le32 *)
2201                 (adev->gfx.me_fw->data +
2202                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2203         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2204         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2205         for (i = 0; i < fw_size; i++)
2206                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2207         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2208
2209         return 0;
2210 }
2211
2212 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2213 {
2214         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2215         const struct cs_section_def *sect = NULL;
2216         const struct cs_extent_def *ext = NULL;
2217         int r, i, tmp;
2218
2219         /* init the CP */
2220         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2221         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2222
2223         gfx_v9_0_cp_gfx_enable(adev, true);
2224
2225         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2226         if (r) {
2227                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2228                 return r;
2229         }
2230
2231         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2232         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2233
2234         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2235         amdgpu_ring_write(ring, 0x80000000);
2236         amdgpu_ring_write(ring, 0x80000000);
2237
2238         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2239                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2240                         if (sect->id == SECT_CONTEXT) {
2241                                 amdgpu_ring_write(ring,
2242                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2243                                                ext->reg_count));
2244                                 amdgpu_ring_write(ring,
2245                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2246                                 for (i = 0; i < ext->reg_count; i++)
2247                                         amdgpu_ring_write(ring, ext->extent[i]);
2248                         }
2249                 }
2250         }
2251
2252         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2253         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2254
2255         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2256         amdgpu_ring_write(ring, 0);
2257
2258         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2259         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2260         amdgpu_ring_write(ring, 0x8000);
2261         amdgpu_ring_write(ring, 0x8000);
2262
2263         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2264         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2265                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2266         amdgpu_ring_write(ring, tmp);
2267         amdgpu_ring_write(ring, 0);
2268
2269         amdgpu_ring_commit(ring);
2270
2271         return 0;
2272 }
2273
2274 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2275 {
2276         struct amdgpu_ring *ring;
2277         u32 tmp;
2278         u32 rb_bufsz;
2279         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2280
2281         /* Set the write pointer delay */
2282         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2283
2284         /* set the RB to use vmid 0 */
2285         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2286
2287         /* Set ring buffer size */
2288         ring = &adev->gfx.gfx_ring[0];
2289         rb_bufsz = order_base_2(ring->ring_size / 8);
2290         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2291         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2292 #ifdef __BIG_ENDIAN
2293         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2294 #endif
2295         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2296
2297         /* Initialize the ring buffer's write pointers */
2298         ring->wptr = 0;
2299         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2300         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2301
2302         /* set the wb address wether it's enabled or not */
2303         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2304         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2305         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2306
2307         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2308         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2309         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2310
2311         mdelay(1);
2312         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2313
2314         rb_addr = ring->gpu_addr >> 8;
2315         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2316         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2317
2318         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2319         if (ring->use_doorbell) {
2320                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2321                                     DOORBELL_OFFSET, ring->doorbell_index);
2322                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2323                                     DOORBELL_EN, 1);
2324         } else {
2325                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2326         }
2327         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2328
2329         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2330                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2331         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2332
2333         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2334                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2335
2336
2337         /* start the ring */
2338         gfx_v9_0_cp_gfx_start(adev);
2339         ring->ready = true;
2340
2341         return 0;
2342 }
2343
2344 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2345 {
2346         int i;
2347
2348         if (enable) {
2349                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2350         } else {
2351                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2352                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2353                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2354                         adev->gfx.compute_ring[i].ready = false;
2355                 adev->gfx.kiq.ring.ready = false;
2356         }
2357         udelay(50);
2358 }
2359
2360 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2361 {
2362         const struct gfx_firmware_header_v1_0 *mec_hdr;
2363         const __le32 *fw_data;
2364         unsigned i;
2365         u32 tmp;
2366
2367         if (!adev->gfx.mec_fw)
2368                 return -EINVAL;
2369
2370         gfx_v9_0_cp_compute_enable(adev, false);
2371
2372         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2373         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2374
2375         fw_data = (const __le32 *)
2376                 (adev->gfx.mec_fw->data +
2377                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2378         tmp = 0;
2379         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2380         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2381         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2382
2383         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2384                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2385         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2386                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2387
2388         /* MEC1 */
2389         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2390                          mec_hdr->jt_offset);
2391         for (i = 0; i < mec_hdr->jt_size; i++)
2392                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2393                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2394
2395         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2396                         adev->gfx.mec_fw_version);
2397         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2398
2399         return 0;
2400 }
2401
2402 /* KIQ functions */
2403 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2404 {
2405         uint32_t tmp;
2406         struct amdgpu_device *adev = ring->adev;
2407
2408         /* tell RLC which is KIQ queue */
2409         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2410         tmp &= 0xffffff00;
2411         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2412         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2413         tmp |= 0x80;
2414         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2415 }
2416
2417 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2418 {
2419         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2420         uint32_t scratch, tmp = 0;
2421         uint64_t queue_mask = 0;
2422         int r, i;
2423
2424         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2425                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2426                         continue;
2427
2428                 /* This situation may be hit in the future if a new HW
2429                  * generation exposes more than 64 queues. If so, the
2430                  * definition of queue_mask needs updating */
2431                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2432                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2433                         break;
2434                 }
2435
2436                 queue_mask |= (1ull << i);
2437         }
2438
2439         r = amdgpu_gfx_scratch_get(adev, &scratch);
2440         if (r) {
2441                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2442                 return r;
2443         }
2444         WREG32(scratch, 0xCAFEDEAD);
2445
2446         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2447         if (r) {
2448                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2449                 amdgpu_gfx_scratch_free(adev, scratch);
2450                 return r;
2451         }
2452
2453         /* set resources */
2454         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2455         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2456                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2457         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2458         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2459         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2460         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2461         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2462         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2463         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2464                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2465                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2466                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2467
2468                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2469                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2470                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2471                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2472                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2473                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2474                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2475                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2476                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2477                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2478                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2479                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2480                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2481                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2482                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2483                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2484                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2485         }
2486         /* write to scratch for completion */
2487         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2488         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2489         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2490         amdgpu_ring_commit(kiq_ring);
2491
2492         for (i = 0; i < adev->usec_timeout; i++) {
2493                 tmp = RREG32(scratch);
2494                 if (tmp == 0xDEADBEEF)
2495                         break;
2496                 DRM_UDELAY(1);
2497         }
2498         if (i >= adev->usec_timeout) {
2499                 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2500                           scratch, tmp);
2501                 r = -EINVAL;
2502         }
2503         amdgpu_gfx_scratch_free(adev, scratch);
2504
2505         return r;
2506 }
2507
2508 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2509 {
2510         struct amdgpu_device *adev = ring->adev;
2511         struct v9_mqd *mqd = ring->mqd_ptr;
2512         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2513         uint32_t tmp;
2514
2515         mqd->header = 0xC0310800;
2516         mqd->compute_pipelinestat_enable = 0x00000001;
2517         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2518         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2519         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2520         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2521         mqd->compute_misc_reserved = 0x00000003;
2522
2523         mqd->dynamic_cu_mask_addr_lo =
2524                 lower_32_bits(ring->mqd_gpu_addr
2525                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2526         mqd->dynamic_cu_mask_addr_hi =
2527                 upper_32_bits(ring->mqd_gpu_addr
2528                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2529
2530         eop_base_addr = ring->eop_gpu_addr >> 8;
2531         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2532         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2533
2534         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2535         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2536         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2537                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2538
2539         mqd->cp_hqd_eop_control = tmp;
2540
2541         /* enable doorbell? */
2542         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2543
2544         if (ring->use_doorbell) {
2545                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2546                                     DOORBELL_OFFSET, ring->doorbell_index);
2547                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2548                                     DOORBELL_EN, 1);
2549                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2550                                     DOORBELL_SOURCE, 0);
2551                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2552                                     DOORBELL_HIT, 0);
2553         } else {
2554                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2555                                          DOORBELL_EN, 0);
2556         }
2557
2558         mqd->cp_hqd_pq_doorbell_control = tmp;
2559
2560         /* disable the queue if it's active */
2561         ring->wptr = 0;
2562         mqd->cp_hqd_dequeue_request = 0;
2563         mqd->cp_hqd_pq_rptr = 0;
2564         mqd->cp_hqd_pq_wptr_lo = 0;
2565         mqd->cp_hqd_pq_wptr_hi = 0;
2566
2567         /* set the pointer to the MQD */
2568         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2569         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2570
2571         /* set MQD vmid to 0 */
2572         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2573         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2574         mqd->cp_mqd_control = tmp;
2575
2576         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2577         hqd_gpu_addr = ring->gpu_addr >> 8;
2578         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2579         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2580
2581         /* set up the HQD, this is similar to CP_RB0_CNTL */
2582         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2583         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2584                             (order_base_2(ring->ring_size / 4) - 1));
2585         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2586                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2587 #ifdef __BIG_ENDIAN
2588         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2589 #endif
2590         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2591         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2592         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2593         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2594         mqd->cp_hqd_pq_control = tmp;
2595
2596         /* set the wb address whether it's enabled or not */
2597         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2598         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2599         mqd->cp_hqd_pq_rptr_report_addr_hi =
2600                 upper_32_bits(wb_gpu_addr) & 0xffff;
2601
2602         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2603         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2604         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2605         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2606
2607         tmp = 0;
2608         /* enable the doorbell if requested */
2609         if (ring->use_doorbell) {
2610                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2611                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2612                                 DOORBELL_OFFSET, ring->doorbell_index);
2613
2614                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2615                                          DOORBELL_EN, 1);
2616                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2617                                          DOORBELL_SOURCE, 0);
2618                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2619                                          DOORBELL_HIT, 0);
2620         }
2621
2622         mqd->cp_hqd_pq_doorbell_control = tmp;
2623
2624         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2625         ring->wptr = 0;
2626         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2627
2628         /* set the vmid for the queue */
2629         mqd->cp_hqd_vmid = 0;
2630
2631         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2632         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2633         mqd->cp_hqd_persistent_state = tmp;
2634
2635         /* set MIN_IB_AVAIL_SIZE */
2636         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2637         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2638         mqd->cp_hqd_ib_control = tmp;
2639
2640         /* activate the queue */
2641         mqd->cp_hqd_active = 1;
2642
2643         return 0;
2644 }
2645
2646 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2647 {
2648         struct amdgpu_device *adev = ring->adev;
2649         struct v9_mqd *mqd = ring->mqd_ptr;
2650         int j;
2651
2652         /* disable wptr polling */
2653         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2654
2655         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2656                mqd->cp_hqd_eop_base_addr_lo);
2657         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2658                mqd->cp_hqd_eop_base_addr_hi);
2659
2660         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2661         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2662                mqd->cp_hqd_eop_control);
2663
2664         /* enable doorbell? */
2665         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2666                mqd->cp_hqd_pq_doorbell_control);
2667
2668         /* disable the queue if it's active */
2669         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2670                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2671                 for (j = 0; j < adev->usec_timeout; j++) {
2672                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2673                                 break;
2674                         udelay(1);
2675                 }
2676                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2677                        mqd->cp_hqd_dequeue_request);
2678                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2679                        mqd->cp_hqd_pq_rptr);
2680                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2681                        mqd->cp_hqd_pq_wptr_lo);
2682                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2683                        mqd->cp_hqd_pq_wptr_hi);
2684         }
2685
2686         /* set the pointer to the MQD */
2687         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2688                mqd->cp_mqd_base_addr_lo);
2689         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2690                mqd->cp_mqd_base_addr_hi);
2691
2692         /* set MQD vmid to 0 */
2693         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2694                mqd->cp_mqd_control);
2695
2696         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2697         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2698                mqd->cp_hqd_pq_base_lo);
2699         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2700                mqd->cp_hqd_pq_base_hi);
2701
2702         /* set up the HQD, this is similar to CP_RB0_CNTL */
2703         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2704                mqd->cp_hqd_pq_control);
2705
2706         /* set the wb address whether it's enabled or not */
2707         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2708                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2709         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2710                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2711
2712         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2713         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2714                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2715         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2716                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2717
2718         /* enable the doorbell if requested */
2719         if (ring->use_doorbell) {
2720                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2721                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2722                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2723                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2724         }
2725
2726         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2727                mqd->cp_hqd_pq_doorbell_control);
2728
2729         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2730         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2731                mqd->cp_hqd_pq_wptr_lo);
2732         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2733                mqd->cp_hqd_pq_wptr_hi);
2734
2735         /* set the vmid for the queue */
2736         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2737
2738         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2739                mqd->cp_hqd_persistent_state);
2740
2741         /* activate the queue */
2742         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2743                mqd->cp_hqd_active);
2744
2745         if (ring->use_doorbell)
2746                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2747
2748         return 0;
2749 }
2750
2751 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2752 {
2753         struct amdgpu_device *adev = ring->adev;
2754         struct v9_mqd *mqd = ring->mqd_ptr;
2755         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2756
2757         gfx_v9_0_kiq_setting(ring);
2758
2759         if (adev->in_gpu_reset) { /* for GPU_RESET case */
2760                 /* reset MQD to a clean status */
2761                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2762                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2763
2764                 /* reset ring buffer */
2765                 ring->wptr = 0;
2766                 amdgpu_ring_clear_ring(ring);
2767
2768                 mutex_lock(&adev->srbm_mutex);
2769                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2770                 gfx_v9_0_kiq_init_register(ring);
2771                 soc15_grbm_select(adev, 0, 0, 0, 0);
2772                 mutex_unlock(&adev->srbm_mutex);
2773         } else {
2774                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2775                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2776                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2777                 mutex_lock(&adev->srbm_mutex);
2778                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2779                 gfx_v9_0_mqd_init(ring);
2780                 gfx_v9_0_kiq_init_register(ring);
2781                 soc15_grbm_select(adev, 0, 0, 0, 0);
2782                 mutex_unlock(&adev->srbm_mutex);
2783
2784                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2785                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
2786         }
2787
2788         return 0;
2789 }
2790
2791 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2792 {
2793         struct amdgpu_device *adev = ring->adev;
2794         struct v9_mqd *mqd = ring->mqd_ptr;
2795         int mqd_idx = ring - &adev->gfx.compute_ring[0];
2796
2797         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
2798                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2799                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2800                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2801                 mutex_lock(&adev->srbm_mutex);
2802                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2803                 gfx_v9_0_mqd_init(ring);
2804                 soc15_grbm_select(adev, 0, 0, 0, 0);
2805                 mutex_unlock(&adev->srbm_mutex);
2806
2807                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2808                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
2809         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
2810                 /* reset MQD to a clean status */
2811                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2812                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2813
2814                 /* reset ring buffer */
2815                 ring->wptr = 0;
2816                 amdgpu_ring_clear_ring(ring);
2817         } else {
2818                 amdgpu_ring_clear_ring(ring);
2819         }
2820
2821         return 0;
2822 }
2823
2824 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2825 {
2826         struct amdgpu_ring *ring = NULL;
2827         int r = 0, i;
2828
2829         gfx_v9_0_cp_compute_enable(adev, true);
2830
2831         ring = &adev->gfx.kiq.ring;
2832
2833         r = amdgpu_bo_reserve(ring->mqd_obj, false);
2834         if (unlikely(r != 0))
2835                 goto done;
2836
2837         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2838         if (!r) {
2839                 r = gfx_v9_0_kiq_init_queue(ring);
2840                 amdgpu_bo_kunmap(ring->mqd_obj);
2841                 ring->mqd_ptr = NULL;
2842         }
2843         amdgpu_bo_unreserve(ring->mqd_obj);
2844         if (r)
2845                 goto done;
2846
2847         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2848                 ring = &adev->gfx.compute_ring[i];
2849
2850                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2851                 if (unlikely(r != 0))
2852                         goto done;
2853                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2854                 if (!r) {
2855                         r = gfx_v9_0_kcq_init_queue(ring);
2856                         amdgpu_bo_kunmap(ring->mqd_obj);
2857                         ring->mqd_ptr = NULL;
2858                 }
2859                 amdgpu_bo_unreserve(ring->mqd_obj);
2860                 if (r)
2861                         goto done;
2862         }
2863
2864         r = gfx_v9_0_kiq_kcq_enable(adev);
2865 done:
2866         return r;
2867 }
2868
2869 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2870 {
2871         int r, i;
2872         struct amdgpu_ring *ring;
2873
2874         if (!(adev->flags & AMD_IS_APU))
2875                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2876
2877         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2878                 /* legacy firmware loading */
2879                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2880                 if (r)
2881                         return r;
2882
2883                 r = gfx_v9_0_cp_compute_load_microcode(adev);
2884                 if (r)
2885                         return r;
2886         }
2887
2888         r = gfx_v9_0_cp_gfx_resume(adev);
2889         if (r)
2890                 return r;
2891
2892         r = gfx_v9_0_kiq_resume(adev);
2893         if (r)
2894                 return r;
2895
2896         ring = &adev->gfx.gfx_ring[0];
2897         r = amdgpu_ring_test_ring(ring);
2898         if (r) {
2899                 ring->ready = false;
2900                 return r;
2901         }
2902
2903         ring = &adev->gfx.kiq.ring;
2904         ring->ready = true;
2905         r = amdgpu_ring_test_ring(ring);
2906         if (r)
2907                 ring->ready = false;
2908
2909         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2910                 ring = &adev->gfx.compute_ring[i];
2911
2912                 ring->ready = true;
2913                 r = amdgpu_ring_test_ring(ring);
2914                 if (r)
2915                         ring->ready = false;
2916         }
2917
2918         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2919
2920         return 0;
2921 }
2922
2923 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2924 {
2925         gfx_v9_0_cp_gfx_enable(adev, enable);
2926         gfx_v9_0_cp_compute_enable(adev, enable);
2927 }
2928
2929 static int gfx_v9_0_hw_init(void *handle)
2930 {
2931         int r;
2932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2933
2934         gfx_v9_0_init_golden_registers(adev);
2935
2936         gfx_v9_0_gpu_init(adev);
2937
2938         r = gfx_v9_0_rlc_resume(adev);
2939         if (r)
2940                 return r;
2941
2942         r = gfx_v9_0_cp_resume(adev);
2943         if (r)
2944                 return r;
2945
2946         r = gfx_v9_0_ngg_en(adev);
2947         if (r)
2948                 return r;
2949
2950         return r;
2951 }
2952
2953 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
2954 {
2955         struct amdgpu_device *adev = kiq_ring->adev;
2956         uint32_t scratch, tmp = 0;
2957         int r, i;
2958
2959         r = amdgpu_gfx_scratch_get(adev, &scratch);
2960         if (r) {
2961                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2962                 return r;
2963         }
2964         WREG32(scratch, 0xCAFEDEAD);
2965
2966         r = amdgpu_ring_alloc(kiq_ring, 10);
2967         if (r) {
2968                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2969                 amdgpu_gfx_scratch_free(adev, scratch);
2970                 return r;
2971         }
2972
2973         /* unmap queues */
2974         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2975         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2976                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
2977                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
2978                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
2979                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
2980         amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
2981         amdgpu_ring_write(kiq_ring, 0);
2982         amdgpu_ring_write(kiq_ring, 0);
2983         amdgpu_ring_write(kiq_ring, 0);
2984         /* write to scratch for completion */
2985         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2986         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2987         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2988         amdgpu_ring_commit(kiq_ring);
2989
2990         for (i = 0; i < adev->usec_timeout; i++) {
2991                 tmp = RREG32(scratch);
2992                 if (tmp == 0xDEADBEEF)
2993                         break;
2994                 DRM_UDELAY(1);
2995         }
2996         if (i >= adev->usec_timeout) {
2997                 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
2998                 r = -EINVAL;
2999         }
3000         amdgpu_gfx_scratch_free(adev, scratch);
3001         return r;
3002 }
3003
3004
3005 static int gfx_v9_0_hw_fini(void *handle)
3006 {
3007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3008         int i;
3009
3010         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3011         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3012
3013         /* disable KCQ to avoid CPC touch memory not valid anymore */
3014         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3015                 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
3016
3017         if (amdgpu_sriov_vf(adev)) {
3018                 pr_debug("For SRIOV client, shouldn't do anything.\n");
3019                 return 0;
3020         }
3021         gfx_v9_0_cp_enable(adev, false);
3022         gfx_v9_0_rlc_stop(adev);
3023
3024         return 0;
3025 }
3026
3027 static int gfx_v9_0_suspend(void *handle)
3028 {
3029         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3030
3031         adev->gfx.in_suspend = true;
3032         return gfx_v9_0_hw_fini(adev);
3033 }
3034
3035 static int gfx_v9_0_resume(void *handle)
3036 {
3037         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3038         int r;
3039
3040         r = gfx_v9_0_hw_init(adev);
3041         adev->gfx.in_suspend = false;
3042         return r;
3043 }
3044
3045 static bool gfx_v9_0_is_idle(void *handle)
3046 {
3047         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3048
3049         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3050                                 GRBM_STATUS, GUI_ACTIVE))
3051                 return false;
3052         else
3053                 return true;
3054 }
3055
3056 static int gfx_v9_0_wait_for_idle(void *handle)
3057 {
3058         unsigned i;
3059         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3060
3061         for (i = 0; i < adev->usec_timeout; i++) {
3062                 if (gfx_v9_0_is_idle(handle))
3063                         return 0;
3064                 udelay(1);
3065         }
3066         return -ETIMEDOUT;
3067 }
3068
3069 static int gfx_v9_0_soft_reset(void *handle)
3070 {
3071         u32 grbm_soft_reset = 0;
3072         u32 tmp;
3073         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3074
3075         /* GRBM_STATUS */
3076         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3077         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3078                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3079                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3080                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3081                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3082                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3083                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3084                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3085                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3086                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3087         }
3088
3089         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3090                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3091                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3092         }
3093
3094         /* GRBM_STATUS2 */
3095         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3096         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3097                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3098                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3099
3100
3101         if (grbm_soft_reset) {
3102                 /* stop the rlc */
3103                 gfx_v9_0_rlc_stop(adev);
3104
3105                 /* Disable GFX parsing/prefetching */
3106                 gfx_v9_0_cp_gfx_enable(adev, false);
3107
3108                 /* Disable MEC parsing/prefetching */
3109                 gfx_v9_0_cp_compute_enable(adev, false);
3110
3111                 if (grbm_soft_reset) {
3112                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3113                         tmp |= grbm_soft_reset;
3114                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3115                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3116                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3117
3118                         udelay(50);
3119
3120                         tmp &= ~grbm_soft_reset;
3121                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3122                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3123                 }
3124
3125                 /* Wait a little for things to settle down */
3126                 udelay(50);
3127         }
3128         return 0;
3129 }
3130
3131 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3132 {
3133         uint64_t clock;
3134
3135         mutex_lock(&adev->gfx.gpu_clock_mutex);
3136         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3137         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3138                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3139         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3140         return clock;
3141 }
3142
3143 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3144                                           uint32_t vmid,
3145                                           uint32_t gds_base, uint32_t gds_size,
3146                                           uint32_t gws_base, uint32_t gws_size,
3147                                           uint32_t oa_base, uint32_t oa_size)
3148 {
3149         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3150         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3151
3152         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3153         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3154
3155         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3156         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3157
3158         /* GDS Base */
3159         gfx_v9_0_write_data_to_reg(ring, 0, false,
3160                                    amdgpu_gds_reg_offset[vmid].mem_base,
3161                                    gds_base);
3162
3163         /* GDS Size */
3164         gfx_v9_0_write_data_to_reg(ring, 0, false,
3165                                    amdgpu_gds_reg_offset[vmid].mem_size,
3166                                    gds_size);
3167
3168         /* GWS */
3169         gfx_v9_0_write_data_to_reg(ring, 0, false,
3170                                    amdgpu_gds_reg_offset[vmid].gws,
3171                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3172
3173         /* OA */
3174         gfx_v9_0_write_data_to_reg(ring, 0, false,
3175                                    amdgpu_gds_reg_offset[vmid].oa,
3176                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3177 }
3178
3179 static int gfx_v9_0_early_init(void *handle)
3180 {
3181         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3182
3183         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3184         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3185         gfx_v9_0_set_ring_funcs(adev);
3186         gfx_v9_0_set_irq_funcs(adev);
3187         gfx_v9_0_set_gds_init(adev);
3188         gfx_v9_0_set_rlc_funcs(adev);
3189
3190         return 0;
3191 }
3192
3193 static int gfx_v9_0_late_init(void *handle)
3194 {
3195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3196         int r;
3197
3198         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3199         if (r)
3200                 return r;
3201
3202         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3203         if (r)
3204                 return r;
3205
3206         return 0;
3207 }
3208
3209 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3210 {
3211         uint32_t rlc_setting, data;
3212         unsigned i;
3213
3214         if (adev->gfx.rlc.in_safe_mode)
3215                 return;
3216
3217         /* if RLC is not enabled, do nothing */
3218         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3219         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3220                 return;
3221
3222         if (adev->cg_flags &
3223             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3224              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3225                 data = RLC_SAFE_MODE__CMD_MASK;
3226                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3227                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3228
3229                 /* wait for RLC_SAFE_MODE */
3230                 for (i = 0; i < adev->usec_timeout; i++) {
3231                         if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3232                                 break;
3233                         udelay(1);
3234                 }
3235                 adev->gfx.rlc.in_safe_mode = true;
3236         }
3237 }
3238
3239 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3240 {
3241         uint32_t rlc_setting, data;
3242
3243         if (!adev->gfx.rlc.in_safe_mode)
3244                 return;
3245
3246         /* if RLC is not enabled, do nothing */
3247         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3248         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3249                 return;
3250
3251         if (adev->cg_flags &
3252             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3253                 /*
3254                  * Try to exit safe mode only if it is already in safe
3255                  * mode.
3256                  */
3257                 data = RLC_SAFE_MODE__CMD_MASK;
3258                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3259                 adev->gfx.rlc.in_safe_mode = false;
3260         }
3261 }
3262
3263 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3264                                                 bool enable)
3265 {
3266         /* TODO: double check if we need to perform under safe mdoe */
3267         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3268
3269         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3270                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3271                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3272                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3273         } else {
3274                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3275                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3276         }
3277
3278         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3279 }
3280
3281 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3282                                                 bool enable)
3283 {
3284         /* TODO: double check if we need to perform under safe mode */
3285         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3286
3287         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3288                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3289         else
3290                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3291
3292         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3293                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3294         else
3295                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3296
3297         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3298 }
3299
3300 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3301                                                       bool enable)
3302 {
3303         uint32_t data, def;
3304
3305         /* It is disabled by HW by default */
3306         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3307                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3308                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3309                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3310                           RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3311                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3312                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3313
3314                 /* only for Vega10 & Raven1 */
3315                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3316
3317                 if (def != data)
3318                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3319
3320                 /* MGLS is a global flag to control all MGLS in GFX */
3321                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3322                         /* 2 - RLC memory Light sleep */
3323                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3324                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3325                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3326                                 if (def != data)
3327                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3328                         }
3329                         /* 3 - CP memory Light sleep */
3330                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3331                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3332                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3333                                 if (def != data)
3334                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3335                         }
3336                 }
3337         } else {
3338                 /* 1 - MGCG_OVERRIDE */
3339                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3340                 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3341                          RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3342                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3343                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3344                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3345                 if (def != data)
3346                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3347
3348                 /* 2 - disable MGLS in RLC */
3349                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3350                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3351                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3352                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3353                 }
3354
3355                 /* 3 - disable MGLS in CP */
3356                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3357                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3358                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3359                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3360                 }
3361         }
3362 }
3363
3364 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3365                                            bool enable)
3366 {
3367         uint32_t data, def;
3368
3369         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3370
3371         /* Enable 3D CGCG/CGLS */
3372         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3373                 /* write cmd to clear cgcg/cgls ov */
3374                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3375                 /* unset CGCG override */
3376                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3377                 /* update CGCG and CGLS override bits */
3378                 if (def != data)
3379                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3380                 /* enable 3Dcgcg FSM(0x0020003f) */
3381                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3382                 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3383                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3384                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3385                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3386                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3387                 if (def != data)
3388                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3389
3390                 /* set IDLE_POLL_COUNT(0x00900100) */
3391                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3392                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3393                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3394                 if (def != data)
3395                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3396         } else {
3397                 /* Disable CGCG/CGLS */
3398                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3399                 /* disable cgcg, cgls should be disabled */
3400                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3401                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3402                 /* disable cgcg and cgls in FSM */
3403                 if (def != data)
3404                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3405         }
3406
3407         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3408 }
3409
3410 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3411                                                       bool enable)
3412 {
3413         uint32_t def, data;
3414
3415         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3416
3417         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3418                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3419                 /* unset CGCG override */
3420                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3421                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3422                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3423                 else
3424                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3425                 /* update CGCG and CGLS override bits */
3426                 if (def != data)
3427                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3428
3429                 /* enable cgcg FSM(0x0020003F) */
3430                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3431                 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3432                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3433                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3434                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3435                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3436                 if (def != data)
3437                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3438
3439                 /* set IDLE_POLL_COUNT(0x00900100) */
3440                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3441                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3442                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3443                 if (def != data)
3444                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3445         } else {
3446                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3447                 /* reset CGCG/CGLS bits */
3448                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3449                 /* disable cgcg and cgls in FSM */
3450                 if (def != data)
3451                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3452         }
3453
3454         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3455 }
3456
3457 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3458                                             bool enable)
3459 {
3460         if (enable) {
3461                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3462                  * ===  MGCG + MGLS ===
3463                  */
3464                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3465                 /* ===  CGCG /CGLS for GFX 3D Only === */
3466                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3467                 /* ===  CGCG + CGLS === */
3468                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3469         } else {
3470                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3471                  * ===  CGCG + CGLS ===
3472                  */
3473                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3474                 /* ===  CGCG /CGLS for GFX 3D Only === */
3475                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3476                 /* ===  MGCG + MGLS === */
3477                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3478         }
3479         return 0;
3480 }
3481
3482 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3483         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3484         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3485 };
3486
3487 static int gfx_v9_0_set_powergating_state(void *handle,
3488                                           enum amd_powergating_state state)
3489 {
3490         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3491         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3492
3493         switch (adev->asic_type) {
3494         case CHIP_RAVEN:
3495                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3496                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3497                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3498                 } else {
3499                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3500                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3501                 }
3502
3503                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3504                         gfx_v9_0_enable_cp_power_gating(adev, true);
3505                 else
3506                         gfx_v9_0_enable_cp_power_gating(adev, false);
3507
3508                 /* update gfx cgpg state */
3509                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3510
3511                 /* update mgcg state */
3512                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3513                 break;
3514         default:
3515                 break;
3516         }
3517
3518         return 0;
3519 }
3520
3521 static int gfx_v9_0_set_clockgating_state(void *handle,
3522                                           enum amd_clockgating_state state)
3523 {
3524         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3525
3526         if (amdgpu_sriov_vf(adev))
3527                 return 0;
3528
3529         switch (adev->asic_type) {
3530         case CHIP_VEGA10:
3531         case CHIP_RAVEN:
3532                 gfx_v9_0_update_gfx_clock_gating(adev,
3533                                                  state == AMD_CG_STATE_GATE ? true : false);
3534                 break;
3535         default:
3536                 break;
3537         }
3538         return 0;
3539 }
3540
3541 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3542 {
3543         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3544         int data;
3545
3546         if (amdgpu_sriov_vf(adev))
3547                 *flags = 0;
3548
3549         /* AMD_CG_SUPPORT_GFX_MGCG */
3550         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3551         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3552                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3553
3554         /* AMD_CG_SUPPORT_GFX_CGCG */
3555         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3556         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3557                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3558
3559         /* AMD_CG_SUPPORT_GFX_CGLS */
3560         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3561                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3562
3563         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3564         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3565         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3566                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3567
3568         /* AMD_CG_SUPPORT_GFX_CP_LS */
3569         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3570         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3571                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3572
3573         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3574         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3575         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3576                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3577
3578         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3579         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3580                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3581 }
3582
3583 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3584 {
3585         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3586 }
3587
3588 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3589 {
3590         struct amdgpu_device *adev = ring->adev;
3591         u64 wptr;
3592
3593         /* XXX check if swapping is necessary on BE */
3594         if (ring->use_doorbell) {
3595                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3596         } else {
3597                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3598                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3599         }
3600
3601         return wptr;
3602 }
3603
3604 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3605 {
3606         struct amdgpu_device *adev = ring->adev;
3607
3608         if (ring->use_doorbell) {
3609                 /* XXX check if swapping is necessary on BE */
3610                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3611                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3612         } else {
3613                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3614                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3615         }
3616 }
3617
3618 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3619 {
3620         u32 ref_and_mask, reg_mem_engine;
3621         const struct nbio_hdp_flush_reg *nbio_hf_reg;
3622
3623         if (ring->adev->flags & AMD_IS_APU)
3624                 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
3625         else
3626                 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3627
3628         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3629                 switch (ring->me) {
3630                 case 1:
3631                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3632                         break;
3633                 case 2:
3634                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3635                         break;
3636                 default:
3637                         return;
3638                 }
3639                 reg_mem_engine = 0;
3640         } else {
3641                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3642                 reg_mem_engine = 1; /* pfp */
3643         }
3644
3645         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3646                               nbio_hf_reg->hdp_flush_req_offset,
3647                               nbio_hf_reg->hdp_flush_done_offset,
3648                               ref_and_mask, ref_and_mask, 0x20);
3649 }
3650
3651 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3652 {
3653         gfx_v9_0_write_data_to_reg(ring, 0, true,
3654                                    SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
3655 }
3656
3657 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3658                                       struct amdgpu_ib *ib,
3659                                       unsigned vm_id, bool ctx_switch)
3660 {
3661         u32 header, control = 0;
3662
3663         if (ib->flags & AMDGPU_IB_FLAG_CE)
3664                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3665         else
3666                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3667
3668         control |= ib->length_dw | (vm_id << 24);
3669
3670         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3671                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3672
3673                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3674                         gfx_v9_0_ring_emit_de_meta(ring);
3675         }
3676
3677         amdgpu_ring_write(ring, header);
3678 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3679         amdgpu_ring_write(ring,
3680 #ifdef __BIG_ENDIAN
3681                 (2 << 0) |
3682 #endif
3683                 lower_32_bits(ib->gpu_addr));
3684         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3685         amdgpu_ring_write(ring, control);
3686 }
3687
3688 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3689                                           struct amdgpu_ib *ib,
3690                                           unsigned vm_id, bool ctx_switch)
3691 {
3692         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3693
3694         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3695         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3696         amdgpu_ring_write(ring,
3697 #ifdef __BIG_ENDIAN
3698                                 (2 << 0) |
3699 #endif
3700                                 lower_32_bits(ib->gpu_addr));
3701         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3702         amdgpu_ring_write(ring, control);
3703 }
3704
3705 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3706                                      u64 seq, unsigned flags)
3707 {
3708         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3709         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3710
3711         /* RELEASE_MEM - flush caches, send int */
3712         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3713         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3714                                  EOP_TC_ACTION_EN |
3715                                  EOP_TC_WB_ACTION_EN |
3716                                  EOP_TC_MD_ACTION_EN |
3717                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3718                                  EVENT_INDEX(5)));
3719         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3720
3721         /*
3722          * the address should be Qword aligned if 64bit write, Dword
3723          * aligned if only send 32bit data low (discard data high)
3724          */
3725         if (write64bit)
3726                 BUG_ON(addr & 0x7);
3727         else
3728                 BUG_ON(addr & 0x3);
3729         amdgpu_ring_write(ring, lower_32_bits(addr));
3730         amdgpu_ring_write(ring, upper_32_bits(addr));
3731         amdgpu_ring_write(ring, lower_32_bits(seq));
3732         amdgpu_ring_write(ring, upper_32_bits(seq));
3733         amdgpu_ring_write(ring, 0);
3734 }
3735
3736 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3737 {
3738         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3739         uint32_t seq = ring->fence_drv.sync_seq;
3740         uint64_t addr = ring->fence_drv.gpu_addr;
3741
3742         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3743                               lower_32_bits(addr), upper_32_bits(addr),
3744                               seq, 0xffffffff, 4);
3745 }
3746
3747 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3748                                         unsigned vm_id, uint64_t pd_addr)
3749 {
3750         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
3751         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3752         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
3753         unsigned eng = ring->vm_inv_eng;
3754
3755         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3756         pd_addr |= AMDGPU_PTE_VALID;
3757
3758         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3759                                    hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3760                                    lower_32_bits(pd_addr));
3761
3762         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3763                                    hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3764                                    upper_32_bits(pd_addr));
3765
3766         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3767                                    hub->vm_inv_eng0_req + eng, req);
3768
3769         /* wait for the invalidate to complete */
3770         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3771                               eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
3772
3773         /* compute doesn't have PFP */
3774         if (usepfp) {
3775                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3776                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3777                 amdgpu_ring_write(ring, 0x0);
3778         }
3779 }
3780
3781 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3782 {
3783         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3784 }
3785
3786 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3787 {
3788         u64 wptr;
3789
3790         /* XXX check if swapping is necessary on BE */
3791         if (ring->use_doorbell)
3792                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3793         else
3794                 BUG();
3795         return wptr;
3796 }
3797
3798 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3799 {
3800         struct amdgpu_device *adev = ring->adev;
3801
3802         /* XXX check if swapping is necessary on BE */
3803         if (ring->use_doorbell) {
3804                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3805                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3806         } else{
3807                 BUG(); /* only DOORBELL method supported on gfx9 now */
3808         }
3809 }
3810
3811 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3812                                          u64 seq, unsigned int flags)
3813 {
3814         /* we only allocate 32bit for each seq wb address */
3815         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3816
3817         /* write fence seq to the "addr" */
3818         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3819         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3820                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3821         amdgpu_ring_write(ring, lower_32_bits(addr));
3822         amdgpu_ring_write(ring, upper_32_bits(addr));
3823         amdgpu_ring_write(ring, lower_32_bits(seq));
3824
3825         if (flags & AMDGPU_FENCE_FLAG_INT) {
3826                 /* set register to trigger INT */
3827                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3828                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3829                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3830                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3831                 amdgpu_ring_write(ring, 0);
3832                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3833         }
3834 }
3835
3836 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3837 {
3838         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3839         amdgpu_ring_write(ring, 0);
3840 }
3841
3842 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3843 {
3844         struct v9_ce_ib_state ce_payload = {0};
3845         uint64_t csa_addr;
3846         int cnt;
3847
3848         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3849         csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3850
3851         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3852         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3853                                  WRITE_DATA_DST_SEL(8) |
3854                                  WR_CONFIRM) |
3855                                  WRITE_DATA_CACHE_POLICY(0));
3856         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3857         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3858         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3859 }
3860
3861 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3862 {
3863         struct v9_de_ib_state de_payload = {0};
3864         uint64_t csa_addr, gds_addr;
3865         int cnt;
3866
3867         csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3868         gds_addr = csa_addr + 4096;
3869         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3870         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3871
3872         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3873         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3874         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3875                                  WRITE_DATA_DST_SEL(8) |
3876                                  WR_CONFIRM) |
3877                                  WRITE_DATA_CACHE_POLICY(0));
3878         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3879         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3880         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3881 }
3882
3883 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3884 {
3885         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3886         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3887 }
3888
3889 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3890 {
3891         uint32_t dw2 = 0;
3892
3893         if (amdgpu_sriov_vf(ring->adev))
3894                 gfx_v9_0_ring_emit_ce_meta(ring);
3895
3896         gfx_v9_0_ring_emit_tmz(ring, true);
3897
3898         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3899         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3900                 /* set load_global_config & load_global_uconfig */
3901                 dw2 |= 0x8001;
3902                 /* set load_cs_sh_regs */
3903                 dw2 |= 0x01000000;
3904                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3905                 dw2 |= 0x10002;
3906
3907                 /* set load_ce_ram if preamble presented */
3908                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3909                         dw2 |= 0x10000000;
3910         } else {
3911                 /* still load_ce_ram if this is the first time preamble presented
3912                  * although there is no context switch happens.
3913                  */
3914                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3915                         dw2 |= 0x10000000;
3916         }
3917
3918         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3919         amdgpu_ring_write(ring, dw2);
3920         amdgpu_ring_write(ring, 0);
3921 }
3922
3923 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3924 {
3925         unsigned ret;
3926         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3927         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3928         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3929         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3930         ret = ring->wptr & ring->buf_mask;
3931         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3932         return ret;
3933 }
3934
3935 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3936 {
3937         unsigned cur;
3938         BUG_ON(offset > ring->buf_mask);
3939         BUG_ON(ring->ring[offset] != 0x55aa55aa);
3940
3941         cur = (ring->wptr & ring->buf_mask) - 1;
3942         if (likely(cur > offset))
3943                 ring->ring[offset] = cur - offset;
3944         else
3945                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3946 }
3947
3948 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3949 {
3950         struct amdgpu_device *adev = ring->adev;
3951
3952         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3953         amdgpu_ring_write(ring, 0 |     /* src: register*/
3954                                 (5 << 8) |      /* dst: memory */
3955                                 (1 << 20));     /* write confirm */
3956         amdgpu_ring_write(ring, reg);
3957         amdgpu_ring_write(ring, 0);
3958         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3959                                 adev->virt.reg_val_offs * 4));
3960         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3961                                 adev->virt.reg_val_offs * 4));
3962 }
3963
3964 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3965                                   uint32_t val)
3966 {
3967         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3968         amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3969         amdgpu_ring_write(ring, reg);
3970         amdgpu_ring_write(ring, 0);
3971         amdgpu_ring_write(ring, val);
3972 }
3973
3974 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3975                                                  enum amdgpu_interrupt_state state)
3976 {
3977         switch (state) {
3978         case AMDGPU_IRQ_STATE_DISABLE:
3979         case AMDGPU_IRQ_STATE_ENABLE:
3980                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3981                                TIME_STAMP_INT_ENABLE,
3982                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
3983                 break;
3984         default:
3985                 break;
3986         }
3987 }
3988
3989 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3990                                                      int me, int pipe,
3991                                                      enum amdgpu_interrupt_state state)
3992 {
3993         u32 mec_int_cntl, mec_int_cntl_reg;
3994
3995         /*
3996          * amdgpu controls only the first MEC. That's why this function only
3997          * handles the setting of interrupts for this specific MEC. All other
3998          * pipes' interrupts are set by amdkfd.
3999          */
4000
4001         if (me == 1) {
4002                 switch (pipe) {
4003                 case 0:
4004                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4005                         break;
4006                 case 1:
4007                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4008                         break;
4009                 case 2:
4010                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4011                         break;
4012                 case 3:
4013                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4014                         break;
4015                 default:
4016                         DRM_DEBUG("invalid pipe %d\n", pipe);
4017                         return;
4018                 }
4019         } else {
4020                 DRM_DEBUG("invalid me %d\n", me);
4021                 return;
4022         }
4023
4024         switch (state) {
4025         case AMDGPU_IRQ_STATE_DISABLE:
4026                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4027                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4028                                              TIME_STAMP_INT_ENABLE, 0);
4029                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4030                 break;
4031         case AMDGPU_IRQ_STATE_ENABLE:
4032                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4033                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4034                                              TIME_STAMP_INT_ENABLE, 1);
4035                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4036                 break;
4037         default:
4038                 break;
4039         }
4040 }
4041
4042 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4043                                              struct amdgpu_irq_src *source,
4044                                              unsigned type,
4045                                              enum amdgpu_interrupt_state state)
4046 {
4047         switch (state) {
4048         case AMDGPU_IRQ_STATE_DISABLE:
4049         case AMDGPU_IRQ_STATE_ENABLE:
4050                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4051                                PRIV_REG_INT_ENABLE,
4052                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4053                 break;
4054         default:
4055                 break;
4056         }
4057
4058         return 0;
4059 }
4060
4061 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4062                                               struct amdgpu_irq_src *source,
4063                                               unsigned type,
4064                                               enum amdgpu_interrupt_state state)
4065 {
4066         switch (state) {
4067         case AMDGPU_IRQ_STATE_DISABLE:
4068         case AMDGPU_IRQ_STATE_ENABLE:
4069                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4070                                PRIV_INSTR_INT_ENABLE,
4071                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4072         default:
4073                 break;
4074         }
4075
4076         return 0;
4077 }
4078
4079 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4080                                             struct amdgpu_irq_src *src,
4081                                             unsigned type,
4082                                             enum amdgpu_interrupt_state state)
4083 {
4084         switch (type) {
4085         case AMDGPU_CP_IRQ_GFX_EOP:
4086                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4087                 break;
4088         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4089                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4090                 break;
4091         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4092                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4093                 break;
4094         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4095                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4096                 break;
4097         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4098                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4099                 break;
4100         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4101                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4102                 break;
4103         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4104                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4105                 break;
4106         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4107                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4108                 break;
4109         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4110                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4111                 break;
4112         default:
4113                 break;
4114         }
4115         return 0;
4116 }
4117
4118 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4119                             struct amdgpu_irq_src *source,
4120                             struct amdgpu_iv_entry *entry)
4121 {
4122         int i;
4123         u8 me_id, pipe_id, queue_id;
4124         struct amdgpu_ring *ring;
4125
4126         DRM_DEBUG("IH: CP EOP\n");
4127         me_id = (entry->ring_id & 0x0c) >> 2;
4128         pipe_id = (entry->ring_id & 0x03) >> 0;
4129         queue_id = (entry->ring_id & 0x70) >> 4;
4130
4131         switch (me_id) {
4132         case 0:
4133                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4134                 break;
4135         case 1:
4136         case 2:
4137                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4138                         ring = &adev->gfx.compute_ring[i];
4139                         /* Per-queue interrupt is supported for MEC starting from VI.
4140                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4141                           */
4142                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4143                                 amdgpu_fence_process(ring);
4144                 }
4145                 break;
4146         }
4147         return 0;
4148 }
4149
4150 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4151                                  struct amdgpu_irq_src *source,
4152                                  struct amdgpu_iv_entry *entry)
4153 {
4154         DRM_ERROR("Illegal register access in command stream\n");
4155         schedule_work(&adev->reset_work);
4156         return 0;
4157 }
4158
4159 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4160                                   struct amdgpu_irq_src *source,
4161                                   struct amdgpu_iv_entry *entry)
4162 {
4163         DRM_ERROR("Illegal instruction in command stream\n");
4164         schedule_work(&adev->reset_work);
4165         return 0;
4166 }
4167
4168 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4169                                             struct amdgpu_irq_src *src,
4170                                             unsigned int type,
4171                                             enum amdgpu_interrupt_state state)
4172 {
4173         uint32_t tmp, target;
4174         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4175
4176         if (ring->me == 1)
4177                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4178         else
4179                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4180         target += ring->pipe;
4181
4182         switch (type) {
4183         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4184                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4185                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4186                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4187                                                  GENERIC2_INT_ENABLE, 0);
4188                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4189
4190                         tmp = RREG32(target);
4191                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4192                                                  GENERIC2_INT_ENABLE, 0);
4193                         WREG32(target, tmp);
4194                 } else {
4195                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4196                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4197                                                  GENERIC2_INT_ENABLE, 1);
4198                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4199
4200                         tmp = RREG32(target);
4201                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4202                                                  GENERIC2_INT_ENABLE, 1);
4203                         WREG32(target, tmp);
4204                 }
4205                 break;
4206         default:
4207                 BUG(); /* kiq only support GENERIC2_INT now */
4208                 break;
4209         }
4210         return 0;
4211 }
4212
4213 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4214                             struct amdgpu_irq_src *source,
4215                             struct amdgpu_iv_entry *entry)
4216 {
4217         u8 me_id, pipe_id, queue_id;
4218         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4219
4220         me_id = (entry->ring_id & 0x0c) >> 2;
4221         pipe_id = (entry->ring_id & 0x03) >> 0;
4222         queue_id = (entry->ring_id & 0x70) >> 4;
4223         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4224                    me_id, pipe_id, queue_id);
4225
4226         amdgpu_fence_process(ring);
4227         return 0;
4228 }
4229
4230 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4231         .name = "gfx_v9_0",
4232         .early_init = gfx_v9_0_early_init,
4233         .late_init = gfx_v9_0_late_init,
4234         .sw_init = gfx_v9_0_sw_init,
4235         .sw_fini = gfx_v9_0_sw_fini,
4236         .hw_init = gfx_v9_0_hw_init,
4237         .hw_fini = gfx_v9_0_hw_fini,
4238         .suspend = gfx_v9_0_suspend,
4239         .resume = gfx_v9_0_resume,
4240         .is_idle = gfx_v9_0_is_idle,
4241         .wait_for_idle = gfx_v9_0_wait_for_idle,
4242         .soft_reset = gfx_v9_0_soft_reset,
4243         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4244         .set_powergating_state = gfx_v9_0_set_powergating_state,
4245         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4246 };
4247
4248 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4249         .type = AMDGPU_RING_TYPE_GFX,
4250         .align_mask = 0xff,
4251         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4252         .support_64bit_ptrs = true,
4253         .vmhub = AMDGPU_GFXHUB,
4254         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4255         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4256         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4257         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4258                 5 +  /* COND_EXEC */
4259                 7 +  /* PIPELINE_SYNC */
4260                 24 + /* VM_FLUSH */
4261                 8 +  /* FENCE for VM_FLUSH */
4262                 20 + /* GDS switch */
4263                 4 + /* double SWITCH_BUFFER,
4264                        the first COND_EXEC jump to the place just
4265                            prior to this double SWITCH_BUFFER  */
4266                 5 + /* COND_EXEC */
4267                 7 +      /*     HDP_flush */
4268                 4 +      /*     VGT_flush */
4269                 14 + /* CE_META */
4270                 31 + /* DE_META */
4271                 3 + /* CNTX_CTRL */
4272                 5 + /* HDP_INVL */
4273                 8 + 8 + /* FENCE x2 */
4274                 2, /* SWITCH_BUFFER */
4275         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4276         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4277         .emit_fence = gfx_v9_0_ring_emit_fence,
4278         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4279         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4280         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4281         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4282         .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4283         .test_ring = gfx_v9_0_ring_test_ring,
4284         .test_ib = gfx_v9_0_ring_test_ib,
4285         .insert_nop = amdgpu_ring_insert_nop,
4286         .pad_ib = amdgpu_ring_generic_pad_ib,
4287         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4288         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4289         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4290         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4291         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4292 };
4293
4294 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4295         .type = AMDGPU_RING_TYPE_COMPUTE,
4296         .align_mask = 0xff,
4297         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4298         .support_64bit_ptrs = true,
4299         .vmhub = AMDGPU_GFXHUB,
4300         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4301         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4302         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4303         .emit_frame_size =
4304                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4305                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4306                 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4307                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4308                 24 + /* gfx_v9_0_ring_emit_vm_flush */
4309                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4310         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4311         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4312         .emit_fence = gfx_v9_0_ring_emit_fence,
4313         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4314         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4315         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4316         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4317         .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4318         .test_ring = gfx_v9_0_ring_test_ring,
4319         .test_ib = gfx_v9_0_ring_test_ib,
4320         .insert_nop = amdgpu_ring_insert_nop,
4321         .pad_ib = amdgpu_ring_generic_pad_ib,
4322 };
4323
4324 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4325         .type = AMDGPU_RING_TYPE_KIQ,
4326         .align_mask = 0xff,
4327         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4328         .support_64bit_ptrs = true,
4329         .vmhub = AMDGPU_GFXHUB,
4330         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4331         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4332         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4333         .emit_frame_size =
4334                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4335                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4336                 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4337                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4338                 24 + /* gfx_v9_0_ring_emit_vm_flush */
4339                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4340         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4341         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4342         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4343         .test_ring = gfx_v9_0_ring_test_ring,
4344         .test_ib = gfx_v9_0_ring_test_ib,
4345         .insert_nop = amdgpu_ring_insert_nop,
4346         .pad_ib = amdgpu_ring_generic_pad_ib,
4347         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4348         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4349 };
4350
4351 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4352 {
4353         int i;
4354
4355         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4356
4357         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4358                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4359
4360         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4361                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4362 }
4363
4364 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4365         .set = gfx_v9_0_kiq_set_interrupt_state,
4366         .process = gfx_v9_0_kiq_irq,
4367 };
4368
4369 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4370         .set = gfx_v9_0_set_eop_interrupt_state,
4371         .process = gfx_v9_0_eop_irq,
4372 };
4373
4374 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4375         .set = gfx_v9_0_set_priv_reg_fault_state,
4376         .process = gfx_v9_0_priv_reg_irq,
4377 };
4378
4379 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4380         .set = gfx_v9_0_set_priv_inst_fault_state,
4381         .process = gfx_v9_0_priv_inst_irq,
4382 };
4383
4384 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4385 {
4386         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4387         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4388
4389         adev->gfx.priv_reg_irq.num_types = 1;
4390         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4391
4392         adev->gfx.priv_inst_irq.num_types = 1;
4393         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4394
4395         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4396         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4397 }
4398
4399 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4400 {
4401         switch (adev->asic_type) {
4402         case CHIP_VEGA10:
4403         case CHIP_RAVEN:
4404                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4405                 break;
4406         default:
4407                 break;
4408         }
4409 }
4410
4411 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4412 {
4413         /* init asci gds info */
4414         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4415         adev->gds.gws.total_size = 64;
4416         adev->gds.oa.total_size = 16;
4417
4418         if (adev->gds.mem.total_size == 64 * 1024) {
4419                 adev->gds.mem.gfx_partition_size = 4096;
4420                 adev->gds.mem.cs_partition_size = 4096;
4421
4422                 adev->gds.gws.gfx_partition_size = 4;
4423                 adev->gds.gws.cs_partition_size = 4;
4424
4425                 adev->gds.oa.gfx_partition_size = 4;
4426                 adev->gds.oa.cs_partition_size = 1;
4427         } else {
4428                 adev->gds.mem.gfx_partition_size = 1024;
4429                 adev->gds.mem.cs_partition_size = 1024;
4430
4431                 adev->gds.gws.gfx_partition_size = 16;
4432                 adev->gds.gws.cs_partition_size = 16;
4433
4434                 adev->gds.oa.gfx_partition_size = 4;
4435                 adev->gds.oa.cs_partition_size = 4;
4436         }
4437 }
4438
4439 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4440                                                  u32 bitmap)
4441 {
4442         u32 data;
4443
4444         if (!bitmap)
4445                 return;
4446
4447         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4448         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4449
4450         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4451 }
4452
4453 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4454 {
4455         u32 data, mask;
4456
4457         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4458         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4459
4460         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4461         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4462
4463         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4464
4465         return (~data) & mask;
4466 }
4467
4468 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4469                                  struct amdgpu_cu_info *cu_info)
4470 {
4471         int i, j, k, counter, active_cu_number = 0;
4472         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4473         unsigned disable_masks[4 * 2];
4474
4475         if (!adev || !cu_info)
4476                 return -EINVAL;
4477
4478         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4479
4480         mutex_lock(&adev->grbm_idx_mutex);
4481         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4482                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4483                         mask = 1;
4484                         ao_bitmap = 0;
4485                         counter = 0;
4486                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4487                         if (i < 4 && j < 2)
4488                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4489                                         adev, disable_masks[i * 2 + j]);
4490                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4491                         cu_info->bitmap[i][j] = bitmap;
4492
4493                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4494                                 if (bitmap & mask) {
4495                                         if (counter < adev->gfx.config.max_cu_per_sh)
4496                                                 ao_bitmap |= mask;
4497                                         counter ++;
4498                                 }
4499                                 mask <<= 1;
4500                         }
4501                         active_cu_number += counter;
4502                         if (i < 2 && j < 2)
4503                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4504                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4505                 }
4506         }
4507         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4508         mutex_unlock(&adev->grbm_idx_mutex);
4509
4510         cu_info->number = active_cu_number;
4511         cu_info->ao_cu_mask = ao_cu_mask;
4512
4513         return 0;
4514 }
4515
4516 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4517 {
4518         .type = AMD_IP_BLOCK_TYPE_GFX,
4519         .major = 9,
4520         .minor = 0,
4521         .rev = 0,
4522         .funcs = &gfx_v9_0_ip_funcs,
4523 };