2 * Procfs interface for the PCI bus.
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/proc_fs.h>
12 #include <linux/seq_file.h>
13 #include <linux/capability.h>
14 #include <asm/uaccess.h>
15 #include <asm/byteorder.h>
18 static int proc_initialized; /* = 0 */
21 proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
24 struct inode *inode = file->f_path.dentry->d_inode;
26 mutex_lock(&inode->i_mutex);
32 new = file->f_pos + off;
35 new = inode->i_size + off;
38 if (new < 0 || new > inode->i_size)
42 mutex_unlock(&inode->i_mutex);
47 proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
49 const struct inode *ino = file->f_path.dentry->d_inode;
50 const struct proc_dir_entry *dp = PDE(ino);
51 struct pci_dev *dev = dp->data;
52 unsigned int pos = *ppos;
53 unsigned int cnt, size;
56 * Normal users can read only the standardized portion of the
57 * configuration space as several chips lock up when trying to read
58 * undefined locations (think of Intel PIIX4 as a typical example).
61 if (capable(CAP_SYS_ADMIN))
63 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
72 if (pos + nbytes > size)
76 if (!access_ok(VERIFY_WRITE, buf, cnt))
79 pci_config_pm_runtime_get(dev);
81 if ((pos & 1) && cnt) {
83 pci_user_read_config_byte(dev, pos, &val);
90 if ((pos & 3) && cnt > 2) {
92 pci_user_read_config_word(dev, pos, &val);
93 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
101 pci_user_read_config_dword(dev, pos, &val);
102 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
110 pci_user_read_config_word(dev, pos, &val);
111 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
119 pci_user_read_config_byte(dev, pos, &val);
120 __put_user(val, buf);
126 pci_config_pm_runtime_put(dev);
133 proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, loff_t *ppos)
135 struct inode *ino = file->f_path.dentry->d_inode;
136 const struct proc_dir_entry *dp = PDE(ino);
137 struct pci_dev *dev = dp->data;
146 if (pos + nbytes > size)
150 if (!access_ok(VERIFY_READ, buf, cnt))
153 pci_config_pm_runtime_get(dev);
155 if ((pos & 1) && cnt) {
157 __get_user(val, buf);
158 pci_user_write_config_byte(dev, pos, val);
164 if ((pos & 3) && cnt > 2) {
166 __get_user(val, (__le16 __user *) buf);
167 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
175 __get_user(val, (__le32 __user *) buf);
176 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
184 __get_user(val, (__le16 __user *) buf);
185 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
193 __get_user(val, buf);
194 pci_user_write_config_byte(dev, pos, val);
200 pci_config_pm_runtime_put(dev);
203 i_size_write(ino, dp->size);
207 struct pci_filp_private {
208 enum pci_mmap_state mmap_state;
212 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
215 const struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
216 struct pci_dev *dev = dp->data;
218 struct pci_filp_private *fpriv = file->private_data;
219 #endif /* HAVE_PCI_MMAP */
223 case PCIIOC_CONTROLLER:
224 ret = pci_domain_nr(dev->bus);
228 case PCIIOC_MMAP_IS_IO:
229 fpriv->mmap_state = pci_mmap_io;
232 case PCIIOC_MMAP_IS_MEM:
233 fpriv->mmap_state = pci_mmap_mem;
236 case PCIIOC_WRITE_COMBINE:
238 fpriv->write_combine = 1;
240 fpriv->write_combine = 0;
243 #endif /* HAVE_PCI_MMAP */
254 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
256 struct inode *inode = file->f_path.dentry->d_inode;
257 const struct proc_dir_entry *dp = PDE(inode);
258 struct pci_dev *dev = dp->data;
259 struct pci_filp_private *fpriv = file->private_data;
262 if (!capable(CAP_SYS_RAWIO))
265 /* Make sure the caller is mapping a real resource for this device */
266 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
267 if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
271 if (i >= PCI_ROM_RESOURCE)
274 ret = pci_mmap_page_range(dev, vma,
276 fpriv->write_combine);
283 static int proc_bus_pci_open(struct inode *inode, struct file *file)
285 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
290 fpriv->mmap_state = pci_mmap_io;
291 fpriv->write_combine = 0;
293 file->private_data = fpriv;
298 static int proc_bus_pci_release(struct inode *inode, struct file *file)
300 kfree(file->private_data);
301 file->private_data = NULL;
305 #endif /* HAVE_PCI_MMAP */
307 static const struct file_operations proc_bus_pci_operations = {
308 .owner = THIS_MODULE,
309 .llseek = proc_bus_pci_lseek,
310 .read = proc_bus_pci_read,
311 .write = proc_bus_pci_write,
312 .unlocked_ioctl = proc_bus_pci_ioctl,
313 .compat_ioctl = proc_bus_pci_ioctl,
315 .open = proc_bus_pci_open,
316 .release = proc_bus_pci_release,
317 .mmap = proc_bus_pci_mmap,
318 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
319 .get_unmapped_area = get_pci_unmapped_area,
320 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
321 #endif /* HAVE_PCI_MMAP */
325 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
327 struct pci_dev *dev = NULL;
330 for_each_pci_dev(dev) {
337 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
339 struct pci_dev *dev = v;
342 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
346 static void pci_seq_stop(struct seq_file *m, void *v)
349 struct pci_dev *dev = v;
354 static int show_device(struct seq_file *m, void *v)
356 const struct pci_dev *dev = v;
357 const struct pci_driver *drv;
363 drv = pci_dev_driver(dev);
364 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
371 /* only print standard and ROM resources to preserve compatibility */
372 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
373 resource_size_t start, end;
374 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
375 seq_printf(m, "\t%16llx",
376 (unsigned long long)(start |
377 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
379 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
380 resource_size_t start, end;
381 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
382 seq_printf(m, "\t%16llx",
383 dev->resource[i].start < dev->resource[i].end ?
384 (unsigned long long)(end - start) + 1 : 0);
388 seq_printf(m, "%s", drv->name);
393 static const struct seq_operations proc_bus_pci_devices_op = {
394 .start = pci_seq_start,
395 .next = pci_seq_next,
396 .stop = pci_seq_stop,
400 static struct proc_dir_entry *proc_bus_pci_dir;
402 int pci_proc_attach_device(struct pci_dev *dev)
404 struct pci_bus *bus = dev->bus;
405 struct proc_dir_entry *e;
408 if (!proc_initialized)
412 if (pci_proc_domain(bus)) {
413 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
416 sprintf(name, "%02x", bus->number);
418 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
423 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
424 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
425 &proc_bus_pci_operations, dev);
428 e->size = dev->cfg_size;
434 int pci_proc_detach_device(struct pci_dev *dev)
436 struct proc_dir_entry *e;
438 if ((e = dev->procent)) {
439 remove_proc_entry(e->name, dev->bus->procdir);
445 int pci_proc_detach_bus(struct pci_bus* bus)
447 struct proc_dir_entry *de = bus->procdir;
449 remove_proc_entry(de->name, proc_bus_pci_dir);
453 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
455 return seq_open(file, &proc_bus_pci_devices_op);
457 static const struct file_operations proc_bus_pci_dev_operations = {
458 .owner = THIS_MODULE,
459 .open = proc_bus_pci_dev_open,
462 .release = seq_release,
465 static int __init pci_proc_init(void)
467 struct pci_dev *dev = NULL;
468 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
469 proc_create("devices", 0, proc_bus_pci_dir,
470 &proc_bus_pci_dev_operations);
471 proc_initialized = 1;
472 for_each_pci_dev(dev)
473 pci_proc_attach_device(dev);
478 device_initcall(pci_proc_init);