drivers/gpu/drm/tiny/arcpgu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARC PGU DRM driver.
   4  *
   5  * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <drm/drm_atomic_helper.h>
  10 #include <drm/drm_debugfs.h>
  11 #include <drm/drm_device.h>
  12 #include <drm/drm_drv.h>
  13 #include <drm/drm_fb_cma_helper.h>
  14 #include <drm/drm_fb_helper.h>
  15 #include <drm/drm_fourcc.h>
  16 #include <drm/drm_gem_cma_helper.h>
  17 #include <drm/drm_gem_framebuffer_helper.h>
  18 #include <drm/drm_of.h>
  19 #include <drm/drm_probe_helper.h>
  20 #include <drm/drm_simple_kms_helper.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/module.h>
  23 #include <linux/of_reserved_mem.h>
  24 #include <linux/platform_device.h>
  25
  26 #define ARCPGU_REG_CTRL         0x00
  27 #define ARCPGU_REG_STAT         0x04
  28 #define ARCPGU_REG_FMT          0x10
  29 #define ARCPGU_REG_HSYNC        0x14
  30 #define ARCPGU_REG_VSYNC        0x18
  31 #define ARCPGU_REG_ACTIVE       0x1c
  32 #define ARCPGU_REG_BUF0_ADDR    0x40
  33 #define ARCPGU_REG_STRIDE       0x50
  34 #define ARCPGU_REG_START_SET    0x84
  35
  36 #define ARCPGU_REG_ID           0x3FC
  37
  38 #define ARCPGU_CTRL_ENABLE_MASK 0x02
  39 #define ARCPGU_CTRL_VS_POL_MASK 0x1
  40 #define ARCPGU_CTRL_VS_POL_OFST 0x3
  41 #define ARCPGU_CTRL_HS_POL_MASK 0x1
  42 #define ARCPGU_CTRL_HS_POL_OFST 0x4
  43 #define ARCPGU_MODE_XRGB8888    BIT(2)
  44 #define ARCPGU_STAT_BUSY_MASK   0x02
  45
  46 struct arcpgu_drm_private {
  47         struct drm_device       drm;
  48         void __iomem            *regs;
  49         struct clk              *clk;
  50         struct drm_simple_display_pipe pipe;
  51         struct drm_connector    sim_conn;
  52 };
  53
  54 #define dev_to_arcpgu(x) container_of(x, struct arcpgu_drm_private, drm)
  55
  56 #define pipe_to_arcpgu_priv(x) container_of(x, struct arcpgu_drm_private, pipe)
  57
  58 static inline void arc_pgu_write(struct arcpgu_drm_private *arcpgu,
  59                                  unsigned int reg, u32 value)
  60 {
  61         iowrite32(value, arcpgu->regs + reg);
  62 }
  63
  64 static inline u32 arc_pgu_read(struct arcpgu_drm_private *arcpgu,
  65                                unsigned int reg)
  66 {
  67         return ioread32(arcpgu->regs + reg);
  68 }
  69
  70 #define XRES_DEF        640
  71 #define YRES_DEF        480
  72
  73 #define XRES_MAX        8192
  74 #define YRES_MAX        8192
  75
  76 static int arcpgu_drm_connector_get_modes(struct drm_connector *connector)
  77 {
  78         int count;
  79
  80         count = drm_add_modes_noedid(connector, XRES_MAX, YRES_MAX);
  81         drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF);
  82         return count;
  83 }
  84
  85 static const struct drm_connector_helper_funcs
  86 arcpgu_drm_connector_helper_funcs = {
  87         .get_modes = arcpgu_drm_connector_get_modes,
  88 };
  89
  90 static const struct drm_connector_funcs arcpgu_drm_connector_funcs = {
  91         .reset = drm_atomic_helper_connector_reset,
  92         .fill_modes = drm_helper_probe_single_connector_modes,
  93         .destroy = drm_connector_cleanup,
  94         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  95         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  96 };
  97
  98 static int arcpgu_drm_sim_init(struct drm_device *drm, struct drm_connector *connector)
  99 {
 100         drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs);
 101         return drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs,
 102                                   DRM_MODE_CONNECTOR_VIRTUAL);
 103 }
 104
 105 #define ENCODE_PGU_XY(x, y)     ((((x) - 1) << 16) | ((y) - 1))
 106
 107 static const u32 arc_pgu_supported_formats[] = {
 108         DRM_FORMAT_RGB565,
 109         DRM_FORMAT_XRGB8888,
 110         DRM_FORMAT_ARGB8888,
 111 };
 112
 113 static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_private *arcpgu)
 114 {
 115         const struct drm_framebuffer *fb = arcpgu->pipe.plane.state->fb;
 116         uint32_t pixel_format = fb->format->format;
 117         u32 format = DRM_FORMAT_INVALID;
 118         int i;
 119         u32 reg_ctrl;
 120
 121         for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) {
 122                 if (arc_pgu_supported_formats[i] == pixel_format)
 123                         format = arc_pgu_supported_formats[i];
 124         }
 125
 126         if (WARN_ON(format == DRM_FORMAT_INVALID))
 127                 return;
 128
 129         reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
 130         if (format == DRM_FORMAT_RGB565)
 131                 reg_ctrl &= ~ARCPGU_MODE_XRGB8888;
 132         else
 133                 reg_ctrl |= ARCPGU_MODE_XRGB8888;
 134         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl);
 135 }
 136
 137 static enum drm_mode_status arc_pgu_mode_valid(struct drm_simple_display_pipe *pipe,
 138                                                const struct drm_display_mode *mode)
 139 {
 140         struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
 141         long rate, clk_rate = mode->clock * 1000;
 142         long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
 143
 144         rate = clk_round_rate(arcpgu->clk, clk_rate);
 145         if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
 146                 return MODE_OK;
 147
 148         return MODE_NOCLOCK;
 149 }
 150
 151 static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu)
 152 {
 153         struct drm_display_mode *m = &arcpgu->pipe.crtc.state->adjusted_mode;
 154         u32 val;
 155
 156         arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
 157                       ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
 158
 159         arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
 160                       ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
 161                                     m->crtc_hsync_end - m->crtc_hdisplay));
 162
 163         arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
 164                       ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
 165                                     m->crtc_vsync_end - m->crtc_vdisplay));
 166
 167         arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
 168                       ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
 169                                     m->crtc_vblank_end - m->crtc_vblank_start));
 170
 171         val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
 172
 173         if (m->flags & DRM_MODE_FLAG_PVSYNC)
 174                 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
 175         else
 176                 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
 177
 178         if (m->flags & DRM_MODE_FLAG_PHSYNC)
 179                 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
 180         else
 181                 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
 182
 183         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
 184         arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
 185         arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
 186
 187         arc_pgu_set_pxl_fmt(arcpgu);
 188
 189         clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
 190 }
 191
 192 static void arc_pgu_enable(struct drm_simple_display_pipe *pipe,
 193                            struct drm_crtc_state *crtc_state,
 194                            struct drm_plane_state *plane_state)
 195 {
 196         struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
 197
 198         arc_pgu_mode_set(arcpgu);
 199
 200         clk_prepare_enable(arcpgu->clk);
 201         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 202                       arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
 203                       ARCPGU_CTRL_ENABLE_MASK);
 204 }
 205
 206 static void arc_pgu_disable(struct drm_simple_display_pipe *pipe)
 207 {
 208         struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
 209
 210         clk_disable_unprepare(arcpgu->clk);
 211         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 212                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
 213                               ~ARCPGU_CTRL_ENABLE_MASK);
 214 }
 215
 216 static void arc_pgu_update(struct drm_simple_display_pipe *pipe,
 217                            struct drm_plane_state *state)
 218 {
 219         struct arcpgu_drm_private *arcpgu;
 220         struct drm_gem_cma_object *gem;
 221
 222         if (!pipe->plane.state->fb)
 223                 return;
 224
 225         arcpgu = pipe_to_arcpgu_priv(pipe);
 226         gem = drm_fb_cma_get_gem_obj(pipe->plane.state->fb, 0);
 227         arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
 228 }
 229
 230 static const struct drm_simple_display_pipe_funcs arc_pgu_pipe_funcs = {
 231         .update = arc_pgu_update,
 232         .mode_valid = arc_pgu_mode_valid,
 233         .enable = arc_pgu_enable,
 234         .disable = arc_pgu_disable,
 235 };
 236
 237 static const struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = {
 238         .fb_create  = drm_gem_fb_create,
 239         .atomic_check = drm_atomic_helper_check,
 240         .atomic_commit = drm_atomic_helper_commit,
 241 };
 242
 243 DEFINE_DRM_GEM_CMA_FOPS(arcpgu_drm_ops);
 244
 245 static int arcpgu_load(struct arcpgu_drm_private *arcpgu)
 246 {
 247         struct platform_device *pdev = to_platform_device(arcpgu->drm.dev);
 248         struct device_node *encoder_node = NULL, *endpoint_node = NULL;
 249         struct drm_connector *connector = NULL;
 250         struct drm_device *drm = &arcpgu->drm;
 251         struct resource *res;
 252         int ret;
 253
 254         arcpgu->clk = devm_clk_get(drm->dev, "pxlclk");
 255         if (IS_ERR(arcpgu->clk))
 256                 return PTR_ERR(arcpgu->clk);
 257
 258         ret = drmm_mode_config_init(drm);
 259         if (ret)
 260                 return ret;
 261
 262         drm->mode_config.min_width = 0;
 263         drm->mode_config.min_height = 0;
 264         drm->mode_config.max_width = 1920;
 265         drm->mode_config.max_height = 1080;
 266         drm->mode_config.funcs = &arcpgu_drm_modecfg_funcs;
 267
 268         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 269         arcpgu->regs = devm_ioremap_resource(&pdev->dev, res);
 270         if (IS_ERR(arcpgu->regs))
 271                 return PTR_ERR(arcpgu->regs);
 272
 273         dev_info(drm->dev, "arc_pgu ID: 0x%x\n",
 274                  arc_pgu_read(arcpgu, ARCPGU_REG_ID));
 275
 276         /* Get the optional framebuffer memory resource */
 277         ret = of_reserved_mem_device_init(drm->dev);
 278         if (ret && ret != -ENODEV)
 279                 return ret;
 280
 281         if (dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)))
 282                 return -ENODEV;
 283
 284         /*
 285          * There is only one output port inside each device. It is linked with
 286          * encoder endpoint.
 287          */
 288         endpoint_node = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
 289         if (endpoint_node) {
 290                 encoder_node = of_graph_get_remote_port_parent(endpoint_node);
 291                 of_node_put(endpoint_node);
 292         } else {
 293                 connector = &arcpgu->sim_conn;
 294                 dev_info(drm->dev, "no encoder found. Assumed virtual LCD on simulation platform\n");
 295                 ret = arcpgu_drm_sim_init(drm, connector);
 296                 if (ret < 0)
 297                         return ret;
 298         }
 299
 300         ret = drm_simple_display_pipe_init(drm, &arcpgu->pipe, &arc_pgu_pipe_funcs,
 301                                            arc_pgu_supported_formats,
 302                                            ARRAY_SIZE(arc_pgu_supported_formats),
 303                                            NULL, connector);
 304         if (ret)
 305                 return ret;
 306
 307         if (encoder_node) {
 308                 struct drm_bridge *bridge;
 309
 310                 /* Locate drm bridge from the hdmi encoder DT node */
 311                 bridge = of_drm_find_bridge(encoder_node);
 312                 if (!bridge)
 313                         return -EPROBE_DEFER;
 314
 315                 ret = drm_simple_display_pipe_attach_bridge(&arcpgu->pipe, bridge);
 316                 if (ret)
 317                         return ret;
 318         }
 319
 320         drm_mode_config_reset(drm);
 321         drm_kms_helper_poll_init(drm);
 322
 323         platform_set_drvdata(pdev, drm);
 324         return 0;
 325 }
 326
 327 static int arcpgu_unload(struct drm_device *drm)
 328 {
 329         drm_kms_helper_poll_fini(drm);
 330         drm_atomic_helper_shutdown(drm);
 331
 332         return 0;
 333 }
 334
 335 #ifdef CONFIG_DEBUG_FS
 336 static int arcpgu_show_pxlclock(struct seq_file *m, void *arg)
 337 {
 338         struct drm_info_node *node = (struct drm_info_node *)m->private;
 339         struct drm_device *drm = node->minor->dev;
 340         struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm);
 341         unsigned long clkrate = clk_get_rate(arcpgu->clk);
 342         unsigned long mode_clock = arcpgu->pipe.crtc.mode.crtc_clock * 1000;
 343
 344         seq_printf(m, "hw  : %lu\n", clkrate);
 345         seq_printf(m, "mode: %lu\n", mode_clock);
 346         return 0;
 347 }
 348
 349 static struct drm_info_list arcpgu_debugfs_list[] = {
 350         { "clocks", arcpgu_show_pxlclock, 0 },
 351 };
 352
 353 static void arcpgu_debugfs_init(struct drm_minor *minor)
 354 {
 355         drm_debugfs_create_files(arcpgu_debugfs_list,
 356                                  ARRAY_SIZE(arcpgu_debugfs_list),
 357                                  minor->debugfs_root, minor);
 358 }
 359 #endif
 360
 361 static const struct drm_driver arcpgu_drm_driver = {
 362         .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 363         .name = "arcpgu",
 364         .desc = "ARC PGU Controller",
 365         .date = "20160219",
 366         .major = 1,
 367         .minor = 0,
 368         .patchlevel = 0,
 369         .fops = &arcpgu_drm_ops,
 370         DRM_GEM_CMA_DRIVER_OPS,
 371 #ifdef CONFIG_DEBUG_FS
 372         .debugfs_init = arcpgu_debugfs_init,
 373 #endif
 374 };
 375
 376 static int arcpgu_probe(struct platform_device *pdev)
 377 {
 378         struct arcpgu_drm_private *arcpgu;
 379         int ret;
 380
 381         arcpgu = devm_drm_dev_alloc(&pdev->dev, &arcpgu_drm_driver,
 382                                     struct arcpgu_drm_private, drm);
 383         if (IS_ERR(arcpgu))
 384                 return PTR_ERR(arcpgu);
 385
 386         ret = arcpgu_load(arcpgu);
 387         if (ret)
 388                 return ret;
 389
 390         ret = drm_dev_register(&arcpgu->drm, 0);
 391         if (ret)
 392                 goto err_unload;
 393
 394         drm_fbdev_generic_setup(&arcpgu->drm, 16);
 395
 396         return 0;
 397
 398 err_unload:
 399         arcpgu_unload(&arcpgu->drm);
 400
 401         return ret;
 402 }
 403
 404 static int arcpgu_remove(struct platform_device *pdev)
 405 {
 406         struct drm_device *drm = platform_get_drvdata(pdev);
 407
 408         drm_dev_unregister(drm);
 409         arcpgu_unload(drm);
 410
 411         return 0;
 412 }
 413
 414 static const struct of_device_id arcpgu_of_table[] = {
 415         {.compatible = "snps,arcpgu"},
 416         {}
 417 };
 418
 419 MODULE_DEVICE_TABLE(of, arcpgu_of_table);
 420
 421 static struct platform_driver arcpgu_platform_driver = {
 422         .probe = arcpgu_probe,
 423         .remove = arcpgu_remove,
 424         .driver = {
 425                    .name = "arcpgu",
 426                    .of_match_table = arcpgu_of_table,
 427                    },
 428 };
 429
 430 module_platform_driver(arcpgu_platform_driver);
 431
 432 MODULE_AUTHOR("Carlos Palminha <[email protected]>");
 433 MODULE_DESCRIPTION("ARC PGU DRM driver");
 434 MODULE_LICENSE("GPL");