drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/platform_device.h>
   7
   8 #include "dsi_phy.h"
   9
  10 #define S_DIV_ROUND_UP(n, d)    \
  11         (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
  12
  13 static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
  14                                 s32 min_result, bool even)
  15 {
  16         s32 v;
  17
  18         v = (tmax - tmin) * percent;
  19         v = S_DIV_ROUND_UP(v, 100) + tmin;
  20         if (even && (v & 0x1))
  21                 return max_t(s32, min_result, v - 1);
  22         else
  23                 return max_t(s32, min_result, v);
  24 }
  25
  26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
  27                                         s32 ui, s32 coeff, s32 pcnt)
  28 {
  29         s32 tmax, tmin, clk_z;
  30         s32 temp;
  31
  32         /* reset */
  33         temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
  34         tmin = S_DIV_ROUND_UP(temp, ui) - 2;
  35         if (tmin > 255) {
  36                 tmax = 511;
  37                 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
  38         } else {
  39                 tmax = 255;
  40                 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
  41         }
  42
  43         /* adjust */
  44         temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
  45         timing->clk_zero = clk_z + 8 - temp;
  46 }
  47
  48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
  49                              struct msm_dsi_phy_clk_request *clk_req)
  50 {
  51         const unsigned long bit_rate = clk_req->bitclk_rate;
  52         const unsigned long esc_rate = clk_req->escclk_rate;
  53         s32 ui, lpx;
  54         s32 tmax, tmin;
  55         s32 pcnt0 = 10;
  56         s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
  57         s32 pcnt2 = 10;
  58         s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
  59         s32 coeff = 1000; /* Precision, should avoid overflow */
  60         s32 temp;
  61
  62         if (!bit_rate || !esc_rate)
  63                 return -EINVAL;
  64
  65         ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
  66         lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
  67
  68         tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
  69         tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
  70         timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
  71
  72         temp = lpx / ui;
  73         if (temp & 0x1)
  74                 timing->hs_rqst = temp;
  75         else
  76                 timing->hs_rqst = max_t(s32, 0, temp - 2);
  77
  78         /* Calculate clk_zero after clk_prepare and hs_rqst */
  79         dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
  80
  81         temp = 105 * coeff + 12 * ui - 20 * coeff;
  82         tmax = S_DIV_ROUND_UP(temp, ui) - 2;
  83         tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
  84         timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
  85
  86         temp = 85 * coeff + 6 * ui;
  87         tmax = S_DIV_ROUND_UP(temp, ui) - 2;
  88         temp = 40 * coeff + 4 * ui;
  89         tmin = S_DIV_ROUND_UP(temp, ui) - 2;
  90         timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
  91
  92         tmax = 255;
  93         temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
  94         temp = 145 * coeff + 10 * ui - temp;
  95         tmin = S_DIV_ROUND_UP(temp, ui) - 2;
  96         timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
  97
  98         temp = 105 * coeff + 12 * ui - 20 * coeff;
  99         tmax = S_DIV_ROUND_UP(temp, ui) - 2;
 100         temp = 60 * coeff + 4 * ui;
 101         tmin = DIV_ROUND_UP(temp, ui) - 2;
 102         timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
 103
 104         tmax = 255;
 105         tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
 106         timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
 107
 108         tmax = 63;
 109         temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
 110         temp = 60 * coeff + 52 * ui - 24 * ui - temp;
 111         tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
 112         timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
 113                                                        false);
 114         tmax = 63;
 115         temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
 116         temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
 117         temp += 8 * ui + lpx;
 118         tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
 119         if (tmin > tmax) {
 120                 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
 121                 timing->shared_timings.clk_pre = temp >> 1;
 122                 timing->shared_timings.clk_pre_inc_by_2 = true;
 123         } else {
 124                 timing->shared_timings.clk_pre =
 125                                 linear_inter(tmax, tmin, pcnt2, 0, false);
 126                 timing->shared_timings.clk_pre_inc_by_2 = false;
 127         }
 128
 129         timing->ta_go = 3;
 130         timing->ta_sure = 0;
 131         timing->ta_get = 4;
 132
 133         DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
 134                 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
 135                 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
 136                 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
 137                 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
 138                 timing->hs_rqst);
 139
 140         return 0;
 141 }
 142
 143 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
 144                                 struct msm_dsi_phy_clk_request *clk_req)
 145 {
 146         const unsigned long bit_rate = clk_req->bitclk_rate;
 147         const unsigned long esc_rate = clk_req->escclk_rate;
 148         s32 ui, ui_x8;
 149         s32 tmax, tmin;
 150         s32 pcnt0 = 50;
 151         s32 pcnt1 = 50;
 152         s32 pcnt2 = 10;
 153         s32 pcnt3 = 30;
 154         s32 pcnt4 = 10;
 155         s32 pcnt5 = 2;
 156         s32 coeff = 1000; /* Precision, should avoid overflow */
 157         s32 hb_en, hb_en_ckln, pd_ckln, pd;
 158         s32 val, val_ckln;
 159         s32 temp;
 160
 161         if (!bit_rate || !esc_rate)
 162                 return -EINVAL;
 163
 164         timing->hs_halfbyte_en = 0;
 165         hb_en = 0;
 166         timing->hs_halfbyte_en_ckln = 0;
 167         hb_en_ckln = 0;
 168         timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
 169         pd_ckln = timing->hs_prep_dly_ckln;
 170         timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
 171         pd = timing->hs_prep_dly;
 172
 173         val = (hb_en << 2) + (pd << 1);
 174         val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
 175
 176         ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
 177         ui_x8 = ui << 3;
 178
 179         temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
 180         tmin = max_t(s32, temp, 0);
 181         temp = (95 * coeff - val_ckln * ui) / ui_x8;
 182         tmax = max_t(s32, temp, 0);
 183         timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
 184
 185         temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
 186         tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
 187         tmax = (tmin > 255) ? 511 : 255;
 188         timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
 189
 190         tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
 191         temp = 105 * coeff + 12 * ui - 20 * coeff;
 192         tmax = (temp + 3 * ui) / ui_x8;
 193         timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
 194
 195         temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
 196         tmin = max_t(s32, temp, 0);
 197         temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
 198         tmax = max_t(s32, temp, 0);
 199         timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
 200
 201         temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
 202         tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
 203         tmax = 255;
 204         timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
 205
 206         tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
 207         temp = 105 * coeff + 12 * ui - 20 * coeff;
 208         tmax = (temp + 3 * ui) / ui_x8;
 209         timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
 210
 211         temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
 212         timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
 213
 214         tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
 215         tmax = 255;
 216         timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
 217
 218         temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
 219         timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
 220
 221         temp = 60 * coeff + 52 * ui - 43 * ui;
 222         tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
 223         tmax = 63;
 224         timing->shared_timings.clk_post =
 225                                 linear_inter(tmax, tmin, pcnt2, 0, false);
 226
 227         temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
 228         temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
 229         temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
 230                                 (((timing->hs_rqst_ckln << 3) + 8) * ui);
 231         tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
 232         tmax = 63;
 233         if (tmin > tmax) {
 234                 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
 235                 timing->shared_timings.clk_pre = temp >> 1;
 236                 timing->shared_timings.clk_pre_inc_by_2 = 1;
 237         } else {
 238                 timing->shared_timings.clk_pre =
 239                                 linear_inter(tmax, tmin, pcnt2, 0, false);
 240                 timing->shared_timings.clk_pre_inc_by_2 = 0;
 241         }
 242
 243         timing->ta_go = 3;
 244         timing->ta_sure = 0;
 245         timing->ta_get = 4;
 246
 247         DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
 248             timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
 249             timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
 250             timing->clk_trail, timing->clk_prepare, timing->hs_exit,
 251             timing->hs_zero, timing->hs_prepare, timing->hs_trail,
 252             timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
 253             timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
 254             timing->hs_prep_dly_ckln);
 255
 256         return 0;
 257 }
 258
 259 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
 260         struct msm_dsi_phy_clk_request *clk_req)
 261 {
 262         const unsigned long bit_rate = clk_req->bitclk_rate;
 263         const unsigned long esc_rate = clk_req->escclk_rate;
 264         s32 ui, ui_x8;
 265         s32 tmax, tmin;
 266         s32 pcnt0 = 50;
 267         s32 pcnt1 = 50;
 268         s32 pcnt2 = 10;
 269         s32 pcnt3 = 30;
 270         s32 pcnt4 = 10;
 271         s32 pcnt5 = 2;
 272         s32 coeff = 1000; /* Precision, should avoid overflow */
 273         s32 hb_en, hb_en_ckln;
 274         s32 temp;
 275
 276         if (!bit_rate || !esc_rate)
 277                 return -EINVAL;
 278
 279         timing->hs_halfbyte_en = 0;
 280         hb_en = 0;
 281         timing->hs_halfbyte_en_ckln = 0;
 282         hb_en_ckln = 0;
 283
 284         ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
 285         ui_x8 = ui << 3;
 286
 287         temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
 288         tmin = max_t(s32, temp, 0);
 289         temp = (95 * coeff) / ui_x8;
 290         tmax = max_t(s32, temp, 0);
 291         timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
 292
 293         temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
 294         tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
 295         tmax = (tmin > 255) ? 511 : 255;
 296         timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
 297
 298         tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
 299         temp = 105 * coeff + 12 * ui - 20 * coeff;
 300         tmax = (temp + 3 * ui) / ui_x8;
 301         timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
 302
 303         temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
 304         tmin = max_t(s32, temp, 0);
 305         temp = (85 * coeff + 6 * ui) / ui_x8;
 306         tmax = max_t(s32, temp, 0);
 307         timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
 308
 309         temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
 310         tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
 311         tmax = 255;
 312         timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
 313
 314         tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
 315         temp = 105 * coeff + 12 * ui - 20 * coeff;
 316         tmax = (temp / ui_x8) - 1;
 317         timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
 318
 319         temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
 320         timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
 321
 322         tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
 323         tmax = 255;
 324         timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
 325
 326         temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
 327         timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
 328
 329         temp = 60 * coeff + 52 * ui - 43 * ui;
 330         tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
 331         tmax = 63;
 332         timing->shared_timings.clk_post =
 333                 linear_inter(tmax, tmin, pcnt2, 0, false);
 334
 335         temp = 8 * ui + (timing->clk_prepare << 3) * ui;
 336         temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
 337         temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
 338                 (((timing->hs_rqst_ckln << 3) + 8) * ui);
 339         tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
 340         tmax = 63;
 341         if (tmin > tmax) {
 342                 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
 343                 timing->shared_timings.clk_pre = temp >> 1;
 344                 timing->shared_timings.clk_pre_inc_by_2 = 1;
 345         } else {
 346                 timing->shared_timings.clk_pre =
 347                         linear_inter(tmax, tmin, pcnt2, 0, false);
 348                         timing->shared_timings.clk_pre_inc_by_2 = 0;
 349         }
 350
 351         timing->ta_go = 3;
 352         timing->ta_sure = 0;
 353         timing->ta_get = 4;
 354
 355         DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
 356                 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
 357                 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
 358                 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
 359                 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
 360                 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
 361                 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
 362                 timing->hs_prep_dly_ckln);
 363
 364         return 0;
 365 }
 366
 367 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
 368         struct msm_dsi_phy_clk_request *clk_req)
 369 {
 370         const unsigned long bit_rate = clk_req->bitclk_rate;
 371         const unsigned long esc_rate = clk_req->escclk_rate;
 372         s32 ui, ui_x8;
 373         s32 tmax, tmin;
 374         s32 pcnt_clk_prep = 50;
 375         s32 pcnt_clk_zero = 2;
 376         s32 pcnt_clk_trail = 30;
 377         s32 pcnt_hs_prep = 50;
 378         s32 pcnt_hs_zero = 10;
 379         s32 pcnt_hs_trail = 30;
 380         s32 pcnt_hs_exit = 10;
 381         s32 coeff = 1000; /* Precision, should avoid overflow */
 382         s32 hb_en;
 383         s32 temp;
 384
 385         if (!bit_rate || !esc_rate)
 386                 return -EINVAL;
 387
 388         hb_en = 0;
 389
 390         ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
 391         ui_x8 = ui << 3;
 392
 393         /* TODO: verify these calculations against latest downstream driver
 394          * everything except clk_post/clk_pre uses calculations from v3 based
 395          * on the downstream driver having the same calculations for v3 and v4
 396          */
 397
 398         temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
 399         tmin = max_t(s32, temp, 0);
 400         temp = (95 * coeff) / ui_x8;
 401         tmax = max_t(s32, temp, 0);
 402         timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false);
 403
 404         temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
 405         tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
 406         tmax = (tmin > 255) ? 511 : 255;
 407         timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false);
 408
 409         tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
 410         temp = 105 * coeff + 12 * ui - 20 * coeff;
 411         tmax = (temp + 3 * ui) / ui_x8;
 412         timing->clk_trail = linear_inter(tmax, tmin, pcnt_clk_trail, 0, false);
 413
 414         temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
 415         tmin = max_t(s32, temp, 0);
 416         temp = (85 * coeff + 6 * ui) / ui_x8;
 417         tmax = max_t(s32, temp, 0);
 418         timing->hs_prepare = linear_inter(tmax, tmin, pcnt_hs_prep, 0, false);
 419
 420         temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
 421         tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
 422         tmax = 255;
 423         timing->hs_zero = linear_inter(tmax, tmin, pcnt_hs_zero, 0, false);
 424
 425         tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
 426         temp = 105 * coeff + 12 * ui - 20 * coeff;
 427         tmax = (temp / ui_x8) - 1;
 428         timing->hs_trail = linear_inter(tmax, tmin, pcnt_hs_trail, 0, false);
 429
 430         temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
 431         timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
 432
 433         tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
 434         tmax = 255;
 435         timing->hs_exit = linear_inter(tmax, tmin, pcnt_hs_exit, 0, false);
 436
 437         /* recommended min
 438          * = roundup((mipi_min_ns + t_hs_trail_ns)/(16*bit_clk_ns), 0) - 1
 439          */
 440         temp = 60 * coeff + 52 * ui + + (timing->hs_trail + 1) * ui_x8;
 441         tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
 442         tmax = 255;
 443         timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false);
 444
 445         /* recommended min
 446          * val1 = (tlpx_ns + clk_prepare_ns + clk_zero_ns + hs_rqst_ns)
 447          * val2 = (16 * bit_clk_ns)
 448          * final = roundup(val1/val2, 0) - 1
 449          */
 450         temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff;
 451         tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
 452         tmax = 255;
 453         timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin;
 454
 455         DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
 456                 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
 457                 timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit,
 458                 timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst);
 459
 460         return 0;
 461 }
 462
 463 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
 464                                 u32 bit_mask)
 465 {
 466         int phy_id = phy->id;
 467         u32 val;
 468
 469         if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
 470                 return;
 471
 472         val = dsi_phy_read(phy->base + reg);
 473
 474         if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
 475                 dsi_phy_write(phy->base + reg, val | bit_mask);
 476         else
 477                 dsi_phy_write(phy->base + reg, val & (~bit_mask));
 478 }
 479
 480 static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
 481 {
 482         struct regulator_bulk_data *s = phy->supplies;
 483         const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
 484         struct device *dev = &phy->pdev->dev;
 485         int num = phy->cfg->reg_cfg.num;
 486         int i, ret;
 487
 488         for (i = 0; i < num; i++)
 489                 s[i].supply = regs[i].name;
 490
 491         ret = devm_regulator_bulk_get(dev, num, s);
 492         if (ret < 0) {
 493                 if (ret != -EPROBE_DEFER) {
 494                         DRM_DEV_ERROR(dev,
 495                                       "%s: failed to init regulator, ret=%d\n",
 496                                       __func__, ret);
 497                 }
 498
 499                 return ret;
 500         }
 501
 502         return 0;
 503 }
 504
 505 static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
 506 {
 507         struct regulator_bulk_data *s = phy->supplies;
 508         const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
 509         int num = phy->cfg->reg_cfg.num;
 510         int i;
 511
 512         DBG("");
 513         for (i = num - 1; i >= 0; i--)
 514                 if (regs[i].disable_load >= 0)
 515                         regulator_set_load(s[i].consumer, regs[i].disable_load);
 516
 517         regulator_bulk_disable(num, s);
 518 }
 519
 520 static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
 521 {
 522         struct regulator_bulk_data *s = phy->supplies;
 523         const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
 524         struct device *dev = &phy->pdev->dev;
 525         int num = phy->cfg->reg_cfg.num;
 526         int ret, i;
 527
 528         DBG("");
 529         for (i = 0; i < num; i++) {
 530                 if (regs[i].enable_load >= 0) {
 531                         ret = regulator_set_load(s[i].consumer,
 532                                                         regs[i].enable_load);
 533                         if (ret < 0) {
 534                                 DRM_DEV_ERROR(dev,
 535                                         "regulator %d set op mode failed, %d\n",
 536                                         i, ret);
 537                                 goto fail;
 538                         }
 539                 }
 540         }
 541
 542         ret = regulator_bulk_enable(num, s);
 543         if (ret < 0) {
 544                 DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret);
 545                 goto fail;
 546         }
 547
 548         return 0;
 549
 550 fail:
 551         for (i--; i >= 0; i--)
 552                 regulator_set_load(s[i].consumer, regs[i].disable_load);
 553         return ret;
 554 }
 555
 556 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
 557 {
 558         struct device *dev = &phy->pdev->dev;
 559         int ret;
 560
 561         pm_runtime_get_sync(dev);
 562
 563         ret = clk_prepare_enable(phy->ahb_clk);
 564         if (ret) {
 565                 DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
 566                 pm_runtime_put_sync(dev);
 567         }
 568
 569         return ret;
 570 }
 571
 572 static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
 573 {
 574         clk_disable_unprepare(phy->ahb_clk);
 575         pm_runtime_put_autosuspend(&phy->pdev->dev);
 576 }
 577
 578 static const struct of_device_id dsi_phy_dt_match[] = {
 579 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
 580         { .compatible = "qcom,dsi-phy-28nm-hpm",
 581           .data = &dsi_phy_28nm_hpm_cfgs },
 582         { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
 583           .data = &dsi_phy_28nm_hpm_famb_cfgs },
 584         { .compatible = "qcom,dsi-phy-28nm-lp",
 585           .data = &dsi_phy_28nm_lp_cfgs },
 586 #endif
 587 #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
 588         { .compatible = "qcom,dsi-phy-20nm",
 589           .data = &dsi_phy_20nm_cfgs },
 590 #endif
 591 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
 592         { .compatible = "qcom,dsi-phy-28nm-8960",
 593           .data = &dsi_phy_28nm_8960_cfgs },
 594 #endif
 595 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
 596         { .compatible = "qcom,dsi-phy-14nm",
 597           .data = &dsi_phy_14nm_cfgs },
 598         { .compatible = "qcom,dsi-phy-14nm-660",
 599           .data = &dsi_phy_14nm_660_cfgs },
 600 #endif
 601 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
 602         { .compatible = "qcom,dsi-phy-10nm",
 603           .data = &dsi_phy_10nm_cfgs },
 604         { .compatible = "qcom,dsi-phy-10nm-8998",
 605           .data = &dsi_phy_10nm_8998_cfgs },
 606 #endif
 607 #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
 608         { .compatible = "qcom,dsi-phy-7nm",
 609           .data = &dsi_phy_7nm_cfgs },
 610         { .compatible = "qcom,dsi-phy-7nm-8150",
 611           .data = &dsi_phy_7nm_8150_cfgs },
 612 #endif
 613         {}
 614 };
 615
 616 /*
 617  * Currently, we only support one SoC for each PHY type. When we have multiple
 618  * SoCs for the same PHY, we can try to make the index searching a bit more
 619  * clever.
 620  */
 621 static int dsi_phy_get_id(struct msm_dsi_phy *phy)
 622 {
 623         struct platform_device *pdev = phy->pdev;
 624         const struct msm_dsi_phy_cfg *cfg = phy->cfg;
 625         struct resource *res;
 626         int i;
 627
 628         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy");
 629         if (!res)
 630                 return -EINVAL;
 631
 632         for (i = 0; i < cfg->num_dsi_phy; i++) {
 633                 if (cfg->io_start[i] == res->start)
 634                         return i;
 635         }
 636
 637         return -EINVAL;
 638 }
 639
 640 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
 641 {
 642         struct platform_device *pdev = phy->pdev;
 643         int ret = 0;
 644
 645         phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
 646                                 "DSI_PHY_REG");
 647         if (IS_ERR(phy->reg_base)) {
 648                 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n",
 649                         __func__);
 650                 ret = -ENOMEM;
 651                 goto fail;
 652         }
 653
 654 fail:
 655         return ret;
 656 }
 657
 658 static int dsi_phy_driver_probe(struct platform_device *pdev)
 659 {
 660         struct msm_dsi_phy *phy;
 661         struct device *dev = &pdev->dev;
 662         const struct of_device_id *match;
 663         int ret;
 664
 665         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 666         if (!phy)
 667                 return -ENOMEM;
 668
 669         match = of_match_node(dsi_phy_dt_match, dev->of_node);
 670         if (!match)
 671                 return -ENODEV;
 672
 673         phy->cfg = match->data;
 674         phy->pdev = pdev;
 675
 676         phy->id = dsi_phy_get_id(phy);
 677         if (phy->id < 0) {
 678                 ret = phy->id;
 679                 DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n",
 680                         __func__, ret);
 681                 goto fail;
 682         }
 683
 684         phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
 685                                 "qcom,dsi-phy-regulator-ldo-mode");
 686
 687         phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
 688         if (IS_ERR(phy->base)) {
 689                 DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
 690                 ret = -ENOMEM;
 691                 goto fail;
 692         }
 693
 694         ret = dsi_phy_regulator_init(phy);
 695         if (ret)
 696                 goto fail;
 697
 698         phy->ahb_clk = msm_clk_get(pdev, "iface");
 699         if (IS_ERR(phy->ahb_clk)) {
 700                 DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__);
 701                 ret = PTR_ERR(phy->ahb_clk);
 702                 goto fail;
 703         }
 704
 705         if (phy->cfg->ops.init) {
 706                 ret = phy->cfg->ops.init(phy);
 707                 if (ret)
 708                         goto fail;
 709         }
 710
 711         /* PLL init will call into clk_register which requires
 712          * register access, so we need to enable power and ahb clock.
 713          */
 714         ret = dsi_phy_enable_resource(phy);
 715         if (ret)
 716                 goto fail;
 717
 718         phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
 719         if (IS_ERR_OR_NULL(phy->pll)) {
 720                 DRM_DEV_INFO(dev,
 721                         "%s: pll init failed: %ld, need separate pll clk driver\n",
 722                         __func__, PTR_ERR(phy->pll));
 723                 phy->pll = NULL;
 724         }
 725
 726         dsi_phy_disable_resource(phy);
 727
 728         platform_set_drvdata(pdev, phy);
 729
 730         return 0;
 731
 732 fail:
 733         return ret;
 734 }
 735
 736 static int dsi_phy_driver_remove(struct platform_device *pdev)
 737 {
 738         struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
 739
 740         if (phy && phy->pll) {
 741                 msm_dsi_pll_destroy(phy->pll);
 742                 phy->pll = NULL;
 743         }
 744
 745         platform_set_drvdata(pdev, NULL);
 746
 747         return 0;
 748 }
 749
 750 static struct platform_driver dsi_phy_platform_driver = {
 751         .probe      = dsi_phy_driver_probe,
 752         .remove     = dsi_phy_driver_remove,
 753         .driver     = {
 754                 .name   = "msm_dsi_phy",
 755                 .of_match_table = dsi_phy_dt_match,
 756         },
 757 };
 758
 759 void __init msm_dsi_phy_driver_register(void)
 760 {
 761         platform_driver_register(&dsi_phy_platform_driver);
 762 }
 763
 764 void __exit msm_dsi_phy_driver_unregister(void)
 765 {
 766         platform_driver_unregister(&dsi_phy_platform_driver);
 767 }
 768
 769 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 770                         struct msm_dsi_phy_clk_request *clk_req)
 771 {
 772         struct device *dev = &phy->pdev->dev;
 773         int ret;
 774
 775         if (!phy || !phy->cfg->ops.enable)
 776                 return -EINVAL;
 777
 778         ret = dsi_phy_enable_resource(phy);
 779         if (ret) {
 780                 DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",
 781                         __func__, ret);
 782                 goto res_en_fail;
 783         }
 784
 785         ret = dsi_phy_regulator_enable(phy);
 786         if (ret) {
 787                 DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",
 788                         __func__, ret);
 789                 goto reg_en_fail;
 790         }
 791
 792         ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
 793         if (ret) {
 794                 DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
 795                 goto phy_en_fail;
 796         }
 797
 798         /*
 799          * Resetting DSI PHY silently changes its PLL registers to reset status,
 800          * which will confuse clock driver and result in wrong output rate of
 801          * link clocks. Restore PLL status if its PLL is being used as clock
 802          * source.
 803          */
 804         if (phy->usecase != MSM_DSI_PHY_SLAVE) {
 805                 ret = msm_dsi_pll_restore_state(phy->pll);
 806                 if (ret) {
 807                         DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",
 808                                 __func__, ret);
 809                         goto pll_restor_fail;
 810                 }
 811         }
 812
 813         return 0;
 814
 815 pll_restor_fail:
 816         if (phy->cfg->ops.disable)
 817                 phy->cfg->ops.disable(phy);
 818 phy_en_fail:
 819         dsi_phy_regulator_disable(phy);
 820 reg_en_fail:
 821         dsi_phy_disable_resource(phy);
 822 res_en_fail:
 823         return ret;
 824 }
 825
 826 void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
 827 {
 828         if (!phy || !phy->cfg->ops.disable)
 829                 return;
 830
 831         phy->cfg->ops.disable(phy);
 832
 833         dsi_phy_regulator_disable(phy);
 834         dsi_phy_disable_resource(phy);
 835 }
 836
 837 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
 838                         struct msm_dsi_phy_shared_timings *shared_timings)
 839 {
 840         memcpy(shared_timings, &phy->timing.shared_timings,
 841                sizeof(*shared_timings));
 842 }
 843
 844 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
 845 {
 846         if (!phy)
 847                 return NULL;
 848
 849         return phy->pll;
 850 }
 851
 852 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
 853                              enum msm_dsi_phy_usecase uc)
 854 {
 855         if (phy)
 856                 phy->usecase = uc;
 857 }