drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "uvd/uvd_7_0_offset.h"
  41 #include "gc/gc_9_0_offset.h"
  42 #include "gc/gc_9_0_sh_mask.h"
  43 #include "sdma0/sdma0_4_0_offset.h"
  44 #include "sdma1/sdma1_4_0_offset.h"
  45 #include "nbio/nbio_7_0_default.h"
  46 #include "nbio/nbio_7_0_offset.h"
  47 #include "nbio/nbio_7_0_sh_mask.h"
  48 #include "nbio/nbio_7_0_smn.h"
  49 #include "mp/mp_9_0_offset.h"
  50
  51 #include "soc15.h"
  52 #include "soc15_common.h"
  53 #include "gfx_v9_0.h"
  54 #include "gmc_v9_0.h"
  55 #include "gfxhub_v1_0.h"
  56 #include "mmhub_v1_0.h"
  57 #include "df_v1_7.h"
  58 #include "df_v3_6.h"
  59 #include "nbio_v6_1.h"
  60 #include "nbio_v7_0.h"
  61 #include "nbio_v7_4.h"
  62 #include "hdp_v4_0.h"
  63 #include "vega10_ih.h"
  64 #include "vega20_ih.h"
  65 #include "navi10_ih.h"
  66 #include "sdma_v4_0.h"
  67 #include "uvd_v7_0.h"
  68 #include "vce_v4_0.h"
  69 #include "vcn_v1_0.h"
  70 #include "vcn_v2_0.h"
  71 #include "jpeg_v2_0.h"
  72 #include "vcn_v2_5.h"
  73 #include "jpeg_v2_5.h"
  74 #include "smuio_v9_0.h"
  75 #include "smuio_v11_0.h"
  76 #include "smuio_v13_0.h"
  77 #include "amdgpu_vkms.h"
  78 #include "mxgpu_ai.h"
  79 #include "amdgpu_ras.h"
  80 #include "amdgpu_xgmi.h"
  81 #include <uapi/linux/kfd_ioctl.h>
  82
  83 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  87
  88 static const struct amd_ip_funcs soc15_common_ip_funcs;
  89
  90 /* Vega, Raven, Arcturus */
  91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
  92 {
  93         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  94         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  95 };
  96
  97 static const struct amdgpu_video_codecs vega_video_codecs_encode =
  98 {
  99         .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
 100         .codec_array = vega_video_codecs_encode_array,
 101 };
 102
 103 /* Vega */
 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
 105 {
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 111         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 112 };
 113
 114 static const struct amdgpu_video_codecs vega_video_codecs_decode =
 115 {
 116         .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
 117         .codec_array = vega_video_codecs_decode_array,
 118 };
 119
 120 /* Raven */
 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
 122 {
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 124         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 125         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 126         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 127         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
 130 };
 131
 132 static const struct amdgpu_video_codecs rv_video_codecs_decode =
 133 {
 134         .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
 135         .codec_array = rv_video_codecs_decode_array,
 136 };
 137
 138 /* Renoir, Arcturus */
 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
 140 {
 141         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 142         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 143         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 144         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 146         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 147         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 148 };
 149
 150 static const struct amdgpu_video_codecs rn_video_codecs_decode =
 151 {
 152         .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
 153         .codec_array = rn_video_codecs_decode_array,
 154 };
 155
 156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
 157                                     const struct amdgpu_video_codecs **codecs)
 158 {
 159         if (adev->ip_versions[VCE_HWIP][0]) {
 160                 switch (adev->ip_versions[VCE_HWIP][0]) {
 161                 case IP_VERSION(4, 0, 0):
 162                 case IP_VERSION(4, 1, 0):
 163                         if (encode)
 164                                 *codecs = &vega_video_codecs_encode;
 165                         else
 166                                 *codecs = &vega_video_codecs_decode;
 167                         return 0;
 168                 default:
 169                         return -EINVAL;
 170                 }
 171         } else {
 172                 switch (adev->ip_versions[UVD_HWIP][0]) {
 173                 case IP_VERSION(1, 0, 0):
 174                 case IP_VERSION(1, 0, 1):
 175                         if (encode)
 176                                 *codecs = &vega_video_codecs_encode;
 177                         else
 178                                 *codecs = &rv_video_codecs_decode;
 179                         return 0;
 180                 case IP_VERSION(2, 5, 0):
 181                 case IP_VERSION(2, 6, 0):
 182                 case IP_VERSION(2, 2, 0):
 183                         if (encode)
 184                                 *codecs = &vega_video_codecs_encode;
 185                         else
 186                                 *codecs = &rn_video_codecs_decode;
 187                         return 0;
 188                 default:
 189                         return -EINVAL;
 190                 }
 191         }
 192 }
 193
 194 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 195 {
 196         unsigned long flags, address, data;
 197         u32 r;
 198
 199         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 200         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 201
 202         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 203         WREG32(address, ((reg) & 0x1ff));
 204         r = RREG32(data);
 205         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 206         return r;
 207 }
 208
 209 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 210 {
 211         unsigned long flags, address, data;
 212
 213         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 214         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 215
 216         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 217         WREG32(address, ((reg) & 0x1ff));
 218         WREG32(data, (v));
 219         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 220 }
 221
 222 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 223 {
 224         unsigned long flags, address, data;
 225         u32 r;
 226
 227         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 228         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 229
 230         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 231         WREG32(address, (reg));
 232         r = RREG32(data);
 233         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 234         return r;
 235 }
 236
 237 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 238 {
 239         unsigned long flags, address, data;
 240
 241         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 242         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 243
 244         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 245         WREG32(address, (reg));
 246         WREG32(data, (v));
 247         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 248 }
 249
 250 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 251 {
 252         unsigned long flags;
 253         u32 r;
 254
 255         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 256         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 257         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 258         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 259         return r;
 260 }
 261
 262 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 263 {
 264         unsigned long flags;
 265
 266         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 267         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 268         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 269         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 270 }
 271
 272 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 273 {
 274         unsigned long flags;
 275         u32 r;
 276
 277         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 278         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 279         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 280         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 281         return r;
 282 }
 283
 284 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 285 {
 286         unsigned long flags;
 287
 288         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 289         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 290         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 291         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 292 }
 293
 294 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 295 {
 296         return adev->nbio.funcs->get_memsize(adev);
 297 }
 298
 299 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 300 {
 301         u32 reference_clock = adev->clock.spll.reference_freq;
 302
 303         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
 304             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1) ||
 305             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
 306             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
 307                 return 10000;
 308
 309         return reference_clock;
 310 }
 311
 312
 313 void soc15_grbm_select(struct amdgpu_device *adev,
 314                      u32 me, u32 pipe, u32 queue, u32 vmid)
 315 {
 316         u32 grbm_gfx_cntl = 0;
 317         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 318         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 319         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 320         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 321
 322         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 323 }
 324
 325 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 326 {
 327         /* todo */
 328 }
 329
 330 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 331 {
 332         /* todo */
 333         return false;
 334 }
 335
 336 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 337         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 338         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 339         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 340         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 341         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 342         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 343         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 344         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 345         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 346         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 347         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 348         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 349         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 350         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 351         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 352         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 353         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 354         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 355         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 356         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 357 };
 358
 359 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 360                                          u32 sh_num, u32 reg_offset)
 361 {
 362         uint32_t val;
 363
 364         mutex_lock(&adev->grbm_idx_mutex);
 365         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 366                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 367
 368         val = RREG32(reg_offset);
 369
 370         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 371                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 372         mutex_unlock(&adev->grbm_idx_mutex);
 373         return val;
 374 }
 375
 376 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 377                                          bool indexed, u32 se_num,
 378                                          u32 sh_num, u32 reg_offset)
 379 {
 380         if (indexed) {
 381                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 382         } else {
 383                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 384                         return adev->gfx.config.gb_addr_config;
 385                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 386                         return adev->gfx.config.db_debug2;
 387                 return RREG32(reg_offset);
 388         }
 389 }
 390
 391 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 392                             u32 sh_num, u32 reg_offset, u32 *value)
 393 {
 394         uint32_t i;
 395         struct soc15_allowed_register_entry  *en;
 396
 397         *value = 0;
 398         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 399                 en = &soc15_allowed_read_registers[i];
 400                 if (!adev->reg_offset[en->hwip][en->inst])
 401                         continue;
 402                 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 403                                         + en->reg_offset))
 404                         continue;
 405
 406                 *value = soc15_get_register_value(adev,
 407                                                   soc15_allowed_read_registers[i].grbm_indexed,
 408                                                   se_num, sh_num, reg_offset);
 409                 return 0;
 410         }
 411         return -EINVAL;
 412 }
 413
 414
 415 /**
 416  * soc15_program_register_sequence - program an array of registers.
 417  *
 418  * @adev: amdgpu_device pointer
 419  * @regs: pointer to the register array
 420  * @array_size: size of the register array
 421  *
 422  * Programs an array or registers with and and or masks.
 423  * This is a helper for setting golden registers.
 424  */
 425
 426 void soc15_program_register_sequence(struct amdgpu_device *adev,
 427                                              const struct soc15_reg_golden *regs,
 428                                              const u32 array_size)
 429 {
 430         const struct soc15_reg_golden *entry;
 431         u32 tmp, reg;
 432         int i;
 433
 434         for (i = 0; i < array_size; ++i) {
 435                 entry = &regs[i];
 436                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 437
 438                 if (entry->and_mask == 0xffffffff) {
 439                         tmp = entry->or_mask;
 440                 } else {
 441                         tmp = (entry->hwip == GC_HWIP) ?
 442                                 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
 443
 444                         tmp &= ~(entry->and_mask);
 445                         tmp |= (entry->or_mask & entry->and_mask);
 446                 }
 447
 448                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 449                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 450                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 451                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 452                         WREG32_RLC(reg, tmp);
 453                 else
 454                         (entry->hwip == GC_HWIP) ?
 455                                 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
 456
 457         }
 458
 459 }
 460
 461 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 462 {
 463         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 464         int ret = 0;
 465
 466         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 467         if (ras && adev->ras_enabled)
 468                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 469
 470         ret = amdgpu_dpm_baco_reset(adev);
 471         if (ret)
 472                 return ret;
 473
 474         /* re-enable doorbell interrupt after BACO exit */
 475         if (ras && adev->ras_enabled)
 476                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 477
 478         return 0;
 479 }
 480
 481 static enum amd_reset_method
 482 soc15_asic_reset_method(struct amdgpu_device *adev)
 483 {
 484         bool baco_reset = false;
 485         bool connected_to_cpu = false;
 486         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 487
 488         if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
 489                 connected_to_cpu = true;
 490
 491         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 492             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 493             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 494             amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
 495                 /* If connected to cpu, driver only support mode2 */
 496                 if (connected_to_cpu)
 497                         return AMD_RESET_METHOD_MODE2;
 498                 return amdgpu_reset_method;
 499         }
 500
 501         if (amdgpu_reset_method != -1)
 502                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 503                                   amdgpu_reset_method);
 504
 505         switch (adev->ip_versions[MP1_HWIP][0]) {
 506         case IP_VERSION(10, 0, 0):
 507         case IP_VERSION(10, 0, 1):
 508         case IP_VERSION(12, 0, 0):
 509         case IP_VERSION(12, 0, 1):
 510                 return AMD_RESET_METHOD_MODE2;
 511         case IP_VERSION(9, 0, 0):
 512         case IP_VERSION(11, 0, 2):
 513                 if (adev->asic_type == CHIP_VEGA20) {
 514                         if (adev->psp.sos.fw_version >= 0x80067)
 515                                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 516                         /*
 517                          * 1. PMFW version > 0x284300: all cases use baco
 518                          * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 519                          */
 520                         if (ras && adev->ras_enabled &&
 521                             adev->pm.fw_version <= 0x283400)
 522                                 baco_reset = false;
 523                 } else {
 524                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 525                 }
 526                 break;
 527         case IP_VERSION(13, 0, 2):
 528                  /*
 529                  * 1.connected to cpu: driver issue mode2 reset
 530                  * 2.discret gpu: driver issue mode1 reset
 531                  */
 532                 if (connected_to_cpu)
 533                         return AMD_RESET_METHOD_MODE2;
 534                 break;
 535         default:
 536                 break;
 537         }
 538
 539         if (baco_reset)
 540                 return AMD_RESET_METHOD_BACO;
 541         else
 542                 return AMD_RESET_METHOD_MODE1;
 543 }
 544
 545 static int soc15_asic_reset(struct amdgpu_device *adev)
 546 {
 547         /* original raven doesn't have full asic reset */
 548         if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
 549             (adev->apu_flags & AMD_APU_IS_RAVEN2))
 550                 return 0;
 551
 552         switch (soc15_asic_reset_method(adev)) {
 553         case AMD_RESET_METHOD_PCI:
 554                 dev_info(adev->dev, "PCI reset\n");
 555                 return amdgpu_device_pci_reset(adev);
 556         case AMD_RESET_METHOD_BACO:
 557                 dev_info(adev->dev, "BACO reset\n");
 558                 return soc15_asic_baco_reset(adev);
 559         case AMD_RESET_METHOD_MODE2:
 560                 dev_info(adev->dev, "MODE2 reset\n");
 561                 return amdgpu_dpm_mode2_reset(adev);
 562         default:
 563                 dev_info(adev->dev, "MODE1 reset\n");
 564                 return amdgpu_device_mode1_reset(adev);
 565         }
 566 }
 567
 568 static bool soc15_supports_baco(struct amdgpu_device *adev)
 569 {
 570         switch (adev->ip_versions[MP1_HWIP][0]) {
 571         case IP_VERSION(9, 0, 0):
 572         case IP_VERSION(11, 0, 2):
 573                 if (adev->asic_type == CHIP_VEGA20) {
 574                         if (adev->psp.sos.fw_version >= 0x80067)
 575                                 return amdgpu_dpm_is_baco_supported(adev);
 576                         return false;
 577                 } else {
 578                         return amdgpu_dpm_is_baco_supported(adev);
 579                 }
 580                 break;
 581         default:
 582                 return false;
 583         }
 584 }
 585
 586 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 587                         u32 cntl_reg, u32 status_reg)
 588 {
 589         return 0;
 590 }*/
 591
 592 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 593 {
 594         /*int r;
 595
 596         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 597         if (r)
 598                 return r;
 599
 600         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 601         */
 602         return 0;
 603 }
 604
 605 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 606 {
 607         /* todo */
 608
 609         return 0;
 610 }
 611
 612 static void soc15_program_aspm(struct amdgpu_device *adev)
 613 {
 614         if (!amdgpu_device_should_use_aspm(adev))
 615                 return;
 616
 617         if (!(adev->flags & AMD_IS_APU) &&
 618             (adev->nbio.funcs->program_aspm))
 619                 adev->nbio.funcs->program_aspm(adev);
 620 }
 621
 622 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 623                                            bool enable)
 624 {
 625         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 626         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 627 }
 628
 629 const struct amdgpu_ip_block_version vega10_common_ip_block =
 630 {
 631         .type = AMD_IP_BLOCK_TYPE_COMMON,
 632         .major = 2,
 633         .minor = 0,
 634         .rev = 0,
 635         .funcs = &soc15_common_ip_funcs,
 636 };
 637
 638 static void soc15_reg_base_init(struct amdgpu_device *adev)
 639 {
 640         /* Set IP register base before any HW register access */
 641         switch (adev->asic_type) {
 642         case CHIP_VEGA10:
 643         case CHIP_VEGA12:
 644         case CHIP_RAVEN:
 645         case CHIP_RENOIR:
 646                 vega10_reg_base_init(adev);
 647                 break;
 648         case CHIP_VEGA20:
 649                 vega20_reg_base_init(adev);
 650                 break;
 651         case CHIP_ARCTURUS:
 652                 arct_reg_base_init(adev);
 653                 break;
 654         case CHIP_ALDEBARAN:
 655                 aldebaran_reg_base_init(adev);
 656                 break;
 657         default:
 658                 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
 659                 break;
 660         }
 661 }
 662
 663 void soc15_set_virt_ops(struct amdgpu_device *adev)
 664 {
 665         adev->virt.ops = &xgpu_ai_virt_ops;
 666
 667         /* init soc15 reg base early enough so we can
 668          * request request full access for sriov before
 669          * set_ip_blocks. */
 670         soc15_reg_base_init(adev);
 671 }
 672
 673 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 674 {
 675         /* change this when we implement soft reset */
 676         return true;
 677 }
 678
 679 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 680                                  uint64_t *count1)
 681 {
 682         uint32_t perfctr = 0;
 683         uint64_t cnt0_of, cnt1_of;
 684         int tmp;
 685
 686         /* This reports 0 on APUs, so return to avoid writing/reading registers
 687          * that may or may not be different from their GPU counterparts
 688          */
 689         if (adev->flags & AMD_IS_APU)
 690                 return;
 691
 692         /* Set the 2 events that we wish to watch, defined above */
 693         /* Reg 40 is # received msgs */
 694         /* Reg 104 is # of posted requests sent */
 695         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 696         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 697
 698         /* Write to enable desired perf counters */
 699         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 700         /* Zero out and enable the perf counters
 701          * Write 0x5:
 702          * Bit 0 = Start all counters(1)
 703          * Bit 2 = Global counter reset enable(1)
 704          */
 705         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 706
 707         msleep(1000);
 708
 709         /* Load the shadow and disable the perf counters
 710          * Write 0x2:
 711          * Bit 0 = Stop counters(0)
 712          * Bit 1 = Load the shadow counters(1)
 713          */
 714         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 715
 716         /* Read register values to get any >32bit overflow */
 717         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 718         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 719         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 720
 721         /* Get the values and add the overflow */
 722         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 723         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 724 }
 725
 726 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 727                                  uint64_t *count1)
 728 {
 729         uint32_t perfctr = 0;
 730         uint64_t cnt0_of, cnt1_of;
 731         int tmp;
 732
 733         /* This reports 0 on APUs, so return to avoid writing/reading registers
 734          * that may or may not be different from their GPU counterparts
 735          */
 736         if (adev->flags & AMD_IS_APU)
 737                 return;
 738
 739         /* Set the 2 events that we wish to watch, defined above */
 740         /* Reg 40 is # received msgs */
 741         /* Reg 108 is # of posted requests sent on VG20 */
 742         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 743                                 EVENT0_SEL, 40);
 744         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 745                                 EVENT1_SEL, 108);
 746
 747         /* Write to enable desired perf counters */
 748         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 749         /* Zero out and enable the perf counters
 750          * Write 0x5:
 751          * Bit 0 = Start all counters(1)
 752          * Bit 2 = Global counter reset enable(1)
 753          */
 754         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 755
 756         msleep(1000);
 757
 758         /* Load the shadow and disable the perf counters
 759          * Write 0x2:
 760          * Bit 0 = Stop counters(0)
 761          * Bit 1 = Load the shadow counters(1)
 762          */
 763         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 764
 765         /* Read register values to get any >32bit overflow */
 766         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 767         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 768         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 769
 770         /* Get the values and add the overflow */
 771         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 772         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 773 }
 774
 775 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 776 {
 777         u32 sol_reg;
 778
 779         /* CP hangs in IGT reloading test on RN, reset to WA */
 780         if (adev->asic_type == CHIP_RENOIR)
 781                 return true;
 782
 783         /* Just return false for soc15 GPUs.  Reset does not seem to
 784          * be necessary.
 785          */
 786         if (!amdgpu_passthrough(adev))
 787                 return false;
 788
 789         if (adev->flags & AMD_IS_APU)
 790                 return false;
 791
 792         /* Check sOS sign of life register to confirm sys driver and sOS
 793          * are already been loaded.
 794          */
 795         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 796         if (sol_reg)
 797                 return true;
 798
 799         return false;
 800 }
 801
 802 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 803 {
 804         uint64_t nak_r, nak_g;
 805
 806         /* Get the number of NAKs received and generated */
 807         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 808         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 809
 810         /* Add the total number of NAKs, i.e the number of replays */
 811         return (nak_r + nak_g);
 812 }
 813
 814 static void soc15_pre_asic_init(struct amdgpu_device *adev)
 815 {
 816         gmc_v9_0_restore_registers(adev);
 817 }
 818
 819 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 820 {
 821         .read_disabled_bios = &soc15_read_disabled_bios,
 822         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 823         .read_register = &soc15_read_register,
 824         .reset = &soc15_asic_reset,
 825         .reset_method = &soc15_asic_reset_method,
 826         .set_vga_state = &soc15_vga_set_state,
 827         .get_xclk = &soc15_get_xclk,
 828         .set_uvd_clocks = &soc15_set_uvd_clocks,
 829         .set_vce_clocks = &soc15_set_vce_clocks,
 830         .get_config_memsize = &soc15_get_config_memsize,
 831         .need_full_reset = &soc15_need_full_reset,
 832         .init_doorbell_index = &vega10_doorbell_index_init,
 833         .get_pcie_usage = &soc15_get_pcie_usage,
 834         .need_reset_on_init = &soc15_need_reset_on_init,
 835         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 836         .supports_baco = &soc15_supports_baco,
 837         .pre_asic_init = &soc15_pre_asic_init,
 838         .query_video_codecs = &soc15_query_video_codecs,
 839 };
 840
 841 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 842 {
 843         .read_disabled_bios = &soc15_read_disabled_bios,
 844         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 845         .read_register = &soc15_read_register,
 846         .reset = &soc15_asic_reset,
 847         .reset_method = &soc15_asic_reset_method,
 848         .set_vga_state = &soc15_vga_set_state,
 849         .get_xclk = &soc15_get_xclk,
 850         .set_uvd_clocks = &soc15_set_uvd_clocks,
 851         .set_vce_clocks = &soc15_set_vce_clocks,
 852         .get_config_memsize = &soc15_get_config_memsize,
 853         .need_full_reset = &soc15_need_full_reset,
 854         .init_doorbell_index = &vega20_doorbell_index_init,
 855         .get_pcie_usage = &vega20_get_pcie_usage,
 856         .need_reset_on_init = &soc15_need_reset_on_init,
 857         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 858         .supports_baco = &soc15_supports_baco,
 859         .pre_asic_init = &soc15_pre_asic_init,
 860         .query_video_codecs = &soc15_query_video_codecs,
 861 };
 862
 863 static int soc15_common_early_init(void *handle)
 864 {
 865 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 866         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 867
 868         if (!amdgpu_sriov_vf(adev)) {
 869                 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 870                 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 871         }
 872         adev->smc_rreg = NULL;
 873         adev->smc_wreg = NULL;
 874         adev->pcie_rreg = &amdgpu_device_indirect_rreg;
 875         adev->pcie_wreg = &amdgpu_device_indirect_wreg;
 876         adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
 877         adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
 878         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 879         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 880         adev->didt_rreg = &soc15_didt_rreg;
 881         adev->didt_wreg = &soc15_didt_wreg;
 882         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 883         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 884         adev->se_cac_rreg = &soc15_se_cac_rreg;
 885         adev->se_cac_wreg = &soc15_se_cac_wreg;
 886
 887         adev->rev_id = amdgpu_device_get_rev_id(adev);
 888         adev->external_rev_id = 0xFF;
 889         /* TODO: split the GC and PG flags based on the relevant IP version for which
 890          * they are relevant.
 891          */
 892         switch (adev->ip_versions[GC_HWIP][0]) {
 893         case IP_VERSION(9, 0, 1):
 894                 adev->asic_funcs = &soc15_asic_funcs;
 895                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 896                         AMD_CG_SUPPORT_GFX_MGLS |
 897                         AMD_CG_SUPPORT_GFX_RLC_LS |
 898                         AMD_CG_SUPPORT_GFX_CP_LS |
 899                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 900                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 901                         AMD_CG_SUPPORT_GFX_CGCG |
 902                         AMD_CG_SUPPORT_GFX_CGLS |
 903                         AMD_CG_SUPPORT_BIF_MGCG |
 904                         AMD_CG_SUPPORT_BIF_LS |
 905                         AMD_CG_SUPPORT_HDP_LS |
 906                         AMD_CG_SUPPORT_DRM_MGCG |
 907                         AMD_CG_SUPPORT_DRM_LS |
 908                         AMD_CG_SUPPORT_ROM_MGCG |
 909                         AMD_CG_SUPPORT_DF_MGCG |
 910                         AMD_CG_SUPPORT_SDMA_MGCG |
 911                         AMD_CG_SUPPORT_SDMA_LS |
 912                         AMD_CG_SUPPORT_MC_MGCG |
 913                         AMD_CG_SUPPORT_MC_LS;
 914                 adev->pg_flags = 0;
 915                 adev->external_rev_id = 0x1;
 916                 break;
 917         case IP_VERSION(9, 2, 1):
 918                 adev->asic_funcs = &soc15_asic_funcs;
 919                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 920                         AMD_CG_SUPPORT_GFX_MGLS |
 921                         AMD_CG_SUPPORT_GFX_CGCG |
 922                         AMD_CG_SUPPORT_GFX_CGLS |
 923                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 924                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 925                         AMD_CG_SUPPORT_GFX_CP_LS |
 926                         AMD_CG_SUPPORT_MC_LS |
 927                         AMD_CG_SUPPORT_MC_MGCG |
 928                         AMD_CG_SUPPORT_SDMA_MGCG |
 929                         AMD_CG_SUPPORT_SDMA_LS |
 930                         AMD_CG_SUPPORT_BIF_MGCG |
 931                         AMD_CG_SUPPORT_BIF_LS |
 932                         AMD_CG_SUPPORT_HDP_MGCG |
 933                         AMD_CG_SUPPORT_HDP_LS |
 934                         AMD_CG_SUPPORT_ROM_MGCG |
 935                         AMD_CG_SUPPORT_VCE_MGCG |
 936                         AMD_CG_SUPPORT_UVD_MGCG;
 937                 adev->pg_flags = 0;
 938                 adev->external_rev_id = adev->rev_id + 0x14;
 939                 break;
 940         case IP_VERSION(9, 4, 0):
 941                 adev->asic_funcs = &vega20_asic_funcs;
 942                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 943                         AMD_CG_SUPPORT_GFX_MGLS |
 944                         AMD_CG_SUPPORT_GFX_CGCG |
 945                         AMD_CG_SUPPORT_GFX_CGLS |
 946                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 947                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 948                         AMD_CG_SUPPORT_GFX_CP_LS |
 949                         AMD_CG_SUPPORT_MC_LS |
 950                         AMD_CG_SUPPORT_MC_MGCG |
 951                         AMD_CG_SUPPORT_SDMA_MGCG |
 952                         AMD_CG_SUPPORT_SDMA_LS |
 953                         AMD_CG_SUPPORT_BIF_MGCG |
 954                         AMD_CG_SUPPORT_BIF_LS |
 955                         AMD_CG_SUPPORT_HDP_MGCG |
 956                         AMD_CG_SUPPORT_HDP_LS |
 957                         AMD_CG_SUPPORT_ROM_MGCG |
 958                         AMD_CG_SUPPORT_VCE_MGCG |
 959                         AMD_CG_SUPPORT_UVD_MGCG;
 960                 adev->pg_flags = 0;
 961                 adev->external_rev_id = adev->rev_id + 0x28;
 962                 break;
 963         case IP_VERSION(9, 1, 0):
 964         case IP_VERSION(9, 2, 2):
 965                 adev->asic_funcs = &soc15_asic_funcs;
 966
 967                 if (adev->rev_id >= 0x8)
 968                         adev->apu_flags |= AMD_APU_IS_RAVEN2;
 969
 970                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 971                         adev->external_rev_id = adev->rev_id + 0x79;
 972                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
 973                         adev->external_rev_id = adev->rev_id + 0x41;
 974                 else if (adev->rev_id == 1)
 975                         adev->external_rev_id = adev->rev_id + 0x20;
 976                 else
 977                         adev->external_rev_id = adev->rev_id + 0x01;
 978
 979                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
 980                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 981                                 AMD_CG_SUPPORT_GFX_MGLS |
 982                                 AMD_CG_SUPPORT_GFX_CP_LS |
 983                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 984                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 985                                 AMD_CG_SUPPORT_GFX_CGCG |
 986                                 AMD_CG_SUPPORT_GFX_CGLS |
 987                                 AMD_CG_SUPPORT_BIF_LS |
 988                                 AMD_CG_SUPPORT_HDP_LS |
 989                                 AMD_CG_SUPPORT_MC_MGCG |
 990                                 AMD_CG_SUPPORT_MC_LS |
 991                                 AMD_CG_SUPPORT_SDMA_MGCG |
 992                                 AMD_CG_SUPPORT_SDMA_LS |
 993                                 AMD_CG_SUPPORT_VCN_MGCG;
 994
 995                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 996                 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
 997                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 998                                 AMD_CG_SUPPORT_GFX_MGLS |
 999                                 AMD_CG_SUPPORT_GFX_CP_LS |
1000                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1001                                 AMD_CG_SUPPORT_GFX_CGCG |
1002                                 AMD_CG_SUPPORT_GFX_CGLS |
1003                                 AMD_CG_SUPPORT_BIF_LS |
1004                                 AMD_CG_SUPPORT_HDP_LS |
1005                                 AMD_CG_SUPPORT_MC_MGCG |
1006                                 AMD_CG_SUPPORT_MC_LS |
1007                                 AMD_CG_SUPPORT_SDMA_MGCG |
1008                                 AMD_CG_SUPPORT_SDMA_LS |
1009                                 AMD_CG_SUPPORT_VCN_MGCG;
1010
1011                         /*
1012                          * MMHUB PG needs to be disabled for Picasso for
1013                          * stability reasons.
1014                          */
1015                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1016                                 AMD_PG_SUPPORT_VCN;
1017                 } else {
1018                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1019                                 AMD_CG_SUPPORT_GFX_MGLS |
1020                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1021                                 AMD_CG_SUPPORT_GFX_CP_LS |
1022                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1023                                 AMD_CG_SUPPORT_GFX_CGCG |
1024                                 AMD_CG_SUPPORT_GFX_CGLS |
1025                                 AMD_CG_SUPPORT_BIF_MGCG |
1026                                 AMD_CG_SUPPORT_BIF_LS |
1027                                 AMD_CG_SUPPORT_HDP_MGCG |
1028                                 AMD_CG_SUPPORT_HDP_LS |
1029                                 AMD_CG_SUPPORT_DRM_MGCG |
1030                                 AMD_CG_SUPPORT_DRM_LS |
1031                                 AMD_CG_SUPPORT_MC_MGCG |
1032                                 AMD_CG_SUPPORT_MC_LS |
1033                                 AMD_CG_SUPPORT_SDMA_MGCG |
1034                                 AMD_CG_SUPPORT_SDMA_LS |
1035                                 AMD_CG_SUPPORT_VCN_MGCG;
1036
1037                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1038                 }
1039                 break;
1040         case IP_VERSION(9, 4, 1):
1041                 adev->asic_funcs = &vega20_asic_funcs;
1042                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1043                         AMD_CG_SUPPORT_GFX_MGLS |
1044                         AMD_CG_SUPPORT_GFX_CGCG |
1045                         AMD_CG_SUPPORT_GFX_CGLS |
1046                         AMD_CG_SUPPORT_GFX_CP_LS |
1047                         AMD_CG_SUPPORT_HDP_MGCG |
1048                         AMD_CG_SUPPORT_HDP_LS |
1049                         AMD_CG_SUPPORT_SDMA_MGCG |
1050                         AMD_CG_SUPPORT_SDMA_LS |
1051                         AMD_CG_SUPPORT_MC_MGCG |
1052                         AMD_CG_SUPPORT_MC_LS |
1053                         AMD_CG_SUPPORT_IH_CG |
1054                         AMD_CG_SUPPORT_VCN_MGCG |
1055                         AMD_CG_SUPPORT_JPEG_MGCG;
1056                 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1057                 adev->external_rev_id = adev->rev_id + 0x32;
1058                 break;
1059         case IP_VERSION(9, 3, 0):
1060                 adev->asic_funcs = &soc15_asic_funcs;
1061
1062                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1063                         adev->external_rev_id = adev->rev_id + 0x91;
1064                 else
1065                         adev->external_rev_id = adev->rev_id + 0xa1;
1066                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1067                                  AMD_CG_SUPPORT_GFX_MGLS |
1068                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1069                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1070                                  AMD_CG_SUPPORT_GFX_CGCG |
1071                                  AMD_CG_SUPPORT_GFX_CGLS |
1072                                  AMD_CG_SUPPORT_GFX_CP_LS |
1073                                  AMD_CG_SUPPORT_MC_MGCG |
1074                                  AMD_CG_SUPPORT_MC_LS |
1075                                  AMD_CG_SUPPORT_SDMA_MGCG |
1076                                  AMD_CG_SUPPORT_SDMA_LS |
1077                                  AMD_CG_SUPPORT_BIF_LS |
1078                                  AMD_CG_SUPPORT_HDP_LS |
1079                                  AMD_CG_SUPPORT_VCN_MGCG |
1080                                  AMD_CG_SUPPORT_JPEG_MGCG |
1081                                  AMD_CG_SUPPORT_IH_CG |
1082                                  AMD_CG_SUPPORT_ATHUB_LS |
1083                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1084                                  AMD_CG_SUPPORT_DF_MGCG;
1085                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1086                                  AMD_PG_SUPPORT_VCN |
1087                                  AMD_PG_SUPPORT_JPEG |
1088                                  AMD_PG_SUPPORT_VCN_DPG;
1089                 break;
1090         case IP_VERSION(9, 4, 2):
1091                 adev->asic_funcs = &vega20_asic_funcs;
1092                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1093                         AMD_CG_SUPPORT_GFX_MGLS |
1094                         AMD_CG_SUPPORT_GFX_CP_LS |
1095                         AMD_CG_SUPPORT_HDP_LS |
1096                         AMD_CG_SUPPORT_SDMA_MGCG |
1097                         AMD_CG_SUPPORT_SDMA_LS |
1098                         AMD_CG_SUPPORT_IH_CG |
1099                         AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1100                 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1101                 adev->external_rev_id = adev->rev_id + 0x3c;
1102                 break;
1103         case IP_VERSION(9, 4, 3):
1104                 adev->asic_funcs = &vega20_asic_funcs;
1105                 adev->cg_flags = 0;
1106                 adev->pg_flags = 0;
1107                 break;
1108         default:
1109                 /* FIXME: not supported yet */
1110                 return -EINVAL;
1111         }
1112
1113         if (amdgpu_sriov_vf(adev)) {
1114                 amdgpu_virt_init_setting(adev);
1115                 xgpu_ai_mailbox_set_irq_funcs(adev);
1116         }
1117
1118         return 0;
1119 }
1120
1121 static int soc15_common_late_init(void *handle)
1122 {
1123         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124
1125         if (amdgpu_sriov_vf(adev))
1126                 xgpu_ai_mailbox_get_irq(adev);
1127
1128         return 0;
1129 }
1130
1131 static int soc15_common_sw_init(void *handle)
1132 {
1133         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1134
1135         if (amdgpu_sriov_vf(adev))
1136                 xgpu_ai_mailbox_add_irq_id(adev);
1137
1138         if (adev->df.funcs &&
1139             adev->df.funcs->sw_init)
1140                 adev->df.funcs->sw_init(adev);
1141
1142         return 0;
1143 }
1144
1145 static int soc15_common_sw_fini(void *handle)
1146 {
1147         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148
1149         if (adev->df.funcs &&
1150             adev->df.funcs->sw_fini)
1151                 adev->df.funcs->sw_fini(adev);
1152         return 0;
1153 }
1154
1155 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1156 {
1157         int i;
1158
1159         /* sdma doorbell range is programed by hypervisor */
1160         if (!amdgpu_sriov_vf(adev)) {
1161                 for (i = 0; i < adev->sdma.num_instances; i++) {
1162                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1163                                 true, adev->doorbell_index.sdma_engine[i] << 1,
1164                                 adev->doorbell_index.sdma_doorbell_range);
1165                 }
1166         }
1167 }
1168
1169 static int soc15_common_hw_init(void *handle)
1170 {
1171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1172
1173         /* enable aspm */
1174         soc15_program_aspm(adev);
1175         /* setup nbio registers */
1176         adev->nbio.funcs->init_registers(adev);
1177         /* remap HDP registers to a hole in mmio space,
1178          * for the purpose of expose those registers
1179          * to process space
1180          */
1181         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1182                 adev->nbio.funcs->remap_hdp_registers(adev);
1183
1184         /* enable the doorbell aperture */
1185         soc15_enable_doorbell_aperture(adev, true);
1186         /* HW doorbell routing policy: doorbell writing not
1187          * in SDMA/IH/MM/ACV range will be routed to CP. So
1188          * we need to init SDMA doorbell range prior
1189          * to CP ip block init and ring test.  IH already
1190          * happens before CP.
1191          */
1192         soc15_sdma_doorbell_range_init(adev);
1193
1194         return 0;
1195 }
1196
1197 static int soc15_common_hw_fini(void *handle)
1198 {
1199         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1200
1201         /* disable the doorbell aperture */
1202         soc15_enable_doorbell_aperture(adev, false);
1203         if (amdgpu_sriov_vf(adev))
1204                 xgpu_ai_mailbox_put_irq(adev);
1205
1206         if (adev->nbio.ras_if &&
1207             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1208                 if (adev->nbio.ras &&
1209                     adev->nbio.ras->init_ras_controller_interrupt)
1210                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1211                 if (adev->nbio.ras &&
1212                     adev->nbio.ras->init_ras_err_event_athub_interrupt)
1213                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1214         }
1215
1216         return 0;
1217 }
1218
1219 static int soc15_common_suspend(void *handle)
1220 {
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223         return soc15_common_hw_fini(adev);
1224 }
1225
1226 static int soc15_common_resume(void *handle)
1227 {
1228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229
1230         return soc15_common_hw_init(adev);
1231 }
1232
1233 static bool soc15_common_is_idle(void *handle)
1234 {
1235         return true;
1236 }
1237
1238 static int soc15_common_wait_for_idle(void *handle)
1239 {
1240         return 0;
1241 }
1242
1243 static int soc15_common_soft_reset(void *handle)
1244 {
1245         return 0;
1246 }
1247
1248 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1249 {
1250         uint32_t def, data;
1251
1252         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1253
1254         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1255                 data &= ~(0x01000000 |
1256                           0x02000000 |
1257                           0x04000000 |
1258                           0x08000000 |
1259                           0x10000000 |
1260                           0x20000000 |
1261                           0x40000000 |
1262                           0x80000000);
1263         else
1264                 data |= (0x01000000 |
1265                          0x02000000 |
1266                          0x04000000 |
1267                          0x08000000 |
1268                          0x10000000 |
1269                          0x20000000 |
1270                          0x40000000 |
1271                          0x80000000);
1272
1273         if (def != data)
1274                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1275 }
1276
1277 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1278 {
1279         uint32_t def, data;
1280
1281         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1282
1283         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1284                 data |= 1;
1285         else
1286                 data &= ~1;
1287
1288         if (def != data)
1289                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1290 }
1291
1292 static int soc15_common_set_clockgating_state(void *handle,
1293                                             enum amd_clockgating_state state)
1294 {
1295         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296
1297         if (amdgpu_sriov_vf(adev))
1298                 return 0;
1299
1300         switch (adev->ip_versions[NBIO_HWIP][0]) {
1301         case IP_VERSION(6, 1, 0):
1302         case IP_VERSION(6, 2, 0):
1303         case IP_VERSION(7, 4, 0):
1304                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1305                                 state == AMD_CG_STATE_GATE);
1306                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1307                                 state == AMD_CG_STATE_GATE);
1308                 adev->hdp.funcs->update_clock_gating(adev,
1309                                 state == AMD_CG_STATE_GATE);
1310                 soc15_update_drm_clock_gating(adev,
1311                                 state == AMD_CG_STATE_GATE);
1312                 soc15_update_drm_light_sleep(adev,
1313                                 state == AMD_CG_STATE_GATE);
1314                 adev->smuio.funcs->update_rom_clock_gating(adev,
1315                                 state == AMD_CG_STATE_GATE);
1316                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1317                                 state == AMD_CG_STATE_GATE);
1318                 break;
1319         case IP_VERSION(7, 0, 0):
1320         case IP_VERSION(7, 0, 1):
1321         case IP_VERSION(2, 5, 0):
1322                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1323                                 state == AMD_CG_STATE_GATE);
1324                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1325                                 state == AMD_CG_STATE_GATE);
1326                 adev->hdp.funcs->update_clock_gating(adev,
1327                                 state == AMD_CG_STATE_GATE);
1328                 soc15_update_drm_clock_gating(adev,
1329                                 state == AMD_CG_STATE_GATE);
1330                 soc15_update_drm_light_sleep(adev,
1331                                 state == AMD_CG_STATE_GATE);
1332                 break;
1333         case IP_VERSION(7, 4, 1):
1334         case IP_VERSION(7, 4, 4):
1335                 adev->hdp.funcs->update_clock_gating(adev,
1336                                 state == AMD_CG_STATE_GATE);
1337                 break;
1338         default:
1339                 break;
1340         }
1341         return 0;
1342 }
1343
1344 static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1345 {
1346         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1347         int data;
1348
1349         if (amdgpu_sriov_vf(adev))
1350                 *flags = 0;
1351
1352         adev->nbio.funcs->get_clockgating_state(adev, flags);
1353
1354         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1355
1356         if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1357
1358                 /* AMD_CG_SUPPORT_DRM_MGCG */
1359                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1360                 if (!(data & 0x01000000))
1361                         *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1362
1363                 /* AMD_CG_SUPPORT_DRM_LS */
1364                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1365                 if (data & 0x1)
1366                         *flags |= AMD_CG_SUPPORT_DRM_LS;
1367         }
1368
1369         /* AMD_CG_SUPPORT_ROM_MGCG */
1370         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1371
1372         adev->df.funcs->get_clockgating_state(adev, flags);
1373 }
1374
1375 static int soc15_common_set_powergating_state(void *handle,
1376                                             enum amd_powergating_state state)
1377 {
1378         /* todo */
1379         return 0;
1380 }
1381
1382 static const struct amd_ip_funcs soc15_common_ip_funcs = {
1383         .name = "soc15_common",
1384         .early_init = soc15_common_early_init,
1385         .late_init = soc15_common_late_init,
1386         .sw_init = soc15_common_sw_init,
1387         .sw_fini = soc15_common_sw_fini,
1388         .hw_init = soc15_common_hw_init,
1389         .hw_fini = soc15_common_hw_fini,
1390         .suspend = soc15_common_suspend,
1391         .resume = soc15_common_resume,
1392         .is_idle = soc15_common_is_idle,
1393         .wait_for_idle = soc15_common_wait_for_idle,
1394         .soft_reset = soc15_common_soft_reset,
1395         .set_clockgating_state = soc15_common_set_clockgating_state,
1396         .set_powergating_state = soc15_common_set_powergating_state,
1397         .get_clockgating_state= soc15_common_get_clockgating_state,
1398 };