1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Linaro Ltd.
6 #include <linux/device.h>
7 #include <linux/firmware.h>
8 #include <linux/kernel.h>
9 #include <linux/iommu.h>
12 #include <linux/of_address.h>
13 #include <linux/of_reserved_mem.h>
14 #include <linux/platform_device.h>
15 #include <linux/of_device.h>
16 #include <linux/firmware/qcom/qcom_scm.h>
17 #include <linux/sizes.h>
18 #include <linux/soc/qcom/mdt_loader.h>
22 #include "hfi_venus_io.h"
24 #define VENUS_PAS_ID 9
25 #define VENUS_FW_MEM_SIZE (6 * SZ_1M)
26 #define VENUS_FW_START_ADDR 0x0
28 static void venus_reset_cpu(struct venus_core *core)
30 u32 fw_size = core->fw.mapped_mem_size;
31 void __iomem *wrapper_base;
34 wrapper_base = core->wrapper_tz_base;
36 wrapper_base = core->wrapper_base;
38 writel(0, wrapper_base + WRAPPER_FW_START_ADDR);
39 writel(fw_size, wrapper_base + WRAPPER_FW_END_ADDR);
40 writel(0, wrapper_base + WRAPPER_CPA_START_ADDR);
41 writel(fw_size, wrapper_base + WRAPPER_CPA_END_ADDR);
42 writel(fw_size, wrapper_base + WRAPPER_NONPIX_START_ADDR);
43 writel(fw_size, wrapper_base + WRAPPER_NONPIX_END_ADDR);
45 if (IS_IRIS2_1(core)) {
46 /* Bring XTSS out of reset */
47 writel(0, wrapper_base + WRAPPER_TZ_XTSS_SW_RESET);
49 writel(0x0, wrapper_base + WRAPPER_CPU_CGC_DIS);
50 writel(0x0, wrapper_base + WRAPPER_CPU_CLOCK_CONFIG);
52 /* Bring ARM9 out of reset */
53 writel(0, wrapper_base + WRAPPER_A9SS_SW_RESET);
57 int venus_set_hw_state(struct venus_core *core, bool resume)
62 ret = qcom_scm_set_remote_state(resume, 0);
63 if (resume && ret == -EINVAL)
69 venus_reset_cpu(core);
72 writel(WRAPPER_XTSS_SW_RESET_BIT,
73 core->wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
75 writel(WRAPPER_A9SS_SW_RESET_BIT,
76 core->wrapper_base + WRAPPER_A9SS_SW_RESET);
82 static int venus_load_fw(struct venus_core *core, const char *fwname,
83 phys_addr_t *mem_phys, size_t *mem_size)
85 const struct firmware *mdt;
86 struct reserved_mem *rmem;
87 struct device_node *node;
97 node = of_parse_phandle(dev->of_node, "memory-region", 0);
99 dev_err(dev, "no memory-region specified\n");
103 rmem = of_reserved_mem_lookup(node);
106 dev_err(dev, "failed to lookup reserved memory-region\n");
110 ret = request_firmware(&mdt, fwname, dev);
114 fw_size = qcom_mdt_get_size(mdt);
120 *mem_phys = rmem->base;
121 *mem_size = rmem->size;
123 if (*mem_size < fw_size || fw_size > VENUS_FW_MEM_SIZE) {
128 mem_va = memremap(*mem_phys, *mem_size, MEMREMAP_WC);
130 dev_err(dev, "unable to map memory region %pa size %#zx\n", mem_phys, *mem_size);
136 ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID,
137 mem_va, *mem_phys, *mem_size, NULL);
139 ret = qcom_mdt_load_no_init(dev, mdt, fwname, VENUS_PAS_ID,
140 mem_va, *mem_phys, *mem_size, NULL);
144 release_firmware(mdt);
148 static int venus_boot_no_tz(struct venus_core *core, phys_addr_t mem_phys,
151 struct iommu_domain *iommu;
157 return -EPROBE_DEFER;
159 iommu = core->fw.iommu_domain;
160 core->fw.mapped_mem_size = mem_size;
162 ret = iommu_map(iommu, VENUS_FW_START_ADDR, mem_phys, mem_size,
163 IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL);
165 dev_err(dev, "could not map video firmware region\n");
169 venus_reset_cpu(core);
174 static int venus_shutdown_no_tz(struct venus_core *core)
176 const size_t mapped = core->fw.mapped_mem_size;
177 struct iommu_domain *iommu;
180 struct device *dev = core->fw.dev;
181 void __iomem *wrapper_base = core->wrapper_base;
182 void __iomem *wrapper_tz_base = core->wrapper_tz_base;
184 if (IS_IRIS2_1(core)) {
185 /* Assert the reset to XTSS */
186 reg = readl(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
187 reg |= WRAPPER_XTSS_SW_RESET_BIT;
188 writel(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
190 /* Assert the reset to ARM9 */
191 reg = readl(wrapper_base + WRAPPER_A9SS_SW_RESET);
192 reg |= WRAPPER_A9SS_SW_RESET_BIT;
193 writel(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);
196 iommu = core->fw.iommu_domain;
198 if (core->fw.mapped_mem_size && iommu) {
199 unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped);
201 if (unmapped != mapped)
202 dev_err(dev, "failed to unmap firmware\n");
204 core->fw.mapped_mem_size = 0;
210 int venus_boot(struct venus_core *core)
212 struct device *dev = core->dev;
213 const struct venus_resources *res = core->res;
214 const char *fwpath = NULL;
215 phys_addr_t mem_phys;
219 if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) ||
220 (core->use_tz && !qcom_scm_is_available()))
221 return -EPROBE_DEFER;
223 ret = of_property_read_string_index(dev->of_node, "firmware-name", 0,
226 fwpath = core->res->fwname;
228 ret = venus_load_fw(core, fwpath, &mem_phys, &mem_size);
230 dev_err(dev, "fail to load video firmware\n");
234 core->fw.mem_size = mem_size;
235 core->fw.mem_phys = mem_phys;
238 ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID);
240 ret = venus_boot_no_tz(core, mem_phys, mem_size);
245 if (core->use_tz && res->cp_size) {
247 * Clues for porting using downstream data:
249 * cp_size = venus_ns/virtual-addr-pool[0] - yes, address and not size!
250 * This works, as the non-secure context bank is placed
251 * contiguously right after the Content Protection region.
253 * cp_nonpixel_start = venus_sec_non_pixel/virtual-addr-pool[0]
254 * cp_nonpixel_size = venus_sec_non_pixel/virtual-addr-pool[1]
256 ret = qcom_scm_mem_protect_video_var(res->cp_start,
258 res->cp_nonpixel_start,
259 res->cp_nonpixel_size);
261 qcom_scm_pas_shutdown(VENUS_PAS_ID);
262 dev_err(dev, "set virtual address ranges fail (%d)\n",
271 int venus_shutdown(struct venus_core *core)
276 ret = qcom_scm_pas_shutdown(VENUS_PAS_ID);
278 ret = venus_shutdown_no_tz(core);
283 int venus_firmware_init(struct venus_core *core)
285 struct platform_device_info info;
286 struct iommu_domain *iommu_dom;
287 struct platform_device *pdev;
288 struct device_node *np;
291 np = of_get_child_by_name(core->dev->of_node, "video-firmware");
297 memset(&info, 0, sizeof(info));
298 info.fwnode = &np->fwnode;
299 info.parent = core->dev;
300 info.name = np->name;
301 info.dma_mask = DMA_BIT_MASK(32);
303 pdev = platform_device_register_full(&info);
306 return PTR_ERR(pdev);
309 pdev->dev.of_node = np;
311 ret = of_dma_configure(&pdev->dev, np, true);
313 dev_err(core->dev, "dma configure fail\n");
317 core->fw.dev = &pdev->dev;
319 iommu_dom = iommu_domain_alloc(&platform_bus_type);
321 dev_err(core->fw.dev, "Failed to allocate iommu domain\n");
326 ret = iommu_attach_device(iommu_dom, core->fw.dev);
328 dev_err(core->fw.dev, "could not attach device\n");
332 core->fw.iommu_domain = iommu_dom;
339 iommu_domain_free(iommu_dom);
341 platform_device_unregister(pdev);
346 void venus_firmware_deinit(struct venus_core *core)
348 struct iommu_domain *iommu;
353 iommu = core->fw.iommu_domain;
355 iommu_detach_device(iommu, core->fw.dev);
357 if (core->fw.iommu_domain) {
358 iommu_domain_free(iommu);
359 core->fw.iommu_domain = NULL;
362 platform_device_unregister(to_platform_device(core->fw.dev));