drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:Mark Yao <[email protected]>
   5  */
   6
   7 #ifndef _ROCKCHIP_DRM_VOP2_H
   8 #define _ROCKCHIP_DRM_VOP2_H
   9
  10 #include "rockchip_drm_vop.h"
  11
  12 #include <linux/regmap.h>
  13 #include <drm/drm_modes.h>
  14
  15 #define VOP_FEATURE_OUTPUT_10BIT        BIT(0)
  16
  17 #define WIN_FEATURE_AFBDC               BIT(0)
  18 #define WIN_FEATURE_CLUSTER             BIT(1)
  19
  20 /*
  21  *  the delay number of a window in different mode.
  22  */
  23 enum win_dly_mode {
  24         VOP2_DLY_MODE_DEFAULT,   /**< default mode */
  25         VOP2_DLY_MODE_HISO_S,    /** HDR in SDR out mode, as a SDR window */
  26         VOP2_DLY_MODE_HIHO_H,    /** HDR in HDR out mode, as a HDR window */
  27         VOP2_DLY_MODE_MAX,
  28 };
  29
  30 enum vop2_scale_up_mode {
  31         VOP2_SCALE_UP_NRST_NBOR,
  32         VOP2_SCALE_UP_BIL,
  33         VOP2_SCALE_UP_BIC,
  34 };
  35
  36 enum vop2_scale_down_mode {
  37         VOP2_SCALE_DOWN_NRST_NBOR,
  38         VOP2_SCALE_DOWN_BIL,
  39         VOP2_SCALE_DOWN_AVG,
  40 };
  41
  42 enum vop2_win_regs {
  43         VOP2_WIN_ENABLE,
  44         VOP2_WIN_FORMAT,
  45         VOP2_WIN_CSC_MODE,
  46         VOP2_WIN_XMIRROR,
  47         VOP2_WIN_YMIRROR,
  48         VOP2_WIN_RB_SWAP,
  49         VOP2_WIN_UV_SWAP,
  50         VOP2_WIN_ACT_INFO,
  51         VOP2_WIN_DSP_INFO,
  52         VOP2_WIN_DSP_ST,
  53         VOP2_WIN_YRGB_MST,
  54         VOP2_WIN_UV_MST,
  55         VOP2_WIN_YRGB_VIR,
  56         VOP2_WIN_UV_VIR,
  57         VOP2_WIN_YUV_CLIP,
  58         VOP2_WIN_Y2R_EN,
  59         VOP2_WIN_R2Y_EN,
  60         VOP2_WIN_COLOR_KEY,
  61         VOP2_WIN_COLOR_KEY_EN,
  62         VOP2_WIN_DITHER_UP,
  63
  64         /* scale regs */
  65         VOP2_WIN_SCALE_YRGB_X,
  66         VOP2_WIN_SCALE_YRGB_Y,
  67         VOP2_WIN_SCALE_CBCR_X,
  68         VOP2_WIN_SCALE_CBCR_Y,
  69         VOP2_WIN_YRGB_HOR_SCL_MODE,
  70         VOP2_WIN_YRGB_HSCL_FILTER_MODE,
  71         VOP2_WIN_YRGB_VER_SCL_MODE,
  72         VOP2_WIN_YRGB_VSCL_FILTER_MODE,
  73         VOP2_WIN_CBCR_VER_SCL_MODE,
  74         VOP2_WIN_CBCR_HSCL_FILTER_MODE,
  75         VOP2_WIN_CBCR_HOR_SCL_MODE,
  76         VOP2_WIN_CBCR_VSCL_FILTER_MODE,
  77         VOP2_WIN_VSD_CBCR_GT2,
  78         VOP2_WIN_VSD_CBCR_GT4,
  79         VOP2_WIN_VSD_YRGB_GT2,
  80         VOP2_WIN_VSD_YRGB_GT4,
  81         VOP2_WIN_BIC_COE_SEL,
  82
  83         /* cluster regs */
  84         VOP2_WIN_CLUSTER_ENABLE,
  85         VOP2_WIN_AFBC_ENABLE,
  86         VOP2_WIN_CLUSTER_LB_MODE,
  87
  88         /* afbc regs */
  89         VOP2_WIN_AFBC_FORMAT,
  90         VOP2_WIN_AFBC_RB_SWAP,
  91         VOP2_WIN_AFBC_UV_SWAP,
  92         VOP2_WIN_AFBC_AUTO_GATING_EN,
  93         VOP2_WIN_AFBC_BLOCK_SPLIT_EN,
  94         VOP2_WIN_AFBC_PIC_VIR_WIDTH,
  95         VOP2_WIN_AFBC_TILE_NUM,
  96         VOP2_WIN_AFBC_PIC_OFFSET,
  97         VOP2_WIN_AFBC_PIC_SIZE,
  98         VOP2_WIN_AFBC_DSP_OFFSET,
  99         VOP2_WIN_AFBC_TRANSFORM_OFFSET,
 100         VOP2_WIN_AFBC_HDR_PTR,
 101         VOP2_WIN_AFBC_HALF_BLOCK_EN,
 102         VOP2_WIN_AFBC_ROTATE_270,
 103         VOP2_WIN_AFBC_ROTATE_90,
 104         VOP2_WIN_MAX_REG,
 105 };
 106
 107 struct vop2_win_data {
 108         const char *name;
 109         unsigned int phys_id;
 110
 111         u32 base;
 112         enum drm_plane_type type;
 113
 114         u32 nformats;
 115         const u32 *formats;
 116         const uint64_t *format_modifiers;
 117         const unsigned int supported_rotations;
 118
 119         /**
 120          * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
 121          */
 122         unsigned int layer_sel_id;
 123         uint64_t feature;
 124
 125         unsigned int max_upscale_factor;
 126         unsigned int max_downscale_factor;
 127         const u8 dly[VOP2_DLY_MODE_MAX];
 128 };
 129
 130 struct vop2_video_port_data {
 131         unsigned int id;
 132         u32 feature;
 133         u16 gamma_lut_len;
 134         u16 cubic_lut_len;
 135         struct vop_rect max_output;
 136         const u8 pre_scan_max_dly[4];
 137         const struct vop2_video_port_regs *regs;
 138         unsigned int offset;
 139 };
 140
 141 struct vop2_data {
 142         u8 nr_vps;
 143         const struct vop2_ctrl *ctrl;
 144         const struct vop2_win_data *win;
 145         const struct vop2_video_port_data *vp;
 146         const struct vop_csc_table *csc_table;
 147         struct vop_rect max_input;
 148         struct vop_rect max_output;
 149
 150         unsigned int win_size;
 151         unsigned int soc_id;
 152 };
 153
 154 /* interrupt define */
 155 #define FS_NEW_INTR                     BIT(4)
 156 #define ADDR_SAME_INTR                  BIT(5)
 157 #define LINE_FLAG1_INTR                 BIT(6)
 158 #define WIN0_EMPTY_INTR                 BIT(7)
 159 #define WIN1_EMPTY_INTR                 BIT(8)
 160 #define WIN2_EMPTY_INTR                 BIT(9)
 161 #define WIN3_EMPTY_INTR                 BIT(10)
 162 #define HWC_EMPTY_INTR                  BIT(11)
 163 #define POST_BUF_EMPTY_INTR             BIT(12)
 164 #define PWM_GEN_INTR                    BIT(13)
 165 #define DMA_FINISH_INTR                 BIT(14)
 166 #define FS_FIELD_INTR                   BIT(15)
 167 #define FE_INTR                         BIT(16)
 168 #define WB_UV_FIFO_FULL_INTR            BIT(17)
 169 #define WB_YRGB_FIFO_FULL_INTR          BIT(18)
 170 #define WB_COMPLETE_INTR                BIT(19)
 171
 172 /*
 173  * display output interface supported by rockchip lcdc
 174  */
 175 #define ROCKCHIP_OUT_MODE_P888          0
 176 #define ROCKCHIP_OUT_MODE_BT1120        0
 177 #define ROCKCHIP_OUT_MODE_P666          1
 178 #define ROCKCHIP_OUT_MODE_P565          2
 179 #define ROCKCHIP_OUT_MODE_BT656         5
 180 #define ROCKCHIP_OUT_MODE_S888          8
 181 #define ROCKCHIP_OUT_MODE_S888_DUMMY    12
 182 #define ROCKCHIP_OUT_MODE_YUV420        14
 183 /* for use special outface */
 184 #define ROCKCHIP_OUT_MODE_AAAA          15
 185
 186 enum vop_csc_format {
 187         CSC_BT601L,
 188         CSC_BT709L,
 189         CSC_BT601F,
 190         CSC_BT2020,
 191 };
 192
 193 enum src_factor_mode {
 194         SRC_FAC_ALPHA_ZERO,
 195         SRC_FAC_ALPHA_ONE,
 196         SRC_FAC_ALPHA_DST,
 197         SRC_FAC_ALPHA_DST_INVERSE,
 198         SRC_FAC_ALPHA_SRC,
 199         SRC_FAC_ALPHA_SRC_GLOBAL,
 200 };
 201
 202 enum dst_factor_mode {
 203         DST_FAC_ALPHA_ZERO,
 204         DST_FAC_ALPHA_ONE,
 205         DST_FAC_ALPHA_SRC,
 206         DST_FAC_ALPHA_SRC_INVERSE,
 207         DST_FAC_ALPHA_DST,
 208         DST_FAC_ALPHA_DST_GLOBAL,
 209 };
 210
 211 #define RK3568_GRF_VO_CON1                      0x0364
 212 /* System registers definition */
 213 #define RK3568_REG_CFG_DONE                     0x000
 214 #define RK3568_VERSION_INFO                     0x004
 215 #define RK3568_SYS_AUTO_GATING_CTRL             0x008
 216 #define RK3568_SYS_AXI_LUT_CTRL                 0x024
 217 #define RK3568_DSP_IF_EN                        0x028
 218 #define RK3568_DSP_IF_CTRL                      0x02c
 219 #define RK3568_DSP_IF_POL                       0x030
 220 #define RK3568_WB_CTRL                          0x40
 221 #define RK3568_WB_XSCAL_FACTOR                  0x44
 222 #define RK3568_WB_YRGB_MST                      0x48
 223 #define RK3568_WB_CBR_MST                       0x4C
 224 #define RK3568_OTP_WIN_EN                       0x050
 225 #define RK3568_LUT_PORT_SEL                     0x058
 226 #define RK3568_SYS_STATUS0                      0x060
 227 #define RK3568_VP_LINE_FLAG(vp)                 (0x70 + (vp) * 0x4)
 228 #define RK3568_SYS0_INT_EN                      0x80
 229 #define RK3568_SYS0_INT_CLR                     0x84
 230 #define RK3568_SYS0_INT_STATUS                  0x88
 231 #define RK3568_SYS1_INT_EN                      0x90
 232 #define RK3568_SYS1_INT_CLR                     0x94
 233 #define RK3568_SYS1_INT_STATUS                  0x98
 234 #define RK3568_VP_INT_EN(vp)                    (0xA0 + (vp) * 0x10)
 235 #define RK3568_VP_INT_CLR(vp)                   (0xA4 + (vp) * 0x10)
 236 #define RK3568_VP_INT_STATUS(vp)                (0xA8 + (vp) * 0x10)
 237 #define RK3568_VP_INT_RAW_STATUS(vp)            (0xAC + (vp) * 0x10)
 238
 239 /* Video Port registers definition */
 240 #define RK3568_VP_DSP_CTRL                      0x00
 241 #define RK3568_VP_MIPI_CTRL                     0x04
 242 #define RK3568_VP_COLOR_BAR_CTRL                0x08
 243 #define RK3568_VP_3D_LUT_CTRL                   0x10
 244 #define RK3568_VP_3D_LUT_MST                    0x20
 245 #define RK3568_VP_DSP_BG                        0x2C
 246 #define RK3568_VP_PRE_SCAN_HTIMING              0x30
 247 #define RK3568_VP_POST_DSP_HACT_INFO            0x34
 248 #define RK3568_VP_POST_DSP_VACT_INFO            0x38
 249 #define RK3568_VP_POST_SCL_FACTOR_YRGB          0x3C
 250 #define RK3568_VP_POST_SCL_CTRL                 0x40
 251 #define RK3568_VP_POST_DSP_VACT_INFO_F1         0x44
 252 #define RK3568_VP_DSP_HTOTAL_HS_END             0x48
 253 #define RK3568_VP_DSP_HACT_ST_END               0x4C
 254 #define RK3568_VP_DSP_VTOTAL_VS_END             0x50
 255 #define RK3568_VP_DSP_VACT_ST_END               0x54
 256 #define RK3568_VP_DSP_VS_ST_END_F1              0x58
 257 #define RK3568_VP_DSP_VACT_ST_END_F1            0x5C
 258 #define RK3568_VP_BCSH_CTRL                     0x60
 259 #define RK3568_VP_BCSH_BCS                      0x64
 260 #define RK3568_VP_BCSH_H                        0x68
 261 #define RK3568_VP_BCSH_COLOR_BAR                0x6C
 262
 263 /* Overlay registers definition    */
 264 #define RK3568_OVL_CTRL                         0x600
 265 #define RK3568_OVL_LAYER_SEL                    0x604
 266 #define RK3568_OVL_PORT_SEL                     0x608
 267 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL      0x610
 268 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL      0x614
 269 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL      0x618
 270 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL      0x61C
 271 #define RK3568_MIX0_SRC_COLOR_CTRL              0x650
 272 #define RK3568_MIX0_DST_COLOR_CTRL              0x654
 273 #define RK3568_MIX0_SRC_ALPHA_CTRL              0x658
 274 #define RK3568_MIX0_DST_ALPHA_CTRL              0x65C
 275 #define RK3568_HDR0_SRC_COLOR_CTRL              0x6C0
 276 #define RK3568_HDR0_DST_COLOR_CTRL              0x6C4
 277 #define RK3568_HDR0_SRC_ALPHA_CTRL              0x6C8
 278 #define RK3568_HDR0_DST_ALPHA_CTRL              0x6CC
 279 #define RK3568_VP_BG_MIX_CTRL(vp)               (0x6E0 + (vp) * 4)
 280 #define RK3568_CLUSTER_DLY_NUM                  0x6F0
 281 #define RK3568_SMART_DLY_NUM                    0x6F8
 282
 283 /* Cluster register definition, offset relative to window base */
 284 #define RK3568_CLUSTER_WIN_CTRL0                0x00
 285 #define RK3568_CLUSTER_WIN_CTRL1                0x04
 286 #define RK3568_CLUSTER_WIN_YRGB_MST             0x10
 287 #define RK3568_CLUSTER_WIN_CBR_MST              0x14
 288 #define RK3568_CLUSTER_WIN_VIR                  0x18
 289 #define RK3568_CLUSTER_WIN_ACT_INFO             0x20
 290 #define RK3568_CLUSTER_WIN_DSP_INFO             0x24
 291 #define RK3568_CLUSTER_WIN_DSP_ST               0x28
 292 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB      0x30
 293 #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET       0x3C
 294 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL    0x50
 295 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE    0x54
 296 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR        0x58
 297 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH      0x5C
 298 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE       0x60
 299 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET     0x64
 300 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET     0x68
 301 #define RK3568_CLUSTER_WIN_AFBCD_CTRL           0x6C
 302
 303 #define RK3568_CLUSTER_CTRL                     0x100
 304
 305 /* (E)smart register definition, offset relative to window base */
 306 #define RK3568_SMART_CTRL0                      0x00
 307 #define RK3568_SMART_CTRL1                      0x04
 308 #define RK3568_SMART_REGION0_CTRL               0x10
 309 #define RK3568_SMART_REGION0_YRGB_MST           0x14
 310 #define RK3568_SMART_REGION0_CBR_MST            0x18
 311 #define RK3568_SMART_REGION0_VIR                0x1C
 312 #define RK3568_SMART_REGION0_ACT_INFO           0x20
 313 #define RK3568_SMART_REGION0_DSP_INFO           0x24
 314 #define RK3568_SMART_REGION0_DSP_ST             0x28
 315 #define RK3568_SMART_REGION0_SCL_CTRL           0x30
 316 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB    0x34
 317 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR     0x38
 318 #define RK3568_SMART_REGION0_SCL_OFFSET         0x3C
 319 #define RK3568_SMART_REGION1_CTRL               0x40
 320 #define RK3568_SMART_REGION1_YRGB_MST           0x44
 321 #define RK3568_SMART_REGION1_CBR_MST            0x48
 322 #define RK3568_SMART_REGION1_VIR                0x4C
 323 #define RK3568_SMART_REGION1_ACT_INFO           0x50
 324 #define RK3568_SMART_REGION1_DSP_INFO           0x54
 325 #define RK3568_SMART_REGION1_DSP_ST             0x58
 326 #define RK3568_SMART_REGION1_SCL_CTRL           0x60
 327 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB    0x64
 328 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR     0x68
 329 #define RK3568_SMART_REGION1_SCL_OFFSET         0x6C
 330 #define RK3568_SMART_REGION2_CTRL               0x70
 331 #define RK3568_SMART_REGION2_YRGB_MST           0x74
 332 #define RK3568_SMART_REGION2_CBR_MST            0x78
 333 #define RK3568_SMART_REGION2_VIR                0x7C
 334 #define RK3568_SMART_REGION2_ACT_INFO           0x80
 335 #define RK3568_SMART_REGION2_DSP_INFO           0x84
 336 #define RK3568_SMART_REGION2_DSP_ST             0x88
 337 #define RK3568_SMART_REGION2_SCL_CTRL           0x90
 338 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB    0x94
 339 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR     0x98
 340 #define RK3568_SMART_REGION2_SCL_OFFSET         0x9C
 341 #define RK3568_SMART_REGION3_CTRL               0xA0
 342 #define RK3568_SMART_REGION3_YRGB_MST           0xA4
 343 #define RK3568_SMART_REGION3_CBR_MST            0xA8
 344 #define RK3568_SMART_REGION3_VIR                0xAC
 345 #define RK3568_SMART_REGION3_ACT_INFO           0xB0
 346 #define RK3568_SMART_REGION3_DSP_INFO           0xB4
 347 #define RK3568_SMART_REGION3_DSP_ST             0xB8
 348 #define RK3568_SMART_REGION3_SCL_CTRL           0xC0
 349 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB    0xC4
 350 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR     0xC8
 351 #define RK3568_SMART_REGION3_SCL_OFFSET         0xCC
 352 #define RK3568_SMART_COLOR_KEY_CTRL             0xD0
 353
 354 /* HDR register definition */
 355 #define RK3568_HDR_LUT_CTRL                     0x2000
 356 #define RK3568_HDR_LUT_MST                      0x2004
 357 #define RK3568_SDR2HDR_CTRL                     0x2010
 358 #define RK3568_HDR2SDR_CTRL                     0x2020
 359 #define RK3568_HDR2SDR_SRC_RANGE                0x2024
 360 #define RK3568_HDR2SDR_NORMFACEETF              0x2028
 361 #define RK3568_HDR2SDR_DST_RANGE                0x202C
 362 #define RK3568_HDR2SDR_NORMFACCGAMMA            0x2030
 363 #define RK3568_HDR_EETF_OETF_Y0                 0x203C
 364 #define RK3568_HDR_SAT_Y0                       0x20C0
 365 #define RK3568_HDR_EOTF_OETF_Y0                 0x20F0
 366 #define RK3568_HDR_OETF_DX_POW1                 0x2200
 367 #define RK3568_HDR_OETF_XN1                     0x2300
 368
 369 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN            BIT(15)
 370
 371 #define RK3568_VP_DSP_CTRL__STANDBY                     BIT(31)
 372 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE            BIT(20)
 373 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL             GENMASK(19, 18)
 374 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN              BIT(17)
 375 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN          BIT(16)
 376 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y            BIT(15)
 377 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP                 BIT(9)
 378 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE               BIT(7)
 379 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL               BIT(6)
 380 #define RK3568_VP_DSP_CTRL__P2I_EN                      BIT(5)
 381 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV               BIT(4)
 382 #define RK3568_VP_DSP_CTRL__OUT_MODE                    GENMASK(3, 0)
 383
 384 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN             BIT(1)
 385 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN             BIT(0)
 386
 387 #define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX              GENMASK(26, 25)
 388 #define RK3568_SYS_DSP_INFACE_EN_LVDS1                  BIT(24)
 389 #define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX              GENMASK(22, 21)
 390 #define RK3568_SYS_DSP_INFACE_EN_MIPI1                  BIT(20)
 391 #define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX              GENMASK(19, 18)
 392 #define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX              GENMASK(17, 16)
 393 #define RK3568_SYS_DSP_INFACE_EN_EDP_MUX                GENMASK(15, 14)
 394 #define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX               GENMASK(11, 10)
 395 #define RK3568_SYS_DSP_INFACE_EN_RGB_MUX                GENMASK(9, 8)
 396 #define RK3568_SYS_DSP_INFACE_EN_LVDS0                  BIT(5)
 397 #define RK3568_SYS_DSP_INFACE_EN_MIPI0                  BIT(4)
 398 #define RK3568_SYS_DSP_INFACE_EN_EDP                    BIT(3)
 399 #define RK3568_SYS_DSP_INFACE_EN_HDMI                   BIT(1)
 400 #define RK3568_SYS_DSP_INFACE_EN_RGB                    BIT(0)
 401
 402 #define RK3568_DSP_IF_POL__MIPI_PIN_POL                 GENMASK(19, 16)
 403 #define RK3568_DSP_IF_POL__EDP_PIN_POL                  GENMASK(15, 12)
 404 #define RK3568_DSP_IF_POL__HDMI_PIN_POL                 GENMASK(7, 4)
 405 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL             GENMASK(3, 0)
 406
 407 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK      BIT(5)
 408 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2                 BIT(4)
 409
 410 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN     BIT(31)
 411
 412 #define RK3568_DSP_IF_POL__CFG_DONE_IMD                 BIT(28)
 413
 414 #define VOP2_SYS_AXI_BUS_NUM                            2
 415
 416 #define VOP2_CLUSTER_YUV444_10                          0x12
 417
 418 #define VOP2_COLOR_KEY_MASK                             BIT(31)
 419
 420 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD           BIT(28)
 421
 422 #define RK3568_VP_BG_MIX_CTRL__BG_DLY                   GENMASK(31, 24)
 423
 424 #define RK3568_OVL_PORT_SEL__SEL_PORT                   GENMASK(31, 16)
 425 #define RK3568_OVL_PORT_SEL__SMART1                     GENMASK(31, 30)
 426 #define RK3568_OVL_PORT_SEL__SMART0                     GENMASK(29, 28)
 427 #define RK3568_OVL_PORT_SEL__ESMART1                    GENMASK(27, 26)
 428 #define RK3568_OVL_PORT_SEL__ESMART0                    GENMASK(25, 24)
 429 #define RK3568_OVL_PORT_SEL__CLUSTER1                   GENMASK(19, 18)
 430 #define RK3568_OVL_PORT_SEL__CLUSTER0                   GENMASK(17, 16)
 431 #define RK3568_OVL_PORT_SET__PORT2_MUX                  GENMASK(11, 8)
 432 #define RK3568_OVL_PORT_SET__PORT1_MUX                  GENMASK(7, 4)
 433 #define RK3568_OVL_PORT_SET__PORT0_MUX                  GENMASK(3, 0)
 434 #define RK3568_OVL_LAYER_SEL__LAYER(layer, x)           ((x) << ((layer) * 4))
 435
 436 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1              GENMASK(31, 24)
 437 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0              GENMASK(23, 16)
 438 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1              GENMASK(15, 8)
 439 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0              GENMASK(7, 0)
 440
 441 #define RK3568_SMART_DLY_NUM__SMART1                    GENMASK(31, 24)
 442 #define RK3568_SMART_DLY_NUM__SMART0                    GENMASK(23, 16)
 443 #define RK3568_SMART_DLY_NUM__ESMART1                   GENMASK(15, 8)
 444 #define RK3568_SMART_DLY_NUM__ESMART0                   GENMASK(7, 0)
 445
 446 #define VP_INT_DSP_HOLD_VALID   BIT(6)
 447 #define VP_INT_FS_FIELD         BIT(5)
 448 #define VP_INT_POST_BUF_EMPTY   BIT(4)
 449 #define VP_INT_LINE_FLAG1       BIT(3)
 450 #define VP_INT_LINE_FLAG0       BIT(2)
 451 #define VOP2_INT_BUS_ERRPR      BIT(1)
 452 #define VP_INT_FS               BIT(0)
 453
 454 #define POLFLAG_DCLK_INV        BIT(3)
 455
 456 enum vop2_layer_phy_id {
 457         ROCKCHIP_VOP2_CLUSTER0 = 0,
 458         ROCKCHIP_VOP2_CLUSTER1,
 459         ROCKCHIP_VOP2_ESMART0,
 460         ROCKCHIP_VOP2_ESMART1,
 461         ROCKCHIP_VOP2_SMART0,
 462         ROCKCHIP_VOP2_SMART1,
 463         ROCKCHIP_VOP2_CLUSTER2,
 464         ROCKCHIP_VOP2_CLUSTER3,
 465         ROCKCHIP_VOP2_ESMART2,
 466         ROCKCHIP_VOP2_ESMART3,
 467         ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
 468 };
 469
 470 extern const struct component_ops vop2_component_ops;
 471
 472 #endif /* _ROCKCHIP_DRM_VOP2_H */