drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         if (HAS_LLC(dev_priv)) {
  62                 /*
  63                  * WaCompressedResourceDisplayNewHashMode:skl,kbl
  64                  * Display WA#0390: skl,kbl
  65                  *
  66                  * Must match Sampler, Pixel Back End, and Media. See
  67                  * WaCompressedResourceSamplerPbeMediaNewHashMode.
  68                  */
  69                 I915_WRITE(CHICKEN_PAR1_1,
  70                            I915_READ(CHICKEN_PAR1_1) |
  71                            SKL_DE_COMPRESSED_HASH_MODE);
  72         }
  73
  74         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  75         I915_WRITE(CHICKEN_PAR1_1,
  76                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  77
  78         I915_WRITE(GEN8_CONFIG0,
  79                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  80
  81         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  82         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  83                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  84
  85         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
  86         /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
  87         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  88                    DISP_FBC_WM_DIS |
  89                    DISP_FBC_MEMORY_WAKE);
  90
  91         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
  92         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  93                    ILK_DPFC_DISABLE_DUMMY0);
  94
  95         if (IS_SKYLAKE(dev_priv)) {
  96                 /* WaDisableDopClockGating */
  97                 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
  98                            & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  99         }
 100 }
 101
 102 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 103 {
 104         gen9_init_clock_gating(dev_priv);
 105
 106         /* WaDisableSDEUnitClockGating:bxt */
 107         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 108                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 109
 110         /*
 111          * FIXME:
 112          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 113          */
 114         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 115                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 116
 117         /*
 118          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 119          * to stay fully on.
 120          */
 121         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 122                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 123 }
 124
 125 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 126 {
 127         u32 val;
 128         gen9_init_clock_gating(dev_priv);
 129
 130         /*
 131          * WaDisablePWMClockGating:glk
 132          * Backlight PWM may stop in the asserted state, causing backlight
 133          * to stay fully on.
 134          */
 135         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 136                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 137
 138         /* WaDDIIOTimeout:glk */
 139         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
 140                 u32 val = I915_READ(CHICKEN_MISC_2);
 141                 val &= ~(GLK_CL0_PWR_DOWN |
 142                          GLK_CL1_PWR_DOWN |
 143                          GLK_CL2_PWR_DOWN);
 144                 I915_WRITE(CHICKEN_MISC_2, val);
 145         }
 146
 147         /* Display WA #1133: WaFbcSkipSegments:glk */
 148         val = I915_READ(ILK_DPFC_CHICKEN);
 149         val &= ~GLK_SKIP_SEG_COUNT_MASK;
 150         val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
 151         I915_WRITE(ILK_DPFC_CHICKEN, val);
 152 }
 153
 154 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 155 {
 156         u32 tmp;
 157
 158         tmp = I915_READ(CLKCFG);
 159
 160         switch (tmp & CLKCFG_FSB_MASK) {
 161         case CLKCFG_FSB_533:
 162                 dev_priv->fsb_freq = 533; /* 133*4 */
 163                 break;
 164         case CLKCFG_FSB_800:
 165                 dev_priv->fsb_freq = 800; /* 200*4 */
 166                 break;
 167         case CLKCFG_FSB_667:
 168                 dev_priv->fsb_freq =  667; /* 167*4 */
 169                 break;
 170         case CLKCFG_FSB_400:
 171                 dev_priv->fsb_freq = 400; /* 100*4 */
 172                 break;
 173         }
 174
 175         switch (tmp & CLKCFG_MEM_MASK) {
 176         case CLKCFG_MEM_533:
 177                 dev_priv->mem_freq = 533;
 178                 break;
 179         case CLKCFG_MEM_667:
 180                 dev_priv->mem_freq = 667;
 181                 break;
 182         case CLKCFG_MEM_800:
 183                 dev_priv->mem_freq = 800;
 184                 break;
 185         }
 186
 187         /* detect pineview DDR3 setting */
 188         tmp = I915_READ(CSHRDDR3CTL);
 189         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 190 }
 191
 192 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 193 {
 194         u16 ddrpll, csipll;
 195
 196         ddrpll = I915_READ16(DDRMPLL1);
 197         csipll = I915_READ16(CSIPLL0);
 198
 199         switch (ddrpll & 0xff) {
 200         case 0xc:
 201                 dev_priv->mem_freq = 800;
 202                 break;
 203         case 0x10:
 204                 dev_priv->mem_freq = 1066;
 205                 break;
 206         case 0x14:
 207                 dev_priv->mem_freq = 1333;
 208                 break;
 209         case 0x18:
 210                 dev_priv->mem_freq = 1600;
 211                 break;
 212         default:
 213                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 214                                  ddrpll & 0xff);
 215                 dev_priv->mem_freq = 0;
 216                 break;
 217         }
 218
 219         dev_priv->ips.r_t = dev_priv->mem_freq;
 220
 221         switch (csipll & 0x3ff) {
 222         case 0x00c:
 223                 dev_priv->fsb_freq = 3200;
 224                 break;
 225         case 0x00e:
 226                 dev_priv->fsb_freq = 3733;
 227                 break;
 228         case 0x010:
 229                 dev_priv->fsb_freq = 4266;
 230                 break;
 231         case 0x012:
 232                 dev_priv->fsb_freq = 4800;
 233                 break;
 234         case 0x014:
 235                 dev_priv->fsb_freq = 5333;
 236                 break;
 237         case 0x016:
 238                 dev_priv->fsb_freq = 5866;
 239                 break;
 240         case 0x018:
 241                 dev_priv->fsb_freq = 6400;
 242                 break;
 243         default:
 244                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 245                                  csipll & 0x3ff);
 246                 dev_priv->fsb_freq = 0;
 247                 break;
 248         }
 249
 250         if (dev_priv->fsb_freq == 3200) {
 251                 dev_priv->ips.c_m = 0;
 252         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 253                 dev_priv->ips.c_m = 1;
 254         } else {
 255                 dev_priv->ips.c_m = 2;
 256         }
 257 }
 258
 259 static const struct cxsr_latency cxsr_latency_table[] = {
 260         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 261         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 262         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 263         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 264         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 265
 266         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 267         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 268         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 269         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 270         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 271
 272         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 273         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 274         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 275         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 276         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 277
 278         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 279         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 280         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 281         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 282         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 283
 284         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 285         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 286         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 287         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 288         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 289
 290         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 291         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 292         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 293         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 294         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 295 };
 296
 297 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 298                                                          bool is_ddr3,
 299                                                          int fsb,
 300                                                          int mem)
 301 {
 302         const struct cxsr_latency *latency;
 303         int i;
 304
 305         if (fsb == 0 || mem == 0)
 306                 return NULL;
 307
 308         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 309                 latency = &cxsr_latency_table[i];
 310                 if (is_desktop == latency->is_desktop &&
 311                     is_ddr3 == latency->is_ddr3 &&
 312                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 313                         return latency;
 314         }
 315
 316         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 317
 318         return NULL;
 319 }
 320
 321 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 322 {
 323         u32 val;
 324
 325         mutex_lock(&dev_priv->pcu_lock);
 326
 327         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 328         if (enable)
 329                 val &= ~FORCE_DDR_HIGH_FREQ;
 330         else
 331                 val |= FORCE_DDR_HIGH_FREQ;
 332         val &= ~FORCE_DDR_LOW_FREQ;
 333         val |= FORCE_DDR_FREQ_REQ_ACK;
 334         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 335
 336         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 337                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 338                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 339
 340         mutex_unlock(&dev_priv->pcu_lock);
 341 }
 342
 343 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 344 {
 345         u32 val;
 346
 347         mutex_lock(&dev_priv->pcu_lock);
 348
 349         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 350         if (enable)
 351                 val |= DSP_MAXFIFO_PM5_ENABLE;
 352         else
 353                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 354         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 355
 356         mutex_unlock(&dev_priv->pcu_lock);
 357 }
 358
 359 #define FW_WM(value, plane) \
 360         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 361
 362 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 363 {
 364         bool was_enabled;
 365         u32 val;
 366
 367         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 368                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 369                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 370                 POSTING_READ(FW_BLC_SELF_VLV);
 371         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 372                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 373                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 374                 POSTING_READ(FW_BLC_SELF);
 375         } else if (IS_PINEVIEW(dev_priv)) {
 376                 val = I915_READ(DSPFW3);
 377                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 378                 if (enable)
 379                         val |= PINEVIEW_SELF_REFRESH_EN;
 380                 else
 381                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 382                 I915_WRITE(DSPFW3, val);
 383                 POSTING_READ(DSPFW3);
 384         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 385                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 386                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 387                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 388                 I915_WRITE(FW_BLC_SELF, val);
 389                 POSTING_READ(FW_BLC_SELF);
 390         } else if (IS_I915GM(dev_priv)) {
 391                 /*
 392                  * FIXME can't find a bit like this for 915G, and
 393                  * and yet it does have the related watermark in
 394                  * FW_BLC_SELF. What's going on?
 395                  */
 396                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 397                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 398                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 399                 I915_WRITE(INSTPM, val);
 400                 POSTING_READ(INSTPM);
 401         } else {
 402                 return false;
 403         }
 404
 405         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 406
 407         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 408                       enableddisabled(enable),
 409                       enableddisabled(was_enabled));
 410
 411         return was_enabled;
 412 }
 413
 414 /**
 415  * intel_set_memory_cxsr - Configure CxSR state
 416  * @dev_priv: i915 device
 417  * @enable: Allow vs. disallow CxSR
 418  *
 419  * Allow or disallow the system to enter a special CxSR
 420  * (C-state self refresh) state. What typically happens in CxSR mode
 421  * is that several display FIFOs may get combined into a single larger
 422  * FIFO for a particular plane (so called max FIFO mode) to allow the
 423  * system to defer memory fetches longer, and the memory will enter
 424  * self refresh.
 425  *
 426  * Note that enabling CxSR does not guarantee that the system enter
 427  * this special mode, nor does it guarantee that the system stays
 428  * in that mode once entered. So this just allows/disallows the system
 429  * to autonomously utilize the CxSR mode. Other factors such as core
 430  * C-states will affect when/if the system actually enters/exits the
 431  * CxSR mode.
 432  *
 433  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 434  * and the system is free to enter/exit memory self refresh at any time
 435  * even when the use of CxSR has been disallowed.
 436  *
 437  * While the system is actually in the CxSR/max FIFO mode, some plane
 438  * control registers will not get latched on vblank. Thus in order to
 439  * guarantee the system will respond to changes in the plane registers
 440  * we must always disallow CxSR prior to making changes to those registers.
 441  * Unfortunately the system will re-evaluate the CxSR conditions at
 442  * frame start which happens after vblank start (which is when the plane
 443  * registers would get latched), so we can't proceed with the plane update
 444  * during the same frame where we disallowed CxSR.
 445  *
 446  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 447  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 448  * the hardware w.r.t. HPLL SR when writing to plane registers.
 449  * Disallowing just CxSR is sufficient.
 450  */
 451 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 452 {
 453         bool ret;
 454
 455         mutex_lock(&dev_priv->wm.wm_mutex);
 456         ret = _intel_set_memory_cxsr(dev_priv, enable);
 457         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 458                 dev_priv->wm.vlv.cxsr = enable;
 459         else if (IS_G4X(dev_priv))
 460                 dev_priv->wm.g4x.cxsr = enable;
 461         mutex_unlock(&dev_priv->wm.wm_mutex);
 462
 463         return ret;
 464 }
 465
 466 /*
 467  * Latency for FIFO fetches is dependent on several factors:
 468  *   - memory configuration (speed, channels)
 469  *   - chipset
 470  *   - current MCH state
 471  * It can be fairly high in some situations, so here we assume a fairly
 472  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 473  * set this value too high, the FIFO will fetch frequently to stay full)
 474  * and power consumption (set it too low to save power and we might see
 475  * FIFO underruns and display "flicker").
 476  *
 477  * A value of 5us seems to be a good balance; safe for very low end
 478  * platforms but not overly aggressive on lower latency configs.
 479  */
 480 static const int pessimal_latency_ns = 5000;
 481
 482 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 483         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 484
 485 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 486 {
 487         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 488         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 489         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 490         enum pipe pipe = crtc->pipe;
 491         int sprite0_start, sprite1_start;
 492
 493         switch (pipe) {
 494                 uint32_t dsparb, dsparb2, dsparb3;
 495         case PIPE_A:
 496                 dsparb = I915_READ(DSPARB);
 497                 dsparb2 = I915_READ(DSPARB2);
 498                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 499                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 500                 break;
 501         case PIPE_B:
 502                 dsparb = I915_READ(DSPARB);
 503                 dsparb2 = I915_READ(DSPARB2);
 504                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 505                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 506                 break;
 507         case PIPE_C:
 508                 dsparb2 = I915_READ(DSPARB2);
 509                 dsparb3 = I915_READ(DSPARB3);
 510                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 511                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 512                 break;
 513         default:
 514                 MISSING_CASE(pipe);
 515                 return;
 516         }
 517
 518         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 519         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 520         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 521         fifo_state->plane[PLANE_CURSOR] = 63;
 522 }
 523
 524 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 525 {
 526         uint32_t dsparb = I915_READ(DSPARB);
 527         int size;
 528
 529         size = dsparb & 0x7f;
 530         if (plane)
 531                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 532
 533         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 534                       plane ? "B" : "A", size);
 535
 536         return size;
 537 }
 538
 539 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 540 {
 541         uint32_t dsparb = I915_READ(DSPARB);
 542         int size;
 543
 544         size = dsparb & 0x1ff;
 545         if (plane)
 546                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 547         size >>= 1; /* Convert to cachelines */
 548
 549         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 550                       plane ? "B" : "A", size);
 551
 552         return size;
 553 }
 554
 555 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 556 {
 557         uint32_t dsparb = I915_READ(DSPARB);
 558         int size;
 559
 560         size = dsparb & 0x7f;
 561         size >>= 2; /* Convert to cachelines */
 562
 563         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 564                       plane ? "B" : "A",
 565                       size);
 566
 567         return size;
 568 }
 569
 570 /* Pineview has different values for various configs */
 571 static const struct intel_watermark_params pineview_display_wm = {
 572         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 573         .max_wm = PINEVIEW_MAX_WM,
 574         .default_wm = PINEVIEW_DFT_WM,
 575         .guard_size = PINEVIEW_GUARD_WM,
 576         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 577 };
 578 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 579         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 580         .max_wm = PINEVIEW_MAX_WM,
 581         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 582         .guard_size = PINEVIEW_GUARD_WM,
 583         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 584 };
 585 static const struct intel_watermark_params pineview_cursor_wm = {
 586         .fifo_size = PINEVIEW_CURSOR_FIFO,
 587         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 588         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 589         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 590         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 591 };
 592 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 593         .fifo_size = PINEVIEW_CURSOR_FIFO,
 594         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 595         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 596         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 597         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 598 };
 599 static const struct intel_watermark_params i965_cursor_wm_info = {
 600         .fifo_size = I965_CURSOR_FIFO,
 601         .max_wm = I965_CURSOR_MAX_WM,
 602         .default_wm = I965_CURSOR_DFT_WM,
 603         .guard_size = 2,
 604         .cacheline_size = I915_FIFO_LINE_SIZE,
 605 };
 606 static const struct intel_watermark_params i945_wm_info = {
 607         .fifo_size = I945_FIFO_SIZE,
 608         .max_wm = I915_MAX_WM,
 609         .default_wm = 1,
 610         .guard_size = 2,
 611         .cacheline_size = I915_FIFO_LINE_SIZE,
 612 };
 613 static const struct intel_watermark_params i915_wm_info = {
 614         .fifo_size = I915_FIFO_SIZE,
 615         .max_wm = I915_MAX_WM,
 616         .default_wm = 1,
 617         .guard_size = 2,
 618         .cacheline_size = I915_FIFO_LINE_SIZE,
 619 };
 620 static const struct intel_watermark_params i830_a_wm_info = {
 621         .fifo_size = I855GM_FIFO_SIZE,
 622         .max_wm = I915_MAX_WM,
 623         .default_wm = 1,
 624         .guard_size = 2,
 625         .cacheline_size = I830_FIFO_LINE_SIZE,
 626 };
 627 static const struct intel_watermark_params i830_bc_wm_info = {
 628         .fifo_size = I855GM_FIFO_SIZE,
 629         .max_wm = I915_MAX_WM/2,
 630         .default_wm = 1,
 631         .guard_size = 2,
 632         .cacheline_size = I830_FIFO_LINE_SIZE,
 633 };
 634 static const struct intel_watermark_params i845_wm_info = {
 635         .fifo_size = I830_FIFO_SIZE,
 636         .max_wm = I915_MAX_WM,
 637         .default_wm = 1,
 638         .guard_size = 2,
 639         .cacheline_size = I830_FIFO_LINE_SIZE,
 640 };
 641
 642 /**
 643  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 644  * @pixel_rate: Pipe pixel rate in kHz
 645  * @cpp: Plane bytes per pixel
 646  * @latency: Memory wakeup latency in 0.1us units
 647  *
 648  * Compute the watermark using the method 1 or "small buffer"
 649  * formula. The caller may additonally add extra cachelines
 650  * to account for TLB misses and clock crossings.
 651  *
 652  * This method is concerned with the short term drain rate
 653  * of the FIFO, ie. it does not account for blanking periods
 654  * which would effectively reduce the average drain rate across
 655  * a longer period. The name "small" refers to the fact the
 656  * FIFO is relatively small compared to the amount of data
 657  * fetched.
 658  *
 659  * The FIFO level vs. time graph might look something like:
 660  *
 661  *   |\   |\
 662  *   | \  | \
 663  * __---__---__ (- plane active, _ blanking)
 664  * -> time
 665  *
 666  * or perhaps like this:
 667  *
 668  *   |\|\  |\|\
 669  * __----__----__ (- plane active, _ blanking)
 670  * -> time
 671  *
 672  * Returns:
 673  * The watermark in bytes
 674  */
 675 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 676                                      unsigned int cpp,
 677                                      unsigned int latency)
 678 {
 679         uint64_t ret;
 680
 681         ret = (uint64_t) pixel_rate * cpp * latency;
 682         ret = DIV_ROUND_UP_ULL(ret, 10000);
 683
 684         return ret;
 685 }
 686
 687 /**
 688  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 689  * @pixel_rate: Pipe pixel rate in kHz
 690  * @htotal: Pipe horizontal total
 691  * @width: Plane width in pixels
 692  * @cpp: Plane bytes per pixel
 693  * @latency: Memory wakeup latency in 0.1us units
 694  *
 695  * Compute the watermark using the method 2 or "large buffer"
 696  * formula. The caller may additonally add extra cachelines
 697  * to account for TLB misses and clock crossings.
 698  *
 699  * This method is concerned with the long term drain rate
 700  * of the FIFO, ie. it does account for blanking periods
 701  * which effectively reduce the average drain rate across
 702  * a longer period. The name "large" refers to the fact the
 703  * FIFO is relatively large compared to the amount of data
 704  * fetched.
 705  *
 706  * The FIFO level vs. time graph might look something like:
 707  *
 708  *    |\___       |\___
 709  *    |    \___   |    \___
 710  *    |        \  |        \
 711  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 712  * -> time
 713  *
 714  * Returns:
 715  * The watermark in bytes
 716  */
 717 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 718                                      unsigned int htotal,
 719                                      unsigned int width,
 720                                      unsigned int cpp,
 721                                      unsigned int latency)
 722 {
 723         unsigned int ret;
 724
 725         /*
 726          * FIXME remove once all users are computing
 727          * watermarks in the correct place.
 728          */
 729         if (WARN_ON_ONCE(htotal == 0))
 730                 htotal = 1;
 731
 732         ret = (latency * pixel_rate) / (htotal * 10000);
 733         ret = (ret + 1) * width * cpp;
 734
 735         return ret;
 736 }
 737
 738 /**
 739  * intel_calculate_wm - calculate watermark level
 740  * @pixel_rate: pixel clock
 741  * @wm: chip FIFO params
 742  * @cpp: bytes per pixel
 743  * @latency_ns: memory latency for the platform
 744  *
 745  * Calculate the watermark level (the level at which the display plane will
 746  * start fetching from memory again).  Each chip has a different display
 747  * FIFO size and allocation, so the caller needs to figure that out and pass
 748  * in the correct intel_watermark_params structure.
 749  *
 750  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 751  * on the pixel size.  When it reaches the watermark level, it'll start
 752  * fetching FIFO line sized based chunks from memory until the FIFO fills
 753  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 754  * will occur, and a display engine hang could result.
 755  */
 756 static unsigned int intel_calculate_wm(int pixel_rate,
 757                                        const struct intel_watermark_params *wm,
 758                                        int fifo_size, int cpp,
 759                                        unsigned int latency_ns)
 760 {
 761         int entries, wm_size;
 762
 763         /*
 764          * Note: we need to make sure we don't overflow for various clock &
 765          * latency values.
 766          * clocks go from a few thousand to several hundred thousand.
 767          * latency is usually a few thousand
 768          */
 769         entries = intel_wm_method1(pixel_rate, cpp,
 770                                    latency_ns / 100);
 771         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 772                 wm->guard_size;
 773         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 774
 775         wm_size = fifo_size - entries;
 776         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 777
 778         /* Don't promote wm_size to unsigned... */
 779         if (wm_size > wm->max_wm)
 780                 wm_size = wm->max_wm;
 781         if (wm_size <= 0)
 782                 wm_size = wm->default_wm;
 783
 784         /*
 785          * Bspec seems to indicate that the value shouldn't be lower than
 786          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 787          * Lets go for 8 which is the burst size since certain platforms
 788          * already use a hardcoded 8 (which is what the spec says should be
 789          * done).
 790          */
 791         if (wm_size <= 8)
 792                 wm_size = 8;
 793
 794         return wm_size;
 795 }
 796
 797 static bool is_disabling(int old, int new, int threshold)
 798 {
 799         return old >= threshold && new < threshold;
 800 }
 801
 802 static bool is_enabling(int old, int new, int threshold)
 803 {
 804         return old < threshold && new >= threshold;
 805 }
 806
 807 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 808 {
 809         return dev_priv->wm.max_level + 1;
 810 }
 811
 812 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 813                                    const struct intel_plane_state *plane_state)
 814 {
 815         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 816
 817         /* FIXME check the 'enable' instead */
 818         if (!crtc_state->base.active)
 819                 return false;
 820
 821         /*
 822          * Treat cursor with fb as always visible since cursor updates
 823          * can happen faster than the vrefresh rate, and the current
 824          * watermark code doesn't handle that correctly. Cursor updates
 825          * which set/clear the fb or change the cursor size are going
 826          * to get throttled by intel_legacy_cursor_update() to work
 827          * around this problem with the watermark code.
 828          */
 829         if (plane->id == PLANE_CURSOR)
 830                 return plane_state->base.fb != NULL;
 831         else
 832                 return plane_state->base.visible;
 833 }
 834
 835 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 836 {
 837         struct intel_crtc *crtc, *enabled = NULL;
 838
 839         for_each_intel_crtc(&dev_priv->drm, crtc) {
 840                 if (intel_crtc_active(crtc)) {
 841                         if (enabled)
 842                                 return NULL;
 843                         enabled = crtc;
 844                 }
 845         }
 846
 847         return enabled;
 848 }
 849
 850 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 851 {
 852         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 853         struct intel_crtc *crtc;
 854         const struct cxsr_latency *latency;
 855         u32 reg;
 856         unsigned int wm;
 857
 858         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 859                                          dev_priv->is_ddr3,
 860                                          dev_priv->fsb_freq,
 861                                          dev_priv->mem_freq);
 862         if (!latency) {
 863                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 864                 intel_set_memory_cxsr(dev_priv, false);
 865                 return;
 866         }
 867
 868         crtc = single_enabled_crtc(dev_priv);
 869         if (crtc) {
 870                 const struct drm_display_mode *adjusted_mode =
 871                         &crtc->config->base.adjusted_mode;
 872                 const struct drm_framebuffer *fb =
 873                         crtc->base.primary->state->fb;
 874                 int cpp = fb->format->cpp[0];
 875                 int clock = adjusted_mode->crtc_clock;
 876
 877                 /* Display SR */
 878                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 879                                         pineview_display_wm.fifo_size,
 880                                         cpp, latency->display_sr);
 881                 reg = I915_READ(DSPFW1);
 882                 reg &= ~DSPFW_SR_MASK;
 883                 reg |= FW_WM(wm, SR);
 884                 I915_WRITE(DSPFW1, reg);
 885                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 886
 887                 /* cursor SR */
 888                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 889                                         pineview_display_wm.fifo_size,
 890                                         4, latency->cursor_sr);
 891                 reg = I915_READ(DSPFW3);
 892                 reg &= ~DSPFW_CURSOR_SR_MASK;
 893                 reg |= FW_WM(wm, CURSOR_SR);
 894                 I915_WRITE(DSPFW3, reg);
 895
 896                 /* Display HPLL off SR */
 897                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 898                                         pineview_display_hplloff_wm.fifo_size,
 899                                         cpp, latency->display_hpll_disable);
 900                 reg = I915_READ(DSPFW3);
 901                 reg &= ~DSPFW_HPLL_SR_MASK;
 902                 reg |= FW_WM(wm, HPLL_SR);
 903                 I915_WRITE(DSPFW3, reg);
 904
 905                 /* cursor HPLL off SR */
 906                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 907                                         pineview_display_hplloff_wm.fifo_size,
 908                                         4, latency->cursor_hpll_disable);
 909                 reg = I915_READ(DSPFW3);
 910                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 911                 reg |= FW_WM(wm, HPLL_CURSOR);
 912                 I915_WRITE(DSPFW3, reg);
 913                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 914
 915                 intel_set_memory_cxsr(dev_priv, true);
 916         } else {
 917                 intel_set_memory_cxsr(dev_priv, false);
 918         }
 919 }
 920
 921 /*
 922  * Documentation says:
 923  * "If the line size is small, the TLB fetches can get in the way of the
 924  *  data fetches, causing some lag in the pixel data return which is not
 925  *  accounted for in the above formulas. The following adjustment only
 926  *  needs to be applied if eight whole lines fit in the buffer at once.
 927  *  The WM is adjusted upwards by the difference between the FIFO size
 928  *  and the size of 8 whole lines. This adjustment is always performed
 929  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 930  */
 931 static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 932 {
 933         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 934
 935         return max(0, tlb_miss);
 936 }
 937
 938 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 939                                 const struct g4x_wm_values *wm)
 940 {
 941         enum pipe pipe;
 942
 943         for_each_pipe(dev_priv, pipe)
 944                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 945
 946         I915_WRITE(DSPFW1,
 947                    FW_WM(wm->sr.plane, SR) |
 948                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 949                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 950                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 951         I915_WRITE(DSPFW2,
 952                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 953                    FW_WM(wm->sr.fbc, FBC_SR) |
 954                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 955                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 956                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 957                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 958         I915_WRITE(DSPFW3,
 959                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 960                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 961                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 962                    FW_WM(wm->hpll.plane, HPLL_SR));
 963
 964         POSTING_READ(DSPFW1);
 965 }
 966
 967 #define FW_WM_VLV(value, plane) \
 968         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 969
 970 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 971                                 const struct vlv_wm_values *wm)
 972 {
 973         enum pipe pipe;
 974
 975         for_each_pipe(dev_priv, pipe) {
 976                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 977
 978                 I915_WRITE(VLV_DDL(pipe),
 979                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 980                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 981                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 982                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 983         }
 984
 985         /*
 986          * Zero the (unused) WM1 watermarks, and also clear all the
 987          * high order bits so that there are no out of bounds values
 988          * present in the registers during the reprogramming.
 989          */
 990         I915_WRITE(DSPHOWM, 0);
 991         I915_WRITE(DSPHOWM1, 0);
 992         I915_WRITE(DSPFW4, 0);
 993         I915_WRITE(DSPFW5, 0);
 994         I915_WRITE(DSPFW6, 0);
 995
 996         I915_WRITE(DSPFW1,
 997                    FW_WM(wm->sr.plane, SR) |
 998                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 999                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1000                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1001         I915_WRITE(DSPFW2,
1002                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1003                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1004                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1005         I915_WRITE(DSPFW3,
1006                    FW_WM(wm->sr.cursor, CURSOR_SR));
1007
1008         if (IS_CHERRYVIEW(dev_priv)) {
1009                 I915_WRITE(DSPFW7_CHV,
1010                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1011                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1012                 I915_WRITE(DSPFW8_CHV,
1013                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1014                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1015                 I915_WRITE(DSPFW9_CHV,
1016                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1017                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1018                 I915_WRITE(DSPHOWM,
1019                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1020                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1021                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1022                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1023                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1024                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1025                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1026                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1027                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1028                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1029         } else {
1030                 I915_WRITE(DSPFW7,
1031                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1032                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1033                 I915_WRITE(DSPHOWM,
1034                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1035                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1036                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1037                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1038                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1039                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1040                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1041         }
1042
1043         POSTING_READ(DSPFW1);
1044 }
1045
1046 #undef FW_WM_VLV
1047
1048 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1049 {
1050         /* all latencies in usec */
1051         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1052         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1053         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1054
1055         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1056 }
1057
1058 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1059 {
1060         /*
1061          * DSPCNTR[13] supposedly controls whether the
1062          * primary plane can use the FIFO space otherwise
1063          * reserved for the sprite plane. It's not 100% clear
1064          * what the actual FIFO size is, but it looks like we
1065          * can happily set both primary and sprite watermarks
1066          * up to 127 cachelines. So that would seem to mean
1067          * that either DSPCNTR[13] doesn't do anything, or that
1068          * the total FIFO is >= 256 cachelines in size. Either
1069          * way, we don't seem to have to worry about this
1070          * repartitioning as the maximum watermark value the
1071          * register can hold for each plane is lower than the
1072          * minimum FIFO size.
1073          */
1074         switch (plane_id) {
1075         case PLANE_CURSOR:
1076                 return 63;
1077         case PLANE_PRIMARY:
1078                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1079         case PLANE_SPRITE0:
1080                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1081         default:
1082                 MISSING_CASE(plane_id);
1083                 return 0;
1084         }
1085 }
1086
1087 static int g4x_fbc_fifo_size(int level)
1088 {
1089         switch (level) {
1090         case G4X_WM_LEVEL_SR:
1091                 return 7;
1092         case G4X_WM_LEVEL_HPLL:
1093                 return 15;
1094         default:
1095                 MISSING_CASE(level);
1096                 return 0;
1097         }
1098 }
1099
1100 static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1101                                const struct intel_plane_state *plane_state,
1102                                int level)
1103 {
1104         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1105         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1106         const struct drm_display_mode *adjusted_mode =
1107                 &crtc_state->base.adjusted_mode;
1108         int clock, htotal, cpp, width, wm;
1109         int latency = dev_priv->wm.pri_latency[level] * 10;
1110
1111         if (latency == 0)
1112                 return USHRT_MAX;
1113
1114         if (!intel_wm_plane_visible(crtc_state, plane_state))
1115                 return 0;
1116
1117         /*
1118          * Not 100% sure which way ELK should go here as the
1119          * spec only says CL/CTG should assume 32bpp and BW
1120          * doesn't need to. But as these things followed the
1121          * mobile vs. desktop lines on gen3 as well, let's
1122          * assume ELK doesn't need this.
1123          *
1124          * The spec also fails to list such a restriction for
1125          * the HPLL watermark, which seems a little strange.
1126          * Let's use 32bpp for the HPLL watermark as well.
1127          */
1128         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1129             level != G4X_WM_LEVEL_NORMAL)
1130                 cpp = 4;
1131         else
1132                 cpp = plane_state->base.fb->format->cpp[0];
1133
1134         clock = adjusted_mode->crtc_clock;
1135         htotal = adjusted_mode->crtc_htotal;
1136
1137         if (plane->id == PLANE_CURSOR)
1138                 width = plane_state->base.crtc_w;
1139         else
1140                 width = drm_rect_width(&plane_state->base.dst);
1141
1142         if (plane->id == PLANE_CURSOR) {
1143                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1144         } else if (plane->id == PLANE_PRIMARY &&
1145                    level == G4X_WM_LEVEL_NORMAL) {
1146                 wm = intel_wm_method1(clock, cpp, latency);
1147         } else {
1148                 int small, large;
1149
1150                 small = intel_wm_method1(clock, cpp, latency);
1151                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1152
1153                 wm = min(small, large);
1154         }
1155
1156         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1157                               width, cpp);
1158
1159         wm = DIV_ROUND_UP(wm, 64) + 2;
1160
1161         return min_t(int, wm, USHRT_MAX);
1162 }
1163
1164 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1165                                  int level, enum plane_id plane_id, u16 value)
1166 {
1167         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1168         bool dirty = false;
1169
1170         for (; level < intel_wm_num_levels(dev_priv); level++) {
1171                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1172
1173                 dirty |= raw->plane[plane_id] != value;
1174                 raw->plane[plane_id] = value;
1175         }
1176
1177         return dirty;
1178 }
1179
1180 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1181                                int level, u16 value)
1182 {
1183         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1184         bool dirty = false;
1185
1186         /* NORMAL level doesn't have an FBC watermark */
1187         level = max(level, G4X_WM_LEVEL_SR);
1188
1189         for (; level < intel_wm_num_levels(dev_priv); level++) {
1190                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1191
1192                 dirty |= raw->fbc != value;
1193                 raw->fbc = value;
1194         }
1195
1196         return dirty;
1197 }
1198
1199 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1200                                    const struct intel_plane_state *pstate,
1201                                    uint32_t pri_val);
1202
1203 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1204                                      const struct intel_plane_state *plane_state)
1205 {
1206         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1207         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1208         enum plane_id plane_id = plane->id;
1209         bool dirty = false;
1210         int level;
1211
1212         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1213                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1214                 if (plane_id == PLANE_PRIMARY)
1215                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1216                 goto out;
1217         }
1218
1219         for (level = 0; level < num_levels; level++) {
1220                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1221                 int wm, max_wm;
1222
1223                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1224                 max_wm = g4x_plane_fifo_size(plane_id, level);
1225
1226                 if (wm > max_wm)
1227                         break;
1228
1229                 dirty |= raw->plane[plane_id] != wm;
1230                 raw->plane[plane_id] = wm;
1231
1232                 if (plane_id != PLANE_PRIMARY ||
1233                     level == G4X_WM_LEVEL_NORMAL)
1234                         continue;
1235
1236                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1237                                         raw->plane[plane_id]);
1238                 max_wm = g4x_fbc_fifo_size(level);
1239
1240                 /*
1241                  * FBC wm is not mandatory as we
1242                  * can always just disable its use.
1243                  */
1244                 if (wm > max_wm)
1245                         wm = USHRT_MAX;
1246
1247                 dirty |= raw->fbc != wm;
1248                 raw->fbc = wm;
1249         }
1250
1251         /* mark watermarks as invalid */
1252         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1253
1254         if (plane_id == PLANE_PRIMARY)
1255                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1256
1257  out:
1258         if (dirty) {
1259                 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1260                               plane->base.name,
1261                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1262                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1263                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1264
1265                 if (plane_id == PLANE_PRIMARY)
1266                         DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1267                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1268                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1269         }
1270
1271         return dirty;
1272 }
1273
1274 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1275                                       enum plane_id plane_id, int level)
1276 {
1277         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1278
1279         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1280 }
1281
1282 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1283                                      int level)
1284 {
1285         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1286
1287         if (level > dev_priv->wm.max_level)
1288                 return false;
1289
1290         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1291                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1292                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1293 }
1294
1295 /* mark all levels starting from 'level' as invalid */
1296 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1297                                struct g4x_wm_state *wm_state, int level)
1298 {
1299         if (level <= G4X_WM_LEVEL_NORMAL) {
1300                 enum plane_id plane_id;
1301
1302                 for_each_plane_id_on_crtc(crtc, plane_id)
1303                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1304         }
1305
1306         if (level <= G4X_WM_LEVEL_SR) {
1307                 wm_state->cxsr = false;
1308                 wm_state->sr.cursor = USHRT_MAX;
1309                 wm_state->sr.plane = USHRT_MAX;
1310                 wm_state->sr.fbc = USHRT_MAX;
1311         }
1312
1313         if (level <= G4X_WM_LEVEL_HPLL) {
1314                 wm_state->hpll_en = false;
1315                 wm_state->hpll.cursor = USHRT_MAX;
1316                 wm_state->hpll.plane = USHRT_MAX;
1317                 wm_state->hpll.fbc = USHRT_MAX;
1318         }
1319 }
1320
1321 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1322 {
1323         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1324         struct intel_atomic_state *state =
1325                 to_intel_atomic_state(crtc_state->base.state);
1326         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1327         int num_active_planes = hweight32(crtc_state->active_planes &
1328                                           ~BIT(PLANE_CURSOR));
1329         const struct g4x_pipe_wm *raw;
1330         const struct intel_plane_state *old_plane_state;
1331         const struct intel_plane_state *new_plane_state;
1332         struct intel_plane *plane;
1333         enum plane_id plane_id;
1334         int i, level;
1335         unsigned int dirty = 0;
1336
1337         for_each_oldnew_intel_plane_in_state(state, plane,
1338                                              old_plane_state,
1339                                              new_plane_state, i) {
1340                 if (new_plane_state->base.crtc != &crtc->base &&
1341                     old_plane_state->base.crtc != &crtc->base)
1342                         continue;
1343
1344                 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1345                         dirty |= BIT(plane->id);
1346         }
1347
1348         if (!dirty)
1349                 return 0;
1350
1351         level = G4X_WM_LEVEL_NORMAL;
1352         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1353                 goto out;
1354
1355         raw = &crtc_state->wm.g4x.raw[level];
1356         for_each_plane_id_on_crtc(crtc, plane_id)
1357                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1358
1359         level = G4X_WM_LEVEL_SR;
1360
1361         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1362                 goto out;
1363
1364         raw = &crtc_state->wm.g4x.raw[level];
1365         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1366         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1367         wm_state->sr.fbc = raw->fbc;
1368
1369         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1370
1371         level = G4X_WM_LEVEL_HPLL;
1372
1373         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1374                 goto out;
1375
1376         raw = &crtc_state->wm.g4x.raw[level];
1377         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1378         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1379         wm_state->hpll.fbc = raw->fbc;
1380
1381         wm_state->hpll_en = wm_state->cxsr;
1382
1383         level++;
1384
1385  out:
1386         if (level == G4X_WM_LEVEL_NORMAL)
1387                 return -EINVAL;
1388
1389         /* invalidate the higher levels */
1390         g4x_invalidate_wms(crtc, wm_state, level);
1391
1392         /*
1393          * Determine if the FBC watermark(s) can be used. IF
1394          * this isn't the case we prefer to disable the FBC
1395          ( watermark(s) rather than disable the SR/HPLL
1396          * level(s) entirely.
1397          */
1398         wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1399
1400         if (level >= G4X_WM_LEVEL_SR &&
1401             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1402                 wm_state->fbc_en = false;
1403         else if (level >= G4X_WM_LEVEL_HPLL &&
1404                  wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1405                 wm_state->fbc_en = false;
1406
1407         return 0;
1408 }
1409
1410 static int g4x_compute_intermediate_wm(struct drm_device *dev,
1411                                        struct intel_crtc *crtc,
1412                                        struct intel_crtc_state *crtc_state)
1413 {
1414         struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate;
1415         const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal;
1416         const struct g4x_wm_state *active = &crtc->wm.active.g4x;
1417         enum plane_id plane_id;
1418
1419         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1420                 !crtc_state->disable_cxsr;
1421         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1422                 !crtc_state->disable_cxsr;
1423         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1424
1425         for_each_plane_id_on_crtc(crtc, plane_id) {
1426                 intermediate->wm.plane[plane_id] =
1427                         max(optimal->wm.plane[plane_id],
1428                             active->wm.plane[plane_id]);
1429
1430                 WARN_ON(intermediate->wm.plane[plane_id] >
1431                         g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1432         }
1433
1434         intermediate->sr.plane = max(optimal->sr.plane,
1435                                      active->sr.plane);
1436         intermediate->sr.cursor = max(optimal->sr.cursor,
1437                                       active->sr.cursor);
1438         intermediate->sr.fbc = max(optimal->sr.fbc,
1439                                    active->sr.fbc);
1440
1441         intermediate->hpll.plane = max(optimal->hpll.plane,
1442                                        active->hpll.plane);
1443         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1444                                         active->hpll.cursor);
1445         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1446                                      active->hpll.fbc);
1447
1448         WARN_ON((intermediate->sr.plane >
1449                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1450                  intermediate->sr.cursor >
1451                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1452                 intermediate->cxsr);
1453         WARN_ON((intermediate->sr.plane >
1454                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1455                  intermediate->sr.cursor >
1456                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1457                 intermediate->hpll_en);
1458
1459         WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1460                 intermediate->fbc_en && intermediate->cxsr);
1461         WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1462                 intermediate->fbc_en && intermediate->hpll_en);
1463
1464         /*
1465          * If our intermediate WM are identical to the final WM, then we can
1466          * omit the post-vblank programming; only update if it's different.
1467          */
1468         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1469                 crtc_state->wm.need_postvbl_update = true;
1470
1471         return 0;
1472 }
1473
1474 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1475                          struct g4x_wm_values *wm)
1476 {
1477         struct intel_crtc *crtc;
1478         int num_active_crtcs = 0;
1479
1480         wm->cxsr = true;
1481         wm->hpll_en = true;
1482         wm->fbc_en = true;
1483
1484         for_each_intel_crtc(&dev_priv->drm, crtc) {
1485                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1486
1487                 if (!crtc->active)
1488                         continue;
1489
1490                 if (!wm_state->cxsr)
1491                         wm->cxsr = false;
1492                 if (!wm_state->hpll_en)
1493                         wm->hpll_en = false;
1494                 if (!wm_state->fbc_en)
1495                         wm->fbc_en = false;
1496
1497                 num_active_crtcs++;
1498         }
1499
1500         if (num_active_crtcs != 1) {
1501                 wm->cxsr = false;
1502                 wm->hpll_en = false;
1503                 wm->fbc_en = false;
1504         }
1505
1506         for_each_intel_crtc(&dev_priv->drm, crtc) {
1507                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1508                 enum pipe pipe = crtc->pipe;
1509
1510                 wm->pipe[pipe] = wm_state->wm;
1511                 if (crtc->active && wm->cxsr)
1512                         wm->sr = wm_state->sr;
1513                 if (crtc->active && wm->hpll_en)
1514                         wm->hpll = wm_state->hpll;
1515         }
1516 }
1517
1518 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1519 {
1520         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1521         struct g4x_wm_values new_wm = {};
1522
1523         g4x_merge_wm(dev_priv, &new_wm);
1524
1525         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1526                 return;
1527
1528         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1529                 _intel_set_memory_cxsr(dev_priv, false);
1530
1531         g4x_write_wm_values(dev_priv, &new_wm);
1532
1533         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1534                 _intel_set_memory_cxsr(dev_priv, true);
1535
1536         *old_wm = new_wm;
1537 }
1538
1539 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1540                                    struct intel_crtc_state *crtc_state)
1541 {
1542         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1543         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1544
1545         mutex_lock(&dev_priv->wm.wm_mutex);
1546         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1547         g4x_program_watermarks(dev_priv);
1548         mutex_unlock(&dev_priv->wm.wm_mutex);
1549 }
1550
1551 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1552                                     struct intel_crtc_state *crtc_state)
1553 {
1554         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1556
1557         if (!crtc_state->wm.need_postvbl_update)
1558                 return;
1559
1560         mutex_lock(&dev_priv->wm.wm_mutex);
1561         intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1562         g4x_program_watermarks(dev_priv);
1563         mutex_unlock(&dev_priv->wm.wm_mutex);
1564 }
1565
1566 /* latency must be in 0.1us units. */
1567 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1568                                    unsigned int htotal,
1569                                    unsigned int width,
1570                                    unsigned int cpp,
1571                                    unsigned int latency)
1572 {
1573         unsigned int ret;
1574
1575         ret = intel_wm_method2(pixel_rate, htotal,
1576                                width, cpp, latency);
1577         ret = DIV_ROUND_UP(ret, 64);
1578
1579         return ret;
1580 }
1581
1582 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1583 {
1584         /* all latencies in usec */
1585         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1586
1587         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1588
1589         if (IS_CHERRYVIEW(dev_priv)) {
1590                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1591                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1592
1593                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1594         }
1595 }
1596
1597 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1598                                      const struct intel_plane_state *plane_state,
1599                                      int level)
1600 {
1601         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1602         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1603         const struct drm_display_mode *adjusted_mode =
1604                 &crtc_state->base.adjusted_mode;
1605         int clock, htotal, cpp, width, wm;
1606
1607         if (dev_priv->wm.pri_latency[level] == 0)
1608                 return USHRT_MAX;
1609
1610         if (!intel_wm_plane_visible(crtc_state, plane_state))
1611                 return 0;
1612
1613         cpp = plane_state->base.fb->format->cpp[0];
1614         clock = adjusted_mode->crtc_clock;
1615         htotal = adjusted_mode->crtc_htotal;
1616         width = crtc_state->pipe_src_w;
1617
1618         if (plane->id == PLANE_CURSOR) {
1619                 /*
1620                  * FIXME the formula gives values that are
1621                  * too big for the cursor FIFO, and hence we
1622                  * would never be able to use cursors. For
1623                  * now just hardcode the watermark.
1624                  */
1625                 wm = 63;
1626         } else {
1627                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1628                                     dev_priv->wm.pri_latency[level] * 10);
1629         }
1630
1631         return min_t(int, wm, USHRT_MAX);
1632 }
1633
1634 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1635 {
1636         return (active_planes & (BIT(PLANE_SPRITE0) |
1637                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1638 }
1639
1640 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1641 {
1642         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1643         const struct g4x_pipe_wm *raw =
1644                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1645         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1646         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1647         int num_active_planes = hweight32(active_planes);
1648         const int fifo_size = 511;
1649         int fifo_extra, fifo_left = fifo_size;
1650         int sprite0_fifo_extra = 0;
1651         unsigned int total_rate;
1652         enum plane_id plane_id;
1653
1654         /*
1655          * When enabling sprite0 after sprite1 has already been enabled
1656          * we tend to get an underrun unless sprite0 already has some
1657          * FIFO space allcoated. Hence we always allocate at least one
1658          * cacheline for sprite0 whenever sprite1 is enabled.
1659          *
1660          * All other plane enable sequences appear immune to this problem.
1661          */
1662         if (vlv_need_sprite0_fifo_workaround(active_planes))
1663                 sprite0_fifo_extra = 1;
1664
1665         total_rate = raw->plane[PLANE_PRIMARY] +
1666                 raw->plane[PLANE_SPRITE0] +
1667                 raw->plane[PLANE_SPRITE1] +
1668                 sprite0_fifo_extra;
1669
1670         if (total_rate > fifo_size)
1671                 return -EINVAL;
1672
1673         if (total_rate == 0)
1674                 total_rate = 1;
1675
1676         for_each_plane_id_on_crtc(crtc, plane_id) {
1677                 unsigned int rate;
1678
1679                 if ((active_planes & BIT(plane_id)) == 0) {
1680                         fifo_state->plane[plane_id] = 0;
1681                         continue;
1682                 }
1683
1684                 rate = raw->plane[plane_id];
1685                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1686                 fifo_left -= fifo_state->plane[plane_id];
1687         }
1688
1689         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1690         fifo_left -= sprite0_fifo_extra;
1691
1692         fifo_state->plane[PLANE_CURSOR] = 63;
1693
1694         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1695
1696         /* spread the remainder evenly */
1697         for_each_plane_id_on_crtc(crtc, plane_id) {
1698                 int plane_extra;
1699
1700                 if (fifo_left == 0)
1701                         break;
1702
1703                 if ((active_planes & BIT(plane_id)) == 0)
1704                         continue;
1705
1706                 plane_extra = min(fifo_extra, fifo_left);
1707                 fifo_state->plane[plane_id] += plane_extra;
1708                 fifo_left -= plane_extra;
1709         }
1710
1711         WARN_ON(active_planes != 0 && fifo_left != 0);
1712
1713         /* give it all to the first plane if none are active */
1714         if (active_planes == 0) {
1715                 WARN_ON(fifo_left != fifo_size);
1716                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1717         }
1718
1719         return 0;
1720 }
1721
1722 /* mark all levels starting from 'level' as invalid */
1723 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1724                                struct vlv_wm_state *wm_state, int level)
1725 {
1726         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1727
1728         for (; level < intel_wm_num_levels(dev_priv); level++) {
1729                 enum plane_id plane_id;
1730
1731                 for_each_plane_id_on_crtc(crtc, plane_id)
1732                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1733
1734                 wm_state->sr[level].cursor = USHRT_MAX;
1735                 wm_state->sr[level].plane = USHRT_MAX;
1736         }
1737 }
1738
1739 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1740 {
1741         if (wm > fifo_size)
1742                 return USHRT_MAX;
1743         else
1744                 return fifo_size - wm;
1745 }
1746
1747 /*
1748  * Starting from 'level' set all higher
1749  * levels to 'value' in the "raw" watermarks.
1750  */
1751 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1752                                  int level, enum plane_id plane_id, u16 value)
1753 {
1754         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1755         int num_levels = intel_wm_num_levels(dev_priv);
1756         bool dirty = false;
1757
1758         for (; level < num_levels; level++) {
1759                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1760
1761                 dirty |= raw->plane[plane_id] != value;
1762                 raw->plane[plane_id] = value;
1763         }
1764
1765         return dirty;
1766 }
1767
1768 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1769                                      const struct intel_plane_state *plane_state)
1770 {
1771         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1772         enum plane_id plane_id = plane->id;
1773         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1774         int level;
1775         bool dirty = false;
1776
1777         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1778                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1779                 goto out;
1780         }
1781
1782         for (level = 0; level < num_levels; level++) {
1783                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1784                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1785                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1786
1787                 if (wm > max_wm)
1788                         break;
1789
1790                 dirty |= raw->plane[plane_id] != wm;
1791                 raw->plane[plane_id] = wm;
1792         }
1793
1794         /* mark all higher levels as invalid */
1795         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1796
1797 out:
1798         if (dirty)
1799                 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1800                               plane->base.name,
1801                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1802                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1803                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1804
1805         return dirty;
1806 }
1807
1808 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1809                                       enum plane_id plane_id, int level)
1810 {
1811         const struct g4x_pipe_wm *raw =
1812                 &crtc_state->wm.vlv.raw[level];
1813         const struct vlv_fifo_state *fifo_state =
1814                 &crtc_state->wm.vlv.fifo_state;
1815
1816         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1817 }
1818
1819 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1820 {
1821         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1822                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1823                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1824                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1825 }
1826
1827 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1828 {
1829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1830         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1831         struct intel_atomic_state *state =
1832                 to_intel_atomic_state(crtc_state->base.state);
1833         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1834         const struct vlv_fifo_state *fifo_state =
1835                 &crtc_state->wm.vlv.fifo_state;
1836         int num_active_planes = hweight32(crtc_state->active_planes &
1837                                           ~BIT(PLANE_CURSOR));
1838         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1839         const struct intel_plane_state *old_plane_state;
1840         const struct intel_plane_state *new_plane_state;
1841         struct intel_plane *plane;
1842         enum plane_id plane_id;
1843         int level, ret, i;
1844         unsigned int dirty = 0;
1845
1846         for_each_oldnew_intel_plane_in_state(state, plane,
1847                                              old_plane_state,
1848                                              new_plane_state, i) {
1849                 if (new_plane_state->base.crtc != &crtc->base &&
1850                     old_plane_state->base.crtc != &crtc->base)
1851                         continue;
1852
1853                 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1854                         dirty |= BIT(plane->id);
1855         }
1856
1857         /*
1858          * DSPARB registers may have been reset due to the
1859          * power well being turned off. Make sure we restore
1860          * them to a consistent state even if no primary/sprite
1861          * planes are initially active.
1862          */
1863         if (needs_modeset)
1864                 crtc_state->fifo_changed = true;
1865
1866         if (!dirty)
1867                 return 0;
1868
1869         /* cursor changes don't warrant a FIFO recompute */
1870         if (dirty & ~BIT(PLANE_CURSOR)) {
1871                 const struct intel_crtc_state *old_crtc_state =
1872                         intel_atomic_get_old_crtc_state(state, crtc);
1873                 const struct vlv_fifo_state *old_fifo_state =
1874                         &old_crtc_state->wm.vlv.fifo_state;
1875
1876                 ret = vlv_compute_fifo(crtc_state);
1877                 if (ret)
1878                         return ret;
1879
1880                 if (needs_modeset ||
1881                     memcmp(old_fifo_state, fifo_state,
1882                            sizeof(*fifo_state)) != 0)
1883                         crtc_state->fifo_changed = true;
1884         }
1885
1886         /* initially allow all levels */
1887         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1888         /*
1889          * Note that enabling cxsr with no primary/sprite planes
1890          * enabled can wedge the pipe. Hence we only allow cxsr
1891          * with exactly one enabled primary/sprite plane.
1892          */
1893         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1894
1895         for (level = 0; level < wm_state->num_levels; level++) {
1896                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1897                 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1898
1899                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1900                         break;
1901
1902                 for_each_plane_id_on_crtc(crtc, plane_id) {
1903                         wm_state->wm[level].plane[plane_id] =
1904                                 vlv_invert_wm_value(raw->plane[plane_id],
1905                                                     fifo_state->plane[plane_id]);
1906                 }
1907
1908                 wm_state->sr[level].plane =
1909                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1910                                                  raw->plane[PLANE_SPRITE0],
1911                                                  raw->plane[PLANE_SPRITE1]),
1912                                             sr_fifo_size);
1913
1914                 wm_state->sr[level].cursor =
1915                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1916                                             63);
1917         }
1918
1919         if (level == 0)
1920                 return -EINVAL;
1921
1922         /* limit to only levels we can actually handle */
1923         wm_state->num_levels = level;
1924
1925         /* invalidate the higher levels */
1926         vlv_invalidate_wms(crtc, wm_state, level);
1927
1928         return 0;
1929 }
1930
1931 #define VLV_FIFO(plane, value) \
1932         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1933
1934 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1935                                    struct intel_crtc_state *crtc_state)
1936 {
1937         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1938         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1939         const struct vlv_fifo_state *fifo_state =
1940                 &crtc_state->wm.vlv.fifo_state;
1941         int sprite0_start, sprite1_start, fifo_size;
1942
1943         if (!crtc_state->fifo_changed)
1944                 return;
1945
1946         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1947         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1948         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1949
1950         WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1951         WARN_ON(fifo_size != 511);
1952
1953         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1954
1955         /*
1956          * uncore.lock serves a double purpose here. It allows us to
1957          * use the less expensive I915_{READ,WRITE}_FW() functions, and
1958          * it protects the DSPARB registers from getting clobbered by
1959          * parallel updates from multiple pipes.
1960          *
1961          * intel_pipe_update_start() has already disabled interrupts
1962          * for us, so a plain spin_lock() is sufficient here.
1963          */
1964         spin_lock(&dev_priv->uncore.lock);
1965
1966         switch (crtc->pipe) {
1967                 uint32_t dsparb, dsparb2, dsparb3;
1968         case PIPE_A:
1969                 dsparb = I915_READ_FW(DSPARB);
1970                 dsparb2 = I915_READ_FW(DSPARB2);
1971
1972                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1973                             VLV_FIFO(SPRITEB, 0xff));
1974                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1975                            VLV_FIFO(SPRITEB, sprite1_start));
1976
1977                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1978                              VLV_FIFO(SPRITEB_HI, 0x1));
1979                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1980                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1981
1982                 I915_WRITE_FW(DSPARB, dsparb);
1983                 I915_WRITE_FW(DSPARB2, dsparb2);
1984                 break;
1985         case PIPE_B:
1986                 dsparb = I915_READ_FW(DSPARB);
1987                 dsparb2 = I915_READ_FW(DSPARB2);
1988
1989                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1990                             VLV_FIFO(SPRITED, 0xff));
1991                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1992                            VLV_FIFO(SPRITED, sprite1_start));
1993
1994                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1995                              VLV_FIFO(SPRITED_HI, 0xff));
1996                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1997                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1998
1999                 I915_WRITE_FW(DSPARB, dsparb);
2000                 I915_WRITE_FW(DSPARB2, dsparb2);
2001                 break;
2002         case PIPE_C:
2003                 dsparb3 = I915_READ_FW(DSPARB3);
2004                 dsparb2 = I915_READ_FW(DSPARB2);
2005
2006                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2007                              VLV_FIFO(SPRITEF, 0xff));
2008                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2009                             VLV_FIFO(SPRITEF, sprite1_start));
2010
2011                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2012                              VLV_FIFO(SPRITEF_HI, 0xff));
2013                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2014                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2015
2016                 I915_WRITE_FW(DSPARB3, dsparb3);
2017                 I915_WRITE_FW(DSPARB2, dsparb2);
2018                 break;
2019         default:
2020                 break;
2021         }
2022
2023         POSTING_READ_FW(DSPARB);
2024
2025         spin_unlock(&dev_priv->uncore.lock);
2026 }
2027
2028 #undef VLV_FIFO
2029
2030 static int vlv_compute_intermediate_wm(struct drm_device *dev,
2031                                        struct intel_crtc *crtc,
2032                                        struct intel_crtc_state *crtc_state)
2033 {
2034         struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate;
2035         const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal;
2036         const struct vlv_wm_state *active = &crtc->wm.active.vlv;
2037         int level;
2038
2039         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2040         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2041                 !crtc_state->disable_cxsr;
2042
2043         for (level = 0; level < intermediate->num_levels; level++) {
2044                 enum plane_id plane_id;
2045
2046                 for_each_plane_id_on_crtc(crtc, plane_id) {
2047                         intermediate->wm[level].plane[plane_id] =
2048                                 min(optimal->wm[level].plane[plane_id],
2049                                     active->wm[level].plane[plane_id]);
2050                 }
2051
2052                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2053                                                     active->sr[level].plane);
2054                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2055                                                      active->sr[level].cursor);
2056         }
2057
2058         vlv_invalidate_wms(crtc, intermediate, level);
2059
2060         /*
2061          * If our intermediate WM are identical to the final WM, then we can
2062          * omit the post-vblank programming; only update if it's different.
2063          */
2064         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2065                 crtc_state->wm.need_postvbl_update = true;
2066
2067         return 0;
2068 }
2069
2070 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2071                          struct vlv_wm_values *wm)
2072 {
2073         struct intel_crtc *crtc;
2074         int num_active_crtcs = 0;
2075
2076         wm->level = dev_priv->wm.max_level;
2077         wm->cxsr = true;
2078
2079         for_each_intel_crtc(&dev_priv->drm, crtc) {
2080                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2081
2082                 if (!crtc->active)
2083                         continue;
2084
2085                 if (!wm_state->cxsr)
2086                         wm->cxsr = false;
2087
2088                 num_active_crtcs++;
2089                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2090         }
2091
2092         if (num_active_crtcs != 1)
2093                 wm->cxsr = false;
2094
2095         if (num_active_crtcs > 1)
2096                 wm->level = VLV_WM_LEVEL_PM2;
2097
2098         for_each_intel_crtc(&dev_priv->drm, crtc) {
2099                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2100                 enum pipe pipe = crtc->pipe;
2101
2102                 wm->pipe[pipe] = wm_state->wm[wm->level];
2103                 if (crtc->active && wm->cxsr)
2104                         wm->sr = wm_state->sr[wm->level];
2105
2106                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2107                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2108                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2109                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2110         }
2111 }
2112
2113 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2114 {
2115         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2116         struct vlv_wm_values new_wm = {};
2117
2118         vlv_merge_wm(dev_priv, &new_wm);
2119
2120         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2121                 return;
2122
2123         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2124                 chv_set_memory_dvfs(dev_priv, false);
2125
2126         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2127                 chv_set_memory_pm5(dev_priv, false);
2128
2129         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2130                 _intel_set_memory_cxsr(dev_priv, false);
2131
2132         vlv_write_wm_values(dev_priv, &new_wm);
2133
2134         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2135                 _intel_set_memory_cxsr(dev_priv, true);
2136
2137         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2138                 chv_set_memory_pm5(dev_priv, true);
2139
2140         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2141                 chv_set_memory_dvfs(dev_priv, true);
2142
2143         *old_wm = new_wm;
2144 }
2145
2146 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2147                                    struct intel_crtc_state *crtc_state)
2148 {
2149         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2150         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2151
2152         mutex_lock(&dev_priv->wm.wm_mutex);
2153         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2154         vlv_program_watermarks(dev_priv);
2155         mutex_unlock(&dev_priv->wm.wm_mutex);
2156 }
2157
2158 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2159                                     struct intel_crtc_state *crtc_state)
2160 {
2161         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2163
2164         if (!crtc_state->wm.need_postvbl_update)
2165                 return;
2166
2167         mutex_lock(&dev_priv->wm.wm_mutex);
2168         intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2169         vlv_program_watermarks(dev_priv);
2170         mutex_unlock(&dev_priv->wm.wm_mutex);
2171 }
2172
2173 static void i965_update_wm(struct intel_crtc *unused_crtc)
2174 {
2175         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2176         struct intel_crtc *crtc;
2177         int srwm = 1;
2178         int cursor_sr = 16;
2179         bool cxsr_enabled;
2180
2181         /* Calc sr entries for one plane configs */
2182         crtc = single_enabled_crtc(dev_priv);
2183         if (crtc) {
2184                 /* self-refresh has much higher latency */
2185                 static const int sr_latency_ns = 12000;
2186                 const struct drm_display_mode *adjusted_mode =
2187                         &crtc->config->base.adjusted_mode;
2188                 const struct drm_framebuffer *fb =
2189                         crtc->base.primary->state->fb;
2190                 int clock = adjusted_mode->crtc_clock;
2191                 int htotal = adjusted_mode->crtc_htotal;
2192                 int hdisplay = crtc->config->pipe_src_w;
2193                 int cpp = fb->format->cpp[0];
2194                 int entries;
2195
2196                 entries = intel_wm_method2(clock, htotal,
2197                                            hdisplay, cpp, sr_latency_ns / 100);
2198                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2199                 srwm = I965_FIFO_SIZE - entries;
2200                 if (srwm < 0)
2201                         srwm = 1;
2202                 srwm &= 0x1ff;
2203                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2204                               entries, srwm);
2205
2206                 entries = intel_wm_method2(clock, htotal,
2207                                            crtc->base.cursor->state->crtc_w, 4,
2208                                            sr_latency_ns / 100);
2209                 entries = DIV_ROUND_UP(entries,
2210                                        i965_cursor_wm_info.cacheline_size) +
2211                         i965_cursor_wm_info.guard_size;
2212
2213                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2214                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2215                         cursor_sr = i965_cursor_wm_info.max_wm;
2216
2217                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2218                               "cursor %d\n", srwm, cursor_sr);
2219
2220                 cxsr_enabled = true;
2221         } else {
2222                 cxsr_enabled = false;
2223                 /* Turn off self refresh if both pipes are enabled */
2224                 intel_set_memory_cxsr(dev_priv, false);
2225         }
2226
2227         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2228                       srwm);
2229
2230         /* 965 has limitations... */
2231         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2232                    FW_WM(8, CURSORB) |
2233                    FW_WM(8, PLANEB) |
2234                    FW_WM(8, PLANEA));
2235         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2236                    FW_WM(8, PLANEC_OLD));
2237         /* update cursor SR watermark */
2238         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2239
2240         if (cxsr_enabled)
2241                 intel_set_memory_cxsr(dev_priv, true);
2242 }
2243
2244 #undef FW_WM
2245
2246 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2247 {
2248         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2249         const struct intel_watermark_params *wm_info;
2250         uint32_t fwater_lo;
2251         uint32_t fwater_hi;
2252         int cwm, srwm = 1;
2253         int fifo_size;
2254         int planea_wm, planeb_wm;
2255         struct intel_crtc *crtc, *enabled = NULL;
2256
2257         if (IS_I945GM(dev_priv))
2258                 wm_info = &i945_wm_info;
2259         else if (!IS_GEN2(dev_priv))
2260                 wm_info = &i915_wm_info;
2261         else
2262                 wm_info = &i830_a_wm_info;
2263
2264         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
2265         crtc = intel_get_crtc_for_plane(dev_priv, 0);
2266         if (intel_crtc_active(crtc)) {
2267                 const struct drm_display_mode *adjusted_mode =
2268                         &crtc->config->base.adjusted_mode;
2269                 const struct drm_framebuffer *fb =
2270                         crtc->base.primary->state->fb;
2271                 int cpp;
2272
2273                 if (IS_GEN2(dev_priv))
2274                         cpp = 4;
2275                 else
2276                         cpp = fb->format->cpp[0];
2277
2278                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2279                                                wm_info, fifo_size, cpp,
2280                                                pessimal_latency_ns);
2281                 enabled = crtc;
2282         } else {
2283                 planea_wm = fifo_size - wm_info->guard_size;
2284                 if (planea_wm > (long)wm_info->max_wm)
2285                         planea_wm = wm_info->max_wm;
2286         }
2287
2288         if (IS_GEN2(dev_priv))
2289                 wm_info = &i830_bc_wm_info;
2290
2291         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
2292         crtc = intel_get_crtc_for_plane(dev_priv, 1);
2293         if (intel_crtc_active(crtc)) {
2294                 const struct drm_display_mode *adjusted_mode =
2295                         &crtc->config->base.adjusted_mode;
2296                 const struct drm_framebuffer *fb =
2297                         crtc->base.primary->state->fb;
2298                 int cpp;
2299
2300                 if (IS_GEN2(dev_priv))
2301                         cpp = 4;
2302                 else
2303                         cpp = fb->format->cpp[0];
2304
2305                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2306                                                wm_info, fifo_size, cpp,
2307                                                pessimal_latency_ns);
2308                 if (enabled == NULL)
2309                         enabled = crtc;
2310                 else
2311                         enabled = NULL;
2312         } else {
2313                 planeb_wm = fifo_size - wm_info->guard_size;
2314                 if (planeb_wm > (long)wm_info->max_wm)
2315                         planeb_wm = wm_info->max_wm;
2316         }
2317
2318         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2319
2320         if (IS_I915GM(dev_priv) && enabled) {
2321                 struct drm_i915_gem_object *obj;
2322
2323                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2324
2325                 /* self-refresh seems busted with untiled */
2326                 if (!i915_gem_object_is_tiled(obj))
2327                         enabled = NULL;
2328         }
2329
2330         /*
2331          * Overlay gets an aggressive default since video jitter is bad.
2332          */
2333         cwm = 2;
2334
2335         /* Play safe and disable self-refresh before adjusting watermarks. */
2336         intel_set_memory_cxsr(dev_priv, false);
2337
2338         /* Calc sr entries for one plane configs */
2339         if (HAS_FW_BLC(dev_priv) && enabled) {
2340                 /* self-refresh has much higher latency */
2341                 static const int sr_latency_ns = 6000;
2342                 const struct drm_display_mode *adjusted_mode =
2343                         &enabled->config->base.adjusted_mode;
2344                 const struct drm_framebuffer *fb =
2345                         enabled->base.primary->state->fb;
2346                 int clock = adjusted_mode->crtc_clock;
2347                 int htotal = adjusted_mode->crtc_htotal;
2348                 int hdisplay = enabled->config->pipe_src_w;
2349                 int cpp;
2350                 int entries;
2351
2352                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2353                         cpp = 4;
2354                 else
2355                         cpp = fb->format->cpp[0];
2356
2357                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2358                                            sr_latency_ns / 100);
2359                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2360                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2361                 srwm = wm_info->fifo_size - entries;
2362                 if (srwm < 0)
2363                         srwm = 1;
2364
2365                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2366                         I915_WRITE(FW_BLC_SELF,
2367                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2368                 else
2369                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2370         }
2371
2372         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2373                       planea_wm, planeb_wm, cwm, srwm);
2374
2375         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2376         fwater_hi = (cwm & 0x1f);
2377
2378         /* Set request length to 8 cachelines per fetch */
2379         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2380         fwater_hi = fwater_hi | (1 << 8);
2381
2382         I915_WRITE(FW_BLC, fwater_lo);
2383         I915_WRITE(FW_BLC2, fwater_hi);
2384
2385         if (enabled)
2386                 intel_set_memory_cxsr(dev_priv, true);
2387 }
2388
2389 static void i845_update_wm(struct intel_crtc *unused_crtc)
2390 {
2391         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2392         struct intel_crtc *crtc;
2393         const struct drm_display_mode *adjusted_mode;
2394         uint32_t fwater_lo;
2395         int planea_wm;
2396
2397         crtc = single_enabled_crtc(dev_priv);
2398         if (crtc == NULL)
2399                 return;
2400
2401         adjusted_mode = &crtc->config->base.adjusted_mode;
2402         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2403                                        &i845_wm_info,
2404                                        dev_priv->display.get_fifo_size(dev_priv, 0),
2405                                        4, pessimal_latency_ns);
2406         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2407         fwater_lo |= (3<<8) | planea_wm;
2408
2409         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2410
2411         I915_WRITE(FW_BLC, fwater_lo);
2412 }
2413
2414 /* latency must be in 0.1us units. */
2415 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2416                                    unsigned int cpp,
2417                                    unsigned int latency)
2418 {
2419         unsigned int ret;
2420
2421         ret = intel_wm_method1(pixel_rate, cpp, latency);
2422         ret = DIV_ROUND_UP(ret, 64) + 2;
2423
2424         return ret;
2425 }
2426
2427 /* latency must be in 0.1us units. */
2428 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2429                                    unsigned int htotal,
2430                                    unsigned int width,
2431                                    unsigned int cpp,
2432                                    unsigned int latency)
2433 {
2434         unsigned int ret;
2435
2436         ret = intel_wm_method2(pixel_rate, htotal,
2437                                width, cpp, latency);
2438         ret = DIV_ROUND_UP(ret, 64) + 2;
2439
2440         return ret;
2441 }
2442
2443 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2444                            uint8_t cpp)
2445 {
2446         /*
2447          * Neither of these should be possible since this function shouldn't be
2448          * called if the CRTC is off or the plane is invisible.  But let's be
2449          * extra paranoid to avoid a potential divide-by-zero if we screw up
2450          * elsewhere in the driver.
2451          */
2452         if (WARN_ON(!cpp))
2453                 return 0;
2454         if (WARN_ON(!horiz_pixels))
2455                 return 0;
2456
2457         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2458 }
2459
2460 struct ilk_wm_maximums {
2461         uint16_t pri;
2462         uint16_t spr;
2463         uint16_t cur;
2464         uint16_t fbc;
2465 };
2466
2467 /*
2468  * For both WM_PIPE and WM_LP.
2469  * mem_value must be in 0.1us units.
2470  */
2471 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
2472                                    const struct intel_plane_state *pstate,
2473                                    uint32_t mem_value,
2474                                    bool is_lp)
2475 {
2476         uint32_t method1, method2;
2477         int cpp;
2478
2479         if (!intel_wm_plane_visible(cstate, pstate))
2480                 return 0;
2481
2482         cpp = pstate->base.fb->format->cpp[0];
2483
2484         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2485
2486         if (!is_lp)
2487                 return method1;
2488
2489         method2 = ilk_wm_method2(cstate->pixel_rate,
2490                                  cstate->base.adjusted_mode.crtc_htotal,
2491                                  drm_rect_width(&pstate->base.dst),
2492                                  cpp, mem_value);
2493
2494         return min(method1, method2);
2495 }
2496
2497 /*
2498  * For both WM_PIPE and WM_LP.
2499  * mem_value must be in 0.1us units.
2500  */
2501 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
2502                                    const struct intel_plane_state *pstate,
2503                                    uint32_t mem_value)
2504 {
2505         uint32_t method1, method2;
2506         int cpp;
2507
2508         if (!intel_wm_plane_visible(cstate, pstate))
2509                 return 0;
2510
2511         cpp = pstate->base.fb->format->cpp[0];
2512
2513         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2514         method2 = ilk_wm_method2(cstate->pixel_rate,
2515                                  cstate->base.adjusted_mode.crtc_htotal,
2516                                  drm_rect_width(&pstate->base.dst),
2517                                  cpp, mem_value);
2518         return min(method1, method2);
2519 }
2520
2521 /*
2522  * For both WM_PIPE and WM_LP.
2523  * mem_value must be in 0.1us units.
2524  */
2525 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
2526                                    const struct intel_plane_state *pstate,
2527                                    uint32_t mem_value)
2528 {
2529         int cpp;
2530
2531         if (!intel_wm_plane_visible(cstate, pstate))
2532                 return 0;
2533
2534         cpp = pstate->base.fb->format->cpp[0];
2535
2536         return ilk_wm_method2(cstate->pixel_rate,
2537                               cstate->base.adjusted_mode.crtc_htotal,
2538                               pstate->base.crtc_w, cpp, mem_value);
2539 }
2540
2541 /* Only for WM_LP. */
2542 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2543                                    const struct intel_plane_state *pstate,
2544                                    uint32_t pri_val)
2545 {
2546         int cpp;
2547
2548         if (!intel_wm_plane_visible(cstate, pstate))
2549                 return 0;
2550
2551         cpp = pstate->base.fb->format->cpp[0];
2552
2553         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
2554 }
2555
2556 static unsigned int
2557 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2558 {
2559         if (INTEL_GEN(dev_priv) >= 8)
2560                 return 3072;
2561         else if (INTEL_GEN(dev_priv) >= 7)
2562                 return 768;
2563         else
2564                 return 512;
2565 }
2566
2567 static unsigned int
2568 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2569                      int level, bool is_sprite)
2570 {
2571         if (INTEL_GEN(dev_priv) >= 8)
2572                 /* BDW primary/sprite plane watermarks */
2573                 return level == 0 ? 255 : 2047;
2574         else if (INTEL_GEN(dev_priv) >= 7)
2575                 /* IVB/HSW primary/sprite plane watermarks */
2576                 return level == 0 ? 127 : 1023;
2577         else if (!is_sprite)
2578                 /* ILK/SNB primary plane watermarks */
2579                 return level == 0 ? 127 : 511;
2580         else
2581                 /* ILK/SNB sprite plane watermarks */
2582                 return level == 0 ? 63 : 255;
2583 }
2584
2585 static unsigned int
2586 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2587 {
2588         if (INTEL_GEN(dev_priv) >= 7)
2589                 return level == 0 ? 63 : 255;
2590         else
2591                 return level == 0 ? 31 : 63;
2592 }
2593
2594 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2595 {
2596         if (INTEL_GEN(dev_priv) >= 8)
2597                 return 31;
2598         else
2599                 return 15;
2600 }
2601
2602 /* Calculate the maximum primary/sprite plane watermark */
2603 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2604                                      int level,
2605                                      const struct intel_wm_config *config,
2606                                      enum intel_ddb_partitioning ddb_partitioning,
2607                                      bool is_sprite)
2608 {
2609         struct drm_i915_private *dev_priv = to_i915(dev);
2610         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2611
2612         /* if sprites aren't enabled, sprites get nothing */
2613         if (is_sprite && !config->sprites_enabled)
2614                 return 0;
2615
2616         /* HSW allows LP1+ watermarks even with multiple pipes */
2617         if (level == 0 || config->num_pipes_active > 1) {
2618                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2619
2620                 /*
2621                  * For some reason the non self refresh
2622                  * FIFO size is only half of the self
2623                  * refresh FIFO size on ILK/SNB.
2624                  */
2625                 if (INTEL_GEN(dev_priv) <= 6)
2626                         fifo_size /= 2;
2627         }
2628
2629         if (config->sprites_enabled) {
2630                 /* level 0 is always calculated with 1:1 split */
2631                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2632                         if (is_sprite)
2633                                 fifo_size *= 5;
2634                         fifo_size /= 6;
2635                 } else {
2636                         fifo_size /= 2;
2637                 }
2638         }
2639
2640         /* clamp to max that the registers can hold */
2641         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2642 }
2643
2644 /* Calculate the maximum cursor plane watermark */
2645 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2646                                       int level,
2647                                       const struct intel_wm_config *config)
2648 {
2649         /* HSW LP1+ watermarks w/ multiple pipes */
2650         if (level > 0 && config->num_pipes_active > 1)
2651                 return 64;
2652
2653         /* otherwise just report max that registers can hold */
2654         return ilk_cursor_wm_reg_max(to_i915(dev), level);
2655 }
2656
2657 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2658                                     int level,
2659                                     const struct intel_wm_config *config,
2660                                     enum intel_ddb_partitioning ddb_partitioning,
2661                                     struct ilk_wm_maximums *max)
2662 {
2663         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2664         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2665         max->cur = ilk_cursor_wm_max(dev, level, config);
2666         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
2667 }
2668
2669 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2670                                         int level,
2671                                         struct ilk_wm_maximums *max)
2672 {
2673         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2674         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2675         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2676         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2677 }
2678
2679 static bool ilk_validate_wm_level(int level,
2680                                   const struct ilk_wm_maximums *max,
2681                                   struct intel_wm_level *result)
2682 {
2683         bool ret;
2684
2685         /* already determined to be invalid? */
2686         if (!result->enable)
2687                 return false;
2688
2689         result->enable = result->pri_val <= max->pri &&
2690                          result->spr_val <= max->spr &&
2691                          result->cur_val <= max->cur;
2692
2693         ret = result->enable;
2694
2695         /*
2696          * HACK until we can pre-compute everything,
2697          * and thus fail gracefully if LP0 watermarks
2698          * are exceeded...
2699          */
2700         if (level == 0 && !result->enable) {
2701                 if (result->pri_val > max->pri)
2702                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2703                                       level, result->pri_val, max->pri);
2704                 if (result->spr_val > max->spr)
2705                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2706                                       level, result->spr_val, max->spr);
2707                 if (result->cur_val > max->cur)
2708                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2709                                       level, result->cur_val, max->cur);
2710
2711                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2712                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2713                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2714                 result->enable = true;
2715         }
2716
2717         return ret;
2718 }
2719
2720 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2721                                  const struct intel_crtc *intel_crtc,
2722                                  int level,
2723                                  struct intel_crtc_state *cstate,
2724                                  struct intel_plane_state *pristate,
2725                                  struct intel_plane_state *sprstate,
2726                                  struct intel_plane_state *curstate,
2727                                  struct intel_wm_level *result)
2728 {
2729         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2730         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2731         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2732
2733         /* WM1+ latency values stored in 0.5us units */
2734         if (level > 0) {
2735                 pri_latency *= 5;
2736                 spr_latency *= 5;
2737                 cur_latency *= 5;
2738         }
2739
2740         if (pristate) {
2741                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2742                                                      pri_latency, level);
2743                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2744         }
2745
2746         if (sprstate)
2747                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2748
2749         if (curstate)
2750                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2751
2752         result->enable = true;
2753 }
2754
2755 static uint32_t
2756 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2757 {
2758         const struct intel_atomic_state *intel_state =
2759                 to_intel_atomic_state(cstate->base.state);
2760         const struct drm_display_mode *adjusted_mode =
2761                 &cstate->base.adjusted_mode;
2762         u32 linetime, ips_linetime;
2763
2764         if (!cstate->base.active)
2765                 return 0;
2766         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2767                 return 0;
2768         if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2769                 return 0;
2770
2771         /* The WM are computed with base on how long it takes to fill a single
2772          * row at the given clock rate, multiplied by 8.
2773          * */
2774         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2775                                      adjusted_mode->crtc_clock);
2776         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2777                                          intel_state->cdclk.logical.cdclk);
2778
2779         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2780                PIPE_WM_LINETIME_TIME(linetime);
2781 }
2782
2783 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2784                                   uint16_t wm[8])
2785 {
2786         if (INTEL_GEN(dev_priv) >= 9) {
2787                 uint32_t val;
2788                 int ret, i;
2789                 int level, max_level = ilk_wm_max_level(dev_priv);
2790
2791                 /* read the first set of memory latencies[0:3] */
2792                 val = 0; /* data0 to be programmed to 0 for first set */
2793                 mutex_lock(&dev_priv->pcu_lock);
2794                 ret = sandybridge_pcode_read(dev_priv,
2795                                              GEN9_PCODE_READ_MEM_LATENCY,
2796                                              &val);
2797                 mutex_unlock(&dev_priv->pcu_lock);
2798
2799                 if (ret) {
2800                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2801                         return;
2802                 }
2803
2804                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2805                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2806                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2807                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2808                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2809                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2810                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2811
2812                 /* read the second set of memory latencies[4:7] */
2813                 val = 1; /* data0 to be programmed to 1 for second set */
2814                 mutex_lock(&dev_priv->pcu_lock);
2815                 ret = sandybridge_pcode_read(dev_priv,
2816                                              GEN9_PCODE_READ_MEM_LATENCY,
2817                                              &val);
2818                 mutex_unlock(&dev_priv->pcu_lock);
2819                 if (ret) {
2820                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2821                         return;
2822                 }
2823
2824                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2825                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2826                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2827                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2828                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2829                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2830                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2831
2832                 /*
2833                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2834                  * need to be disabled. We make sure to sanitize the values out
2835                  * of the punit to satisfy this requirement.
2836                  */
2837                 for (level = 1; level <= max_level; level++) {
2838                         if (wm[level] == 0) {
2839                                 for (i = level + 1; i <= max_level; i++)
2840                                         wm[i] = 0;
2841                                 break;
2842                         }
2843                 }
2844
2845                 /*
2846                  * WaWmMemoryReadLatency:skl+,glk
2847                  *
2848                  * punit doesn't take into account the read latency so we need
2849                  * to add 2us to the various latency levels we retrieve from the
2850                  * punit when level 0 response data us 0us.
2851                  */
2852                 if (wm[0] == 0) {
2853                         wm[0] += 2;
2854                         for (level = 1; level <= max_level; level++) {
2855                                 if (wm[level] == 0)
2856                                         break;
2857                                 wm[level] += 2;
2858                         }
2859                 }
2860
2861         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2862                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2863
2864                 wm[0] = (sskpd >> 56) & 0xFF;
2865                 if (wm[0] == 0)
2866                         wm[0] = sskpd & 0xF;
2867                 wm[1] = (sskpd >> 4) & 0xFF;
2868                 wm[2] = (sskpd >> 12) & 0xFF;
2869                 wm[3] = (sskpd >> 20) & 0x1FF;
2870                 wm[4] = (sskpd >> 32) & 0x1FF;
2871         } else if (INTEL_GEN(dev_priv) >= 6) {
2872                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2873
2874                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2875                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2876                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2877                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2878         } else if (INTEL_GEN(dev_priv) >= 5) {
2879                 uint32_t mltr = I915_READ(MLTR_ILK);
2880
2881                 /* ILK primary LP0 latency is 700 ns */
2882                 wm[0] = 7;
2883                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2884                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2885         } else {
2886                 MISSING_CASE(INTEL_DEVID(dev_priv));
2887         }
2888 }
2889
2890 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2891                                        uint16_t wm[5])
2892 {
2893         /* ILK sprite LP0 latency is 1300 ns */
2894         if (IS_GEN5(dev_priv))
2895                 wm[0] = 13;
2896 }
2897
2898 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2899                                        uint16_t wm[5])
2900 {
2901         /* ILK cursor LP0 latency is 1300 ns */
2902         if (IS_GEN5(dev_priv))
2903                 wm[0] = 13;
2904
2905         /* WaDoubleCursorLP3Latency:ivb */
2906         if (IS_IVYBRIDGE(dev_priv))
2907                 wm[3] *= 2;
2908 }
2909
2910 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2911 {
2912         /* how many WM levels are we expecting */
2913         if (INTEL_GEN(dev_priv) >= 9)
2914                 return 7;
2915         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2916                 return 4;
2917         else if (INTEL_GEN(dev_priv) >= 6)
2918                 return 3;
2919         else
2920                 return 2;
2921 }
2922
2923 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2924                                    const char *name,
2925                                    const uint16_t wm[8])
2926 {
2927         int level, max_level = ilk_wm_max_level(dev_priv);
2928
2929         for (level = 0; level <= max_level; level++) {
2930                 unsigned int latency = wm[level];
2931
2932                 if (latency == 0) {
2933                         DRM_ERROR("%s WM%d latency not provided\n",
2934                                   name, level);
2935                         continue;
2936                 }
2937
2938                 /*
2939                  * - latencies are in us on gen9.
2940                  * - before then, WM1+ latency values are in 0.5us units
2941                  */
2942                 if (INTEL_GEN(dev_priv) >= 9)
2943                         latency *= 10;
2944                 else if (level > 0)
2945                         latency *= 5;
2946
2947                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2948                               name, level, wm[level],
2949                               latency / 10, latency % 10);
2950         }
2951 }
2952
2953 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2954                                     uint16_t wm[5], uint16_t min)
2955 {
2956         int level, max_level = ilk_wm_max_level(dev_priv);
2957
2958         if (wm[0] >= min)
2959                 return false;
2960
2961         wm[0] = max(wm[0], min);
2962         for (level = 1; level <= max_level; level++)
2963                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2964
2965         return true;
2966 }
2967
2968 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2969 {
2970         bool changed;
2971
2972         /*
2973          * The BIOS provided WM memory latency values are often
2974          * inadequate for high resolution displays. Adjust them.
2975          */
2976         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2977                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2978                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2979
2980         if (!changed)
2981                 return;
2982
2983         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2984         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2985         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2986         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2987 }
2988
2989 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2990 {
2991         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2992
2993         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2994                sizeof(dev_priv->wm.pri_latency));
2995         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2996                sizeof(dev_priv->wm.pri_latency));
2997
2998         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2999         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3000
3001         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3002         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3003         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3004
3005         if (IS_GEN6(dev_priv))
3006                 snb_wm_latency_quirk(dev_priv);
3007 }
3008
3009 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3010 {
3011         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3012         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3013 }
3014
3015 static bool ilk_validate_pipe_wm(struct drm_device *dev,
3016                                  struct intel_pipe_wm *pipe_wm)
3017 {
3018         /* LP0 watermark maximums depend on this pipe alone */
3019         const struct intel_wm_config config = {
3020                 .num_pipes_active = 1,
3021                 .sprites_enabled = pipe_wm->sprites_enabled,
3022                 .sprites_scaled = pipe_wm->sprites_scaled,
3023         };
3024         struct ilk_wm_maximums max;
3025
3026         /* LP0 watermarks always use 1/2 DDB partitioning */
3027         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
3028
3029         /* At least LP0 must be valid */
3030         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3031                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3032                 return false;
3033         }
3034
3035         return true;
3036 }
3037
3038 /* Compute new watermarks for the pipe */
3039 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
3040 {
3041         struct drm_atomic_state *state = cstate->base.state;
3042         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3043         struct intel_pipe_wm *pipe_wm;
3044         struct drm_device *dev = state->dev;
3045         const struct drm_i915_private *dev_priv = to_i915(dev);
3046         struct intel_plane *intel_plane;
3047         struct intel_plane_state *pristate = NULL;
3048         struct intel_plane_state *sprstate = NULL;
3049         struct intel_plane_state *curstate = NULL;
3050         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3051         struct ilk_wm_maximums max;
3052
3053         pipe_wm = &cstate->wm.ilk.optimal;
3054
3055         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3056                 struct intel_plane_state *ps;
3057
3058                 ps = intel_atomic_get_existing_plane_state(state,
3059                                                            intel_plane);
3060                 if (!ps)
3061                         continue;
3062
3063                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3064                         pristate = ps;
3065                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3066                         sprstate = ps;
3067                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
3068                         curstate = ps;
3069         }
3070
3071         pipe_wm->pipe_enabled = cstate->base.active;
3072         if (sprstate) {
3073                 pipe_wm->sprites_enabled = sprstate->base.visible;
3074                 pipe_wm->sprites_scaled = sprstate->base.visible &&
3075                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3076                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3077         }
3078
3079         usable_level = max_level;
3080
3081         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3082         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3083                 usable_level = 1;
3084
3085         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3086         if (pipe_wm->sprites_scaled)
3087                 usable_level = 0;
3088
3089         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3090                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
3091
3092         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3093         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
3094
3095         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3096                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
3097
3098         if (!ilk_validate_pipe_wm(dev, pipe_wm))
3099                 return -EINVAL;
3100
3101         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3102
3103         for (level = 1; level <= max_level; level++) {
3104                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
3105
3106                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
3107                                      pristate, sprstate, curstate, wm);
3108
3109                 /*
3110                  * Disable any watermark level that exceeds the
3111                  * register maximums since such watermarks are
3112                  * always invalid.
3113                  */
3114                 if (level > usable_level)
3115                         continue;
3116
3117                 if (ilk_validate_wm_level(level, &max, wm))
3118                         pipe_wm->wm[level] = *wm;
3119                 else
3120                         usable_level = level;
3121         }
3122
3123         return 0;
3124 }
3125
3126 /*
3127  * Build a set of 'intermediate' watermark values that satisfy both the old
3128  * state and the new state.  These can be programmed to the hardware
3129  * immediately.
3130  */
3131 static int ilk_compute_intermediate_wm(struct drm_device *dev,
3132                                        struct intel_crtc *intel_crtc,
3133                                        struct intel_crtc_state *newstate)
3134 {
3135         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3136         struct intel_atomic_state *intel_state =
3137                 to_intel_atomic_state(newstate->base.state);
3138         const struct intel_crtc_state *oldstate =
3139                 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3140         const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3141         int level, max_level = ilk_wm_max_level(to_i915(dev));
3142
3143         /*
3144          * Start with the final, target watermarks, then combine with the
3145          * currently active watermarks to get values that are safe both before
3146          * and after the vblank.
3147          */
3148         *a = newstate->wm.ilk.optimal;
3149         if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base))
3150                 return 0;
3151
3152         a->pipe_enabled |= b->pipe_enabled;
3153         a->sprites_enabled |= b->sprites_enabled;
3154         a->sprites_scaled |= b->sprites_scaled;
3155
3156         for (level = 0; level <= max_level; level++) {
3157                 struct intel_wm_level *a_wm = &a->wm[level];
3158                 const struct intel_wm_level *b_wm = &b->wm[level];
3159
3160                 a_wm->enable &= b_wm->enable;
3161                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3162                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3163                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3164                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3165         }
3166
3167         /*
3168          * We need to make sure that these merged watermark values are
3169          * actually a valid configuration themselves.  If they're not,
3170          * there's no safe way to transition from the old state to
3171          * the new state, so we need to fail the atomic transaction.
3172          */
3173         if (!ilk_validate_pipe_wm(dev, a))
3174                 return -EINVAL;
3175
3176         /*
3177          * If our intermediate WM are identical to the final WM, then we can
3178          * omit the post-vblank programming; only update if it's different.
3179          */
3180         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3181                 newstate->wm.need_postvbl_update = true;
3182
3183         return 0;
3184 }
3185
3186 /*
3187  * Merge the watermarks from all active pipes for a specific level.
3188  */
3189 static void ilk_merge_wm_level(struct drm_device *dev,
3190                                int level,
3191                                struct intel_wm_level *ret_wm)
3192 {
3193         const struct intel_crtc *intel_crtc;
3194
3195         ret_wm->enable = true;
3196
3197         for_each_intel_crtc(dev, intel_crtc) {
3198                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3199                 const struct intel_wm_level *wm = &active->wm[level];
3200
3201                 if (!active->pipe_enabled)
3202                         continue;
3203
3204                 /*
3205                  * The watermark values may have been used in the past,
3206                  * so we must maintain them in the registers for some
3207                  * time even if the level is now disabled.
3208                  */
3209                 if (!wm->enable)
3210                         ret_wm->enable = false;
3211
3212                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3213                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3214                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3215                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3216         }
3217 }
3218
3219 /*
3220  * Merge all low power watermarks for all active pipes.
3221  */
3222 static void ilk_wm_merge(struct drm_device *dev,
3223                          const struct intel_wm_config *config,
3224                          const struct ilk_wm_maximums *max,
3225                          struct intel_pipe_wm *merged)
3226 {
3227         struct drm_i915_private *dev_priv = to_i915(dev);
3228         int level, max_level = ilk_wm_max_level(dev_priv);
3229         int last_enabled_level = max_level;
3230
3231         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3232         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3233             config->num_pipes_active > 1)
3234                 last_enabled_level = 0;
3235
3236         /* ILK: FBC WM must be disabled always */
3237         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3238
3239         /* merge each WM1+ level */
3240         for (level = 1; level <= max_level; level++) {
3241                 struct intel_wm_level *wm = &merged->wm[level];
3242
3243                 ilk_merge_wm_level(dev, level, wm);
3244
3245                 if (level > last_enabled_level)
3246                         wm->enable = false;
3247                 else if (!ilk_validate_wm_level(level, max, wm))
3248                         /* make sure all following levels get disabled */
3249                         last_enabled_level = level - 1;
3250
3251                 /*
3252                  * The spec says it is preferred to disable
3253                  * FBC WMs instead of disabling a WM level.
3254                  */
3255                 if (wm->fbc_val > max->fbc) {
3256                         if (wm->enable)
3257                                 merged->fbc_wm_enabled = false;
3258                         wm->fbc_val = 0;
3259                 }
3260         }
3261
3262         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3263         /*
3264          * FIXME this is racy. FBC might get enabled later.
3265          * What we should check here is whether FBC can be
3266          * enabled sometime later.
3267          */
3268         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
3269             intel_fbc_is_active(dev_priv)) {
3270                 for (level = 2; level <= max_level; level++) {
3271                         struct intel_wm_level *wm = &merged->wm[level];
3272
3273                         wm->enable = false;
3274                 }
3275         }
3276 }
3277
3278 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3279 {
3280         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3281         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3282 }
3283
3284 /* The value we need to program into the WM_LPx latency field */
3285 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
3286 {
3287         struct drm_i915_private *dev_priv = to_i915(dev);
3288
3289         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3290                 return 2 * level;
3291         else
3292                 return dev_priv->wm.pri_latency[level];
3293 }
3294
3295 static void ilk_compute_wm_results(struct drm_device *dev,
3296                                    const struct intel_pipe_wm *merged,
3297                                    enum intel_ddb_partitioning partitioning,
3298                                    struct ilk_wm_values *results)
3299 {
3300         struct drm_i915_private *dev_priv = to_i915(dev);
3301         struct intel_crtc *intel_crtc;
3302         int level, wm_lp;
3303
3304         results->enable_fbc_wm = merged->fbc_wm_enabled;
3305         results->partitioning = partitioning;
3306
3307         /* LP1+ register values */
3308         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3309                 const struct intel_wm_level *r;
3310
3311                 level = ilk_wm_lp_to_level(wm_lp, merged);
3312
3313                 r = &merged->wm[level];
3314
3315                 /*
3316                  * Maintain the watermark values even if the level is
3317                  * disabled. Doing otherwise could cause underruns.
3318                  */
3319                 results->wm_lp[wm_lp - 1] =
3320                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
3321                         (r->pri_val << WM1_LP_SR_SHIFT) |
3322                         r->cur_val;
3323
3324                 if (r->enable)
3325                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3326
3327                 if (INTEL_GEN(dev_priv) >= 8)
3328                         results->wm_lp[wm_lp - 1] |=
3329                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3330                 else
3331                         results->wm_lp[wm_lp - 1] |=
3332                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3333
3334                 /*
3335                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3336                  * level is disabled. Doing otherwise could cause underruns.
3337                  */
3338                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3339                         WARN_ON(wm_lp != 1);
3340                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3341                 } else
3342                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3343         }
3344
3345         /* LP0 register values */
3346         for_each_intel_crtc(dev, intel_crtc) {
3347                 enum pipe pipe = intel_crtc->pipe;
3348                 const struct intel_wm_level *r =
3349                         &intel_crtc->wm.active.ilk.wm[0];
3350
3351                 if (WARN_ON(!r->enable))
3352                         continue;
3353
3354                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3355
3356                 results->wm_pipe[pipe] =
3357                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3358                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3359                         r->cur_val;
3360         }
3361 }
3362
3363 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3364  * case both are at the same level. Prefer r1 in case they're the same. */
3365 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
3366                                                   struct intel_pipe_wm *r1,
3367                                                   struct intel_pipe_wm *r2)
3368 {
3369         int level, max_level = ilk_wm_max_level(to_i915(dev));
3370         int level1 = 0, level2 = 0;
3371
3372         for (level = 1; level <= max_level; level++) {
3373                 if (r1->wm[level].enable)
3374                         level1 = level;
3375                 if (r2->wm[level].enable)
3376                         level2 = level;
3377         }
3378
3379         if (level1 == level2) {
3380                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3381                         return r2;
3382                 else
3383                         return r1;
3384         } else if (level1 > level2) {
3385                 return r1;
3386         } else {
3387                 return r2;
3388         }
3389 }
3390
3391 /* dirty bits used to track which watermarks need changes */
3392 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3393 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3394 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3395 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3396 #define WM_DIRTY_FBC (1 << 24)
3397 #define WM_DIRTY_DDB (1 << 25)
3398
3399 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3400                                          const struct ilk_wm_values *old,
3401                                          const struct ilk_wm_values *new)
3402 {
3403         unsigned int dirty = 0;
3404         enum pipe pipe;
3405         int wm_lp;
3406
3407         for_each_pipe(dev_priv, pipe) {
3408                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3409                         dirty |= WM_DIRTY_LINETIME(pipe);
3410                         /* Must disable LP1+ watermarks too */
3411                         dirty |= WM_DIRTY_LP_ALL;
3412                 }
3413
3414                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3415                         dirty |= WM_DIRTY_PIPE(pipe);
3416                         /* Must disable LP1+ watermarks too */
3417                         dirty |= WM_DIRTY_LP_ALL;
3418                 }
3419         }
3420
3421         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3422                 dirty |= WM_DIRTY_FBC;
3423                 /* Must disable LP1+ watermarks too */
3424                 dirty |= WM_DIRTY_LP_ALL;
3425         }
3426
3427         if (old->partitioning != new->partitioning) {
3428                 dirty |= WM_DIRTY_DDB;
3429                 /* Must disable LP1+ watermarks too */
3430                 dirty |= WM_DIRTY_LP_ALL;
3431         }
3432
3433         /* LP1+ watermarks already deemed dirty, no need to continue */
3434         if (dirty & WM_DIRTY_LP_ALL)
3435                 return dirty;
3436
3437         /* Find the lowest numbered LP1+ watermark in need of an update... */
3438         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3439                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3440                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3441                         break;
3442         }
3443
3444         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3445         for (; wm_lp <= 3; wm_lp++)
3446                 dirty |= WM_DIRTY_LP(wm_lp);
3447
3448         return dirty;
3449 }
3450
3451 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3452                                unsigned int dirty)
3453 {
3454         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3455         bool changed = false;
3456
3457         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3458                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3459                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3460                 changed = true;
3461         }
3462         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3463                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3464                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3465                 changed = true;
3466         }
3467         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3468                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3469                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3470                 changed = true;
3471         }
3472
3473         /*
3474          * Don't touch WM1S_LP_EN here.
3475          * Doing so could cause underruns.
3476          */
3477
3478         return changed;
3479 }
3480
3481 /*
3482  * The spec says we shouldn't write when we don't need, because every write
3483  * causes WMs to be re-evaluated, expending some power.
3484  */
3485 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3486                                 struct ilk_wm_values *results)
3487 {
3488         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3489         unsigned int dirty;
3490         uint32_t val;
3491
3492         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3493         if (!dirty)
3494                 return;
3495
3496         _ilk_disable_lp_wm(dev_priv, dirty);
3497
3498         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3499                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3500         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3501                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3502         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3503                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3504
3505         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3506                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3507         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3508                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3509         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3510                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3511
3512         if (dirty & WM_DIRTY_DDB) {
3513                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3514                         val = I915_READ(WM_MISC);
3515                         if (results->partitioning == INTEL_DDB_PART_1_2)
3516                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3517                         else
3518                                 val |= WM_MISC_DATA_PARTITION_5_6;
3519                         I915_WRITE(WM_MISC, val);
3520                 } else {
3521                         val = I915_READ(DISP_ARB_CTL2);
3522                         if (results->partitioning == INTEL_DDB_PART_1_2)
3523                                 val &= ~DISP_DATA_PARTITION_5_6;
3524                         else
3525                                 val |= DISP_DATA_PARTITION_5_6;
3526                         I915_WRITE(DISP_ARB_CTL2, val);
3527                 }
3528         }
3529
3530         if (dirty & WM_DIRTY_FBC) {
3531                 val = I915_READ(DISP_ARB_CTL);
3532                 if (results->enable_fbc_wm)
3533                         val &= ~DISP_FBC_WM_DIS;
3534                 else
3535                         val |= DISP_FBC_WM_DIS;
3536                 I915_WRITE(DISP_ARB_CTL, val);
3537         }
3538
3539         if (dirty & WM_DIRTY_LP(1) &&
3540             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3541                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3542
3543         if (INTEL_GEN(dev_priv) >= 7) {
3544                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3545                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3546                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3547                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3548         }
3549
3550         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3551                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3552         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3553                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3554         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3555                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3556
3557         dev_priv->wm.hw = *results;
3558 }
3559
3560 bool ilk_disable_lp_wm(struct drm_device *dev)
3561 {
3562         struct drm_i915_private *dev_priv = to_i915(dev);
3563
3564         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3565 }
3566
3567 /*
3568  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3569  * so assume we'll always need it in order to avoid underruns.
3570  */
3571 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
3572 {
3573         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3574
3575         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
3576                 return true;
3577
3578         return false;
3579 }
3580
3581 static bool
3582 intel_has_sagv(struct drm_i915_private *dev_priv)
3583 {
3584         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
3585             IS_CANNONLAKE(dev_priv))
3586                 return true;
3587
3588         if (IS_SKYLAKE(dev_priv) &&
3589             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
3590                 return true;
3591
3592         return false;
3593 }
3594
3595 /*
3596  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3597  * depending on power and performance requirements. The display engine access
3598  * to system memory is blocked during the adjustment time. Because of the
3599  * blocking time, having this enabled can cause full system hangs and/or pipe
3600  * underruns if we don't meet all of the following requirements:
3601  *
3602  *  - <= 1 pipe enabled
3603  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3604  *  - We're not using an interlaced display configuration
3605  */
3606 int
3607 intel_enable_sagv(struct drm_i915_private *dev_priv)
3608 {
3609         int ret;
3610
3611         if (!intel_has_sagv(dev_priv))
3612                 return 0;
3613
3614         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3615                 return 0;
3616
3617         DRM_DEBUG_KMS("Enabling the SAGV\n");
3618         mutex_lock(&dev_priv->pcu_lock);
3619
3620         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3621                                       GEN9_SAGV_ENABLE);
3622
3623         /* We don't need to wait for the SAGV when enabling */
3624         mutex_unlock(&dev_priv->pcu_lock);
3625
3626         /*
3627          * Some skl systems, pre-release machines in particular,
3628          * don't actually have an SAGV.
3629          */
3630         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3631                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3632                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3633                 return 0;
3634         } else if (ret < 0) {
3635                 DRM_ERROR("Failed to enable the SAGV\n");
3636                 return ret;
3637         }
3638
3639         dev_priv->sagv_status = I915_SAGV_ENABLED;
3640         return 0;
3641 }
3642
3643 int
3644 intel_disable_sagv(struct drm_i915_private *dev_priv)
3645 {
3646         int ret;
3647
3648         if (!intel_has_sagv(dev_priv))
3649                 return 0;
3650
3651         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3652                 return 0;
3653
3654         DRM_DEBUG_KMS("Disabling the SAGV\n");
3655         mutex_lock(&dev_priv->pcu_lock);
3656
3657         /* bspec says to keep retrying for at least 1 ms */
3658         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3659                                 GEN9_SAGV_DISABLE,
3660                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3661                                 1);
3662         mutex_unlock(&dev_priv->pcu_lock);
3663
3664         /*
3665          * Some skl systems, pre-release machines in particular,
3666          * don't actually have an SAGV.
3667          */
3668         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3669                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3670                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3671                 return 0;
3672         } else if (ret < 0) {
3673                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3674                 return ret;
3675         }
3676
3677         dev_priv->sagv_status = I915_SAGV_DISABLED;
3678         return 0;
3679 }
3680
3681 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3682 {
3683         struct drm_device *dev = state->dev;
3684         struct drm_i915_private *dev_priv = to_i915(dev);
3685         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3686         struct intel_crtc *crtc;
3687         struct intel_plane *plane;
3688         struct intel_crtc_state *cstate;
3689         enum pipe pipe;
3690         int level, latency;
3691         int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
3692
3693         if (!intel_has_sagv(dev_priv))
3694                 return false;
3695
3696         /*
3697          * SKL+ workaround: bspec recommends we disable the SAGV when we have
3698          * more then one pipe enabled
3699          *
3700          * If there are no active CRTCs, no additional checks need be performed
3701          */
3702         if (hweight32(intel_state->active_crtcs) == 0)
3703                 return true;
3704         else if (hweight32(intel_state->active_crtcs) > 1)
3705                 return false;
3706
3707         /* Since we're now guaranteed to only have one active CRTC... */
3708         pipe = ffs(intel_state->active_crtcs) - 1;
3709         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3710         cstate = to_intel_crtc_state(crtc->base.state);
3711
3712         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3713                 return false;
3714
3715         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3716                 struct skl_plane_wm *wm =
3717                         &cstate->wm.skl.optimal.planes[plane->id];
3718
3719                 /* Skip this plane if it's not enabled */
3720                 if (!wm->wm[0].plane_en)
3721                         continue;
3722
3723                 /* Find the highest enabled wm level for this plane */
3724                 for (level = ilk_wm_max_level(dev_priv);
3725                      !wm->wm[level].plane_en; --level)
3726                      { }
3727
3728                 latency = dev_priv->wm.skl_latency[level];
3729
3730                 if (skl_needs_memory_bw_wa(intel_state) &&
3731                     plane->base.state->fb->modifier ==
3732                     I915_FORMAT_MOD_X_TILED)
3733                         latency += 15;
3734
3735                 /*
3736                  * If any of the planes on this pipe don't enable wm levels that
3737                  * incur memory latencies higher than sagv_block_time_us we
3738                  * can't enable the SAGV.
3739                  */
3740                 if (latency < sagv_block_time_us)
3741                         return false;
3742         }
3743
3744         return true;
3745 }
3746
3747 static void
3748 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3749                                    const struct intel_crtc_state *cstate,
3750                                    struct skl_ddb_entry *alloc, /* out */
3751                                    int *num_active /* out */)
3752 {
3753         struct drm_atomic_state *state = cstate->base.state;
3754         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3755         struct drm_i915_private *dev_priv = to_i915(dev);
3756         struct drm_crtc *for_crtc = cstate->base.crtc;
3757         unsigned int pipe_size, ddb_size;
3758         int nth_active_pipe;
3759
3760         if (WARN_ON(!state) || !cstate->base.active) {
3761                 alloc->start = 0;
3762                 alloc->end = 0;
3763                 *num_active = hweight32(dev_priv->active_crtcs);
3764                 return;
3765         }
3766
3767         if (intel_state->active_pipe_changes)
3768                 *num_active = hweight32(intel_state->active_crtcs);
3769         else
3770                 *num_active = hweight32(dev_priv->active_crtcs);
3771
3772         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3773         WARN_ON(ddb_size == 0);
3774
3775         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3776
3777         /*
3778          * If the state doesn't change the active CRTC's, then there's
3779          * no need to recalculate; the existing pipe allocation limits
3780          * should remain unchanged.  Note that we're safe from racing
3781          * commits since any racing commit that changes the active CRTC
3782          * list would need to grab _all_ crtc locks, including the one
3783          * we currently hold.
3784          */
3785         if (!intel_state->active_pipe_changes) {
3786                 /*
3787                  * alloc may be cleared by clear_intel_crtc_state,
3788                  * copy from old state to be sure
3789                  */
3790                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3791                 return;
3792         }
3793
3794         nth_active_pipe = hweight32(intel_state->active_crtcs &
3795                                     (drm_crtc_mask(for_crtc) - 1));
3796         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3797         alloc->start = nth_active_pipe * ddb_size / *num_active;
3798         alloc->end = alloc->start + pipe_size;
3799 }
3800
3801 static unsigned int skl_cursor_allocation(int num_active)
3802 {
3803         if (num_active == 1)
3804                 return 32;
3805
3806         return 8;
3807 }
3808
3809 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3810 {
3811         entry->start = reg & 0x3ff;
3812         entry->end = (reg >> 16) & 0x3ff;
3813         if (entry->end)
3814                 entry->end += 1;
3815 }
3816
3817 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3818                           struct skl_ddb_allocation *ddb /* out */)
3819 {
3820         struct intel_crtc *crtc;
3821
3822         memset(ddb, 0, sizeof(*ddb));
3823
3824         for_each_intel_crtc(&dev_priv->drm, crtc) {
3825                 enum intel_display_power_domain power_domain;
3826                 enum plane_id plane_id;
3827                 enum pipe pipe = crtc->pipe;
3828
3829                 power_domain = POWER_DOMAIN_PIPE(pipe);
3830                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3831                         continue;
3832
3833                 for_each_plane_id_on_crtc(crtc, plane_id) {
3834                         u32 val;
3835
3836                         if (plane_id != PLANE_CURSOR)
3837                                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3838                         else
3839                                 val = I915_READ(CUR_BUF_CFG(pipe));
3840
3841                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3842                 }
3843
3844                 intel_display_power_put(dev_priv, power_domain);
3845         }
3846 }
3847
3848 /*
3849  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3850  * The bspec defines downscale amount as:
3851  *
3852  * """
3853  * Horizontal down scale amount = maximum[1, Horizontal source size /
3854  *                                           Horizontal destination size]
3855  * Vertical down scale amount = maximum[1, Vertical source size /
3856  *                                         Vertical destination size]
3857  * Total down scale amount = Horizontal down scale amount *
3858  *                           Vertical down scale amount
3859  * """
3860  *
3861  * Return value is provided in 16.16 fixed point form to retain fractional part.
3862  * Caller should take care of dividing & rounding off the value.
3863  */
3864 static uint_fixed_16_16_t
3865 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
3866                            const struct intel_plane_state *pstate)
3867 {
3868         struct intel_plane *plane = to_intel_plane(pstate->base.plane);
3869         uint32_t src_w, src_h, dst_w, dst_h;
3870         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3871         uint_fixed_16_16_t downscale_h, downscale_w;
3872
3873         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3874                 return u32_to_fixed16(0);
3875
3876         /* n.b., src is 16.16 fixed point, dst is whole integer */
3877         if (plane->id == PLANE_CURSOR) {
3878                 /*
3879                  * Cursors only support 0/180 degree rotation,
3880                  * hence no need to account for rotation here.
3881                  */
3882                 src_w = pstate->base.src_w >> 16;
3883                 src_h = pstate->base.src_h >> 16;
3884                 dst_w = pstate->base.crtc_w;
3885                 dst_h = pstate->base.crtc_h;
3886         } else {
3887                 /*
3888                  * Src coordinates are already rotated by 270 degrees for
3889                  * the 90/270 degree plane rotation cases (to match the
3890                  * GTT mapping), hence no need to account for rotation here.
3891                  */
3892                 src_w = drm_rect_width(&pstate->base.src) >> 16;
3893                 src_h = drm_rect_height(&pstate->base.src) >> 16;
3894                 dst_w = drm_rect_width(&pstate->base.dst);
3895                 dst_h = drm_rect_height(&pstate->base.dst);
3896         }
3897
3898         fp_w_ratio = div_fixed16(src_w, dst_w);
3899         fp_h_ratio = div_fixed16(src_h, dst_h);
3900         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3901         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3902
3903         return mul_fixed16(downscale_w, downscale_h);
3904 }
3905
3906 static uint_fixed_16_16_t
3907 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
3908 {
3909         uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
3910
3911         if (!crtc_state->base.enable)
3912                 return pipe_downscale;
3913
3914         if (crtc_state->pch_pfit.enabled) {
3915                 uint32_t src_w, src_h, dst_w, dst_h;
3916                 uint32_t pfit_size = crtc_state->pch_pfit.size;
3917                 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3918                 uint_fixed_16_16_t downscale_h, downscale_w;
3919
3920                 src_w = crtc_state->pipe_src_w;
3921                 src_h = crtc_state->pipe_src_h;
3922                 dst_w = pfit_size >> 16;
3923                 dst_h = pfit_size & 0xffff;
3924
3925                 if (!dst_w || !dst_h)
3926                         return pipe_downscale;
3927
3928                 fp_w_ratio = div_fixed16(src_w, dst_w);
3929                 fp_h_ratio = div_fixed16(src_h, dst_h);
3930                 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3931                 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3932
3933                 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
3934         }
3935
3936         return pipe_downscale;
3937 }
3938
3939 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
3940                                   struct intel_crtc_state *cstate)
3941 {
3942         struct drm_crtc_state *crtc_state = &cstate->base;
3943         struct drm_atomic_state *state = crtc_state->state;
3944         struct drm_plane *plane;
3945         const struct drm_plane_state *pstate;
3946         struct intel_plane_state *intel_pstate;
3947         int crtc_clock, dotclk;
3948         uint32_t pipe_max_pixel_rate;
3949         uint_fixed_16_16_t pipe_downscale;
3950         uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
3951
3952         if (!cstate->base.enable)
3953                 return 0;
3954
3955         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
3956                 uint_fixed_16_16_t plane_downscale;
3957                 uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
3958                 int bpp;
3959
3960                 if (!intel_wm_plane_visible(cstate,
3961                                             to_intel_plane_state(pstate)))
3962                         continue;
3963
3964                 if (WARN_ON(!pstate->fb))
3965                         return -EINVAL;
3966
3967                 intel_pstate = to_intel_plane_state(pstate);
3968                 plane_downscale = skl_plane_downscale_amount(cstate,
3969                                                              intel_pstate);
3970                 bpp = pstate->fb->format->cpp[0] * 8;
3971                 if (bpp == 64)
3972                         plane_downscale = mul_fixed16(plane_downscale,
3973                                                       fp_9_div_8);
3974
3975                 max_downscale = max_fixed16(plane_downscale, max_downscale);
3976         }
3977         pipe_downscale = skl_pipe_downscale_amount(cstate);
3978
3979         pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
3980
3981         crtc_clock = crtc_state->adjusted_mode.crtc_clock;
3982         dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
3983
3984         if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
3985                 dotclk *= 2;
3986
3987         pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
3988
3989         if (pipe_max_pixel_rate < crtc_clock) {
3990                 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3991                 return -EINVAL;
3992         }
3993
3994         return 0;
3995 }
3996
3997 static unsigned int
3998 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3999                              const struct drm_plane_state *pstate,
4000                              int y)
4001 {
4002         struct intel_plane *plane = to_intel_plane(pstate->plane);
4003         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4004         uint32_t data_rate;
4005         uint32_t width = 0, height = 0;
4006         struct drm_framebuffer *fb;
4007         u32 format;
4008         uint_fixed_16_16_t down_scale_amount;
4009
4010         if (!intel_pstate->base.visible)
4011                 return 0;
4012
4013         fb = pstate->fb;
4014         format = fb->format->format;
4015
4016         if (plane->id == PLANE_CURSOR)
4017                 return 0;
4018         if (y && format != DRM_FORMAT_NV12)
4019                 return 0;
4020
4021         /*
4022          * Src coordinates are already rotated by 270 degrees for
4023          * the 90/270 degree plane rotation cases (to match the
4024          * GTT mapping), hence no need to account for rotation here.
4025          */
4026         width = drm_rect_width(&intel_pstate->base.src) >> 16;
4027         height = drm_rect_height(&intel_pstate->base.src) >> 16;
4028
4029         /* for planar format */
4030         if (format == DRM_FORMAT_NV12) {
4031                 if (y)  /* y-plane data rate */
4032                         data_rate = width * height *
4033                                 fb->format->cpp[0];
4034                 else    /* uv-plane data rate */
4035                         data_rate = (width / 2) * (height / 2) *
4036                                 fb->format->cpp[1];
4037         } else {
4038                 /* for packed formats */
4039                 data_rate = width * height * fb->format->cpp[0];
4040         }
4041
4042         down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
4043
4044         return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4045 }
4046
4047 /*
4048  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4049  * a 8192x4096@32bpp framebuffer:
4050  *   3 * 4096 * 8192  * 4 < 2^32
4051  */
4052 static unsigned int
4053 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
4054                                  unsigned *plane_data_rate,
4055                                  unsigned *plane_y_data_rate)
4056 {
4057         struct drm_crtc_state *cstate = &intel_cstate->base;
4058         struct drm_atomic_state *state = cstate->state;
4059         struct drm_plane *plane;
4060         const struct drm_plane_state *pstate;
4061         unsigned int total_data_rate = 0;
4062
4063         if (WARN_ON(!state))
4064                 return 0;
4065
4066         /* Calculate and cache data rate for each plane */
4067         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
4068                 enum plane_id plane_id = to_intel_plane(plane)->id;
4069                 unsigned int rate;
4070
4071                 /* packed/uv */
4072                 rate = skl_plane_relative_data_rate(intel_cstate,
4073                                                     pstate, 0);
4074                 plane_data_rate[plane_id] = rate;
4075
4076                 total_data_rate += rate;
4077
4078                 /* y-plane */
4079                 rate = skl_plane_relative_data_rate(intel_cstate,
4080                                                     pstate, 1);
4081                 plane_y_data_rate[plane_id] = rate;
4082
4083                 total_data_rate += rate;
4084         }
4085
4086         return total_data_rate;
4087 }
4088
4089 static uint16_t
4090 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
4091                   const int y)
4092 {
4093         struct drm_framebuffer *fb = pstate->fb;
4094         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4095         uint32_t src_w, src_h;
4096         uint32_t min_scanlines = 8;
4097         uint8_t plane_bpp;
4098
4099         if (WARN_ON(!fb))
4100                 return 0;
4101
4102         /* For packed formats, no y-plane, return 0 */
4103         if (y && fb->format->format != DRM_FORMAT_NV12)
4104                 return 0;
4105
4106         /* For Non Y-tile return 8-blocks */
4107         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
4108             fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
4109             fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
4110             fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
4111                 return 8;
4112
4113         /*
4114          * Src coordinates are already rotated by 270 degrees for
4115          * the 90/270 degree plane rotation cases (to match the
4116          * GTT mapping), hence no need to account for rotation here.
4117          */
4118         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
4119         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
4120
4121         /* Halve UV plane width and height for NV12 */
4122         if (fb->format->format == DRM_FORMAT_NV12 && !y) {
4123                 src_w /= 2;
4124                 src_h /= 2;
4125         }
4126
4127         if (fb->format->format == DRM_FORMAT_NV12 && !y)
4128                 plane_bpp = fb->format->cpp[1];
4129         else
4130                 plane_bpp = fb->format->cpp[0];
4131
4132         if (drm_rotation_90_or_270(pstate->rotation)) {
4133                 switch (plane_bpp) {
4134                 case 1:
4135                         min_scanlines = 32;
4136                         break;
4137                 case 2:
4138                         min_scanlines = 16;
4139                         break;
4140                 case 4:
4141                         min_scanlines = 8;
4142                         break;
4143                 case 8:
4144                         min_scanlines = 4;
4145                         break;
4146                 default:
4147                         WARN(1, "Unsupported pixel depth %u for rotation",
4148                              plane_bpp);
4149                         min_scanlines = 32;
4150                 }
4151         }
4152
4153         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
4154 }
4155
4156 static void
4157 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
4158                  uint16_t *minimum, uint16_t *y_minimum)
4159 {
4160         const struct drm_plane_state *pstate;
4161         struct drm_plane *plane;
4162
4163         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
4164                 enum plane_id plane_id = to_intel_plane(plane)->id;
4165
4166                 if (plane_id == PLANE_CURSOR)
4167                         continue;
4168
4169                 if (!pstate->visible)
4170                         continue;
4171
4172                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
4173                 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
4174         }
4175
4176         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
4177 }
4178
4179 static int
4180 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
4181                       struct skl_ddb_allocation *ddb /* out */)
4182 {
4183         struct drm_atomic_state *state = cstate->base.state;
4184         struct drm_crtc *crtc = cstate->base.crtc;
4185         struct drm_device *dev = crtc->dev;
4186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4187         enum pipe pipe = intel_crtc->pipe;
4188         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
4189         uint16_t alloc_size, start;
4190         uint16_t minimum[I915_MAX_PLANES] = {};
4191         uint16_t y_minimum[I915_MAX_PLANES] = {};
4192         unsigned int total_data_rate;
4193         enum plane_id plane_id;
4194         int num_active;
4195         unsigned plane_data_rate[I915_MAX_PLANES] = {};
4196         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
4197         uint16_t total_min_blocks = 0;
4198
4199         /* Clear the partitioning for disabled planes. */
4200         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4201         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
4202
4203         if (WARN_ON(!state))
4204                 return 0;
4205
4206         if (!cstate->base.active) {
4207                 alloc->start = alloc->end = 0;
4208                 return 0;
4209         }
4210
4211         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
4212         alloc_size = skl_ddb_entry_size(alloc);
4213         if (alloc_size == 0)
4214                 return 0;
4215
4216         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
4217
4218         /*
4219          * 1. Allocate the mininum required blocks for each active plane
4220          * and allocate the cursor, it doesn't require extra allocation
4221          * proportional to the data rate.
4222          */
4223
4224         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4225                 total_min_blocks += minimum[plane_id];
4226                 total_min_blocks += y_minimum[plane_id];
4227         }
4228
4229         if (total_min_blocks > alloc_size) {
4230                 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4231                 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks,
4232                                                         alloc_size);
4233                 return -EINVAL;
4234         }
4235
4236         alloc_size -= total_min_blocks;
4237         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
4238         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
4239
4240         /*
4241          * 2. Distribute the remaining space in proportion to the amount of
4242          * data each plane needs to fetch from memory.
4243          *
4244          * FIXME: we may not allocate every single block here.
4245          */
4246         total_data_rate = skl_get_total_relative_data_rate(cstate,
4247                                                            plane_data_rate,
4248                                                            plane_y_data_rate);
4249         if (total_data_rate == 0)
4250                 return 0;
4251
4252         start = alloc->start;
4253         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4254                 unsigned int data_rate, y_data_rate;
4255                 uint16_t plane_blocks, y_plane_blocks = 0;
4256
4257                 if (plane_id == PLANE_CURSOR)
4258                         continue;
4259
4260                 data_rate = plane_data_rate[plane_id];
4261
4262                 /*
4263                  * allocation for (packed formats) or (uv-plane part of planar format):
4264                  * promote the expression to 64 bits to avoid overflowing, the
4265                  * result is < available as data_rate / total_data_rate < 1
4266                  */
4267                 plane_blocks = minimum[plane_id];
4268                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
4269                                         total_data_rate);
4270
4271                 /* Leave disabled planes at (0,0) */
4272                 if (data_rate) {
4273                         ddb->plane[pipe][plane_id].start = start;
4274                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
4275                 }
4276
4277                 start += plane_blocks;
4278
4279                 /*
4280                  * allocation for y_plane part of planar format:
4281                  */
4282                 y_data_rate = plane_y_data_rate[plane_id];
4283
4284                 y_plane_blocks = y_minimum[plane_id];
4285                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
4286                                         total_data_rate);
4287
4288                 if (y_data_rate) {
4289                         ddb->y_plane[pipe][plane_id].start = start;
4290                         ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
4291                 }
4292
4293                 start += y_plane_blocks;
4294         }
4295
4296         return 0;
4297 }
4298
4299 /*
4300  * The max latency should be 257 (max the punit can code is 255 and we add 2us
4301  * for the read latency) and cpp should always be <= 8, so that
4302  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4303  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4304 */
4305 static uint_fixed_16_16_t
4306 skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
4307                uint8_t cpp, uint32_t latency)
4308 {
4309         uint32_t wm_intermediate_val;
4310         uint_fixed_16_16_t ret;
4311
4312         if (latency == 0)
4313                 return FP_16_16_MAX;
4314
4315         wm_intermediate_val = latency * pixel_rate * cpp;
4316         ret = div_fixed16(wm_intermediate_val, 1000 * 512);
4317
4318         if (INTEL_GEN(dev_priv) >= 10)
4319                 ret = add_fixed16_u32(ret, 1);
4320
4321         return ret;
4322 }
4323
4324 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
4325                         uint32_t pipe_htotal,
4326                         uint32_t latency,
4327                         uint_fixed_16_16_t plane_blocks_per_line)
4328 {
4329         uint32_t wm_intermediate_val;
4330         uint_fixed_16_16_t ret;
4331
4332         if (latency == 0)
4333                 return FP_16_16_MAX;
4334
4335         wm_intermediate_val = latency * pixel_rate;
4336         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4337                                            pipe_htotal * 1000);
4338         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
4339         return ret;
4340 }
4341
4342 static uint_fixed_16_16_t
4343 intel_get_linetime_us(struct intel_crtc_state *cstate)
4344 {
4345         uint32_t pixel_rate;
4346         uint32_t crtc_htotal;
4347         uint_fixed_16_16_t linetime_us;
4348
4349         if (!cstate->base.active)
4350                 return u32_to_fixed16(0);
4351
4352         pixel_rate = cstate->pixel_rate;
4353
4354         if (WARN_ON(pixel_rate == 0))
4355                 return u32_to_fixed16(0);
4356
4357         crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
4358         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
4359
4360         return linetime_us;
4361 }
4362
4363 static uint32_t
4364 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
4365                               const struct intel_plane_state *pstate)
4366 {
4367         uint64_t adjusted_pixel_rate;
4368         uint_fixed_16_16_t downscale_amount;
4369
4370         /* Shouldn't reach here on disabled planes... */
4371         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
4372                 return 0;
4373
4374         /*
4375          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4376          * with additional adjustments for plane-specific scaling.
4377          */
4378         adjusted_pixel_rate = cstate->pixel_rate;
4379         downscale_amount = skl_plane_downscale_amount(cstate, pstate);
4380
4381         return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4382                                             downscale_amount);
4383 }
4384
4385 static int
4386 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
4387                             struct intel_crtc_state *cstate,
4388                             const struct intel_plane_state *intel_pstate,
4389                             struct skl_wm_params *wp)
4390 {
4391         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
4392         const struct drm_plane_state *pstate = &intel_pstate->base;
4393         const struct drm_framebuffer *fb = pstate->fb;
4394         uint32_t interm_pbpl;
4395         struct intel_atomic_state *state =
4396                 to_intel_atomic_state(cstate->base.state);
4397         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4398
4399         if (!intel_wm_plane_visible(cstate, intel_pstate))
4400                 return 0;
4401
4402         wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
4403                       fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
4404                       fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4405                       fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4406         wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
4407         wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4408                          fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4409
4410         if (plane->id == PLANE_CURSOR) {
4411                 wp->width = intel_pstate->base.crtc_w;
4412         } else {
4413                 /*
4414                  * Src coordinates are already rotated by 270 degrees for
4415                  * the 90/270 degree plane rotation cases (to match the
4416                  * GTT mapping), hence no need to account for rotation here.
4417                  */
4418                 wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
4419         }
4420
4421         wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
4422                                                             fb->format->cpp[0];
4423         wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
4424                                                              intel_pstate);
4425
4426         if (drm_rotation_90_or_270(pstate->rotation)) {
4427
4428                 switch (wp->cpp) {
4429                 case 1:
4430                         wp->y_min_scanlines = 16;
4431                         break;
4432                 case 2:
4433                         wp->y_min_scanlines = 8;
4434                         break;
4435                 case 4:
4436                         wp->y_min_scanlines = 4;
4437                         break;
4438                 default:
4439                         MISSING_CASE(wp->cpp);
4440                         return -EINVAL;
4441                 }
4442         } else {
4443                 wp->y_min_scanlines = 4;
4444         }
4445
4446         if (apply_memory_bw_wa)
4447                 wp->y_min_scanlines *= 2;
4448
4449         wp->plane_bytes_per_line = wp->width * wp->cpp;
4450         if (wp->y_tiled) {
4451                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
4452                                            wp->y_min_scanlines, 512);
4453
4454                 if (INTEL_GEN(dev_priv) >= 10)
4455                         interm_pbpl++;
4456
4457                 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
4458                                                         wp->y_min_scanlines);
4459         } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
4460                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
4461                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4462         } else {
4463                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
4464                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4465         }
4466
4467         wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
4468                                              wp->plane_blocks_per_line);
4469         wp->linetime_us = fixed16_to_u32_round_up(
4470                                         intel_get_linetime_us(cstate));
4471
4472         return 0;
4473 }
4474
4475 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4476                                 struct intel_crtc_state *cstate,
4477                                 const struct intel_plane_state *intel_pstate,
4478                                 uint16_t ddb_allocation,
4479                                 int level,
4480                                 const struct skl_wm_params *wp,
4481                                 uint16_t *out_blocks, /* out */
4482                                 uint8_t *out_lines, /* out */
4483                                 bool *enabled /* out */)
4484 {
4485         const struct drm_plane_state *pstate = &intel_pstate->base;
4486         uint32_t latency = dev_priv->wm.skl_latency[level];
4487         uint_fixed_16_16_t method1, method2;
4488         uint_fixed_16_16_t selected_result;
4489         uint32_t res_blocks, res_lines;
4490         struct intel_atomic_state *state =
4491                 to_intel_atomic_state(cstate->base.state);
4492         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4493
4494         if (latency == 0 ||
4495             !intel_wm_plane_visible(cstate, intel_pstate)) {
4496                 *enabled = false;
4497                 return 0;
4498         }
4499
4500         /* Display WA #1141: kbl,cfl */
4501         if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
4502             IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
4503             dev_priv->ipc_enabled)
4504                 latency += 4;
4505
4506         if (apply_memory_bw_wa && wp->x_tiled)
4507                 latency += 15;
4508
4509         method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
4510                                  wp->cpp, latency);
4511         method2 = skl_wm_method2(wp->plane_pixel_rate,
4512                                  cstate->base.adjusted_mode.crtc_htotal,
4513                                  latency,
4514                                  wp->plane_blocks_per_line);
4515
4516         if (wp->y_tiled) {
4517                 selected_result = max_fixed16(method2, wp->y_tile_minimum);
4518         } else {
4519                 if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
4520                      512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
4521                         selected_result = method2;
4522                 else if (ddb_allocation >=
4523                          fixed16_to_u32_round_up(wp->plane_blocks_per_line))
4524                         selected_result = min_fixed16(method1, method2);
4525                 else if (latency >= wp->linetime_us)
4526                         selected_result = min_fixed16(method1, method2);
4527                 else
4528                         selected_result = method1;
4529         }
4530
4531         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
4532         res_lines = div_round_up_fixed16(selected_result,
4533                                          wp->plane_blocks_per_line);
4534
4535         /* Display WA #1125: skl,bxt,kbl,glk */
4536         if (level == 0 && wp->rc_surface)
4537                 res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
4538
4539         /* Display WA #1126: skl,bxt,kbl,glk */
4540         if (level >= 1 && level <= 7) {
4541                 if (wp->y_tiled) {
4542                         res_blocks += fixed16_to_u32_round_up(
4543                                                         wp->y_tile_minimum);
4544                         res_lines += wp->y_min_scanlines;
4545                 } else {
4546                         res_blocks++;
4547                 }
4548         }
4549
4550         if (res_blocks >= ddb_allocation || res_lines > 31) {
4551                 *enabled = false;
4552
4553                 /*
4554                  * If there are no valid level 0 watermarks, then we can't
4555                  * support this display configuration.
4556                  */
4557                 if (level) {
4558                         return 0;
4559                 } else {
4560                         struct drm_plane *plane = pstate->plane;
4561
4562                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4563                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4564                                       plane->base.id, plane->name,
4565                                       res_blocks, ddb_allocation, res_lines);
4566                         return -EINVAL;
4567                 }
4568         }
4569
4570         *out_blocks = res_blocks;
4571         *out_lines = res_lines;
4572         *enabled = true;
4573
4574         return 0;
4575 }
4576
4577 static int
4578 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
4579                       struct skl_ddb_allocation *ddb,
4580                       struct intel_crtc_state *cstate,
4581                       const struct intel_plane_state *intel_pstate,
4582                       const struct skl_wm_params *wm_params,
4583                       struct skl_plane_wm *wm)
4584 {
4585         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4586         struct drm_plane *plane = intel_pstate->base.plane;
4587         struct intel_plane *intel_plane = to_intel_plane(plane);
4588         uint16_t ddb_blocks;
4589         enum pipe pipe = intel_crtc->pipe;
4590         int level, max_level = ilk_wm_max_level(dev_priv);
4591         int ret;
4592
4593         if (WARN_ON(!intel_pstate->base.fb))
4594                 return -EINVAL;
4595
4596         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
4597
4598         for (level = 0; level <= max_level; level++) {
4599                 struct skl_wm_level *result = &wm->wm[level];
4600
4601                 ret = skl_compute_plane_wm(dev_priv,
4602                                            cstate,
4603                                            intel_pstate,
4604                                            ddb_blocks,
4605                                            level,
4606                                            wm_params,
4607                                            &result->plane_res_b,
4608                                            &result->plane_res_l,
4609                                            &result->plane_en);
4610                 if (ret)
4611                         return ret;
4612         }
4613
4614         return 0;
4615 }
4616
4617 static uint32_t
4618 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
4619 {
4620         struct drm_atomic_state *state = cstate->base.state;
4621         struct drm_i915_private *dev_priv = to_i915(state->dev);
4622         uint_fixed_16_16_t linetime_us;
4623         uint32_t linetime_wm;
4624
4625         linetime_us = intel_get_linetime_us(cstate);
4626
4627         if (is_fixed16_zero(linetime_us))
4628                 return 0;
4629
4630         linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
4631
4632         /* Display WA #1135: bxt:ALL GLK:ALL */
4633         if ((IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) &&
4634             dev_priv->ipc_enabled)
4635                 linetime_wm /= 2;
4636
4637         return linetime_wm;
4638 }
4639
4640 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
4641                                       struct skl_wm_params *wp,
4642                                       struct skl_wm_level *wm_l0,
4643                                       uint16_t ddb_allocation,
4644                                       struct skl_wm_level *trans_wm /* out */)
4645 {
4646         struct drm_device *dev = cstate->base.crtc->dev;
4647         const struct drm_i915_private *dev_priv = to_i915(dev);
4648         uint16_t trans_min, trans_y_tile_min;
4649         const uint16_t trans_amount = 10; /* This is configurable amount */
4650         uint16_t trans_offset_b, res_blocks;
4651
4652         if (!cstate->base.active)
4653                 goto exit;
4654
4655         /* Transition WM are not recommended by HW team for GEN9 */
4656         if (INTEL_GEN(dev_priv) <= 9)
4657                 goto exit;
4658
4659         /* Transition WM don't make any sense if ipc is disabled */
4660         if (!dev_priv->ipc_enabled)
4661                 goto exit;
4662
4663         if (INTEL_GEN(dev_priv) >= 10)
4664                 trans_min = 4;
4665
4666         trans_offset_b = trans_min + trans_amount;
4667
4668         if (wp->y_tiled) {
4669                 trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
4670                                                         wp->y_tile_minimum);
4671                 res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) +
4672                                 trans_offset_b;
4673         } else {
4674                 res_blocks = wm_l0->plane_res_b + trans_offset_b;
4675
4676                 /* WA BUG:1938466 add one block for non y-tile planes */
4677                 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
4678                         res_blocks += 1;
4679
4680         }
4681
4682         res_blocks += 1;
4683
4684         if (res_blocks < ddb_allocation) {
4685                 trans_wm->plane_res_b = res_blocks;
4686                 trans_wm->plane_en = true;
4687                 return;
4688         }
4689
4690 exit:
4691         trans_wm->plane_en = false;
4692 }
4693
4694 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
4695                              struct skl_ddb_allocation *ddb,
4696                              struct skl_pipe_wm *pipe_wm)
4697 {
4698         struct drm_device *dev = cstate->base.crtc->dev;
4699         struct drm_crtc_state *crtc_state = &cstate->base;
4700         const struct drm_i915_private *dev_priv = to_i915(dev);
4701         struct drm_plane *plane;
4702         const struct drm_plane_state *pstate;
4703         struct skl_plane_wm *wm;
4704         int ret;
4705
4706         /*
4707          * We'll only calculate watermarks for planes that are actually
4708          * enabled, so make sure all other planes are set as disabled.
4709          */
4710         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
4711
4712         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
4713                 const struct intel_plane_state *intel_pstate =
4714                                                 to_intel_plane_state(pstate);
4715                 enum plane_id plane_id = to_intel_plane(plane)->id;
4716                 struct skl_wm_params wm_params;
4717                 enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
4718                 uint16_t ddb_blocks;
4719
4720                 wm = &pipe_wm->planes[plane_id];
4721                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
4722                 memset(&wm_params, 0, sizeof(struct skl_wm_params));
4723
4724                 ret = skl_compute_plane_wm_params(dev_priv, cstate,
4725                                                   intel_pstate, &wm_params);
4726                 if (ret)
4727                         return ret;
4728
4729                 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4730                                             intel_pstate, &wm_params, wm);
4731                 if (ret)
4732                         return ret;
4733                 skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
4734                                           ddb_blocks, &wm->trans_wm);
4735         }
4736         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
4737
4738         return 0;
4739 }
4740
4741 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
4742                                 i915_reg_t reg,
4743                                 const struct skl_ddb_entry *entry)
4744 {
4745         if (entry->end)
4746                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
4747         else
4748                 I915_WRITE(reg, 0);
4749 }
4750
4751 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
4752                                i915_reg_t reg,
4753                                const struct skl_wm_level *level)
4754 {
4755         uint32_t val = 0;
4756
4757         if (level->plane_en) {
4758                 val |= PLANE_WM_EN;
4759                 val |= level->plane_res_b;
4760                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
4761         }
4762
4763         I915_WRITE(reg, val);
4764 }
4765
4766 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
4767                                const struct skl_plane_wm *wm,
4768                                const struct skl_ddb_allocation *ddb,
4769                                enum plane_id plane_id)
4770 {
4771         struct drm_crtc *crtc = &intel_crtc->base;
4772         struct drm_device *dev = crtc->dev;
4773         struct drm_i915_private *dev_priv = to_i915(dev);
4774         int level, max_level = ilk_wm_max_level(dev_priv);
4775         enum pipe pipe = intel_crtc->pipe;
4776
4777         for (level = 0; level <= max_level; level++) {
4778                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
4779                                    &wm->wm[level]);
4780         }
4781         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
4782                            &wm->trans_wm);
4783
4784         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4785                             &ddb->plane[pipe][plane_id]);
4786         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
4787                             &ddb->y_plane[pipe][plane_id]);
4788 }
4789
4790 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
4791                                 const struct skl_plane_wm *wm,
4792                                 const struct skl_ddb_allocation *ddb)
4793 {
4794         struct drm_crtc *crtc = &intel_crtc->base;
4795         struct drm_device *dev = crtc->dev;
4796         struct drm_i915_private *dev_priv = to_i915(dev);
4797         int level, max_level = ilk_wm_max_level(dev_priv);
4798         enum pipe pipe = intel_crtc->pipe;
4799
4800         for (level = 0; level <= max_level; level++) {
4801                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
4802                                    &wm->wm[level]);
4803         }
4804         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
4805
4806         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4807                             &ddb->plane[pipe][PLANE_CURSOR]);
4808 }
4809
4810 bool skl_wm_level_equals(const struct skl_wm_level *l1,
4811                          const struct skl_wm_level *l2)
4812 {
4813         if (l1->plane_en != l2->plane_en)
4814                 return false;
4815
4816         /* If both planes aren't enabled, the rest shouldn't matter */
4817         if (!l1->plane_en)
4818                 return true;
4819
4820         return (l1->plane_res_l == l2->plane_res_l &&
4821                 l1->plane_res_b == l2->plane_res_b);
4822 }
4823
4824 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
4825                                            const struct skl_ddb_entry *b)
4826 {
4827         return a->start < b->end && b->start < a->end;
4828 }
4829
4830 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
4831                                  const struct skl_ddb_entry **entries,
4832                                  const struct skl_ddb_entry *ddb,
4833                                  int ignore)
4834 {
4835         enum pipe pipe;
4836
4837         for_each_pipe(dev_priv, pipe) {
4838                 if (pipe != ignore && entries[pipe] &&
4839                     skl_ddb_entries_overlap(ddb, entries[pipe]))
4840                         return true;
4841         }
4842
4843         return false;
4844 }
4845
4846 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
4847                               const struct skl_pipe_wm *old_pipe_wm,
4848                               struct skl_pipe_wm *pipe_wm, /* out */
4849                               struct skl_ddb_allocation *ddb, /* out */
4850                               bool *changed /* out */)
4851 {
4852         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
4853         int ret;
4854
4855         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
4856         if (ret)
4857                 return ret;
4858
4859         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
4860                 *changed = false;
4861         else
4862                 *changed = true;
4863
4864         return 0;
4865 }
4866
4867 static uint32_t
4868 pipes_modified(struct drm_atomic_state *state)
4869 {
4870         struct drm_crtc *crtc;
4871         struct drm_crtc_state *cstate;
4872         uint32_t i, ret = 0;
4873
4874         for_each_new_crtc_in_state(state, crtc, cstate, i)
4875                 ret |= drm_crtc_mask(crtc);
4876
4877         return ret;
4878 }
4879
4880 static int
4881 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
4882 {
4883         struct drm_atomic_state *state = cstate->base.state;
4884         struct drm_device *dev = state->dev;
4885         struct drm_crtc *crtc = cstate->base.crtc;
4886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887         struct drm_i915_private *dev_priv = to_i915(dev);
4888         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4889         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4890         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4891         struct drm_plane_state *plane_state;
4892         struct drm_plane *plane;
4893         enum pipe pipe = intel_crtc->pipe;
4894
4895         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4896
4897         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
4898                 enum plane_id plane_id = to_intel_plane(plane)->id;
4899
4900                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
4901                                         &new_ddb->plane[pipe][plane_id]) &&
4902                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
4903                                         &new_ddb->y_plane[pipe][plane_id]))
4904                         continue;
4905
4906                 plane_state = drm_atomic_get_plane_state(state, plane);
4907                 if (IS_ERR(plane_state))
4908                         return PTR_ERR(plane_state);
4909         }
4910
4911         return 0;
4912 }
4913
4914 static int
4915 skl_compute_ddb(struct drm_atomic_state *state)
4916 {
4917         struct drm_device *dev = state->dev;
4918         struct drm_i915_private *dev_priv = to_i915(dev);
4919         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4920         struct intel_crtc *intel_crtc;
4921         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4922         uint32_t realloc_pipes = pipes_modified(state);
4923         int ret;
4924
4925         /*
4926          * If this is our first atomic update following hardware readout,
4927          * we can't trust the DDB that the BIOS programmed for us.  Let's
4928          * pretend that all pipes switched active status so that we'll
4929          * ensure a full DDB recompute.
4930          */
4931         if (dev_priv->wm.distrust_bios_wm) {
4932                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4933                                        state->acquire_ctx);
4934                 if (ret)
4935                         return ret;
4936
4937                 intel_state->active_pipe_changes = ~0;
4938
4939                 /*
4940                  * We usually only initialize intel_state->active_crtcs if we
4941                  * we're doing a modeset; make sure this field is always
4942                  * initialized during the sanitization process that happens
4943                  * on the first commit too.
4944                  */
4945                 if (!intel_state->modeset)
4946                         intel_state->active_crtcs = dev_priv->active_crtcs;
4947         }
4948
4949         /*
4950          * If the modeset changes which CRTC's are active, we need to
4951          * recompute the DDB allocation for *all* active pipes, even
4952          * those that weren't otherwise being modified in any way by this
4953          * atomic commit.  Due to the shrinking of the per-pipe allocations
4954          * when new active CRTC's are added, it's possible for a pipe that
4955          * we were already using and aren't changing at all here to suddenly
4956          * become invalid if its DDB needs exceeds its new allocation.
4957          *
4958          * Note that if we wind up doing a full DDB recompute, we can't let
4959          * any other display updates race with this transaction, so we need
4960          * to grab the lock on *all* CRTC's.
4961          */
4962         if (intel_state->active_pipe_changes) {
4963                 realloc_pipes = ~0;
4964                 intel_state->wm_results.dirty_pipes = ~0;
4965         }
4966
4967         /*
4968          * We're not recomputing for the pipes not included in the commit, so
4969          * make sure we start with the current state.
4970          */
4971         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4972
4973         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4974                 struct intel_crtc_state *cstate;
4975
4976                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4977                 if (IS_ERR(cstate))
4978                         return PTR_ERR(cstate);
4979
4980                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4981                 if (ret)
4982                         return ret;
4983
4984                 ret = skl_ddb_add_affected_planes(cstate);
4985                 if (ret)
4986                         return ret;
4987         }
4988
4989         return 0;
4990 }
4991
4992 static void
4993 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4994                      struct skl_wm_values *src,
4995                      enum pipe pipe)
4996 {
4997         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4998                sizeof(dst->ddb.y_plane[pipe]));
4999         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
5000                sizeof(dst->ddb.plane[pipe]));
5001 }
5002
5003 static void
5004 skl_print_wm_changes(const struct drm_atomic_state *state)
5005 {
5006         const struct drm_device *dev = state->dev;
5007         const struct drm_i915_private *dev_priv = to_i915(dev);
5008         const struct intel_atomic_state *intel_state =
5009                 to_intel_atomic_state(state);
5010         const struct drm_crtc *crtc;
5011         const struct drm_crtc_state *cstate;
5012         const struct intel_plane *intel_plane;
5013         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
5014         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
5015         int i;
5016
5017         for_each_new_crtc_in_state(state, crtc, cstate, i) {
5018                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5019                 enum pipe pipe = intel_crtc->pipe;
5020
5021                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
5022                         enum plane_id plane_id = intel_plane->id;
5023                         const struct skl_ddb_entry *old, *new;
5024
5025                         old = &old_ddb->plane[pipe][plane_id];
5026                         new = &new_ddb->plane[pipe][plane_id];
5027
5028                         if (skl_ddb_entry_equal(old, new))
5029                                 continue;
5030
5031                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
5032                                          intel_plane->base.base.id,
5033                                          intel_plane->base.name,
5034                                          old->start, old->end,
5035                                          new->start, new->end);
5036                 }
5037         }
5038 }
5039
5040 static int
5041 skl_compute_wm(struct drm_atomic_state *state)
5042 {
5043         struct drm_crtc *crtc;
5044         struct drm_crtc_state *cstate;
5045         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5046         struct skl_wm_values *results = &intel_state->wm_results;
5047         struct drm_device *dev = state->dev;
5048         struct skl_pipe_wm *pipe_wm;
5049         bool changed = false;
5050         int ret, i;
5051
5052         /*
5053          * When we distrust bios wm we always need to recompute to set the
5054          * expected DDB allocations for each CRTC.
5055          */
5056         if (to_i915(dev)->wm.distrust_bios_wm)
5057                 changed = true;
5058
5059         /*
5060          * If this transaction isn't actually touching any CRTC's, don't
5061          * bother with watermark calculation.  Note that if we pass this
5062          * test, we're guaranteed to hold at least one CRTC state mutex,
5063          * which means we can safely use values like dev_priv->active_crtcs
5064          * since any racing commits that want to update them would need to
5065          * hold _all_ CRTC state mutexes.
5066          */
5067         for_each_new_crtc_in_state(state, crtc, cstate, i)
5068                 changed = true;
5069
5070         if (!changed)
5071                 return 0;
5072
5073         /* Clear all dirty flags */
5074         results->dirty_pipes = 0;
5075
5076         ret = skl_compute_ddb(state);
5077         if (ret)
5078                 return ret;
5079
5080         /*
5081          * Calculate WM's for all pipes that are part of this transaction.
5082          * Note that the DDB allocation above may have added more CRTC's that
5083          * weren't otherwise being modified (and set bits in dirty_pipes) if
5084          * pipe allocations had to change.
5085          *
5086          * FIXME:  Now that we're doing this in the atomic check phase, we
5087          * should allow skl_update_pipe_wm() to return failure in cases where
5088          * no suitable watermark values can be found.
5089          */
5090         for_each_new_crtc_in_state(state, crtc, cstate, i) {
5091                 struct intel_crtc_state *intel_cstate =
5092                         to_intel_crtc_state(cstate);
5093                 const struct skl_pipe_wm *old_pipe_wm =
5094                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
5095
5096                 pipe_wm = &intel_cstate->wm.skl.optimal;
5097                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
5098                                          &results->ddb, &changed);
5099                 if (ret)
5100                         return ret;
5101
5102                 if (changed)
5103                         results->dirty_pipes |= drm_crtc_mask(crtc);
5104
5105                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
5106                         /* This pipe's WM's did not change */
5107                         continue;
5108
5109                 intel_cstate->update_wm_pre = true;
5110         }
5111
5112         skl_print_wm_changes(state);
5113
5114         return 0;
5115 }
5116
5117 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
5118                                       struct intel_crtc_state *cstate)
5119 {
5120         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
5121         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5122         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
5123         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5124         enum pipe pipe = crtc->pipe;
5125         enum plane_id plane_id;
5126
5127         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5128                 return;
5129
5130         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5131
5132         for_each_plane_id_on_crtc(crtc, plane_id) {
5133                 if (plane_id != PLANE_CURSOR)
5134                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
5135                                            ddb, plane_id);
5136                 else
5137                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
5138                                             ddb);
5139         }
5140 }
5141
5142 static void skl_initial_wm(struct intel_atomic_state *state,
5143                            struct intel_crtc_state *cstate)
5144 {
5145         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5146         struct drm_device *dev = intel_crtc->base.dev;
5147         struct drm_i915_private *dev_priv = to_i915(dev);
5148         struct skl_wm_values *results = &state->wm_results;
5149         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
5150         enum pipe pipe = intel_crtc->pipe;
5151
5152         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5153                 return;
5154
5155         mutex_lock(&dev_priv->wm.wm_mutex);
5156
5157         if (cstate->base.active_changed)
5158                 skl_atomic_update_crtc_wm(state, cstate);
5159
5160         skl_copy_wm_for_pipe(hw_vals, results, pipe);
5161
5162         mutex_unlock(&dev_priv->wm.wm_mutex);
5163 }
5164
5165 static void ilk_compute_wm_config(struct drm_device *dev,
5166                                   struct intel_wm_config *config)
5167 {
5168         struct intel_crtc *crtc;
5169
5170         /* Compute the currently _active_ config */
5171         for_each_intel_crtc(dev, crtc) {
5172                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5173
5174                 if (!wm->pipe_enabled)
5175                         continue;
5176
5177                 config->sprites_enabled |= wm->sprites_enabled;
5178                 config->sprites_scaled |= wm->sprites_scaled;
5179                 config->num_pipes_active++;
5180         }
5181 }
5182
5183 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5184 {
5185         struct drm_device *dev = &dev_priv->drm;
5186         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5187         struct ilk_wm_maximums max;
5188         struct intel_wm_config config = {};
5189         struct ilk_wm_values results = {};
5190         enum intel_ddb_partitioning partitioning;
5191
5192         ilk_compute_wm_config(dev, &config);
5193
5194         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
5195         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
5196
5197         /* 5/6 split only in single pipe config on IVB+ */
5198         if (INTEL_GEN(dev_priv) >= 7 &&
5199             config.num_pipes_active == 1 && config.sprites_enabled) {
5200                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
5201                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
5202
5203                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
5204         } else {
5205                 best_lp_wm = &lp_wm_1_2;
5206         }
5207
5208         partitioning = (best_lp_wm == &lp_wm_1_2) ?
5209                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5210
5211         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
5212
5213         ilk_write_wm_values(dev_priv, &results);
5214 }
5215
5216 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5217                                    struct intel_crtc_state *cstate)
5218 {
5219         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5220         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5221
5222         mutex_lock(&dev_priv->wm.wm_mutex);
5223         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
5224         ilk_program_watermarks(dev_priv);
5225         mutex_unlock(&dev_priv->wm.wm_mutex);
5226 }
5227
5228 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5229                                     struct intel_crtc_state *cstate)
5230 {
5231         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5232         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5233
5234         mutex_lock(&dev_priv->wm.wm_mutex);
5235         if (cstate->wm.need_postvbl_update) {
5236                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
5237                 ilk_program_watermarks(dev_priv);
5238         }
5239         mutex_unlock(&dev_priv->wm.wm_mutex);
5240 }
5241
5242 static inline void skl_wm_level_from_reg_val(uint32_t val,
5243                                              struct skl_wm_level *level)
5244 {
5245         level->plane_en = val & PLANE_WM_EN;
5246         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5247         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5248                 PLANE_WM_LINES_MASK;
5249 }
5250
5251 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
5252                               struct skl_pipe_wm *out)
5253 {
5254         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5256         enum pipe pipe = intel_crtc->pipe;
5257         int level, max_level;
5258         enum plane_id plane_id;
5259         uint32_t val;
5260
5261         max_level = ilk_wm_max_level(dev_priv);
5262
5263         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
5264                 struct skl_plane_wm *wm = &out->planes[plane_id];
5265
5266                 for (level = 0; level <= max_level; level++) {
5267                         if (plane_id != PLANE_CURSOR)
5268                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5269                         else
5270                                 val = I915_READ(CUR_WM(pipe, level));
5271
5272                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
5273                 }
5274
5275                 if (plane_id != PLANE_CURSOR)
5276                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5277                 else
5278                         val = I915_READ(CUR_WM_TRANS(pipe));
5279
5280                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5281         }
5282
5283         if (!intel_crtc->active)
5284                 return;
5285
5286         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5287 }
5288
5289 void skl_wm_get_hw_state(struct drm_device *dev)
5290 {
5291         struct drm_i915_private *dev_priv = to_i915(dev);
5292         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
5293         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5294         struct drm_crtc *crtc;
5295         struct intel_crtc *intel_crtc;
5296         struct intel_crtc_state *cstate;
5297
5298         skl_ddb_get_hw_state(dev_priv, ddb);
5299         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5300                 intel_crtc = to_intel_crtc(crtc);
5301                 cstate = to_intel_crtc_state(crtc->state);
5302
5303                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
5304
5305                 if (intel_crtc->active)
5306                         hw->dirty_pipes |= drm_crtc_mask(crtc);
5307         }
5308
5309         if (dev_priv->active_crtcs) {
5310                 /* Fully recompute DDB on first atomic commit */
5311                 dev_priv->wm.distrust_bios_wm = true;
5312         } else {
5313                 /* Easy/common case; just sanitize DDB now if everything off */
5314                 memset(ddb, 0, sizeof(*ddb));
5315         }
5316 }
5317
5318 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
5319 {
5320         struct drm_device *dev = crtc->dev;
5321         struct drm_i915_private *dev_priv = to_i915(dev);
5322         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5324         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
5325         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
5326         enum pipe pipe = intel_crtc->pipe;
5327         static const i915_reg_t wm0_pipe_reg[] = {
5328                 [PIPE_A] = WM0_PIPEA_ILK,
5329                 [PIPE_B] = WM0_PIPEB_ILK,
5330                 [PIPE_C] = WM0_PIPEC_IVB,
5331         };
5332
5333         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5334         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5335                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5336
5337         memset(active, 0, sizeof(*active));
5338
5339         active->pipe_enabled = intel_crtc->active;
5340
5341         if (active->pipe_enabled) {
5342                 u32 tmp = hw->wm_pipe[pipe];
5343
5344                 /*
5345                  * For active pipes LP0 watermark is marked as
5346                  * enabled, and LP1+ watermaks as disabled since
5347                  * we can't really reverse compute them in case
5348                  * multiple pipes are active.
5349                  */
5350                 active->wm[0].enable = true;
5351                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5352                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5353                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5354                 active->linetime = hw->wm_linetime[pipe];
5355         } else {
5356                 int level, max_level = ilk_wm_max_level(dev_priv);
5357
5358                 /*
5359                  * For inactive pipes, all watermark levels
5360                  * should be marked as enabled but zeroed,
5361                  * which is what we'd compute them to.
5362                  */
5363                 for (level = 0; level <= max_level; level++)
5364                         active->wm[level].enable = true;
5365         }
5366
5367         intel_crtc->wm.active.ilk = *active;
5368 }
5369
5370 #define _FW_WM(value, plane) \
5371         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5372 #define _FW_WM_VLV(value, plane) \
5373         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5374
5375 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5376                                struct g4x_wm_values *wm)
5377 {
5378         uint32_t tmp;
5379
5380         tmp = I915_READ(DSPFW1);
5381         wm->sr.plane = _FW_WM(tmp, SR);
5382         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5383         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5384         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5385
5386         tmp = I915_READ(DSPFW2);
5387         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5388         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5389         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5390         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5391         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5392         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5393
5394         tmp = I915_READ(DSPFW3);
5395         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5396         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5397         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5398         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5399 }
5400
5401 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5402                                struct vlv_wm_values *wm)
5403 {
5404         enum pipe pipe;
5405         uint32_t tmp;
5406
5407         for_each_pipe(dev_priv, pipe) {
5408                 tmp = I915_READ(VLV_DDL(pipe));
5409
5410                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5411                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5412                 wm->ddl[pipe].plane[PLANE_CURSOR] =
5413                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5414                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5415                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5416                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5417                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5418         }
5419
5420         tmp = I915_READ(DSPFW1);
5421         wm->sr.plane = _FW_WM(tmp, SR);
5422         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5423         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5424         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5425
5426         tmp = I915_READ(DSPFW2);
5427         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5428         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5429         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5430
5431         tmp = I915_READ(DSPFW3);
5432         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5433
5434         if (IS_CHERRYVIEW(dev_priv)) {
5435                 tmp = I915_READ(DSPFW7_CHV);
5436                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5437                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5438
5439                 tmp = I915_READ(DSPFW8_CHV);
5440                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5441                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5442
5443                 tmp = I915_READ(DSPFW9_CHV);
5444                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5445                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5446
5447                 tmp = I915_READ(DSPHOWM);
5448                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5449                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5450                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5451                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5452                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5453                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5454                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5455                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5456                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5457                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5458         } else {
5459                 tmp = I915_READ(DSPFW7);
5460                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5461                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5462
5463                 tmp = I915_READ(DSPHOWM);
5464                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5465                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5466                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5467                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5468                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5469                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5470                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5471         }
5472 }
5473
5474 #undef _FW_WM
5475 #undef _FW_WM_VLV
5476
5477 void g4x_wm_get_hw_state(struct drm_device *dev)
5478 {
5479         struct drm_i915_private *dev_priv = to_i915(dev);
5480         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5481         struct intel_crtc *crtc;
5482
5483         g4x_read_wm_values(dev_priv, wm);
5484
5485         wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5486
5487         for_each_intel_crtc(dev, crtc) {
5488                 struct intel_crtc_state *crtc_state =
5489                         to_intel_crtc_state(crtc->base.state);
5490                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5491                 struct g4x_pipe_wm *raw;
5492                 enum pipe pipe = crtc->pipe;
5493                 enum plane_id plane_id;
5494                 int level, max_level;
5495
5496                 active->cxsr = wm->cxsr;
5497                 active->hpll_en = wm->hpll_en;
5498                 active->fbc_en = wm->fbc_en;
5499
5500                 active->sr = wm->sr;
5501                 active->hpll = wm->hpll;
5502
5503                 for_each_plane_id_on_crtc(crtc, plane_id) {
5504                         active->wm.plane[plane_id] =
5505                                 wm->pipe[pipe].plane[plane_id];
5506                 }
5507
5508                 if (wm->cxsr && wm->hpll_en)
5509                         max_level = G4X_WM_LEVEL_HPLL;
5510                 else if (wm->cxsr)
5511                         max_level = G4X_WM_LEVEL_SR;
5512                 else
5513                         max_level = G4X_WM_LEVEL_NORMAL;
5514
5515                 level = G4X_WM_LEVEL_NORMAL;
5516                 raw = &crtc_state->wm.g4x.raw[level];
5517                 for_each_plane_id_on_crtc(crtc, plane_id)
5518                         raw->plane[plane_id] = active->wm.plane[plane_id];
5519
5520                 if (++level > max_level)
5521                         goto out;
5522
5523                 raw = &crtc_state->wm.g4x.raw[level];
5524                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
5525                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
5526                 raw->plane[PLANE_SPRITE0] = 0;
5527                 raw->fbc = active->sr.fbc;
5528
5529                 if (++level > max_level)
5530                         goto out;
5531
5532                 raw = &crtc_state->wm.g4x.raw[level];
5533                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
5534                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
5535                 raw->plane[PLANE_SPRITE0] = 0;
5536                 raw->fbc = active->hpll.fbc;
5537
5538         out:
5539                 for_each_plane_id_on_crtc(crtc, plane_id)
5540                         g4x_raw_plane_wm_set(crtc_state, level,
5541                                              plane_id, USHRT_MAX);
5542                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
5543
5544                 crtc_state->wm.g4x.optimal = *active;
5545                 crtc_state->wm.g4x.intermediate = *active;
5546
5547                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5548                               pipe_name(pipe),
5549                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5550                               wm->pipe[pipe].plane[PLANE_CURSOR],
5551                               wm->pipe[pipe].plane[PLANE_SPRITE0]);
5552         }
5553
5554         DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5555                       wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
5556         DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5557                       wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5558         DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5559                       yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
5560 }
5561
5562 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
5563 {
5564         struct intel_plane *plane;
5565         struct intel_crtc *crtc;
5566
5567         mutex_lock(&dev_priv->wm.wm_mutex);
5568
5569         for_each_intel_plane(&dev_priv->drm, plane) {
5570                 struct intel_crtc *crtc =
5571                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5572                 struct intel_crtc_state *crtc_state =
5573                         to_intel_crtc_state(crtc->base.state);
5574                 struct intel_plane_state *plane_state =
5575                         to_intel_plane_state(plane->base.state);
5576                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
5577                 enum plane_id plane_id = plane->id;
5578                 int level;
5579
5580                 if (plane_state->base.visible)
5581                         continue;
5582
5583                 for (level = 0; level < 3; level++) {
5584                         struct g4x_pipe_wm *raw =
5585                                 &crtc_state->wm.g4x.raw[level];
5586
5587                         raw->plane[plane_id] = 0;
5588                         wm_state->wm.plane[plane_id] = 0;
5589                 }
5590
5591                 if (plane_id == PLANE_PRIMARY) {
5592                         for (level = 0; level < 3; level++) {
5593                                 struct g4x_pipe_wm *raw =
5594                                         &crtc_state->wm.g4x.raw[level];
5595                                 raw->fbc = 0;
5596                         }
5597
5598                         wm_state->sr.fbc = 0;
5599                         wm_state->hpll.fbc = 0;
5600                         wm_state->fbc_en = false;
5601                 }
5602         }
5603
5604         for_each_intel_crtc(&dev_priv->drm, crtc) {
5605                 struct intel_crtc_state *crtc_state =
5606                         to_intel_crtc_state(crtc->base.state);
5607
5608                 crtc_state->wm.g4x.intermediate =
5609                         crtc_state->wm.g4x.optimal;
5610                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
5611         }
5612
5613         g4x_program_watermarks(dev_priv);
5614
5615         mutex_unlock(&dev_priv->wm.wm_mutex);
5616 }
5617
5618 void vlv_wm_get_hw_state(struct drm_device *dev)
5619 {
5620         struct drm_i915_private *dev_priv = to_i915(dev);
5621         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
5622         struct intel_crtc *crtc;
5623         u32 val;
5624
5625         vlv_read_wm_values(dev_priv, wm);
5626
5627         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5628         wm->level = VLV_WM_LEVEL_PM2;
5629
5630         if (IS_CHERRYVIEW(dev_priv)) {
5631                 mutex_lock(&dev_priv->pcu_lock);
5632
5633                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5634                 if (val & DSP_MAXFIFO_PM5_ENABLE)
5635                         wm->level = VLV_WM_LEVEL_PM5;
5636
5637                 /*
5638                  * If DDR DVFS is disabled in the BIOS, Punit
5639                  * will never ack the request. So if that happens
5640                  * assume we don't have to enable/disable DDR DVFS
5641                  * dynamically. To test that just set the REQ_ACK
5642                  * bit to poke the Punit, but don't change the
5643                  * HIGH/LOW bits so that we don't actually change
5644                  * the current state.
5645                  */
5646                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5647                 val |= FORCE_DDR_FREQ_REQ_ACK;
5648                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
5649
5650                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
5651                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
5652                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5653                                       "assuming DDR DVFS is disabled\n");
5654                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
5655                 } else {
5656                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5657                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
5658                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
5659                 }
5660
5661                 mutex_unlock(&dev_priv->pcu_lock);
5662         }
5663
5664         for_each_intel_crtc(dev, crtc) {
5665                 struct intel_crtc_state *crtc_state =
5666                         to_intel_crtc_state(crtc->base.state);
5667                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
5668                 const struct vlv_fifo_state *fifo_state =
5669                         &crtc_state->wm.vlv.fifo_state;
5670                 enum pipe pipe = crtc->pipe;
5671                 enum plane_id plane_id;
5672                 int level;
5673
5674                 vlv_get_fifo_size(crtc_state);
5675
5676                 active->num_levels = wm->level + 1;
5677                 active->cxsr = wm->cxsr;
5678
5679                 for (level = 0; level < active->num_levels; level++) {
5680                         struct g4x_pipe_wm *raw =
5681                                 &crtc_state->wm.vlv.raw[level];
5682
5683                         active->sr[level].plane = wm->sr.plane;
5684                         active->sr[level].cursor = wm->sr.cursor;
5685
5686                         for_each_plane_id_on_crtc(crtc, plane_id) {
5687                                 active->wm[level].plane[plane_id] =
5688                                         wm->pipe[pipe].plane[plane_id];
5689
5690                                 raw->plane[plane_id] =
5691                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
5692                                                             fifo_state->plane[plane_id]);
5693                         }
5694                 }
5695
5696                 for_each_plane_id_on_crtc(crtc, plane_id)
5697                         vlv_raw_plane_wm_set(crtc_state, level,
5698                                              plane_id, USHRT_MAX);
5699                 vlv_invalidate_wms(crtc, active, level);
5700
5701                 crtc_state->wm.vlv.optimal = *active;
5702                 crtc_state->wm.vlv.intermediate = *active;
5703
5704                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5705                               pipe_name(pipe),
5706                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5707                               wm->pipe[pipe].plane[PLANE_CURSOR],
5708                               wm->pipe[pipe].plane[PLANE_SPRITE0],
5709                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
5710         }
5711
5712         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5713                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
5714 }
5715
5716 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
5717 {
5718         struct intel_plane *plane;
5719         struct intel_crtc *crtc;
5720
5721         mutex_lock(&dev_priv->wm.wm_mutex);
5722
5723         for_each_intel_plane(&dev_priv->drm, plane) {
5724                 struct intel_crtc *crtc =
5725                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5726                 struct intel_crtc_state *crtc_state =
5727                         to_intel_crtc_state(crtc->base.state);
5728                 struct intel_plane_state *plane_state =
5729                         to_intel_plane_state(plane->base.state);
5730                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
5731                 const struct vlv_fifo_state *fifo_state =
5732                         &crtc_state->wm.vlv.fifo_state;
5733                 enum plane_id plane_id = plane->id;
5734                 int level;
5735
5736                 if (plane_state->base.visible)
5737                         continue;
5738
5739                 for (level = 0; level < wm_state->num_levels; level++) {
5740                         struct g4x_pipe_wm *raw =
5741                                 &crtc_state->wm.vlv.raw[level];
5742
5743                         raw->plane[plane_id] = 0;
5744
5745                         wm_state->wm[level].plane[plane_id] =
5746                                 vlv_invert_wm_value(raw->plane[plane_id],
5747                                                     fifo_state->plane[plane_id]);
5748                 }
5749         }
5750
5751         for_each_intel_crtc(&dev_priv->drm, crtc) {
5752                 struct intel_crtc_state *crtc_state =
5753                         to_intel_crtc_state(crtc->base.state);
5754
5755                 crtc_state->wm.vlv.intermediate =
5756                         crtc_state->wm.vlv.optimal;
5757                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
5758         }
5759
5760         vlv_program_watermarks(dev_priv);
5761
5762         mutex_unlock(&dev_priv->wm.wm_mutex);
5763 }
5764
5765 /*
5766  * FIXME should probably kill this and improve
5767  * the real watermark readout/sanitation instead
5768  */
5769 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
5770 {
5771         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5772         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5773         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5774
5775         /*
5776          * Don't touch WM1S_LP_EN here.
5777          * Doing so could cause underruns.
5778          */
5779 }
5780
5781 void ilk_wm_get_hw_state(struct drm_device *dev)
5782 {
5783         struct drm_i915_private *dev_priv = to_i915(dev);
5784         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5785         struct drm_crtc *crtc;
5786
5787         ilk_init_lp_watermarks(dev_priv);
5788
5789         for_each_crtc(dev, crtc)
5790                 ilk_pipe_wm_get_hw_state(crtc);
5791
5792         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
5793         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
5794         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
5795
5796         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
5797         if (INTEL_GEN(dev_priv) >= 7) {
5798                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
5799                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
5800         }
5801
5802         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5803                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
5804                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5805         else if (IS_IVYBRIDGE(dev_priv))
5806                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
5807                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5808
5809         hw->enable_fbc_wm =
5810                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
5811 }
5812
5813 /**
5814  * intel_update_watermarks - update FIFO watermark values based on current modes
5815  *
5816  * Calculate watermark values for the various WM regs based on current mode
5817  * and plane configuration.
5818  *
5819  * There are several cases to deal with here:
5820  *   - normal (i.e. non-self-refresh)
5821  *   - self-refresh (SR) mode
5822  *   - lines are large relative to FIFO size (buffer can hold up to 2)
5823  *   - lines are small relative to FIFO size (buffer can hold more than 2
5824  *     lines), so need to account for TLB latency
5825  *
5826  *   The normal calculation is:
5827  *     watermark = dotclock * bytes per pixel * latency
5828  *   where latency is platform & configuration dependent (we assume pessimal
5829  *   values here).
5830  *
5831  *   The SR calculation is:
5832  *     watermark = (trunc(latency/line time)+1) * surface width *
5833  *       bytes per pixel
5834  *   where
5835  *     line time = htotal / dotclock
5836  *     surface width = hdisplay for normal plane and 64 for cursor
5837  *   and latency is assumed to be high, as above.
5838  *
5839  * The final value programmed to the register should always be rounded up,
5840  * and include an extra 2 entries to account for clock crossings.
5841  *
5842  * We don't use the sprite, so we can ignore that.  And on Crestline we have
5843  * to set the non-SR watermarks to 8.
5844  */
5845 void intel_update_watermarks(struct intel_crtc *crtc)
5846 {
5847         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5848
5849         if (dev_priv->display.update_wm)
5850                 dev_priv->display.update_wm(crtc);
5851 }
5852
5853 void intel_enable_ipc(struct drm_i915_private *dev_priv)
5854 {
5855         u32 val;
5856
5857         /* Display WA #0477 WaDisableIPC: skl */
5858         if (IS_SKYLAKE(dev_priv)) {
5859                 dev_priv->ipc_enabled = false;
5860                 return;
5861         }
5862
5863         val = I915_READ(DISP_ARB_CTL2);
5864
5865         if (dev_priv->ipc_enabled)
5866                 val |= DISP_IPC_ENABLE;
5867         else
5868                 val &= ~DISP_IPC_ENABLE;
5869
5870         I915_WRITE(DISP_ARB_CTL2, val);
5871 }
5872
5873 void intel_init_ipc(struct drm_i915_private *dev_priv)
5874 {
5875         dev_priv->ipc_enabled = false;
5876         if (!HAS_IPC(dev_priv))
5877                 return;
5878
5879         dev_priv->ipc_enabled = true;
5880         intel_enable_ipc(dev_priv);
5881 }
5882
5883 /*
5884  * Lock protecting IPS related data structures
5885  */
5886 DEFINE_SPINLOCK(mchdev_lock);
5887
5888 /* Global for IPS driver to get at the current i915 device. Protected by
5889  * mchdev_lock. */
5890 static struct drm_i915_private *i915_mch_dev;
5891
5892 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
5893 {
5894         u16 rgvswctl;
5895
5896         lockdep_assert_held(&mchdev_lock);
5897
5898         rgvswctl = I915_READ16(MEMSWCTL);
5899         if (rgvswctl & MEMCTL_CMD_STS) {
5900                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5901                 return false; /* still busy with another command */
5902         }
5903
5904         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5905                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5906         I915_WRITE16(MEMSWCTL, rgvswctl);
5907         POSTING_READ16(MEMSWCTL);
5908
5909         rgvswctl |= MEMCTL_CMD_STS;
5910         I915_WRITE16(MEMSWCTL, rgvswctl);
5911
5912         return true;
5913 }
5914
5915 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
5916 {
5917         u32 rgvmodectl;
5918         u8 fmax, fmin, fstart, vstart;
5919
5920         spin_lock_irq(&mchdev_lock);
5921
5922         rgvmodectl = I915_READ(MEMMODECTL);
5923
5924         /* Enable temp reporting */
5925         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5926         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5927
5928         /* 100ms RC evaluation intervals */
5929         I915_WRITE(RCUPEI, 100000);
5930         I915_WRITE(RCDNEI, 100000);
5931
5932         /* Set max/min thresholds to 90ms and 80ms respectively */
5933         I915_WRITE(RCBMAXAVG, 90000);
5934         I915_WRITE(RCBMINAVG, 80000);
5935
5936         I915_WRITE(MEMIHYST, 1);
5937
5938         /* Set up min, max, and cur for interrupt handling */
5939         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5940         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5941         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5942                 MEMMODE_FSTART_SHIFT;
5943
5944         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
5945                 PXVFREQ_PX_SHIFT;
5946
5947         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
5948         dev_priv->ips.fstart = fstart;
5949
5950         dev_priv->ips.max_delay = fstart;
5951         dev_priv->ips.min_delay = fmin;
5952         dev_priv->ips.cur_delay = fstart;
5953
5954         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5955                          fmax, fmin, fstart);
5956
5957         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5958
5959         /*
5960          * Interrupts will be enabled in ironlake_irq_postinstall
5961          */
5962
5963         I915_WRITE(VIDSTART, vstart);
5964         POSTING_READ(VIDSTART);
5965
5966         rgvmodectl |= MEMMODE_SWMODE_EN;
5967         I915_WRITE(MEMMODECTL, rgvmodectl);
5968
5969         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5970                 DRM_ERROR("stuck trying to change perf mode\n");
5971         mdelay(1);
5972
5973         ironlake_set_drps(dev_priv, fstart);
5974
5975         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
5976                 I915_READ(DDREC) + I915_READ(CSIEC);
5977         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
5978         dev_priv->ips.last_count2 = I915_READ(GFXEC);
5979         dev_priv->ips.last_time2 = ktime_get_raw_ns();
5980
5981         spin_unlock_irq(&mchdev_lock);
5982 }
5983
5984 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
5985 {
5986         u16 rgvswctl;
5987
5988         spin_lock_irq(&mchdev_lock);
5989
5990         rgvswctl = I915_READ16(MEMSWCTL);
5991
5992         /* Ack interrupts, disable EFC interrupt */
5993         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5994         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5995         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5996         I915_WRITE(DEIIR, DE_PCU_EVENT);
5997         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5998
5999         /* Go back to the starting frequency */
6000         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
6001         mdelay(1);
6002         rgvswctl |= MEMCTL_CMD_STS;
6003         I915_WRITE(MEMSWCTL, rgvswctl);
6004         mdelay(1);
6005
6006         spin_unlock_irq(&mchdev_lock);
6007 }
6008
6009 /* There's a funny hw issue where the hw returns all 0 when reading from
6010  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
6011  * ourselves, instead of doing a rmw cycle (which might result in us clearing
6012  * all limits and the gpu stuck at whatever frequency it is at atm).
6013  */
6014 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
6015 {
6016         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6017         u32 limits;
6018
6019         /* Only set the down limit when we've reached the lowest level to avoid
6020          * getting more interrupts, otherwise leave this clear. This prevents a
6021          * race in the hw when coming out of rc6: There's a tiny window where
6022          * the hw runs at the minimal clock before selecting the desired
6023          * frequency, if the down threshold expires in that window we will not
6024          * receive a down interrupt. */
6025         if (INTEL_GEN(dev_priv) >= 9) {
6026                 limits = (rps->max_freq_softlimit) << 23;
6027                 if (val <= rps->min_freq_softlimit)
6028                         limits |= (rps->min_freq_softlimit) << 14;
6029         } else {
6030                 limits = rps->max_freq_softlimit << 24;
6031                 if (val <= rps->min_freq_softlimit)
6032                         limits |= rps->min_freq_softlimit << 16;
6033         }
6034
6035         return limits;
6036 }
6037
6038 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
6039 {
6040         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6041         int new_power;
6042         u32 threshold_up = 0, threshold_down = 0; /* in % */
6043         u32 ei_up = 0, ei_down = 0;
6044
6045         new_power = rps->power;
6046         switch (rps->power) {
6047         case LOW_POWER:
6048                 if (val > rps->efficient_freq + 1 &&
6049                     val > rps->cur_freq)
6050                         new_power = BETWEEN;
6051                 break;
6052
6053         case BETWEEN:
6054                 if (val <= rps->efficient_freq &&
6055                     val < rps->cur_freq)
6056                         new_power = LOW_POWER;
6057                 else if (val >= rps->rp0_freq &&
6058                          val > rps->cur_freq)
6059                         new_power = HIGH_POWER;
6060                 break;
6061
6062         case HIGH_POWER:
6063                 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
6064                     val < rps->cur_freq)
6065                         new_power = BETWEEN;
6066                 break;
6067         }
6068         /* Max/min bins are special */
6069         if (val <= rps->min_freq_softlimit)
6070                 new_power = LOW_POWER;
6071         if (val >= rps->max_freq_softlimit)
6072                 new_power = HIGH_POWER;
6073         if (new_power == rps->power)
6074                 return;
6075
6076         /* Note the units here are not exactly 1us, but 1280ns. */
6077         switch (new_power) {
6078         case LOW_POWER:
6079                 /* Upclock if more than 95% busy over 16ms */
6080                 ei_up = 16000;
6081                 threshold_up = 95;
6082
6083                 /* Downclock if less than 85% busy over 32ms */
6084                 ei_down = 32000;
6085                 threshold_down = 85;
6086                 break;
6087
6088         case BETWEEN:
6089                 /* Upclock if more than 90% busy over 13ms */
6090                 ei_up = 13000;
6091                 threshold_up = 90;
6092
6093                 /* Downclock if less than 75% busy over 32ms */
6094                 ei_down = 32000;
6095                 threshold_down = 75;
6096                 break;
6097
6098         case HIGH_POWER:
6099                 /* Upclock if more than 85% busy over 10ms */
6100                 ei_up = 10000;
6101                 threshold_up = 85;
6102
6103                 /* Downclock if less than 60% busy over 32ms */
6104                 ei_down = 32000;
6105                 threshold_down = 60;
6106                 break;
6107         }
6108
6109         /* When byt can survive without system hang with dynamic
6110          * sw freq adjustments, this restriction can be lifted.
6111          */
6112         if (IS_VALLEYVIEW(dev_priv))
6113                 goto skip_hw_write;
6114
6115         I915_WRITE(GEN6_RP_UP_EI,
6116                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
6117         I915_WRITE(GEN6_RP_UP_THRESHOLD,
6118                    GT_INTERVAL_FROM_US(dev_priv,
6119                                        ei_up * threshold_up / 100));
6120
6121         I915_WRITE(GEN6_RP_DOWN_EI,
6122                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
6123         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
6124                    GT_INTERVAL_FROM_US(dev_priv,
6125                                        ei_down * threshold_down / 100));
6126
6127         I915_WRITE(GEN6_RP_CONTROL,
6128                    GEN6_RP_MEDIA_TURBO |
6129                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6130                    GEN6_RP_MEDIA_IS_GFX |
6131                    GEN6_RP_ENABLE |
6132                    GEN6_RP_UP_BUSY_AVG |
6133                    GEN6_RP_DOWN_IDLE_AVG);
6134
6135 skip_hw_write:
6136         rps->power = new_power;
6137         rps->up_threshold = threshold_up;
6138         rps->down_threshold = threshold_down;
6139         rps->last_adj = 0;
6140 }
6141
6142 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
6143 {
6144         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6145         u32 mask = 0;
6146
6147         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6148         if (val > rps->min_freq_softlimit)
6149                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
6150         if (val < rps->max_freq_softlimit)
6151                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
6152
6153         mask &= dev_priv->pm_rps_events;
6154
6155         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
6156 }
6157
6158 /* gen6_set_rps is called to update the frequency request, but should also be
6159  * called when the range (min_delay and max_delay) is modified so that we can
6160  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6161 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
6162 {
6163         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6164
6165         /* min/max delay may still have been modified so be sure to
6166          * write the limits value.
6167          */
6168         if (val != rps->cur_freq) {
6169                 gen6_set_rps_thresholds(dev_priv, val);
6170
6171                 if (INTEL_GEN(dev_priv) >= 9)
6172                         I915_WRITE(GEN6_RPNSWREQ,
6173                                    GEN9_FREQUENCY(val));
6174                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6175                         I915_WRITE(GEN6_RPNSWREQ,
6176                                    HSW_FREQUENCY(val));
6177                 else
6178                         I915_WRITE(GEN6_RPNSWREQ,
6179                                    GEN6_FREQUENCY(val) |
6180                                    GEN6_OFFSET(0) |
6181                                    GEN6_AGGRESSIVE_TURBO);
6182         }
6183
6184         /* Make sure we continue to get interrupts
6185          * until we hit the minimum or maximum frequencies.
6186          */
6187         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6188         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6189
6190         rps->cur_freq = val;
6191         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6192
6193         return 0;
6194 }
6195
6196 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6197 {
6198         int err;
6199
6200         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6201                       "Odd GPU freq value\n"))
6202                 val &= ~1;
6203
6204         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6205
6206         if (val != dev_priv->gt_pm.rps.cur_freq) {
6207                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6208                 if (err)
6209                         return err;
6210
6211                 gen6_set_rps_thresholds(dev_priv, val);
6212         }
6213
6214         dev_priv->gt_pm.rps.cur_freq = val;
6215         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6216
6217         return 0;
6218 }
6219
6220 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6221  *
6222  * * If Gfx is Idle, then
6223  * 1. Forcewake Media well.
6224  * 2. Request idle freq.
6225  * 3. Release Forcewake of Media well.
6226 */
6227 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6228 {
6229         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6230         u32 val = rps->idle_freq;
6231         int err;
6232
6233         if (rps->cur_freq <= val)
6234                 return;
6235
6236         /* The punit delays the write of the frequency and voltage until it
6237          * determines the GPU is awake. During normal usage we don't want to
6238          * waste power changing the frequency if the GPU is sleeping (rc6).
6239          * However, the GPU and driver is now idle and we do not want to delay
6240          * switching to minimum voltage (reducing power whilst idle) as we do
6241          * not expect to be woken in the near future and so must flush the
6242          * change by waking the device.
6243          *
6244          * We choose to take the media powerwell (either would do to trick the
6245          * punit into committing the voltage change) as that takes a lot less
6246          * power than the render powerwell.
6247          */
6248         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
6249         err = valleyview_set_rps(dev_priv, val);
6250         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
6251
6252         if (err)
6253                 DRM_ERROR("Failed to set RPS for idle\n");
6254 }
6255
6256 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6257 {
6258         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6259
6260         mutex_lock(&dev_priv->pcu_lock);
6261         if (rps->enabled) {
6262                 u8 freq;
6263
6264                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6265                         gen6_rps_reset_ei(dev_priv);
6266                 I915_WRITE(GEN6_PMINTRMSK,
6267                            gen6_rps_pm_mask(dev_priv, rps->cur_freq));
6268
6269                 gen6_enable_rps_interrupts(dev_priv);
6270
6271                 /* Use the user's desired frequency as a guide, but for better
6272                  * performance, jump directly to RPe as our starting frequency.
6273                  */
6274                 freq = max(rps->cur_freq,
6275                            rps->efficient_freq);
6276
6277                 if (intel_set_rps(dev_priv,
6278                                   clamp(freq,
6279                                         rps->min_freq_softlimit,
6280                                         rps->max_freq_softlimit)))
6281                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6282         }
6283         mutex_unlock(&dev_priv->pcu_lock);
6284 }
6285
6286 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6287 {
6288         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6289
6290         /* Flush our bottom-half so that it does not race with us
6291          * setting the idle frequency and so that it is bounded by
6292          * our rpm wakeref. And then disable the interrupts to stop any
6293          * futher RPS reclocking whilst we are asleep.
6294          */
6295         gen6_disable_rps_interrupts(dev_priv);
6296
6297         mutex_lock(&dev_priv->pcu_lock);
6298         if (rps->enabled) {
6299                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6300                         vlv_set_rps_idle(dev_priv);
6301                 else
6302                         gen6_set_rps(dev_priv, rps->idle_freq);
6303                 rps->last_adj = 0;
6304                 I915_WRITE(GEN6_PMINTRMSK,
6305                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6306         }
6307         mutex_unlock(&dev_priv->pcu_lock);
6308 }
6309
6310 void gen6_rps_boost(struct drm_i915_gem_request *rq,
6311                     struct intel_rps_client *rps_client)
6312 {
6313         struct intel_rps *rps = &rq->i915->gt_pm.rps;
6314         unsigned long flags;
6315         bool boost;
6316
6317         /* This is intentionally racy! We peek at the state here, then
6318          * validate inside the RPS worker.
6319          */
6320         if (!rps->enabled)
6321                 return;
6322
6323         boost = false;
6324         spin_lock_irqsave(&rq->lock, flags);
6325         if (!rq->waitboost && !i915_gem_request_completed(rq)) {
6326                 atomic_inc(&rps->num_waiters);
6327                 rq->waitboost = true;
6328                 boost = true;
6329         }
6330         spin_unlock_irqrestore(&rq->lock, flags);
6331         if (!boost)
6332                 return;
6333
6334         if (READ_ONCE(rps->cur_freq) < rps->boost_freq)
6335                 schedule_work(&rps->work);
6336
6337         atomic_inc(rps_client ? &rps_client->boosts : &rps->boosts);
6338 }
6339
6340 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6341 {
6342         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6343         int err;
6344
6345         lockdep_assert_held(&dev_priv->pcu_lock);
6346         GEM_BUG_ON(val > rps->max_freq);
6347         GEM_BUG_ON(val < rps->min_freq);
6348
6349         if (!rps->enabled) {
6350                 rps->cur_freq = val;
6351                 return 0;
6352         }
6353
6354         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6355                 err = valleyview_set_rps(dev_priv, val);
6356         else
6357                 err = gen6_set_rps(dev_priv, val);
6358
6359         return err;
6360 }
6361
6362 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6363 {
6364         I915_WRITE(GEN6_RC_CONTROL, 0);
6365         I915_WRITE(GEN9_PG_ENABLE, 0);
6366 }
6367
6368 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6369 {
6370         I915_WRITE(GEN6_RP_CONTROL, 0);
6371 }
6372
6373 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
6374 {
6375         I915_WRITE(GEN6_RC_CONTROL, 0);
6376 }
6377
6378 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6379 {
6380         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6381         I915_WRITE(GEN6_RP_CONTROL, 0);
6382 }
6383
6384 static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
6385 {
6386         I915_WRITE(GEN6_RC_CONTROL, 0);
6387 }
6388
6389 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6390 {
6391         I915_WRITE(GEN6_RP_CONTROL, 0);
6392 }
6393
6394 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
6395 {
6396         /* We're doing forcewake before Disabling RC6,
6397          * This what the BIOS expects when going into suspend */
6398         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6399
6400         I915_WRITE(GEN6_RC_CONTROL, 0);
6401
6402         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6403 }
6404
6405 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6406 {
6407         I915_WRITE(GEN6_RP_CONTROL, 0);
6408 }
6409
6410 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
6411 {
6412         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6413                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
6414                         mode = GEN6_RC_CTL_RC6_ENABLE;
6415                 else
6416                         mode = 0;
6417         }
6418         if (HAS_RC6p(dev_priv))
6419                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6420                                  "RC6 %s RC6p %s RC6pp %s\n",
6421                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
6422                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
6423                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
6424
6425         else
6426                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6427                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
6428 }
6429
6430 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6431 {
6432         struct i915_ggtt *ggtt = &dev_priv->ggtt;
6433         bool enable_rc6 = true;
6434         unsigned long rc6_ctx_base;
6435         u32 rc_ctl;
6436         int rc_sw_target;
6437
6438         rc_ctl = I915_READ(GEN6_RC_CONTROL);
6439         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6440                        RC_SW_TARGET_STATE_SHIFT;
6441         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6442                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6443                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6444                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6445                          rc_sw_target);
6446
6447         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6448                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6449                 enable_rc6 = false;
6450         }
6451
6452         /*
6453          * The exact context size is not known for BXT, so assume a page size
6454          * for this check.
6455          */
6456         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
6457         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
6458               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
6459                                         ggtt->stolen_reserved_size))) {
6460                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6461                 enable_rc6 = false;
6462         }
6463
6464         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
6465               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
6466               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
6467               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
6468                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6469                 enable_rc6 = false;
6470         }
6471
6472         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
6473             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
6474             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
6475                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6476                 enable_rc6 = false;
6477         }
6478
6479         if (!I915_READ(GEN6_GFXPAUSE)) {
6480                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6481                 enable_rc6 = false;
6482         }
6483
6484         if (!I915_READ(GEN8_MISC_CTRL0)) {
6485                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6486                 enable_rc6 = false;
6487         }
6488
6489         return enable_rc6;
6490 }
6491
6492 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
6493 {
6494         /* No RC6 before Ironlake and code is gone for ilk. */
6495         if (INTEL_INFO(dev_priv)->gen < 6)
6496                 return 0;
6497
6498         if (!enable_rc6)
6499                 return 0;
6500
6501         if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
6502                 DRM_INFO("RC6 disabled by BIOS\n");
6503                 return 0;
6504         }
6505
6506         /* Respect the kernel parameter if it is set */
6507         if (enable_rc6 >= 0) {
6508                 int mask;
6509
6510                 if (HAS_RC6p(dev_priv))
6511                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
6512                                INTEL_RC6pp_ENABLE;
6513                 else
6514                         mask = INTEL_RC6_ENABLE;
6515
6516                 if ((enable_rc6 & mask) != enable_rc6)
6517                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6518                                          "(requested %d, valid %d)\n",
6519                                          enable_rc6 & mask, enable_rc6, mask);
6520
6521                 return enable_rc6 & mask;
6522         }
6523
6524         if (IS_IVYBRIDGE(dev_priv))
6525                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
6526
6527         return INTEL_RC6_ENABLE;
6528 }
6529
6530 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
6531 {
6532         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6533
6534         /* All of these values are in units of 50MHz */
6535
6536         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6537         if (IS_GEN9_LP(dev_priv)) {
6538                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
6539                 rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
6540                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
6541                 rps->min_freq = (rp_state_cap >>  0) & 0xff;
6542         } else {
6543                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6544                 rps->rp0_freq = (rp_state_cap >>  0) & 0xff;
6545                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
6546                 rps->min_freq = (rp_state_cap >> 16) & 0xff;
6547         }
6548         /* hw_max = RP0 until we check for overclocking */
6549         rps->max_freq = rps->rp0_freq;
6550
6551         rps->efficient_freq = rps->rp1_freq;
6552         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
6553             IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6554                 u32 ddcc_status = 0;
6555
6556                 if (sandybridge_pcode_read(dev_priv,
6557                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
6558                                            &ddcc_status) == 0)
6559                         rps->efficient_freq =
6560                                 clamp_t(u8,
6561                                         ((ddcc_status >> 8) & 0xff),
6562                                         rps->min_freq,
6563                                         rps->max_freq);
6564         }
6565
6566         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6567                 /* Store the frequency values in 16.66 MHZ units, which is
6568                  * the natural hardware unit for SKL
6569                  */
6570                 rps->rp0_freq *= GEN9_FREQ_SCALER;
6571                 rps->rp1_freq *= GEN9_FREQ_SCALER;
6572                 rps->min_freq *= GEN9_FREQ_SCALER;
6573                 rps->max_freq *= GEN9_FREQ_SCALER;
6574                 rps->efficient_freq *= GEN9_FREQ_SCALER;
6575         }
6576 }
6577
6578 static void reset_rps(struct drm_i915_private *dev_priv,
6579                       int (*set)(struct drm_i915_private *, u8))
6580 {
6581         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6582         u8 freq = rps->cur_freq;
6583
6584         /* force a reset */
6585         rps->power = -1;
6586         rps->cur_freq = -1;
6587
6588         if (set(dev_priv, freq))
6589                 DRM_ERROR("Failed to reset RPS to initial values\n");
6590 }
6591
6592 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6593 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
6594 {
6595         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6596
6597         /* Program defaults and thresholds for RPS*/
6598         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6599                 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
6600
6601         /* 1 second timeout*/
6602         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
6603                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
6604
6605         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
6606
6607         /* Leaning on the below call to gen6_set_rps to program/setup the
6608          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6609          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6610         reset_rps(dev_priv, gen6_set_rps);
6611
6612         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6613 }
6614
6615 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
6616 {
6617         struct intel_engine_cs *engine;
6618         enum intel_engine_id id;
6619         u32 rc6_mode, rc6_mask = 0;
6620
6621         /* 1a: Software RC state - RC0 */
6622         I915_WRITE(GEN6_RC_STATE, 0);
6623
6624         /* 1b: Get forcewake during program sequence. Although the driver
6625          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6626         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6627
6628         /* 2a: Disable RC states. */
6629         I915_WRITE(GEN6_RC_CONTROL, 0);
6630
6631         /* 2b: Program RC6 thresholds.*/
6632
6633         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6634         if (IS_SKYLAKE(dev_priv))
6635                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
6636         else
6637                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
6638         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6639         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6640         for_each_engine(engine, dev_priv, id)
6641                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6642
6643         if (HAS_GUC(dev_priv))
6644                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
6645
6646         I915_WRITE(GEN6_RC_SLEEP, 0);
6647
6648         /* 2c: Program Coarse Power Gating Policies. */
6649         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
6650         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
6651
6652         /* 3a: Enable RC6 */
6653         if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
6654                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6655         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
6656         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
6657
6658         /* WaRsUseTimeoutMode:cnl (pre-prod) */
6659         if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
6660                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6661         else
6662                 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
6663
6664         I915_WRITE(GEN6_RC_CONTROL,
6665                    GEN6_RC_CTL_HW_ENABLE | rc6_mode | rc6_mask);
6666
6667         /*
6668          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6669          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6670          */
6671         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
6672                 I915_WRITE(GEN9_PG_ENABLE, 0);
6673         else
6674                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
6675                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
6676
6677         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6678 }
6679
6680 static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
6681 {
6682         struct intel_engine_cs *engine;
6683         enum intel_engine_id id;
6684         uint32_t rc6_mask = 0;
6685
6686         /* 1a: Software RC state - RC0 */
6687         I915_WRITE(GEN6_RC_STATE, 0);
6688
6689         /* 1b: Get forcewake during program sequence. Although the driver
6690          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6691         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6692
6693         /* 2a: Disable RC states. */
6694         I915_WRITE(GEN6_RC_CONTROL, 0);
6695
6696         /* 2b: Program RC6 thresholds.*/
6697         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6698         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6699         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6700         for_each_engine(engine, dev_priv, id)
6701                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6702         I915_WRITE(GEN6_RC_SLEEP, 0);
6703         I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
6704
6705         /* 3: Enable RC6 */
6706         if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
6707                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6708         intel_print_rc6_info(dev_priv, rc6_mask);
6709
6710         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6711                         GEN7_RC_CTL_TO_MODE |
6712                         rc6_mask);
6713
6714         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6715 }
6716
6717 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6718 {
6719         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6720
6721         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6722
6723         /* 1 Program defaults and thresholds for RPS*/
6724         I915_WRITE(GEN6_RPNSWREQ,
6725                    HSW_FREQUENCY(rps->rp1_freq));
6726         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6727                    HSW_FREQUENCY(rps->rp1_freq));
6728         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6729         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
6730
6731         /* Docs recommend 900MHz, and 300 MHz respectively */
6732         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6733                    rps->max_freq_softlimit << 24 |
6734                    rps->min_freq_softlimit << 16);
6735
6736         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
6737         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6738         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
6739         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
6740
6741         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6742
6743         /* 2: Enable RPS */
6744         I915_WRITE(GEN6_RP_CONTROL,
6745                    GEN6_RP_MEDIA_TURBO |
6746                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6747                    GEN6_RP_MEDIA_IS_GFX |
6748                    GEN6_RP_ENABLE |
6749                    GEN6_RP_UP_BUSY_AVG |
6750                    GEN6_RP_DOWN_IDLE_AVG);
6751
6752         reset_rps(dev_priv, gen6_set_rps);
6753
6754         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6755 }
6756
6757 static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
6758 {
6759         struct intel_engine_cs *engine;
6760         enum intel_engine_id id;
6761         u32 rc6vids, rc6_mask = 0;
6762         u32 gtfifodbg;
6763         int rc6_mode;
6764         int ret;
6765
6766         I915_WRITE(GEN6_RC_STATE, 0);
6767
6768         /* Clear the DBG now so we don't confuse earlier errors */
6769         gtfifodbg = I915_READ(GTFIFODBG);
6770         if (gtfifodbg) {
6771                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
6772                 I915_WRITE(GTFIFODBG, gtfifodbg);
6773         }
6774
6775         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6776
6777         /* disable the counters and set deterministic thresholds */
6778         I915_WRITE(GEN6_RC_CONTROL, 0);
6779
6780         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6781         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6782         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6783         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6784         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6785
6786         for_each_engine(engine, dev_priv, id)
6787                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6788
6789         I915_WRITE(GEN6_RC_SLEEP, 0);
6790         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6791         if (IS_IVYBRIDGE(dev_priv))
6792                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
6793         else
6794                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6795         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
6796         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6797
6798         /* Check if we are enabling RC6 */
6799         rc6_mode = intel_rc6_enabled();
6800         if (rc6_mode & INTEL_RC6_ENABLE)
6801                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
6802
6803         /* We don't use those on Haswell */
6804         if (!IS_HASWELL(dev_priv)) {
6805                 if (rc6_mode & INTEL_RC6p_ENABLE)
6806                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
6807
6808                 if (rc6_mode & INTEL_RC6pp_ENABLE)
6809                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
6810         }
6811
6812         intel_print_rc6_info(dev_priv, rc6_mask);
6813
6814         I915_WRITE(GEN6_RC_CONTROL,
6815                    rc6_mask |
6816                    GEN6_RC_CTL_EI_MODE(1) |
6817                    GEN6_RC_CTL_HW_ENABLE);
6818
6819         rc6vids = 0;
6820         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
6821         if (IS_GEN6(dev_priv) && ret) {
6822                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6823         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
6824                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6825                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
6826                 rc6vids &= 0xffff00;
6827                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
6828                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
6829                 if (ret)
6830                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6831         }
6832
6833         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6834 }
6835
6836 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
6837 {
6838         /* Here begins a magic sequence of register writes to enable
6839          * auto-downclocking.
6840          *
6841          * Perhaps there might be some value in exposing these to
6842          * userspace...
6843          */
6844         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6845
6846         /* Power down if completely idle for over 50ms */
6847         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
6848         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6849
6850         reset_rps(dev_priv, gen6_set_rps);
6851
6852         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6853 }
6854
6855 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
6856 {
6857         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6858         int min_freq = 15;
6859         unsigned int gpu_freq;
6860         unsigned int max_ia_freq, min_ring_freq;
6861         unsigned int max_gpu_freq, min_gpu_freq;
6862         int scaling_factor = 180;
6863         struct cpufreq_policy *policy;
6864
6865         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
6866
6867         policy = cpufreq_cpu_get(0);
6868         if (policy) {
6869                 max_ia_freq = policy->cpuinfo.max_freq;
6870                 cpufreq_cpu_put(policy);
6871         } else {
6872                 /*
6873                  * Default to measured freq if none found, PCU will ensure we
6874                  * don't go over
6875                  */
6876                 max_ia_freq = tsc_khz;
6877         }
6878
6879         /* Convert from kHz to MHz */
6880         max_ia_freq /= 1000;
6881
6882         min_ring_freq = I915_READ(DCLK) & 0xf;
6883         /* convert DDR frequency from units of 266.6MHz to bandwidth */
6884         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
6885
6886         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6887                 /* Convert GT frequency to 50 HZ units */
6888                 min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER;
6889                 max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER;
6890         } else {
6891                 min_gpu_freq = rps->min_freq;
6892                 max_gpu_freq = rps->max_freq;
6893         }
6894
6895         /*
6896          * For each potential GPU frequency, load a ring frequency we'd like
6897          * to use for memory access.  We do this by specifying the IA frequency
6898          * the PCU should use as a reference to determine the ring frequency.
6899          */
6900         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
6901                 int diff = max_gpu_freq - gpu_freq;
6902                 unsigned int ia_freq = 0, ring_freq = 0;
6903
6904                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6905                         /*
6906                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
6907                          * No floor required for ring frequency on SKL.
6908                          */
6909                         ring_freq = gpu_freq;
6910                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
6911                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
6912                         ring_freq = max(min_ring_freq, gpu_freq);
6913                 } else if (IS_HASWELL(dev_priv)) {
6914                         ring_freq = mult_frac(gpu_freq, 5, 4);
6915                         ring_freq = max(min_ring_freq, ring_freq);
6916                         /* leave ia_freq as the default, chosen by cpufreq */
6917                 } else {
6918                         /* On older processors, there is no separate ring
6919                          * clock domain, so in order to boost the bandwidth
6920                          * of the ring, we need to upclock the CPU (ia_freq).
6921                          *
6922                          * For GPU frequencies less than 750MHz,
6923                          * just use the lowest ring freq.
6924                          */
6925                         if (gpu_freq < min_freq)
6926                                 ia_freq = 800;
6927                         else
6928                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
6929                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
6930                 }
6931
6932                 sandybridge_pcode_write(dev_priv,
6933                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
6934                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
6935                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
6936                                         gpu_freq);
6937         }
6938 }
6939
6940 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
6941 {
6942         u32 val, rp0;
6943
6944         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6945
6946         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
6947         case 8:
6948                 /* (2 * 4) config */
6949                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
6950                 break;
6951         case 12:
6952                 /* (2 * 6) config */
6953                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
6954                 break;
6955         case 16:
6956                 /* (2 * 8) config */
6957         default:
6958                 /* Setting (2 * 8) Min RP0 for any other combination */
6959                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
6960                 break;
6961         }
6962
6963         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
6964
6965         return rp0;
6966 }
6967
6968 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6969 {
6970         u32 val, rpe;
6971
6972         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
6973         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
6974
6975         return rpe;
6976 }
6977
6978 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
6979 {
6980         u32 val, rp1;
6981
6982         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6983         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
6984
6985         return rp1;
6986 }
6987
6988 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
6989 {
6990         u32 val, rpn;
6991
6992         val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
6993         rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
6994                        FB_GFX_FREQ_FUSE_MASK);
6995
6996         return rpn;
6997 }
6998
6999 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
7000 {
7001         u32 val, rp1;
7002
7003         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7004
7005         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
7006
7007         return rp1;
7008 }
7009
7010 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
7011 {
7012         u32 val, rp0;
7013
7014         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7015
7016         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
7017         /* Clamp to max */
7018         rp0 = min_t(u32, rp0, 0xea);
7019
7020         return rp0;
7021 }
7022
7023 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
7024 {
7025         u32 val, rpe;
7026
7027         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
7028         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
7029         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
7030         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
7031
7032         return rpe;
7033 }
7034
7035 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
7036 {
7037         u32 val;
7038
7039         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
7040         /*
7041          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
7042          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
7043          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
7044          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
7045          * to make sure it matches what Punit accepts.
7046          */
7047         return max_t(u32, val, 0xc0);
7048 }
7049
7050 /* Check that the pctx buffer wasn't move under us. */
7051 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
7052 {
7053         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7054
7055         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
7056                              dev_priv->vlv_pctx->stolen->start);
7057 }
7058
7059
7060 /* Check that the pcbr address is not empty. */
7061 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
7062 {
7063         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7064
7065         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
7066 }
7067
7068 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
7069 {
7070         struct i915_ggtt *ggtt = &dev_priv->ggtt;
7071         unsigned long pctx_paddr, paddr;
7072         u32 pcbr;
7073         int pctx_size = 32*1024;
7074
7075         pcbr = I915_READ(VLV_PCBR);
7076         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
7077                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7078                 paddr = (dev_priv->mm.stolen_base +
7079                          (ggtt->stolen_size - pctx_size));
7080
7081                 pctx_paddr = (paddr & (~4095));
7082                 I915_WRITE(VLV_PCBR, pctx_paddr);
7083         }
7084
7085         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7086 }
7087
7088 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
7089 {
7090         struct drm_i915_gem_object *pctx;
7091         unsigned long pctx_paddr;
7092         u32 pcbr;
7093         int pctx_size = 24*1024;
7094
7095         pcbr = I915_READ(VLV_PCBR);
7096         if (pcbr) {
7097                 /* BIOS set it up already, grab the pre-alloc'd space */
7098                 int pcbr_offset;
7099
7100                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
7101                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
7102                                                                       pcbr_offset,
7103                                                                       I915_GTT_OFFSET_NONE,
7104                                                                       pctx_size);
7105                 goto out;
7106         }
7107
7108         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7109
7110         /*
7111          * From the Gunit register HAS:
7112          * The Gfx driver is expected to program this register and ensure
7113          * proper allocation within Gfx stolen memory.  For example, this
7114          * register should be programmed such than the PCBR range does not
7115          * overlap with other ranges, such as the frame buffer, protected
7116          * memory, or any other relevant ranges.
7117          */
7118         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
7119         if (!pctx) {
7120                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
7121                 goto out;
7122         }
7123
7124         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
7125         I915_WRITE(VLV_PCBR, pctx_paddr);
7126
7127 out:
7128         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7129         dev_priv->vlv_pctx = pctx;
7130 }
7131
7132 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
7133 {
7134         if (WARN_ON(!dev_priv->vlv_pctx))
7135                 return;
7136
7137         i915_gem_object_put(dev_priv->vlv_pctx);
7138         dev_priv->vlv_pctx = NULL;
7139 }
7140
7141 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
7142 {
7143         dev_priv->gt_pm.rps.gpll_ref_freq =
7144                 vlv_get_cck_clock(dev_priv, "GPLL ref",
7145                                   CCK_GPLL_CLOCK_CONTROL,
7146                                   dev_priv->czclk_freq);
7147
7148         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
7149                          dev_priv->gt_pm.rps.gpll_ref_freq);
7150 }
7151
7152 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
7153 {
7154         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7155         u32 val;
7156
7157         valleyview_setup_pctx(dev_priv);
7158
7159         vlv_init_gpll_ref_freq(dev_priv);
7160
7161         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7162         switch ((val >> 6) & 3) {
7163         case 0:
7164         case 1:
7165                 dev_priv->mem_freq = 800;
7166                 break;
7167         case 2:
7168                 dev_priv->mem_freq = 1066;
7169                 break;
7170         case 3:
7171                 dev_priv->mem_freq = 1333;
7172                 break;
7173         }
7174         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7175
7176         rps->max_freq = valleyview_rps_max_freq(dev_priv);
7177         rps->rp0_freq = rps->max_freq;
7178         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7179                          intel_gpu_freq(dev_priv, rps->max_freq),
7180                          rps->max_freq);
7181
7182         rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv);
7183         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7184                          intel_gpu_freq(dev_priv, rps->efficient_freq),
7185                          rps->efficient_freq);
7186
7187         rps->rp1_freq = valleyview_rps_guar_freq(dev_priv);
7188         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7189                          intel_gpu_freq(dev_priv, rps->rp1_freq),
7190                          rps->rp1_freq);
7191
7192         rps->min_freq = valleyview_rps_min_freq(dev_priv);
7193         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7194                          intel_gpu_freq(dev_priv, rps->min_freq),
7195                          rps->min_freq);
7196 }
7197
7198 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
7199 {
7200         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7201         u32 val;
7202
7203         cherryview_setup_pctx(dev_priv);
7204
7205         vlv_init_gpll_ref_freq(dev_priv);
7206
7207         mutex_lock(&dev_priv->sb_lock);
7208         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
7209         mutex_unlock(&dev_priv->sb_lock);
7210
7211         switch ((val >> 2) & 0x7) {
7212         case 3:
7213                 dev_priv->mem_freq = 2000;
7214                 break;
7215         default:
7216                 dev_priv->mem_freq = 1600;
7217                 break;
7218         }
7219         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7220
7221         rps->max_freq = cherryview_rps_max_freq(dev_priv);
7222         rps->rp0_freq = rps->max_freq;
7223         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7224                          intel_gpu_freq(dev_priv, rps->max_freq),
7225                          rps->max_freq);
7226
7227         rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7228         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7229                          intel_gpu_freq(dev_priv, rps->efficient_freq),
7230                          rps->efficient_freq);
7231
7232         rps->rp1_freq = cherryview_rps_guar_freq(dev_priv);
7233         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7234                          intel_gpu_freq(dev_priv, rps->rp1_freq),
7235                          rps->rp1_freq);
7236
7237         rps->min_freq = cherryview_rps_min_freq(dev_priv);
7238         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7239                          intel_gpu_freq(dev_priv, rps->min_freq),
7240                          rps->min_freq);
7241
7242         WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
7243                    rps->min_freq) & 1,
7244                   "Odd GPU freq values\n");
7245 }
7246
7247 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7248 {
7249         valleyview_cleanup_pctx(dev_priv);
7250 }
7251
7252 static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
7253 {
7254         struct intel_engine_cs *engine;
7255         enum intel_engine_id id;
7256         u32 gtfifodbg, rc6_mode = 0, pcbr;
7257
7258         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7259                                              GT_FIFO_FREE_ENTRIES_CHV);
7260         if (gtfifodbg) {
7261                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7262                                  gtfifodbg);
7263                 I915_WRITE(GTFIFODBG, gtfifodbg);
7264         }
7265
7266         cherryview_check_pctx(dev_priv);
7267
7268         /* 1a & 1b: Get forcewake during program sequence. Although the driver
7269          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7270         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7271
7272         /*  Disable RC states. */
7273         I915_WRITE(GEN6_RC_CONTROL, 0);
7274
7275         /* 2a: Program RC6 thresholds.*/
7276         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7277         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7278         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7279
7280         for_each_engine(engine, dev_priv, id)
7281                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7282         I915_WRITE(GEN6_RC_SLEEP, 0);
7283
7284         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7285         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7286
7287         /* Allows RC6 residency counter to work */
7288         I915_WRITE(VLV_COUNTER_CONTROL,
7289                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7290                                       VLV_MEDIA_RC6_COUNT_EN |
7291                                       VLV_RENDER_RC6_COUNT_EN));
7292
7293         /* For now we assume BIOS is allocating and populating the PCBR  */
7294         pcbr = I915_READ(VLV_PCBR);
7295
7296         /* 3: Enable RC6 */
7297         if ((intel_rc6_enabled() & INTEL_RC6_ENABLE) &&
7298             (pcbr >> VLV_PCBR_ADDR_SHIFT))
7299                 rc6_mode = GEN7_RC_CTL_TO_MODE;
7300
7301         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7302
7303         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7304 }
7305
7306 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7307 {
7308         u32 val;
7309
7310         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7311
7312         /* 1: Program defaults and thresholds for RPS*/
7313         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7314         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7315         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7316         I915_WRITE(GEN6_RP_UP_EI, 66000);
7317         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7318
7319         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7320
7321         /* 2: Enable RPS */
7322         I915_WRITE(GEN6_RP_CONTROL,
7323                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7324                    GEN6_RP_MEDIA_IS_GFX |
7325                    GEN6_RP_ENABLE |
7326                    GEN6_RP_UP_BUSY_AVG |
7327                    GEN6_RP_DOWN_IDLE_AVG);
7328
7329         /* Setting Fixed Bias */
7330         val = VLV_OVERRIDE_EN |
7331                   VLV_SOC_TDP_EN |
7332                   CHV_BIAS_CPU_50_SOC_50;
7333         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7334
7335         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7336
7337         /* RPS code assumes GPLL is used */
7338         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7339
7340         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7341         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7342
7343         reset_rps(dev_priv, valleyview_set_rps);
7344
7345         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7346 }
7347
7348 static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
7349 {
7350         struct intel_engine_cs *engine;
7351         enum intel_engine_id id;
7352         u32 gtfifodbg, rc6_mode = 0;
7353
7354         valleyview_check_pctx(dev_priv);
7355
7356         gtfifodbg = I915_READ(GTFIFODBG);
7357         if (gtfifodbg) {
7358                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7359                                  gtfifodbg);
7360                 I915_WRITE(GTFIFODBG, gtfifodbg);
7361         }
7362
7363         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7364
7365         /*  Disable RC states. */
7366         I915_WRITE(GEN6_RC_CONTROL, 0);
7367
7368         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
7369         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7370         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7371
7372         for_each_engine(engine, dev_priv, id)
7373                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7374
7375         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
7376
7377         /* Allows RC6 residency counter to work */
7378         I915_WRITE(VLV_COUNTER_CONTROL,
7379                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7380                                       VLV_MEDIA_RC0_COUNT_EN |
7381                                       VLV_RENDER_RC0_COUNT_EN |
7382                                       VLV_MEDIA_RC6_COUNT_EN |
7383                                       VLV_RENDER_RC6_COUNT_EN));
7384
7385         if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
7386                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
7387
7388         intel_print_rc6_info(dev_priv, rc6_mode);
7389
7390         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7391
7392         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7393 }
7394
7395 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
7396 {
7397         u32 val;
7398
7399         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7400
7401         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7402         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7403         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7404         I915_WRITE(GEN6_RP_UP_EI, 66000);
7405         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7406
7407         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7408
7409         I915_WRITE(GEN6_RP_CONTROL,
7410                    GEN6_RP_MEDIA_TURBO |
7411                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7412                    GEN6_RP_MEDIA_IS_GFX |
7413                    GEN6_RP_ENABLE |
7414                    GEN6_RP_UP_BUSY_AVG |
7415                    GEN6_RP_DOWN_IDLE_CONT);
7416
7417         /* Setting Fixed Bias */
7418         val = VLV_OVERRIDE_EN |
7419                   VLV_SOC_TDP_EN |
7420                   VLV_BIAS_CPU_125_SOC_875;
7421         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7422
7423         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7424
7425         /* RPS code assumes GPLL is used */
7426         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7427
7428         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7429         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7430
7431         reset_rps(dev_priv, valleyview_set_rps);
7432
7433         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7434 }
7435
7436 static unsigned long intel_pxfreq(u32 vidfreq)
7437 {
7438         unsigned long freq;
7439         int div = (vidfreq & 0x3f0000) >> 16;
7440         int post = (vidfreq & 0x3000) >> 12;
7441         int pre = (vidfreq & 0x7);
7442
7443         if (!pre)
7444                 return 0;
7445
7446         freq = ((div * 133333) / ((1<<post) * pre));
7447
7448         return freq;
7449 }
7450
7451 static const struct cparams {
7452         u16 i;
7453         u16 t;
7454         u16 m;
7455         u16 c;
7456 } cparams[] = {
7457         { 1, 1333, 301, 28664 },
7458         { 1, 1066, 294, 24460 },
7459         { 1, 800, 294, 25192 },
7460         { 0, 1333, 276, 27605 },
7461         { 0, 1066, 276, 27605 },
7462         { 0, 800, 231, 23784 },
7463 };
7464
7465 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
7466 {
7467         u64 total_count, diff, ret;
7468         u32 count1, count2, count3, m = 0, c = 0;
7469         unsigned long now = jiffies_to_msecs(jiffies), diff1;
7470         int i;
7471
7472         lockdep_assert_held(&mchdev_lock);
7473
7474         diff1 = now - dev_priv->ips.last_time1;
7475
7476         /* Prevent division-by-zero if we are asking too fast.
7477          * Also, we don't get interesting results if we are polling
7478          * faster than once in 10ms, so just return the saved value
7479          * in such cases.
7480          */
7481         if (diff1 <= 10)
7482                 return dev_priv->ips.chipset_power;
7483
7484         count1 = I915_READ(DMIEC);
7485         count2 = I915_READ(DDREC);
7486         count3 = I915_READ(CSIEC);
7487
7488         total_count = count1 + count2 + count3;
7489
7490         /* FIXME: handle per-counter overflow */
7491         if (total_count < dev_priv->ips.last_count1) {
7492                 diff = ~0UL - dev_priv->ips.last_count1;
7493                 diff += total_count;
7494         } else {
7495                 diff = total_count - dev_priv->ips.last_count1;
7496         }
7497
7498         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
7499                 if (cparams[i].i == dev_priv->ips.c_m &&
7500                     cparams[i].t == dev_priv->ips.r_t) {
7501                         m = cparams[i].m;
7502                         c = cparams[i].c;
7503                         break;
7504                 }
7505         }
7506
7507         diff = div_u64(diff, diff1);
7508         ret = ((m * diff) + c);
7509         ret = div_u64(ret, 10);
7510
7511         dev_priv->ips.last_count1 = total_count;
7512         dev_priv->ips.last_time1 = now;
7513
7514         dev_priv->ips.chipset_power = ret;
7515
7516         return ret;
7517 }
7518
7519 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
7520 {
7521         unsigned long val;
7522
7523         if (INTEL_INFO(dev_priv)->gen != 5)
7524                 return 0;
7525
7526         spin_lock_irq(&mchdev_lock);
7527
7528         val = __i915_chipset_val(dev_priv);
7529
7530         spin_unlock_irq(&mchdev_lock);
7531
7532         return val;
7533 }
7534
7535 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
7536 {
7537         unsigned long m, x, b;
7538         u32 tsfs;
7539
7540         tsfs = I915_READ(TSFS);
7541
7542         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
7543         x = I915_READ8(TR1);
7544
7545         b = tsfs & TSFS_INTR_MASK;
7546
7547         return ((m * x) / 127) - b;
7548 }
7549
7550 static int _pxvid_to_vd(u8 pxvid)
7551 {
7552         if (pxvid == 0)
7553                 return 0;
7554
7555         if (pxvid >= 8 && pxvid < 31)
7556                 pxvid = 31;
7557
7558         return (pxvid + 2) * 125;
7559 }
7560
7561 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7562 {
7563         const int vd = _pxvid_to_vd(pxvid);
7564         const int vm = vd - 1125;
7565
7566         if (INTEL_INFO(dev_priv)->is_mobile)
7567                 return vm > 0 ? vm : 0;
7568
7569         return vd;
7570 }
7571
7572 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
7573 {
7574         u64 now, diff, diffms;
7575         u32 count;
7576
7577         lockdep_assert_held(&mchdev_lock);
7578
7579         now = ktime_get_raw_ns();
7580         diffms = now - dev_priv->ips.last_time2;
7581         do_div(diffms, NSEC_PER_MSEC);
7582
7583         /* Don't divide by 0 */
7584         if (!diffms)
7585                 return;
7586
7587         count = I915_READ(GFXEC);
7588
7589         if (count < dev_priv->ips.last_count2) {
7590                 diff = ~0UL - dev_priv->ips.last_count2;
7591                 diff += count;
7592         } else {
7593                 diff = count - dev_priv->ips.last_count2;
7594         }
7595
7596         dev_priv->ips.last_count2 = count;
7597         dev_priv->ips.last_time2 = now;
7598
7599         /* More magic constants... */
7600         diff = diff * 1181;
7601         diff = div_u64(diff, diffms * 10);
7602         dev_priv->ips.gfx_power = diff;
7603 }
7604
7605 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
7606 {
7607         if (INTEL_INFO(dev_priv)->gen != 5)
7608                 return;
7609
7610         spin_lock_irq(&mchdev_lock);
7611
7612         __i915_update_gfx_val(dev_priv);
7613
7614         spin_unlock_irq(&mchdev_lock);
7615 }
7616
7617 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
7618 {
7619         unsigned long t, corr, state1, corr2, state2;
7620         u32 pxvid, ext_v;
7621
7622         lockdep_assert_held(&mchdev_lock);
7623
7624         pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
7625         pxvid = (pxvid >> 24) & 0x7f;
7626         ext_v = pvid_to_extvid(dev_priv, pxvid);
7627
7628         state1 = ext_v;
7629
7630         t = i915_mch_val(dev_priv);
7631
7632         /* Revel in the empirically derived constants */
7633
7634         /* Correction factor in 1/100000 units */
7635         if (t > 80)
7636                 corr = ((t * 2349) + 135940);
7637         else if (t >= 50)
7638                 corr = ((t * 964) + 29317);
7639         else /* < 50 */
7640                 corr = ((t * 301) + 1004);
7641
7642         corr = corr * ((150142 * state1) / 10000 - 78642);
7643         corr /= 100000;
7644         corr2 = (corr * dev_priv->ips.corr);
7645
7646         state2 = (corr2 * state1) / 10000;
7647         state2 /= 100; /* convert to mW */
7648
7649         __i915_update_gfx_val(dev_priv);
7650
7651         return dev_priv->ips.gfx_power + state2;
7652 }
7653
7654 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
7655 {
7656         unsigned long val;
7657
7658         if (INTEL_INFO(dev_priv)->gen != 5)
7659                 return 0;
7660
7661         spin_lock_irq(&mchdev_lock);
7662
7663         val = __i915_gfx_val(dev_priv);
7664
7665         spin_unlock_irq(&mchdev_lock);
7666
7667         return val;
7668 }
7669
7670 /**
7671  * i915_read_mch_val - return value for IPS use
7672  *
7673  * Calculate and return a value for the IPS driver to use when deciding whether
7674  * we have thermal and power headroom to increase CPU or GPU power budget.
7675  */
7676 unsigned long i915_read_mch_val(void)
7677 {
7678         struct drm_i915_private *dev_priv;
7679         unsigned long chipset_val, graphics_val, ret = 0;
7680
7681         spin_lock_irq(&mchdev_lock);
7682         if (!i915_mch_dev)
7683                 goto out_unlock;
7684         dev_priv = i915_mch_dev;
7685
7686         chipset_val = __i915_chipset_val(dev_priv);
7687         graphics_val = __i915_gfx_val(dev_priv);
7688
7689         ret = chipset_val + graphics_val;
7690
7691 out_unlock:
7692         spin_unlock_irq(&mchdev_lock);
7693
7694         return ret;
7695 }
7696 EXPORT_SYMBOL_GPL(i915_read_mch_val);
7697
7698 /**
7699  * i915_gpu_raise - raise GPU frequency limit
7700  *
7701  * Raise the limit; IPS indicates we have thermal headroom.
7702  */
7703 bool i915_gpu_raise(void)
7704 {
7705         struct drm_i915_private *dev_priv;
7706         bool ret = true;
7707
7708         spin_lock_irq(&mchdev_lock);
7709         if (!i915_mch_dev) {
7710                 ret = false;
7711                 goto out_unlock;
7712         }
7713         dev_priv = i915_mch_dev;
7714
7715         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
7716                 dev_priv->ips.max_delay--;
7717
7718 out_unlock:
7719         spin_unlock_irq(&mchdev_lock);
7720
7721         return ret;
7722 }
7723 EXPORT_SYMBOL_GPL(i915_gpu_raise);
7724
7725 /**
7726  * i915_gpu_lower - lower GPU frequency limit
7727  *
7728  * IPS indicates we're close to a thermal limit, so throttle back the GPU
7729  * frequency maximum.
7730  */
7731 bool i915_gpu_lower(void)
7732 {
7733         struct drm_i915_private *dev_priv;
7734         bool ret = true;
7735
7736         spin_lock_irq(&mchdev_lock);
7737         if (!i915_mch_dev) {
7738                 ret = false;
7739                 goto out_unlock;
7740         }
7741         dev_priv = i915_mch_dev;
7742
7743         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
7744                 dev_priv->ips.max_delay++;
7745
7746 out_unlock:
7747         spin_unlock_irq(&mchdev_lock);
7748
7749         return ret;
7750 }
7751 EXPORT_SYMBOL_GPL(i915_gpu_lower);
7752
7753 /**
7754  * i915_gpu_busy - indicate GPU business to IPS
7755  *
7756  * Tell the IPS driver whether or not the GPU is busy.
7757  */
7758 bool i915_gpu_busy(void)
7759 {
7760         bool ret = false;
7761
7762         spin_lock_irq(&mchdev_lock);
7763         if (i915_mch_dev)
7764                 ret = i915_mch_dev->gt.awake;
7765         spin_unlock_irq(&mchdev_lock);
7766
7767         return ret;
7768 }
7769 EXPORT_SYMBOL_GPL(i915_gpu_busy);
7770
7771 /**
7772  * i915_gpu_turbo_disable - disable graphics turbo
7773  *
7774  * Disable graphics turbo by resetting the max frequency and setting the
7775  * current frequency to the default.
7776  */
7777 bool i915_gpu_turbo_disable(void)
7778 {
7779         struct drm_i915_private *dev_priv;
7780         bool ret = true;
7781
7782         spin_lock_irq(&mchdev_lock);
7783         if (!i915_mch_dev) {
7784                 ret = false;
7785                 goto out_unlock;
7786         }
7787         dev_priv = i915_mch_dev;
7788
7789         dev_priv->ips.max_delay = dev_priv->ips.fstart;
7790
7791         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
7792                 ret = false;
7793
7794 out_unlock:
7795         spin_unlock_irq(&mchdev_lock);
7796
7797         return ret;
7798 }
7799 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
7800
7801 /**
7802  * Tells the intel_ips driver that the i915 driver is now loaded, if
7803  * IPS got loaded first.
7804  *
7805  * This awkward dance is so that neither module has to depend on the
7806  * other in order for IPS to do the appropriate communication of
7807  * GPU turbo limits to i915.
7808  */
7809 static void
7810 ips_ping_for_i915_load(void)
7811 {
7812         void (*link)(void);
7813
7814         link = symbol_get(ips_link_to_i915_driver);
7815         if (link) {
7816                 link();
7817                 symbol_put(ips_link_to_i915_driver);
7818         }
7819 }
7820
7821 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
7822 {
7823         /* We only register the i915 ips part with intel-ips once everything is
7824          * set up, to avoid intel-ips sneaking in and reading bogus values. */
7825         spin_lock_irq(&mchdev_lock);
7826         i915_mch_dev = dev_priv;
7827         spin_unlock_irq(&mchdev_lock);
7828
7829         ips_ping_for_i915_load();
7830 }
7831
7832 void intel_gpu_ips_teardown(void)
7833 {
7834         spin_lock_irq(&mchdev_lock);
7835         i915_mch_dev = NULL;
7836         spin_unlock_irq(&mchdev_lock);
7837 }
7838
7839 static void intel_init_emon(struct drm_i915_private *dev_priv)
7840 {
7841         u32 lcfuse;
7842         u8 pxw[16];
7843         int i;
7844
7845         /* Disable to program */
7846         I915_WRITE(ECR, 0);
7847         POSTING_READ(ECR);
7848
7849         /* Program energy weights for various events */
7850         I915_WRITE(SDEW, 0x15040d00);
7851         I915_WRITE(CSIEW0, 0x007f0000);
7852         I915_WRITE(CSIEW1, 0x1e220004);
7853         I915_WRITE(CSIEW2, 0x04000004);
7854
7855         for (i = 0; i < 5; i++)
7856                 I915_WRITE(PEW(i), 0);
7857         for (i = 0; i < 3; i++)
7858                 I915_WRITE(DEW(i), 0);
7859
7860         /* Program P-state weights to account for frequency power adjustment */
7861         for (i = 0; i < 16; i++) {
7862                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
7863                 unsigned long freq = intel_pxfreq(pxvidfreq);
7864                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7865                         PXVFREQ_PX_SHIFT;
7866                 unsigned long val;
7867
7868                 val = vid * vid;
7869                 val *= (freq / 1000);
7870                 val *= 255;
7871                 val /= (127*127*900);
7872                 if (val > 0xff)
7873                         DRM_ERROR("bad pxval: %ld\n", val);
7874                 pxw[i] = val;
7875         }
7876         /* Render standby states get 0 weight */
7877         pxw[14] = 0;
7878         pxw[15] = 0;
7879
7880         for (i = 0; i < 4; i++) {
7881                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7882                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7883                 I915_WRITE(PXW(i), val);
7884         }
7885
7886         /* Adjust magic regs to magic values (more experimental results) */
7887         I915_WRITE(OGW0, 0);
7888         I915_WRITE(OGW1, 0);
7889         I915_WRITE(EG0, 0x00007f00);
7890         I915_WRITE(EG1, 0x0000000e);
7891         I915_WRITE(EG2, 0x000e0000);
7892         I915_WRITE(EG3, 0x68000300);
7893         I915_WRITE(EG4, 0x42000000);
7894         I915_WRITE(EG5, 0x00140031);
7895         I915_WRITE(EG6, 0);
7896         I915_WRITE(EG7, 0);
7897
7898         for (i = 0; i < 8; i++)
7899                 I915_WRITE(PXWL(i), 0);
7900
7901         /* Enable PMON + select events */
7902         I915_WRITE(ECR, 0x80000019);
7903
7904         lcfuse = I915_READ(LCFUSE02);
7905
7906         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
7907 }
7908
7909 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
7910 {
7911         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7912
7913         /*
7914          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7915          * requirement.
7916          */
7917         if (!i915_modparams.enable_rc6) {
7918                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7919                 intel_runtime_pm_get(dev_priv);
7920         }
7921
7922         mutex_lock(&dev_priv->drm.struct_mutex);
7923         mutex_lock(&dev_priv->pcu_lock);
7924
7925         /* Initialize RPS limits (for userspace) */
7926         if (IS_CHERRYVIEW(dev_priv))
7927                 cherryview_init_gt_powersave(dev_priv);
7928         else if (IS_VALLEYVIEW(dev_priv))
7929                 valleyview_init_gt_powersave(dev_priv);
7930         else if (INTEL_GEN(dev_priv) >= 6)
7931                 gen6_init_rps_frequencies(dev_priv);
7932
7933         /* Derive initial user preferences/limits from the hardware limits */
7934         rps->idle_freq = rps->min_freq;
7935         rps->cur_freq = rps->idle_freq;
7936
7937         rps->max_freq_softlimit = rps->max_freq;
7938         rps->min_freq_softlimit = rps->min_freq;
7939
7940         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
7941                 rps->min_freq_softlimit =
7942                         max_t(int,
7943                               rps->efficient_freq,
7944                               intel_freq_opcode(dev_priv, 450));
7945
7946         /* After setting max-softlimit, find the overclock max freq */
7947         if (IS_GEN6(dev_priv) ||
7948             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
7949                 u32 params = 0;
7950
7951                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
7952                 if (params & BIT(31)) { /* OC supported */
7953                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7954                                          (rps->max_freq & 0xff) * 50,
7955                                          (params & 0xff) * 50);
7956                         rps->max_freq = params & 0xff;
7957                 }
7958         }
7959
7960         /* Finally allow us to boost to max by default */
7961         rps->boost_freq = rps->max_freq;
7962
7963         mutex_unlock(&dev_priv->pcu_lock);
7964         mutex_unlock(&dev_priv->drm.struct_mutex);
7965
7966         intel_autoenable_gt_powersave(dev_priv);
7967 }
7968
7969 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7970 {
7971         if (IS_VALLEYVIEW(dev_priv))
7972                 valleyview_cleanup_gt_powersave(dev_priv);
7973
7974         if (!i915_modparams.enable_rc6)
7975                 intel_runtime_pm_put(dev_priv);
7976 }
7977
7978 /**
7979  * intel_suspend_gt_powersave - suspend PM work and helper threads
7980  * @dev_priv: i915 device
7981  *
7982  * We don't want to disable RC6 or other features here, we just want
7983  * to make sure any work we've queued has finished and won't bother
7984  * us while we're suspended.
7985  */
7986 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
7987 {
7988         if (INTEL_GEN(dev_priv) < 6)
7989                 return;
7990
7991         if (cancel_delayed_work_sync(&dev_priv->gt_pm.autoenable_work))
7992                 intel_runtime_pm_put(dev_priv);
7993
7994         /* gen6_rps_idle() will be called later to disable interrupts */
7995 }
7996
7997 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
7998 {
7999         dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
8000         dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
8001         intel_disable_gt_powersave(dev_priv);
8002
8003         gen6_reset_rps_interrupts(dev_priv);
8004 }
8005
8006 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
8007 {
8008         lockdep_assert_held(&i915->pcu_lock);
8009
8010         if (!i915->gt_pm.llc_pstate.enabled)
8011                 return;
8012
8013         /* Currently there is no HW configuration to be done to disable. */
8014
8015         i915->gt_pm.llc_pstate.enabled = false;
8016 }
8017
8018 static void intel_disable_rc6(struct drm_i915_private *dev_priv)
8019 {
8020         lockdep_assert_held(&dev_priv->pcu_lock);
8021
8022         if (!dev_priv->gt_pm.rc6.enabled)
8023                 return;
8024
8025         if (INTEL_GEN(dev_priv) >= 9)
8026                 gen9_disable_rc6(dev_priv);
8027         else if (IS_CHERRYVIEW(dev_priv))
8028                 cherryview_disable_rc6(dev_priv);
8029         else if (IS_VALLEYVIEW(dev_priv))
8030                 valleyview_disable_rc6(dev_priv);
8031         else if (INTEL_GEN(dev_priv) >= 6)
8032                 gen6_disable_rc6(dev_priv);
8033
8034         dev_priv->gt_pm.rc6.enabled = false;
8035 }
8036
8037 static void intel_disable_rps(struct drm_i915_private *dev_priv)
8038 {
8039         lockdep_assert_held(&dev_priv->pcu_lock);
8040
8041         if (!dev_priv->gt_pm.rps.enabled)
8042                 return;
8043
8044         if (INTEL_GEN(dev_priv) >= 9)
8045                 gen9_disable_rps(dev_priv);
8046         else if (IS_CHERRYVIEW(dev_priv))
8047                 cherryview_disable_rps(dev_priv);
8048         else if (IS_VALLEYVIEW(dev_priv))
8049                 valleyview_disable_rps(dev_priv);
8050         else if (INTEL_GEN(dev_priv) >= 6)
8051                 gen6_disable_rps(dev_priv);
8052         else if (IS_IRONLAKE_M(dev_priv))
8053                 ironlake_disable_drps(dev_priv);
8054
8055         dev_priv->gt_pm.rps.enabled = false;
8056 }
8057
8058 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8059 {
8060         mutex_lock(&dev_priv->pcu_lock);
8061
8062         intel_disable_rc6(dev_priv);
8063         intel_disable_rps(dev_priv);
8064         if (HAS_LLC(dev_priv))
8065                 intel_disable_llc_pstate(dev_priv);
8066
8067         mutex_unlock(&dev_priv->pcu_lock);
8068 }
8069
8070 static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
8071 {
8072         lockdep_assert_held(&i915->pcu_lock);
8073
8074         if (i915->gt_pm.llc_pstate.enabled)
8075                 return;
8076
8077         gen6_update_ring_freq(i915);
8078
8079         i915->gt_pm.llc_pstate.enabled = true;
8080 }
8081
8082 static void intel_enable_rc6(struct drm_i915_private *dev_priv)
8083 {
8084         lockdep_assert_held(&dev_priv->pcu_lock);
8085
8086         if (dev_priv->gt_pm.rc6.enabled)
8087                 return;
8088
8089         if (IS_CHERRYVIEW(dev_priv))
8090                 cherryview_enable_rc6(dev_priv);
8091         else if (IS_VALLEYVIEW(dev_priv))
8092                 valleyview_enable_rc6(dev_priv);
8093         else if (INTEL_GEN(dev_priv) >= 9)
8094                 gen9_enable_rc6(dev_priv);
8095         else if (IS_BROADWELL(dev_priv))
8096                 gen8_enable_rc6(dev_priv);
8097         else if (INTEL_GEN(dev_priv) >= 6)
8098                 gen6_enable_rc6(dev_priv);
8099
8100         dev_priv->gt_pm.rc6.enabled = true;
8101 }
8102
8103 static void intel_enable_rps(struct drm_i915_private *dev_priv)
8104 {
8105         struct intel_rps *rps = &dev_priv->gt_pm.rps;
8106
8107         lockdep_assert_held(&dev_priv->pcu_lock);
8108
8109         if (rps->enabled)
8110                 return;
8111
8112         if (IS_CHERRYVIEW(dev_priv)) {
8113                 cherryview_enable_rps(dev_priv);
8114         } else if (IS_VALLEYVIEW(dev_priv)) {
8115                 valleyview_enable_rps(dev_priv);
8116         } else if (INTEL_GEN(dev_priv) >= 9) {
8117                 gen9_enable_rps(dev_priv);
8118         } else if (IS_BROADWELL(dev_priv)) {
8119                 gen8_enable_rps(dev_priv);
8120         } else if (INTEL_GEN(dev_priv) >= 6) {
8121                 gen6_enable_rps(dev_priv);
8122         } else if (IS_IRONLAKE_M(dev_priv)) {
8123                 ironlake_enable_drps(dev_priv);
8124                 intel_init_emon(dev_priv);
8125         }
8126
8127         WARN_ON(rps->max_freq < rps->min_freq);
8128         WARN_ON(rps->idle_freq > rps->max_freq);
8129
8130         WARN_ON(rps->efficient_freq < rps->min_freq);
8131         WARN_ON(rps->efficient_freq > rps->max_freq);
8132
8133         rps->enabled = true;
8134 }
8135
8136 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8137 {
8138         /* Powersaving is controlled by the host when inside a VM */
8139         if (intel_vgpu_active(dev_priv))
8140                 return;
8141
8142         mutex_lock(&dev_priv->pcu_lock);
8143
8144         intel_enable_rc6(dev_priv);
8145         intel_enable_rps(dev_priv);
8146         if (HAS_LLC(dev_priv))
8147                 intel_enable_llc_pstate(dev_priv);
8148
8149         mutex_unlock(&dev_priv->pcu_lock);
8150 }
8151
8152 static void __intel_autoenable_gt_powersave(struct work_struct *work)
8153 {
8154         struct drm_i915_private *dev_priv =
8155                 container_of(work,
8156                              typeof(*dev_priv),
8157                              gt_pm.autoenable_work.work);
8158         struct intel_engine_cs *rcs;
8159         struct drm_i915_gem_request *req;
8160
8161         rcs = dev_priv->engine[RCS];
8162         if (rcs->last_retired_context)
8163                 goto out;
8164
8165         if (!rcs->init_context)
8166                 goto out;
8167
8168         mutex_lock(&dev_priv->drm.struct_mutex);
8169
8170         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
8171         if (IS_ERR(req))
8172                 goto unlock;
8173
8174         if (!i915_modparams.enable_execlists && i915_switch_context(req) == 0)
8175                 rcs->init_context(req);
8176
8177         /* Mark the device busy, calling intel_enable_gt_powersave() */
8178         i915_add_request(req);
8179
8180 unlock:
8181         mutex_unlock(&dev_priv->drm.struct_mutex);
8182 out:
8183         intel_runtime_pm_put(dev_priv);
8184 }
8185
8186 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
8187 {
8188         if (IS_IRONLAKE_M(dev_priv)) {
8189                 ironlake_enable_drps(dev_priv);
8190                 intel_init_emon(dev_priv);
8191         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
8192                 /*
8193                  * PCU communication is slow and this doesn't need to be
8194                  * done at any specific time, so do this out of our fast path
8195                  * to make resume and init faster.
8196                  *
8197                  * We depend on the HW RC6 power context save/restore
8198                  * mechanism when entering D3 through runtime PM suspend. So
8199                  * disable RPM until RPS/RC6 is properly setup. We can only
8200                  * get here via the driver load/system resume/runtime resume
8201                  * paths, so the _noresume version is enough (and in case of
8202                  * runtime resume it's necessary).
8203                  */
8204                 if (queue_delayed_work(dev_priv->wq,
8205                                        &dev_priv->gt_pm.autoenable_work,
8206                                        round_jiffies_up_relative(HZ)))
8207                         intel_runtime_pm_get_noresume(dev_priv);
8208         }
8209 }
8210
8211 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
8212 {
8213         /*
8214          * On Ibex Peak and Cougar Point, we need to disable clock
8215          * gating for the panel power sequencer or it will fail to
8216          * start up when no ports are active.
8217          */
8218         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8219 }
8220
8221 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
8222 {
8223         enum pipe pipe;
8224
8225         for_each_pipe(dev_priv, pipe) {
8226                 I915_WRITE(DSPCNTR(pipe),
8227                            I915_READ(DSPCNTR(pipe)) |
8228                            DISPPLANE_TRICKLE_FEED_DISABLE);
8229
8230                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
8231                 POSTING_READ(DSPSURF(pipe));
8232         }
8233 }
8234
8235 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
8236 {
8237         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8238
8239         /*
8240          * Required for FBC
8241          * WaFbcDisableDpfcClockGating:ilk
8242          */
8243         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
8244                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
8245                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
8246
8247         I915_WRITE(PCH_3DCGDIS0,
8248                    MARIUNIT_CLOCK_GATE_DISABLE |
8249                    SVSMUNIT_CLOCK_GATE_DISABLE);
8250         I915_WRITE(PCH_3DCGDIS1,
8251                    VFMUNIT_CLOCK_GATE_DISABLE);
8252
8253         /*
8254          * According to the spec the following bits should be set in
8255          * order to enable memory self-refresh
8256          * The bit 22/21 of 0x42004
8257          * The bit 5 of 0x42020
8258          * The bit 15 of 0x45000
8259          */
8260         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8261                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8262                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8263         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
8264         I915_WRITE(DISP_ARB_CTL,
8265                    (I915_READ(DISP_ARB_CTL) |
8266                     DISP_FBC_WM_DIS));
8267
8268         /*
8269          * Based on the document from hardware guys the following bits
8270          * should be set unconditionally in order to enable FBC.
8271          * The bit 22 of 0x42000
8272          * The bit 22 of 0x42004
8273          * The bit 7,8,9 of 0x42020.
8274          */
8275         if (IS_IRONLAKE_M(dev_priv)) {
8276                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8277                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8278                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8279                            ILK_FBCQ_DIS);
8280                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8281                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8282                            ILK_DPARB_GATE);
8283         }
8284
8285         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8286
8287         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8288                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8289                    ILK_ELPIN_409_SELECT);
8290         I915_WRITE(_3D_CHICKEN2,
8291                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8292                    _3D_CHICKEN2_WM_READ_PIPELINED);
8293
8294         /* WaDisableRenderCachePipelinedFlush:ilk */
8295         I915_WRITE(CACHE_MODE_0,
8296                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8297
8298         /* WaDisable_RenderCache_OperationalFlush:ilk */
8299         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8300
8301         g4x_disable_trickle_feed(dev_priv);
8302
8303         ibx_init_clock_gating(dev_priv);
8304 }
8305
8306 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8307 {
8308         int pipe;
8309         uint32_t val;
8310
8311         /*
8312          * On Ibex Peak and Cougar Point, we need to disable clock
8313          * gating for the panel power sequencer or it will fail to
8314          * start up when no ports are active.
8315          */
8316         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8317                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8318                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
8319         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8320                    DPLS_EDP_PPS_FIX_DIS);
8321         /* The below fixes the weird display corruption, a few pixels shifted
8322          * downward, on (only) LVDS of some HP laptops with IVY.
8323          */
8324         for_each_pipe(dev_priv, pipe) {
8325                 val = I915_READ(TRANS_CHICKEN2(pipe));
8326                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8327                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8328                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
8329                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8330                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
8331                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
8332                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
8333                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
8334         }
8335         /* WADP0ClockGatingDisable */
8336         for_each_pipe(dev_priv, pipe) {
8337                 I915_WRITE(TRANS_CHICKEN1(pipe),
8338                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8339         }
8340 }
8341
8342 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
8343 {
8344         uint32_t tmp;
8345
8346         tmp = I915_READ(MCH_SSKPD);
8347         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
8348                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8349                               tmp);
8350 }
8351
8352 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
8353 {
8354         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8355
8356         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8357
8358         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8359                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8360                    ILK_ELPIN_409_SELECT);
8361
8362         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8363         I915_WRITE(_3D_CHICKEN,
8364                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8365
8366         /* WaDisable_RenderCache_OperationalFlush:snb */
8367         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8368
8369         /*
8370          * BSpec recoomends 8x4 when MSAA is used,
8371          * however in practice 16x4 seems fastest.
8372          *
8373          * Note that PS/WM thread counts depend on the WIZ hashing
8374          * disable bit, which we don't touch here, but it's good
8375          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8376          */
8377         I915_WRITE(GEN6_GT_MODE,
8378                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8379
8380         I915_WRITE(CACHE_MODE_0,
8381                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
8382
8383         I915_WRITE(GEN6_UCGCTL1,
8384                    I915_READ(GEN6_UCGCTL1) |
8385                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8386                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8387
8388         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8389          * gating disable must be set.  Failure to set it results in
8390          * flickering pixels due to Z write ordering failures after
8391          * some amount of runtime in the Mesa "fire" demo, and Unigine
8392          * Sanctuary and Tropics, and apparently anything else with
8393          * alpha test or pixel discard.
8394          *
8395          * According to the spec, bit 11 (RCCUNIT) must also be set,
8396          * but we didn't debug actual testcases to find it out.
8397          *
8398          * WaDisableRCCUnitClockGating:snb
8399          * WaDisableRCPBUnitClockGating:snb
8400          */
8401         I915_WRITE(GEN6_UCGCTL2,
8402                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8403                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8404
8405         /* WaStripsFansDisableFastClipPerformanceFix:snb */
8406         I915_WRITE(_3D_CHICKEN3,
8407                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
8408
8409         /*
8410          * Bspec says:
8411          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8412          * 3DSTATE_SF number of SF output attributes is more than 16."
8413          */
8414         I915_WRITE(_3D_CHICKEN3,
8415                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
8416
8417         /*
8418          * According to the spec the following bits should be
8419          * set in order to enable memory self-refresh and fbc:
8420          * The bit21 and bit22 of 0x42000
8421          * The bit21 and bit22 of 0x42004
8422          * The bit5 and bit7 of 0x42020
8423          * The bit14 of 0x70180
8424          * The bit14 of 0x71180
8425          *
8426          * WaFbcAsynchFlipDisableFbcQueue:snb
8427          */
8428         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8429                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8430                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8431         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8432                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8433                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8434         I915_WRITE(ILK_DSPCLK_GATE_D,
8435                    I915_READ(ILK_DSPCLK_GATE_D) |
8436                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
8437                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
8438
8439         g4x_disable_trickle_feed(dev_priv);
8440
8441         cpt_init_clock_gating(dev_priv);
8442
8443         gen6_check_mch_setup(dev_priv);
8444 }
8445
8446 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8447 {
8448         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8449
8450         /*
8451          * WaVSThreadDispatchOverride:ivb,vlv
8452          *
8453          * This actually overrides the dispatch
8454          * mode for all thread types.
8455          */
8456         reg &= ~GEN7_FF_SCHED_MASK;
8457         reg |= GEN7_FF_TS_SCHED_HW;
8458         reg |= GEN7_FF_VS_SCHED_HW;
8459         reg |= GEN7_FF_DS_SCHED_HW;
8460
8461         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8462 }
8463
8464 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
8465 {
8466         /*
8467          * TODO: this bit should only be enabled when really needed, then
8468          * disabled when not needed anymore in order to save power.
8469          */
8470         if (HAS_PCH_LPT_LP(dev_priv))
8471                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
8472                            I915_READ(SOUTH_DSPCLK_GATE_D) |
8473                            PCH_LP_PARTITION_LEVEL_DISABLE);
8474
8475         /* WADPOClockGatingDisable:hsw */
8476         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
8477                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
8478                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8479 }
8480
8481 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
8482 {
8483         if (HAS_PCH_LPT_LP(dev_priv)) {
8484                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
8485
8486                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8487                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8488         }
8489 }
8490
8491 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
8492                                    int general_prio_credits,
8493                                    int high_prio_credits)
8494 {
8495         u32 misccpctl;
8496         u32 val;
8497
8498         /* WaTempDisableDOPClkGating:bdw */
8499         misccpctl = I915_READ(GEN7_MISCCPCTL);
8500         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
8501
8502         val = I915_READ(GEN8_L3SQCREG1);
8503         val &= ~L3_PRIO_CREDITS_MASK;
8504         val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
8505         val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
8506         I915_WRITE(GEN8_L3SQCREG1, val);
8507
8508         /*
8509          * Wait at least 100 clocks before re-enabling clock gating.
8510          * See the definition of L3SQCREG1 in BSpec.
8511          */
8512         POSTING_READ(GEN8_L3SQCREG1);
8513         udelay(1);
8514         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
8515 }
8516
8517 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
8518 {
8519         if (!HAS_PCH_CNP(dev_priv))
8520                 return;
8521
8522         /* Wa #1181 */
8523         I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
8524                    CNP_PWM_CGE_GATING_DISABLE);
8525 }
8526
8527 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
8528 {
8529         u32 val;
8530         cnp_init_clock_gating(dev_priv);
8531
8532         /* This is not an Wa. Enable for better image quality */
8533         I915_WRITE(_3D_CHICKEN3,
8534                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
8535
8536         /* WaEnableChickenDCPR:cnl */
8537         I915_WRITE(GEN8_CHICKEN_DCPR_1,
8538                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
8539
8540         /* WaFbcWakeMemOn:cnl */
8541         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
8542                    DISP_FBC_MEMORY_WAKE);
8543
8544         /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
8545         if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
8546                 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
8547                            I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
8548                            SARBUNIT_CLKGATE_DIS);
8549
8550         /* Display WA #1133: WaFbcSkipSegments:cnl */
8551         val = I915_READ(ILK_DPFC_CHICKEN);
8552         val &= ~GLK_SKIP_SEG_COUNT_MASK;
8553         val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
8554         I915_WRITE(ILK_DPFC_CHICKEN, val);
8555 }
8556
8557 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
8558 {
8559         cnp_init_clock_gating(dev_priv);
8560         gen9_init_clock_gating(dev_priv);
8561
8562         /* WaFbcNukeOnHostModify:cfl */
8563         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8564                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8565 }
8566
8567 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
8568 {
8569         gen9_init_clock_gating(dev_priv);
8570
8571         /* WaDisableSDEUnitClockGating:kbl */
8572         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8573                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8574                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8575
8576         /* WaDisableGamClockGating:kbl */
8577         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8578                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8579                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
8580
8581         /* WaFbcNukeOnHostModify:kbl */
8582         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8583                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8584 }
8585
8586 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
8587 {
8588         gen9_init_clock_gating(dev_priv);
8589
8590         /* WAC6entrylatency:skl */
8591         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
8592                    FBC_LLC_FULLY_OPEN);
8593
8594         /* WaFbcNukeOnHostModify:skl */
8595         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8596                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8597 }
8598
8599 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
8600 {
8601         /* The GTT cache must be disabled if the system is using 2M pages. */
8602         bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
8603                                                  I915_GTT_PAGE_SIZE_2M);
8604         enum pipe pipe;
8605
8606         /* WaSwitchSolVfFArbitrationPriority:bdw */
8607         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8608
8609         /* WaPsrDPAMaskVBlankInSRD:bdw */
8610         I915_WRITE(CHICKEN_PAR1_1,
8611                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
8612
8613         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8614         for_each_pipe(dev_priv, pipe) {
8615                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
8616                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
8617                            BDW_DPRS_MASK_VBLANK_SRD);
8618         }
8619
8620         /* WaVSRefCountFullforceMissDisable:bdw */
8621         /* WaDSRefCountFullforceMissDisable:bdw */
8622         I915_WRITE(GEN7_FF_THREAD_MODE,
8623                    I915_READ(GEN7_FF_THREAD_MODE) &
8624                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8625
8626         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8627                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8628
8629         /* WaDisableSDEUnitClockGating:bdw */
8630         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8631                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8632
8633         /* WaProgramL3SqcReg1Default:bdw */
8634         gen8_set_l3sqc_credits(dev_priv, 30, 2);
8635
8636         /* WaGttCachingOffByDefault:bdw */
8637         I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
8638
8639         /* WaKVMNotificationOnConfigChange:bdw */
8640         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
8641                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
8642
8643         lpt_init_clock_gating(dev_priv);
8644
8645         /* WaDisableDopClockGating:bdw
8646          *
8647          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8648          * clock gating.
8649          */
8650         I915_WRITE(GEN6_UCGCTL1,
8651                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
8652 }
8653
8654 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
8655 {
8656         /* L3 caching of data atomics doesn't work -- disable it. */
8657         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
8658         I915_WRITE(HSW_ROW_CHICKEN3,
8659                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
8660
8661         /* This is required by WaCatErrorRejectionIssue:hsw */
8662         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8663                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8664                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8665
8666         /* WaVSRefCountFullforceMissDisable:hsw */
8667         I915_WRITE(GEN7_FF_THREAD_MODE,
8668                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
8669
8670         /* WaDisable_RenderCache_OperationalFlush:hsw */
8671         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8672
8673         /* enable HiZ Raw Stall Optimization */
8674         I915_WRITE(CACHE_MODE_0_GEN7,
8675                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8676
8677         /* WaDisable4x2SubspanOptimization:hsw */
8678         I915_WRITE(CACHE_MODE_1,
8679                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8680
8681         /*
8682          * BSpec recommends 8x4 when MSAA is used,
8683          * however in practice 16x4 seems fastest.
8684          *
8685          * Note that PS/WM thread counts depend on the WIZ hashing
8686          * disable bit, which we don't touch here, but it's good
8687          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8688          */
8689         I915_WRITE(GEN7_GT_MODE,
8690                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8691
8692         /* WaSampleCChickenBitEnable:hsw */
8693         I915_WRITE(HALF_SLICE_CHICKEN3,
8694                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
8695
8696         /* WaSwitchSolVfFArbitrationPriority:hsw */
8697         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8698
8699         lpt_init_clock_gating(dev_priv);
8700 }
8701
8702 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
8703 {
8704         uint32_t snpcr;
8705
8706         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
8707
8708         /* WaDisableEarlyCull:ivb */
8709         I915_WRITE(_3D_CHICKEN3,
8710                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8711
8712         /* WaDisableBackToBackFlipFix:ivb */
8713         I915_WRITE(IVB_CHICKEN3,
8714                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8715                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8716
8717         /* WaDisablePSDDualDispatchEnable:ivb */
8718         if (IS_IVB_GT1(dev_priv))
8719                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8720                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8721
8722         /* WaDisable_RenderCache_OperationalFlush:ivb */
8723         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8724
8725         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8726         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8727                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8728
8729         /* WaApplyL3ControlAndL3ChickenMode:ivb */
8730         I915_WRITE(GEN7_L3CNTLREG1,
8731                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8732         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8733                    GEN7_WA_L3_CHICKEN_MODE);
8734         if (IS_IVB_GT1(dev_priv))
8735                 I915_WRITE(GEN7_ROW_CHICKEN2,
8736                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8737         else {
8738                 /* must write both registers */
8739                 I915_WRITE(GEN7_ROW_CHICKEN2,
8740                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8741                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
8742                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8743         }
8744
8745         /* WaForceL3Serialization:ivb */
8746         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8747                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8748
8749         /*
8750          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8751          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8752          */
8753         I915_WRITE(GEN6_UCGCTL2,
8754                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8755
8756         /* This is required by WaCatErrorRejectionIssue:ivb */
8757         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8758                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8759                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8760
8761         g4x_disable_trickle_feed(dev_priv);
8762
8763         gen7_setup_fixed_func_scheduler(dev_priv);
8764
8765         if (0) { /* causes HiZ corruption on ivb:gt1 */
8766                 /* enable HiZ Raw Stall Optimization */
8767                 I915_WRITE(CACHE_MODE_0_GEN7,
8768                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8769         }
8770
8771         /* WaDisable4x2SubspanOptimization:ivb */
8772         I915_WRITE(CACHE_MODE_1,
8773                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8774
8775         /*
8776          * BSpec recommends 8x4 when MSAA is used,
8777          * however in practice 16x4 seems fastest.
8778          *
8779          * Note that PS/WM thread counts depend on the WIZ hashing
8780          * disable bit, which we don't touch here, but it's good
8781          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8782          */
8783         I915_WRITE(GEN7_GT_MODE,
8784                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8785
8786         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
8787         snpcr &= ~GEN6_MBC_SNPCR_MASK;
8788         snpcr |= GEN6_MBC_SNPCR_MED;
8789         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
8790
8791         if (!HAS_PCH_NOP(dev_priv))
8792                 cpt_init_clock_gating(dev_priv);
8793
8794         gen6_check_mch_setup(dev_priv);
8795 }
8796
8797 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
8798 {
8799         /* WaDisableEarlyCull:vlv */
8800         I915_WRITE(_3D_CHICKEN3,
8801                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8802
8803         /* WaDisableBackToBackFlipFix:vlv */
8804         I915_WRITE(IVB_CHICKEN3,
8805                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8806                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8807
8808         /* WaPsdDispatchEnable:vlv */
8809         /* WaDisablePSDDualDispatchEnable:vlv */
8810         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8811                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
8812                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8813
8814         /* WaDisable_RenderCache_OperationalFlush:vlv */
8815         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8816
8817         /* WaForceL3Serialization:vlv */
8818         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8819                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8820
8821         /* WaDisableDopClockGating:vlv */
8822         I915_WRITE(GEN7_ROW_CHICKEN2,
8823                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8824
8825         /* This is required by WaCatErrorRejectionIssue:vlv */
8826         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8827                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8828                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8829
8830         gen7_setup_fixed_func_scheduler(dev_priv);
8831
8832         /*
8833          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8834          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8835          */
8836         I915_WRITE(GEN6_UCGCTL2,
8837                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8838
8839         /* WaDisableL3Bank2xClockGate:vlv
8840          * Disabling L3 clock gating- MMIO 940c[25] = 1
8841          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8842         I915_WRITE(GEN7_UCGCTL4,
8843                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
8844
8845         /*
8846          * BSpec says this must be set, even though
8847          * WaDisable4x2SubspanOptimization isn't listed for VLV.
8848          */
8849         I915_WRITE(CACHE_MODE_1,
8850                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8851
8852         /*
8853          * BSpec recommends 8x4 when MSAA is used,
8854          * however in practice 16x4 seems fastest.
8855          *
8856          * Note that PS/WM thread counts depend on the WIZ hashing
8857          * disable bit, which we don't touch here, but it's good
8858          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8859          */
8860         I915_WRITE(GEN7_GT_MODE,
8861                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8862
8863         /*
8864          * WaIncreaseL3CreditsForVLVB0:vlv
8865          * This is the hardware default actually.
8866          */
8867         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
8868
8869         /*
8870          * WaDisableVLVClockGating_VBIIssue:vlv
8871          * Disable clock gating on th GCFG unit to prevent a delay
8872          * in the reporting of vblank events.
8873          */
8874         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
8875 }
8876
8877 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
8878 {
8879         /* WaVSRefCountFullforceMissDisable:chv */
8880         /* WaDSRefCountFullforceMissDisable:chv */
8881         I915_WRITE(GEN7_FF_THREAD_MODE,
8882                    I915_READ(GEN7_FF_THREAD_MODE) &
8883                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8884
8885         /* WaDisableSemaphoreAndSyncFlipWait:chv */
8886         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8887                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8888
8889         /* WaDisableCSUnitClockGating:chv */
8890         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8891                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8892
8893         /* WaDisableSDEUnitClockGating:chv */
8894         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8895                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8896
8897         /*
8898          * WaProgramL3SqcReg1Default:chv
8899          * See gfxspecs/Related Documents/Performance Guide/
8900          * LSQC Setting Recommendations.
8901          */
8902         gen8_set_l3sqc_credits(dev_priv, 38, 2);
8903
8904         /*
8905          * GTT cache may not work with big pages, so if those
8906          * are ever enabled GTT cache may need to be disabled.
8907          */
8908         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8909 }
8910
8911 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
8912 {
8913         uint32_t dspclk_gate;
8914
8915         I915_WRITE(RENCLK_GATE_D1, 0);
8916         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8917                    GS_UNIT_CLOCK_GATE_DISABLE |
8918                    CL_UNIT_CLOCK_GATE_DISABLE);
8919         I915_WRITE(RAMCLK_GATE_D, 0);
8920         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8921                 OVRUNIT_CLOCK_GATE_DISABLE |
8922                 OVCUNIT_CLOCK_GATE_DISABLE;
8923         if (IS_GM45(dev_priv))
8924                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8925         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8926
8927         /* WaDisableRenderCachePipelinedFlush */
8928         I915_WRITE(CACHE_MODE_0,
8929                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8930
8931         /* WaDisable_RenderCache_OperationalFlush:g4x */
8932         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8933
8934         g4x_disable_trickle_feed(dev_priv);
8935 }
8936
8937 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
8938 {
8939         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8940         I915_WRITE(RENCLK_GATE_D2, 0);
8941         I915_WRITE(DSPCLK_GATE_D, 0);
8942         I915_WRITE(RAMCLK_GATE_D, 0);
8943         I915_WRITE16(DEUC, 0);
8944         I915_WRITE(MI_ARB_STATE,
8945                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8946
8947         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8948         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8949 }
8950
8951 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
8952 {
8953         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8954                    I965_RCC_CLOCK_GATE_DISABLE |
8955                    I965_RCPB_CLOCK_GATE_DISABLE |
8956                    I965_ISC_CLOCK_GATE_DISABLE |
8957                    I965_FBC_CLOCK_GATE_DISABLE);
8958         I915_WRITE(RENCLK_GATE_D2, 0);
8959         I915_WRITE(MI_ARB_STATE,
8960                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8961
8962         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8963         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8964 }
8965
8966 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
8967 {
8968         u32 dstate = I915_READ(D_STATE);
8969
8970         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8971                 DSTATE_DOT_CLOCK_GATING;
8972         I915_WRITE(D_STATE, dstate);
8973
8974         if (IS_PINEVIEW(dev_priv))
8975                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
8976
8977         /* IIR "flip pending" means done if this bit is set */
8978         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
8979
8980         /* interrupts should cause a wake up from C3 */
8981         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
8982
8983         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8984         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
8985
8986         I915_WRITE(MI_ARB_STATE,
8987                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8988 }
8989
8990 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
8991 {
8992         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8993
8994         /* interrupts should cause a wake up from C3 */
8995         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
8996                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
8997
8998         I915_WRITE(MEM_MODE,
8999                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
9000 }
9001
9002 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
9003 {
9004         I915_WRITE(MEM_MODE,
9005                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
9006                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
9007 }
9008
9009 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
9010 {
9011         dev_priv->display.init_clock_gating(dev_priv);
9012 }
9013
9014 void intel_suspend_hw(struct drm_i915_private *dev_priv)
9015 {
9016         if (HAS_PCH_LPT(dev_priv))
9017                 lpt_suspend_hw(dev_priv);
9018 }
9019
9020 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
9021 {
9022         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
9023 }
9024
9025 /**
9026  * intel_init_clock_gating_hooks - setup the clock gating hooks
9027  * @dev_priv: device private
9028  *
9029  * Setup the hooks that configure which clocks of a given platform can be
9030  * gated and also apply various GT and display specific workarounds for these
9031  * platforms. Note that some GT specific workarounds are applied separately
9032  * when GPU contexts or batchbuffers start their execution.
9033  */
9034 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
9035 {
9036         if (IS_CANNONLAKE(dev_priv))
9037                 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
9038         else if (IS_COFFEELAKE(dev_priv))
9039                 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
9040         else if (IS_SKYLAKE(dev_priv))
9041                 dev_priv->display.init_clock_gating = skl_init_clock_gating;
9042         else if (IS_KABYLAKE(dev_priv))
9043                 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
9044         else if (IS_BROXTON(dev_priv))
9045                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
9046         else if (IS_GEMINILAKE(dev_priv))
9047                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
9048         else if (IS_BROADWELL(dev_priv))
9049                 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
9050         else if (IS_CHERRYVIEW(dev_priv))
9051                 dev_priv->display.init_clock_gating = chv_init_clock_gating;
9052         else if (IS_HASWELL(dev_priv))
9053                 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
9054         else if (IS_IVYBRIDGE(dev_priv))
9055                 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
9056         else if (IS_VALLEYVIEW(dev_priv))
9057                 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
9058         else if (IS_GEN6(dev_priv))
9059                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9060         else if (IS_GEN5(dev_priv))
9061                 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
9062         else if (IS_G4X(dev_priv))
9063                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9064         else if (IS_I965GM(dev_priv))
9065                 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
9066         else if (IS_I965G(dev_priv))
9067                 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
9068         else if (IS_GEN3(dev_priv))
9069                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9070         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
9071                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9072         else if (IS_GEN2(dev_priv))
9073                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9074         else {
9075                 MISSING_CASE(INTEL_DEVID(dev_priv));
9076                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
9077         }
9078 }
9079
9080 /* Set up chip specific power management-related functions */
9081 void intel_init_pm(struct drm_i915_private *dev_priv)
9082 {
9083         intel_fbc_init(dev_priv);
9084
9085         /* For cxsr */
9086         if (IS_PINEVIEW(dev_priv))
9087                 i915_pineview_get_mem_freq(dev_priv);
9088         else if (IS_GEN5(dev_priv))
9089                 i915_ironlake_get_mem_freq(dev_priv);
9090
9091         /* For FIFO watermark updates */
9092         if (INTEL_GEN(dev_priv) >= 9) {
9093                 skl_setup_wm_latency(dev_priv);
9094                 dev_priv->display.initial_watermarks = skl_initial_wm;
9095                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
9096                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
9097         } else if (HAS_PCH_SPLIT(dev_priv)) {
9098                 ilk_setup_wm_latency(dev_priv);
9099
9100                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
9101                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
9102                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
9103                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
9104                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
9105                         dev_priv->display.compute_intermediate_wm =
9106                                 ilk_compute_intermediate_wm;
9107                         dev_priv->display.initial_watermarks =
9108                                 ilk_initial_watermarks;
9109                         dev_priv->display.optimize_watermarks =
9110                                 ilk_optimize_watermarks;
9111                 } else {
9112                         DRM_DEBUG_KMS("Failed to read display plane latency. "
9113                                       "Disable CxSR\n");
9114                 }
9115         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9116                 vlv_setup_wm_latency(dev_priv);
9117                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
9118                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
9119                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
9120                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
9121                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
9122         } else if (IS_G4X(dev_priv)) {
9123                 g4x_setup_wm_latency(dev_priv);
9124                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
9125                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
9126                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
9127                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
9128         } else if (IS_PINEVIEW(dev_priv)) {
9129                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
9130                                             dev_priv->is_ddr3,
9131                                             dev_priv->fsb_freq,
9132                                             dev_priv->mem_freq)) {
9133                         DRM_INFO("failed to find known CxSR latency "
9134                                  "(found ddr%s fsb freq %d, mem freq %d), "
9135                                  "disabling CxSR\n",
9136                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9137                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9138                         /* Disable CxSR and never update its watermark again */
9139                         intel_set_memory_cxsr(dev_priv, false);
9140                         dev_priv->display.update_wm = NULL;
9141                 } else
9142                         dev_priv->display.update_wm = pineview_update_wm;
9143         } else if (IS_GEN4(dev_priv)) {
9144                 dev_priv->display.update_wm = i965_update_wm;
9145         } else if (IS_GEN3(dev_priv)) {
9146                 dev_priv->display.update_wm = i9xx_update_wm;
9147                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9148         } else if (IS_GEN2(dev_priv)) {
9149                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
9150                         dev_priv->display.update_wm = i845_update_wm;
9151                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9152                 } else {
9153                         dev_priv->display.update_wm = i9xx_update_wm;
9154                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9155                 }
9156         } else {
9157                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
9158         }
9159 }
9160
9161 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
9162 {
9163         uint32_t flags =
9164                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
9165
9166         switch (flags) {
9167         case GEN6_PCODE_SUCCESS:
9168                 return 0;
9169         case GEN6_PCODE_UNIMPLEMENTED_CMD:
9170                 return -ENODEV;
9171         case GEN6_PCODE_ILLEGAL_CMD:
9172                 return -ENXIO;
9173         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9174         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9175                 return -EOVERFLOW;
9176         case GEN6_PCODE_TIMEOUT:
9177                 return -ETIMEDOUT;
9178         default:
9179                 MISSING_CASE(flags);
9180                 return 0;
9181         }
9182 }
9183
9184 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
9185 {
9186         uint32_t flags =
9187                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
9188
9189         switch (flags) {
9190         case GEN6_PCODE_SUCCESS:
9191                 return 0;
9192         case GEN6_PCODE_ILLEGAL_CMD:
9193                 return -ENXIO;
9194         case GEN7_PCODE_TIMEOUT:
9195                 return -ETIMEDOUT;
9196         case GEN7_PCODE_ILLEGAL_DATA:
9197                 return -EINVAL;
9198         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9199                 return -EOVERFLOW;
9200         default:
9201                 MISSING_CASE(flags);
9202                 return 0;
9203         }
9204 }
9205
9206 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
9207 {
9208         int status;
9209
9210         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9211
9212         /* GEN6_PCODE_* are outside of the forcewake domain, we can
9213          * use te fw I915_READ variants to reduce the amount of work
9214          * required when reading/writing.
9215          */
9216
9217         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
9218                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
9219                                  mbox, __builtin_return_address(0));
9220                 return -EAGAIN;
9221         }
9222
9223         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
9224         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
9225         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
9226
9227         if (__intel_wait_for_register_fw(dev_priv,
9228                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
9229                                          500, 0, NULL)) {
9230                 DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
9231                           mbox, __builtin_return_address(0));
9232                 return -ETIMEDOUT;
9233         }
9234
9235         *val = I915_READ_FW(GEN6_PCODE_DATA);
9236         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
9237
9238         if (INTEL_GEN(dev_priv) > 6)
9239                 status = gen7_check_mailbox_status(dev_priv);
9240         else
9241                 status = gen6_check_mailbox_status(dev_priv);
9242
9243         if (status) {
9244                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
9245                                  mbox, __builtin_return_address(0), status);
9246                 return status;
9247         }
9248
9249         return 0;
9250 }
9251
9252 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
9253                             u32 mbox, u32 val)
9254 {
9255         int status;
9256
9257         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9258
9259         /* GEN6_PCODE_* are outside of the forcewake domain, we can
9260          * use te fw I915_READ variants to reduce the amount of work
9261          * required when reading/writing.
9262          */
9263
9264         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
9265                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
9266                                  val, mbox, __builtin_return_address(0));
9267                 return -EAGAIN;
9268         }
9269
9270         I915_WRITE_FW(GEN6_PCODE_DATA, val);
9271         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
9272         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
9273
9274         if (__intel_wait_for_register_fw(dev_priv,
9275                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
9276                                          500, 0, NULL)) {
9277                 DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
9278                           val, mbox, __builtin_return_address(0));
9279                 return -ETIMEDOUT;
9280         }
9281
9282         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
9283
9284         if (INTEL_GEN(dev_priv) > 6)
9285                 status = gen7_check_mailbox_status(dev_priv);
9286         else
9287                 status = gen6_check_mailbox_status(dev_priv);
9288
9289         if (status) {
9290                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
9291                                  val, mbox, __builtin_return_address(0), status);
9292                 return status;
9293         }
9294
9295         return 0;
9296 }
9297
9298 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
9299                                   u32 request, u32 reply_mask, u32 reply,
9300                                   u32 *status)
9301 {
9302         u32 val = request;
9303
9304         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
9305
9306         return *status || ((val & reply_mask) == reply);
9307 }
9308
9309 /**
9310  * skl_pcode_request - send PCODE request until acknowledgment
9311  * @dev_priv: device private
9312  * @mbox: PCODE mailbox ID the request is targeted for
9313  * @request: request ID
9314  * @reply_mask: mask used to check for request acknowledgment
9315  * @reply: value used to check for request acknowledgment
9316  * @timeout_base_ms: timeout for polling with preemption enabled
9317  *
9318  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
9319  * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
9320  * The request is acknowledged once the PCODE reply dword equals @reply after
9321  * applying @reply_mask. Polling is first attempted with preemption enabled
9322  * for @timeout_base_ms and if this times out for another 50 ms with
9323  * preemption disabled.
9324  *
9325  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
9326  * other error as reported by PCODE.
9327  */
9328 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
9329                       u32 reply_mask, u32 reply, int timeout_base_ms)
9330 {
9331         u32 status;
9332         int ret;
9333
9334         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9335
9336 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9337                                    &status)
9338
9339         /*
9340          * Prime the PCODE by doing a request first. Normally it guarantees
9341          * that a subsequent request, at most @timeout_base_ms later, succeeds.
9342          * _wait_for() doesn't guarantee when its passed condition is evaluated
9343          * first, so send the first request explicitly.
9344          */
9345         if (COND) {
9346                 ret = 0;
9347                 goto out;
9348         }
9349         ret = _wait_for(COND, timeout_base_ms * 1000, 10);
9350         if (!ret)
9351                 goto out;
9352
9353         /*
9354          * The above can time out if the number of requests was low (2 in the
9355          * worst case) _and_ PCODE was busy for some reason even after a
9356          * (queued) request and @timeout_base_ms delay. As a workaround retry
9357          * the poll with preemption disabled to maximize the number of
9358          * requests. Increase the timeout from @timeout_base_ms to 50ms to
9359          * account for interrupts that could reduce the number of these
9360          * requests, and for any quirks of the PCODE firmware that delays
9361          * the request completion.
9362          */
9363         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9364         WARN_ON_ONCE(timeout_base_ms > 3);
9365         preempt_disable();
9366         ret = wait_for_atomic(COND, 50);
9367         preempt_enable();
9368
9369 out:
9370         return ret ? ret : status;
9371 #undef COND
9372 }
9373
9374 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9375 {
9376         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9377
9378         /*
9379          * N = val - 0xb7
9380          * Slow = Fast = GPLL ref * N
9381          */
9382         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
9383 }
9384
9385 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9386 {
9387         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9388
9389         return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
9390 }
9391
9392 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9393 {
9394         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9395
9396         /*
9397          * N = val / 2
9398          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9399          */
9400         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
9401 }
9402
9403 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9404 {
9405         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9406
9407         /* CHV needs even values */
9408         return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
9409 }
9410
9411 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9412 {
9413         if (INTEL_GEN(dev_priv) >= 9)
9414                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9415                                          GEN9_FREQ_SCALER);
9416         else if (IS_CHERRYVIEW(dev_priv))
9417                 return chv_gpu_freq(dev_priv, val);
9418         else if (IS_VALLEYVIEW(dev_priv))
9419                 return byt_gpu_freq(dev_priv, val);
9420         else
9421                 return val * GT_FREQUENCY_MULTIPLIER;
9422 }
9423
9424 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9425 {
9426         if (INTEL_GEN(dev_priv) >= 9)
9427                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9428                                          GT_FREQUENCY_MULTIPLIER);
9429         else if (IS_CHERRYVIEW(dev_priv))
9430                 return chv_freq_opcode(dev_priv, val);
9431         else if (IS_VALLEYVIEW(dev_priv))
9432                 return byt_freq_opcode(dev_priv, val);
9433         else
9434                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9435 }
9436
9437 void intel_pm_setup(struct drm_i915_private *dev_priv)
9438 {
9439         mutex_init(&dev_priv->pcu_lock);
9440
9441         INIT_DELAYED_WORK(&dev_priv->gt_pm.autoenable_work,
9442                           __intel_autoenable_gt_powersave);
9443         atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
9444
9445         dev_priv->runtime_pm.suspended = false;
9446         atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
9447 }
9448
9449 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9450                              const i915_reg_t reg)
9451 {
9452         u32 lower, upper, tmp;
9453         int loop = 2;
9454
9455         /* The register accessed do not need forcewake. We borrow
9456          * uncore lock to prevent concurrent access to range reg.
9457          */
9458         spin_lock_irq(&dev_priv->uncore.lock);
9459
9460         /* vlv and chv residency counters are 40 bits in width.
9461          * With a control bit, we can choose between upper or lower
9462          * 32bit window into this counter.
9463          *
9464          * Although we always use the counter in high-range mode elsewhere,
9465          * userspace may attempt to read the value before rc6 is initialised,
9466          * before we have set the default VLV_COUNTER_CONTROL value. So always
9467          * set the high bit to be safe.
9468          */
9469         I915_WRITE_FW(VLV_COUNTER_CONTROL,
9470                       _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9471         upper = I915_READ_FW(reg);
9472         do {
9473                 tmp = upper;
9474
9475                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9476                               _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9477                 lower = I915_READ_FW(reg);
9478
9479                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9480                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9481                 upper = I915_READ_FW(reg);
9482         } while (upper != tmp && --loop);
9483
9484         /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9485          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9486          * now.
9487          */
9488
9489         spin_unlock_irq(&dev_priv->uncore.lock);
9490
9491         return lower | (u64)upper << 8;
9492 }
9493
9494 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
9495                            const i915_reg_t reg)
9496 {
9497         u64 time_hw, units, div;
9498
9499         if (!intel_rc6_enabled())
9500                 return 0;
9501
9502         intel_runtime_pm_get(dev_priv);
9503
9504         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9505         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9506                 units = 1000;
9507                 div = dev_priv->czclk_freq;
9508
9509                 time_hw = vlv_residency_raw(dev_priv, reg);
9510         } else if (IS_GEN9_LP(dev_priv)) {
9511                 units = 1000;
9512                 div = 1200;             /* 833.33ns */
9513
9514                 time_hw = I915_READ(reg);
9515         } else {
9516                 units = 128000; /* 1.28us */
9517                 div = 100000;
9518
9519                 time_hw = I915_READ(reg);
9520         }
9521
9522         intel_runtime_pm_put(dev_priv);
9523         return DIV_ROUND_UP_ULL(time_hw * units, div);
9524 }