drivers/cpufreq/s3c64xx-cpufreq.c

   1 /*
   2  * Copyright 2009 Wolfson Microelectronics plc
   3  *
   4  * S3C64xx CPUfreq Support
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/init.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/regulator/consumer.h>
  18
  19 static struct clk *armclk;
  20 static struct regulator *vddarm;
  21 static unsigned long regulator_latency;
  22
  23 #ifdef CONFIG_CPU_S3C6410
  24 struct s3c64xx_dvfs {
  25         unsigned int vddarm_min;
  26         unsigned int vddarm_max;
  27 };
  28
  29 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
  30         [0] = { 1000000, 1150000 },
  31         [1] = { 1050000, 1150000 },
  32         [2] = { 1100000, 1150000 },
  33         [3] = { 1200000, 1350000 },
  34         [4] = { 1300000, 1350000 },
  35 };
  36
  37 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
  38         { 0,  66000 },
  39         { 0, 100000 },
  40         { 0, 133000 },
  41         { 1, 200000 },
  42         { 1, 222000 },
  43         { 1, 266000 },
  44         { 2, 333000 },
  45         { 2, 400000 },
  46         { 2, 532000 },
  47         { 2, 533000 },
  48         { 3, 667000 },
  49         { 4, 800000 },
  50         { 0, CPUFREQ_TABLE_END },
  51 };
  52 #endif
  53
  54 static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
  55 {
  56         if (policy->cpu != 0)
  57                 return -EINVAL;
  58
  59         return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
  60 }
  61
  62 static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
  63 {
  64         if (cpu != 0)
  65                 return 0;
  66
  67         return clk_get_rate(armclk) / 1000;
  68 }
  69
  70 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
  71                                       unsigned int target_freq,
  72                                       unsigned int relation)
  73 {
  74         int ret;
  75         unsigned int i;
  76         struct cpufreq_freqs freqs;
  77         struct s3c64xx_dvfs *dvfs;
  78
  79         ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
  80                                              target_freq, relation, &i);
  81         if (ret != 0)
  82                 return ret;
  83
  84         freqs.cpu = 0;
  85         freqs.old = clk_get_rate(armclk) / 1000;
  86         freqs.new = s3c64xx_freq_table[i].frequency;
  87         freqs.flags = 0;
  88         dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
  89
  90         if (freqs.old == freqs.new)
  91                 return 0;
  92
  93         pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
  94
  95         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  96
  97 #ifdef CONFIG_REGULATOR
  98         if (vddarm && freqs.new > freqs.old) {
  99                 ret = regulator_set_voltage(vddarm,
 100                                             dvfs->vddarm_min,
 101                                             dvfs->vddarm_max);
 102                 if (ret != 0) {
 103                         pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
 104                                freqs.new, ret);
 105                         goto err;
 106                 }
 107         }
 108 #endif
 109
 110         ret = clk_set_rate(armclk, freqs.new * 1000);
 111         if (ret < 0) {
 112                 pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
 113                        freqs.new, ret);
 114                 goto err;
 115         }
 116
 117         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 118
 119 #ifdef CONFIG_REGULATOR
 120         if (vddarm && freqs.new < freqs.old) {
 121                 ret = regulator_set_voltage(vddarm,
 122                                             dvfs->vddarm_min,
 123                                             dvfs->vddarm_max);
 124                 if (ret != 0) {
 125                         pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
 126                                freqs.new, ret);
 127                         goto err_clk;
 128                 }
 129         }
 130 #endif
 131
 132         pr_debug("cpufreq: Set actual frequency %lukHz\n",
 133                  clk_get_rate(armclk) / 1000);
 134
 135         return 0;
 136
 137 err_clk:
 138         if (clk_set_rate(armclk, freqs.old * 1000) < 0)
 139                 pr_err("Failed to restore original clock rate\n");
 140 err:
 141         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 142
 143         return ret;
 144 }
 145
 146 #ifdef CONFIG_REGULATOR
 147 static void __init s3c64xx_cpufreq_config_regulator(void)
 148 {
 149         int count, v, i, found;
 150         struct cpufreq_frequency_table *freq;
 151         struct s3c64xx_dvfs *dvfs;
 152
 153         count = regulator_count_voltages(vddarm);
 154         if (count < 0) {
 155                 pr_err("cpufreq: Unable to check supported voltages\n");
 156         }
 157
 158         freq = s3c64xx_freq_table;
 159         while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
 160                 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
 161                         continue;
 162
 163                 dvfs = &s3c64xx_dvfs_table[freq->index];
 164                 found = 0;
 165
 166                 for (i = 0; i < count; i++) {
 167                         v = regulator_list_voltage(vddarm, i);
 168                         if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
 169                                 found = 1;
 170                 }
 171
 172                 if (!found) {
 173                         pr_debug("cpufreq: %dkHz unsupported by regulator\n",
 174                                  freq->frequency);
 175                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 176                 }
 177
 178                 freq++;
 179         }
 180
 181         /* Guess based on having to do an I2C/SPI write; in future we
 182          * will be able to query the regulator performance here. */
 183         regulator_latency = 1 * 1000 * 1000;
 184 }
 185 #endif
 186
 187 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 188 {
 189         int ret;
 190         struct cpufreq_frequency_table *freq;
 191
 192         if (policy->cpu != 0)
 193                 return -EINVAL;
 194
 195         if (s3c64xx_freq_table == NULL) {
 196                 pr_err("cpufreq: No frequency information for this CPU\n");
 197                 return -ENODEV;
 198         }
 199
 200         armclk = clk_get(NULL, "armclk");
 201         if (IS_ERR(armclk)) {
 202                 pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
 203                        PTR_ERR(armclk));
 204                 return PTR_ERR(armclk);
 205         }
 206
 207 #ifdef CONFIG_REGULATOR
 208         vddarm = regulator_get(NULL, "vddarm");
 209         if (IS_ERR(vddarm)) {
 210                 ret = PTR_ERR(vddarm);
 211                 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
 212                 pr_err("cpufreq: Only frequency scaling available\n");
 213                 vddarm = NULL;
 214         } else {
 215                 s3c64xx_cpufreq_config_regulator();
 216         }
 217 #endif
 218
 219         freq = s3c64xx_freq_table;
 220         while (freq->frequency != CPUFREQ_TABLE_END) {
 221                 unsigned long r;
 222
 223                 /* Check for frequencies we can generate */
 224                 r = clk_round_rate(armclk, freq->frequency * 1000);
 225                 r /= 1000;
 226                 if (r != freq->frequency) {
 227                         pr_debug("cpufreq: %dkHz unsupported by clock\n",
 228                                  freq->frequency);
 229                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 230                 }
 231
 232                 /* If we have no regulator then assume startup
 233                  * frequency is the maximum we can support. */
 234                 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
 235                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 236
 237                 freq++;
 238         }
 239
 240         policy->cur = clk_get_rate(armclk) / 1000;
 241
 242         /* Datasheet says PLL stabalisation time (if we were to use
 243          * the PLLs, which we don't currently) is ~300us worst case,
 244          * but add some fudge.
 245          */
 246         policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
 247
 248         ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
 249         if (ret != 0) {
 250                 pr_err("cpufreq: Failed to configure frequency table: %d\n",
 251                        ret);
 252                 regulator_put(vddarm);
 253                 clk_put(armclk);
 254         }
 255
 256         return ret;
 257 }
 258
 259 static struct cpufreq_driver s3c64xx_cpufreq_driver = {
 260         .owner          = THIS_MODULE,
 261         .flags          = 0,
 262         .verify         = s3c64xx_cpufreq_verify_speed,
 263         .target         = s3c64xx_cpufreq_set_target,
 264         .get            = s3c64xx_cpufreq_get_speed,
 265         .init           = s3c64xx_cpufreq_driver_init,
 266         .name           = "s3c",
 267 };
 268
 269 static int __init s3c64xx_cpufreq_init(void)
 270 {
 271         return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
 272 }
 273 module_init(s3c64xx_cpufreq_init);