drivers/spi/spi-fsl-spi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale SPI controller driver.
   4  *
   5  * Maintainer: Kumar Gala
   6  *
   7  * Copyright (C) 2006 Polycom, Inc.
   8  * Copyright 2010 Freescale Semiconductor, Inc.
   9  *
  10  * CPM SPI and QE buffer descriptors mode support:
  11  * Copyright (c) 2009  MontaVista Software, Inc.
  12  * Author: Anton Vorontsov <[email protected]>
  13  *
  14  * GRLIB support:
  15  * Copyright (c) 2012 Aeroflex Gaisler AB.
  16  * Author: Andreas Larsson <[email protected]>
  17  */
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/fsl_devices.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35 #include <linux/types.h>
  36
  37 #ifdef CONFIG_FSL_SOC
  38 #include <sysdev/fsl_soc.h>
  39 #endif
  40
  41 /* Specific to the MPC8306/MPC8309 */
  42 #define IMMR_SPI_CS_OFFSET 0x14c
  43 #define SPI_BOOT_SEL_BIT   0x80000000
  44
  45 #include "spi-fsl-lib.h"
  46 #include "spi-fsl-cpm.h"
  47 #include "spi-fsl-spi.h"
  48
  49 #define TYPE_FSL        0
  50 #define TYPE_GRLIB      1
  51
  52 struct fsl_spi_match_data {
  53         int type;
  54 };
  55
  56 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  57         .type = TYPE_FSL,
  58 };
  59
  60 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  61         .type = TYPE_GRLIB,
  62 };
  63
  64 static const struct of_device_id of_fsl_spi_match[] = {
  65         {
  66                 .compatible = "fsl,spi",
  67                 .data = &of_fsl_spi_fsl_config,
  68         },
  69         {
  70                 .compatible = "aeroflexgaisler,spictrl",
  71                 .data = &of_fsl_spi_grlib_config,
  72         },
  73         {}
  74 };
  75 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  76
  77 static int fsl_spi_get_type(struct device *dev)
  78 {
  79         const struct of_device_id *match;
  80
  81         if (dev->of_node) {
  82                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  83                 if (match && match->data)
  84                         return ((struct fsl_spi_match_data *)match->data)->type;
  85         }
  86         return TYPE_FSL;
  87 }
  88
  89 static void fsl_spi_change_mode(struct spi_device *spi)
  90 {
  91         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  92         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  93         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  94         __be32 __iomem *mode = &reg_base->mode;
  95         unsigned long flags;
  96
  97         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  98                 return;
  99
 100         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 101         local_irq_save(flags);
 102
 103         /* Turn off SPI unit prior changing mode */
 104         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 105
 106         /* When in CPM mode, we need to reinit tx and rx. */
 107         if (mspi->flags & SPI_CPM_MODE) {
 108                 fsl_spi_cpm_reinit_txrx(mspi);
 109         }
 110         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 111         local_irq_restore(flags);
 112 }
 113
 114 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 115                                       int bits_per_word, int msb_first)
 116 {
 117         *rx_shift = 0;
 118         *tx_shift = 0;
 119         if (msb_first) {
 120                 if (bits_per_word <= 8) {
 121                         *rx_shift = 16;
 122                         *tx_shift = 24;
 123                 } else if (bits_per_word <= 16) {
 124                         *rx_shift = 16;
 125                         *tx_shift = 16;
 126                 }
 127         } else {
 128                 if (bits_per_word <= 8)
 129                         *rx_shift = 8;
 130         }
 131 }
 132
 133 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 134                                      int bits_per_word, int msb_first)
 135 {
 136         *rx_shift = 0;
 137         *tx_shift = 0;
 138         if (bits_per_word <= 16) {
 139                 if (msb_first) {
 140                         *rx_shift = 16; /* LSB in bit 16 */
 141                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 142                 } else {
 143                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 144                 }
 145         }
 146 }
 147
 148 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 149                                 struct spi_device *spi,
 150                                 struct mpc8xxx_spi *mpc8xxx_spi,
 151                                 int bits_per_word)
 152 {
 153         cs->rx_shift = 0;
 154         cs->tx_shift = 0;
 155         if (bits_per_word <= 8) {
 156                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 157                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 158         } else if (bits_per_word <= 16) {
 159                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 160                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 161         } else if (bits_per_word <= 32) {
 162                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 163                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 164         } else
 165                 return -EINVAL;
 166
 167         if (mpc8xxx_spi->set_shifts)
 168                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 169                                         bits_per_word,
 170                                         !(spi->mode & SPI_LSB_FIRST));
 171
 172         mpc8xxx_spi->rx_shift = cs->rx_shift;
 173         mpc8xxx_spi->tx_shift = cs->tx_shift;
 174         mpc8xxx_spi->get_rx = cs->get_rx;
 175         mpc8xxx_spi->get_tx = cs->get_tx;
 176
 177         return bits_per_word;
 178 }
 179
 180 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 181                                 struct spi_device *spi,
 182                                 int bits_per_word)
 183 {
 184         /* QE uses Little Endian for words > 8
 185          * so transform all words > 8 into 8 bits
 186          * Unfortnatly that doesn't work for LSB so
 187          * reject these for now */
 188         /* Note: 32 bits word, LSB works iff
 189          * tfcr/rfcr is set to CPMFCR_GBL */
 190         if (spi->mode & SPI_LSB_FIRST &&
 191             bits_per_word > 8)
 192                 return -EINVAL;
 193         if (bits_per_word > 8)
 194                 return 8; /* pretend its 8 bits */
 195         return bits_per_word;
 196 }
 197
 198 static int fsl_spi_setup_transfer(struct spi_device *spi,
 199                                         struct spi_transfer *t)
 200 {
 201         struct mpc8xxx_spi *mpc8xxx_spi;
 202         int bits_per_word = 0;
 203         u8 pm;
 204         u32 hz = 0;
 205         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 206
 207         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 208
 209         if (t) {
 210                 bits_per_word = t->bits_per_word;
 211                 hz = t->speed_hz;
 212         }
 213
 214         /* spi_transfer level calls that work per-word */
 215         if (!bits_per_word)
 216                 bits_per_word = spi->bits_per_word;
 217
 218         if (!hz)
 219                 hz = spi->max_speed_hz;
 220
 221         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 222                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 223                                                            mpc8xxx_spi,
 224                                                            bits_per_word);
 225         else if (mpc8xxx_spi->flags & SPI_QE)
 226                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 227                                                           bits_per_word);
 228
 229         if (bits_per_word < 0)
 230                 return bits_per_word;
 231
 232         if (bits_per_word == 32)
 233                 bits_per_word = 0;
 234         else
 235                 bits_per_word = bits_per_word - 1;
 236
 237         /* mask out bits we are going to set */
 238         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 239                                   | SPMODE_PM(0xF));
 240
 241         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 242
 243         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 244                 cs->hw_mode |= SPMODE_DIV16;
 245                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 246                 WARN_ONCE(pm > 16,
 247                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
 248                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
 249                 if (pm > 16)
 250                         pm = 16;
 251         } else {
 252                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 253         }
 254         if (pm)
 255                 pm--;
 256
 257         cs->hw_mode |= SPMODE_PM(pm);
 258
 259         fsl_spi_change_mode(spi);
 260         return 0;
 261 }
 262
 263 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 264                                 struct spi_transfer *t, unsigned int len)
 265 {
 266         u32 word;
 267         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 268
 269         mspi->count = len;
 270
 271         /* enable rx ints */
 272         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 273
 274         /* transmit word */
 275         word = mspi->get_tx(mspi);
 276         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 277
 278         return 0;
 279 }
 280
 281 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 282                             bool is_dma_mapped)
 283 {
 284         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 285         struct fsl_spi_reg __iomem *reg_base;
 286         unsigned int len = t->len;
 287         u8 bits_per_word;
 288         int ret;
 289
 290         reg_base = mpc8xxx_spi->reg_base;
 291         bits_per_word = spi->bits_per_word;
 292         if (t->bits_per_word)
 293                 bits_per_word = t->bits_per_word;
 294
 295         if (bits_per_word > 8) {
 296                 /* invalid length? */
 297                 if (len & 1)
 298                         return -EINVAL;
 299                 len /= 2;
 300         }
 301         if (bits_per_word > 16) {
 302                 /* invalid length? */
 303                 if (len & 1)
 304                         return -EINVAL;
 305                 len /= 2;
 306         }
 307
 308         mpc8xxx_spi->tx = t->tx_buf;
 309         mpc8xxx_spi->rx = t->rx_buf;
 310
 311         reinit_completion(&mpc8xxx_spi->done);
 312
 313         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 314                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 315         else
 316                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 317         if (ret)
 318                 return ret;
 319
 320         wait_for_completion(&mpc8xxx_spi->done);
 321
 322         /* disable rx ints */
 323         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 324
 325         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 326                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 327
 328         return mpc8xxx_spi->count;
 329 }
 330
 331 static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 332                                    struct spi_message *m)
 333 {
 334         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
 335         struct spi_transfer *t;
 336
 337         /*
 338          * In CPU mode, optimize large byte transfers to use larger
 339          * bits_per_word values to reduce number of interrupts taken.
 340          */
 341         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 342                 list_for_each_entry(t, &m->transfers, transfer_list) {
 343                         if (t->len < 256 || t->bits_per_word != 8)
 344                                 continue;
 345                         if ((t->len & 3) == 0)
 346                                 t->bits_per_word = 32;
 347                         else if ((t->len & 1) == 0)
 348                                 t->bits_per_word = 16;
 349                 }
 350         }
 351         return 0;
 352 }
 353
 354 static int fsl_spi_transfer_one(struct spi_controller *controller,
 355                                 struct spi_device *spi,
 356                                 struct spi_transfer *t)
 357 {
 358         int status;
 359
 360         status = fsl_spi_setup_transfer(spi, t);
 361         if (status < 0)
 362                 return status;
 363         if (t->len)
 364                 status = fsl_spi_bufs(spi, t, !!t->tx_dma || !!t->rx_dma);
 365         if (status > 0)
 366                 return -EMSGSIZE;
 367
 368         return status;
 369 }
 370
 371 static int fsl_spi_unprepare_message(struct spi_controller *controller,
 372                                      struct spi_message *msg)
 373 {
 374         return fsl_spi_setup_transfer(msg->spi, NULL);
 375 }
 376
 377 static int fsl_spi_setup(struct spi_device *spi)
 378 {
 379         struct mpc8xxx_spi *mpc8xxx_spi;
 380         struct fsl_spi_reg __iomem *reg_base;
 381         bool initial_setup = false;
 382         int retval;
 383         u32 hw_mode;
 384         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 385
 386         if (!spi->max_speed_hz)
 387                 return -EINVAL;
 388
 389         if (!cs) {
 390                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 391                 if (!cs)
 392                         return -ENOMEM;
 393                 spi_set_ctldata(spi, cs);
 394                 initial_setup = true;
 395         }
 396         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 397
 398         reg_base = mpc8xxx_spi->reg_base;
 399
 400         hw_mode = cs->hw_mode; /* Save original settings */
 401         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 402         /* mask out bits we are going to set */
 403         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 404                          | SPMODE_REV | SPMODE_LOOP);
 405
 406         if (spi->mode & SPI_CPHA)
 407                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 408         if (spi->mode & SPI_CPOL)
 409                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 410         if (!(spi->mode & SPI_LSB_FIRST))
 411                 cs->hw_mode |= SPMODE_REV;
 412         if (spi->mode & SPI_LOOP)
 413                 cs->hw_mode |= SPMODE_LOOP;
 414
 415         retval = fsl_spi_setup_transfer(spi, NULL);
 416         if (retval < 0) {
 417                 cs->hw_mode = hw_mode; /* Restore settings */
 418                 if (initial_setup)
 419                         kfree(cs);
 420                 return retval;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static void fsl_spi_cleanup(struct spi_device *spi)
 427 {
 428         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 429
 430         kfree(cs);
 431         spi_set_ctldata(spi, NULL);
 432 }
 433
 434 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 435 {
 436         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 437
 438         /* We need handle RX first */
 439         if (events & SPIE_NE) {
 440                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 441
 442                 if (mspi->rx)
 443                         mspi->get_rx(rx_data, mspi);
 444         }
 445
 446         if ((events & SPIE_NF) == 0)
 447                 /* spin until TX is done */
 448                 while (((events =
 449                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 450                                                 SPIE_NF) == 0)
 451                         cpu_relax();
 452
 453         /* Clear the events */
 454         mpc8xxx_spi_write_reg(&reg_base->event, events);
 455
 456         mspi->count -= 1;
 457         if (mspi->count) {
 458                 u32 word = mspi->get_tx(mspi);
 459
 460                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 461         } else {
 462                 complete(&mspi->done);
 463         }
 464 }
 465
 466 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 467 {
 468         struct mpc8xxx_spi *mspi = context_data;
 469         irqreturn_t ret = IRQ_NONE;
 470         u32 events;
 471         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 472
 473         /* Get interrupt events(tx/rx) */
 474         events = mpc8xxx_spi_read_reg(&reg_base->event);
 475         if (events)
 476                 ret = IRQ_HANDLED;
 477
 478         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 479
 480         if (mspi->flags & SPI_CPM_MODE)
 481                 fsl_spi_cpm_irq(mspi, events);
 482         else
 483                 fsl_spi_cpu_irq(mspi, events);
 484
 485         return ret;
 486 }
 487
 488 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 489 {
 490         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 491         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 492         u32 slvsel;
 493         u16 cs = spi->chip_select;
 494
 495         if (cs < mpc8xxx_spi->native_chipselects) {
 496                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 497                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 498                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 499         }
 500 }
 501
 502 static void fsl_spi_grlib_probe(struct device *dev)
 503 {
 504         struct spi_master *master = dev_get_drvdata(dev);
 505         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 506         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 507         int mbits;
 508         u32 capabilities;
 509
 510         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 511
 512         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 513         mbits = SPCAP_MAXWLEN(capabilities);
 514         if (mbits)
 515                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 516
 517         mpc8xxx_spi->native_chipselects = 0;
 518         if (SPCAP_SSEN(capabilities)) {
 519                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 520                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 521         }
 522         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 523         master->set_cs = fsl_spi_grlib_cs_control;
 524 }
 525
 526 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 527 {
 528         struct device *dev = spi->dev.parent->parent;
 529         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 530         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 531
 532         if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
 533                 return;
 534         iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
 535 }
 536
 537 static struct spi_master *fsl_spi_probe(struct device *dev,
 538                 struct resource *mem, unsigned int irq)
 539 {
 540         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 541         struct spi_master *master;
 542         struct mpc8xxx_spi *mpc8xxx_spi;
 543         struct fsl_spi_reg __iomem *reg_base;
 544         u32 regval;
 545         int ret = 0;
 546
 547         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 548         if (master == NULL) {
 549                 ret = -ENOMEM;
 550                 goto err;
 551         }
 552
 553         dev_set_drvdata(dev, master);
 554
 555         mpc8xxx_spi_probe(dev, mem, irq);
 556
 557         master->setup = fsl_spi_setup;
 558         master->cleanup = fsl_spi_cleanup;
 559         master->prepare_message = fsl_spi_prepare_message;
 560         master->transfer_one = fsl_spi_transfer_one;
 561         master->unprepare_message = fsl_spi_unprepare_message;
 562         master->use_gpio_descriptors = true;
 563         master->set_cs = fsl_spi_cs_control;
 564
 565         mpc8xxx_spi = spi_master_get_devdata(master);
 566         mpc8xxx_spi->max_bits_per_word = 32;
 567         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 568
 569         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 570         if (ret)
 571                 goto err_cpm_init;
 572
 573         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 574         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 575                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 576                 goto err_probe;
 577         }
 578
 579         if (mpc8xxx_spi->type == TYPE_GRLIB)
 580                 fsl_spi_grlib_probe(dev);
 581
 582         master->bits_per_word_mask =
 583                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
 584                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 585
 586         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 587                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 588
 589         if (mpc8xxx_spi->set_shifts)
 590                 /* 8 bits per word and MSB first */
 591                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 592                                         &mpc8xxx_spi->tx_shift, 8, 1);
 593
 594         /* Register for SPI Interrupt */
 595         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 596                                0, "fsl_spi", mpc8xxx_spi);
 597
 598         if (ret != 0)
 599                 goto err_probe;
 600
 601         reg_base = mpc8xxx_spi->reg_base;
 602
 603         /* SPI controller initializations */
 604         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 605         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 606         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 607         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 608
 609         /* Enable SPI interface */
 610         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 611         if (mpc8xxx_spi->max_bits_per_word < 8) {
 612                 regval &= ~SPMODE_LEN(0xF);
 613                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 614         }
 615         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 616                 regval |= SPMODE_OP;
 617
 618         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 619
 620         ret = devm_spi_register_master(dev, master);
 621         if (ret < 0)
 622                 goto err_probe;
 623
 624         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 625                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 626
 627         return master;
 628
 629 err_probe:
 630         fsl_spi_cpm_free(mpc8xxx_spi);
 631 err_cpm_init:
 632         spi_master_put(master);
 633 err:
 634         return ERR_PTR(ret);
 635 }
 636
 637 static int of_fsl_spi_probe(struct platform_device *ofdev)
 638 {
 639         struct device *dev = &ofdev->dev;
 640         struct device_node *np = ofdev->dev.of_node;
 641         struct spi_master *master;
 642         struct resource mem;
 643         int irq, type;
 644         int ret;
 645         bool spisel_boot = false;
 646 #if IS_ENABLED(CONFIG_FSL_SOC)
 647         struct mpc8xxx_spi_probe_info *pinfo = NULL;
 648 #endif
 649
 650
 651         ret = of_mpc8xxx_spi_probe(ofdev);
 652         if (ret)
 653                 return ret;
 654
 655         type = fsl_spi_get_type(&ofdev->dev);
 656         if (type == TYPE_FSL) {
 657                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 658 #if IS_ENABLED(CONFIG_FSL_SOC)
 659                 pinfo = to_of_pinfo(pdata);
 660
 661                 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
 662                 if (spisel_boot) {
 663                         pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
 664                         if (!pinfo->immr_spi_cs)
 665                                 return -ENOMEM;
 666                 }
 667 #endif
 668                 /*
 669                  * Handle the case where we have one hardwired (always selected)
 670                  * device on the first "chipselect". Else we let the core code
 671                  * handle any GPIOs or native chip selects and assign the
 672                  * appropriate callback for dealing with the CS lines. This isn't
 673                  * supported on the GRLIB variant.
 674                  */
 675                 ret = gpiod_count(dev, "cs");
 676                 if (ret < 0)
 677                         ret = 0;
 678                 if (ret == 0 && !spisel_boot)
 679                         pdata->max_chipselect = 1;
 680                 else
 681                         pdata->max_chipselect = ret + spisel_boot;
 682         }
 683
 684         ret = of_address_to_resource(np, 0, &mem);
 685         if (ret)
 686                 goto unmap_out;
 687
 688         irq = platform_get_irq(ofdev, 0);
 689         if (irq < 0) {
 690                 ret = irq;
 691                 goto unmap_out;
 692         }
 693
 694         master = fsl_spi_probe(dev, &mem, irq);
 695
 696         return PTR_ERR_OR_ZERO(master);
 697
 698 unmap_out:
 699 #if IS_ENABLED(CONFIG_FSL_SOC)
 700         if (spisel_boot)
 701                 iounmap(pinfo->immr_spi_cs);
 702 #endif
 703         return ret;
 704 }
 705
 706 static int of_fsl_spi_remove(struct platform_device *ofdev)
 707 {
 708         struct spi_master *master = platform_get_drvdata(ofdev);
 709         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 710
 711         fsl_spi_cpm_free(mpc8xxx_spi);
 712         return 0;
 713 }
 714
 715 static struct platform_driver of_fsl_spi_driver = {
 716         .driver = {
 717                 .name = "fsl_spi",
 718                 .of_match_table = of_fsl_spi_match,
 719         },
 720         .probe          = of_fsl_spi_probe,
 721         .remove         = of_fsl_spi_remove,
 722 };
 723
 724 #ifdef CONFIG_MPC832x_RDB
 725 /*
 726  * XXX XXX XXX
 727  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 728  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 729  * tree can work with OpenFirmware driver. But for now we support old trees
 730  * as well.
 731  */
 732 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 733 {
 734         struct resource *mem;
 735         int irq;
 736         struct spi_master *master;
 737
 738         if (!dev_get_platdata(&pdev->dev))
 739                 return -EINVAL;
 740
 741         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 742         if (!mem)
 743                 return -EINVAL;
 744
 745         irq = platform_get_irq(pdev, 0);
 746         if (irq <= 0)
 747                 return -EINVAL;
 748
 749         master = fsl_spi_probe(&pdev->dev, mem, irq);
 750         return PTR_ERR_OR_ZERO(master);
 751 }
 752
 753 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 754 {
 755         struct spi_master *master = platform_get_drvdata(pdev);
 756         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 757
 758         fsl_spi_cpm_free(mpc8xxx_spi);
 759
 760         return 0;
 761 }
 762
 763 MODULE_ALIAS("platform:mpc8xxx_spi");
 764 static struct platform_driver mpc8xxx_spi_driver = {
 765         .probe = plat_mpc8xxx_spi_probe,
 766         .remove = plat_mpc8xxx_spi_remove,
 767         .driver = {
 768                 .name = "mpc8xxx_spi",
 769         },
 770 };
 771
 772 static bool legacy_driver_failed;
 773
 774 static void __init legacy_driver_register(void)
 775 {
 776         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 777 }
 778
 779 static void __exit legacy_driver_unregister(void)
 780 {
 781         if (legacy_driver_failed)
 782                 return;
 783         platform_driver_unregister(&mpc8xxx_spi_driver);
 784 }
 785 #else
 786 static void __init legacy_driver_register(void) {}
 787 static void __exit legacy_driver_unregister(void) {}
 788 #endif /* CONFIG_MPC832x_RDB */
 789
 790 static int __init fsl_spi_init(void)
 791 {
 792         legacy_driver_register();
 793         return platform_driver_register(&of_fsl_spi_driver);
 794 }
 795 module_init(fsl_spi_init);
 796
 797 static void __exit fsl_spi_exit(void)
 798 {
 799         platform_driver_unregister(&of_fsl_spi_driver);
 800         legacy_driver_unregister();
 801 }
 802 module_exit(fsl_spi_exit);
 803
 804 MODULE_AUTHOR("Kumar Gala");
 805 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 806 MODULE_LICENSE("GPL");