drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_8_0_d.h"
  36 #include "dce/dce_8_0_sh_mask.h"
  37
  38 #include "gca/gfx_7_2_enum.h"
  39
  40 #include "gmc/gmc_7_1_d.h"
  41 #include "gmc/gmc_7_1_sh_mask.h"
  42
  43 #include "oss/oss_2_0_d.h"
  44 #include "oss/oss_2_0_sh_mask.h"
  45
  46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
  47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  48
  49 static const u32 crtc_offsets[6] =
  50 {
  51         CRTC0_REGISTER_OFFSET,
  52         CRTC1_REGISTER_OFFSET,
  53         CRTC2_REGISTER_OFFSET,
  54         CRTC3_REGISTER_OFFSET,
  55         CRTC4_REGISTER_OFFSET,
  56         CRTC5_REGISTER_OFFSET
  57 };
  58
  59 static const u32 hpd_offsets[] =
  60 {
  61         HPD0_REGISTER_OFFSET,
  62         HPD1_REGISTER_OFFSET,
  63         HPD2_REGISTER_OFFSET,
  64         HPD3_REGISTER_OFFSET,
  65         HPD4_REGISTER_OFFSET,
  66         HPD5_REGISTER_OFFSET
  67 };
  68
  69 static const uint32_t dig_offsets[] = {
  70         CRTC0_REGISTER_OFFSET,
  71         CRTC1_REGISTER_OFFSET,
  72         CRTC2_REGISTER_OFFSET,
  73         CRTC3_REGISTER_OFFSET,
  74         CRTC4_REGISTER_OFFSET,
  75         CRTC5_REGISTER_OFFSET,
  76         (0x13830 - 0x7030) >> 2,
  77 };
  78
  79 static const struct {
  80         uint32_t        reg;
  81         uint32_t        vblank;
  82         uint32_t        vline;
  83         uint32_t        hpd;
  84
  85 } interrupt_status_offsets[6] = { {
  86         .reg = mmDISP_INTERRUPT_STATUS,
  87         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 115 } };
 116
 117 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
 118                                      u32 block_offset, u32 reg)
 119 {
 120         unsigned long flags;
 121         u32 r;
 122
 123         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 124         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 125         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 126         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 127
 128         return r;
 129 }
 130
 131 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
 132                                       u32 block_offset, u32 reg, u32 v)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 137         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 138         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 139         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 140 }
 141
 142 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 143 {
 144         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 145                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 146                 return true;
 147         else
 148                 return false;
 149 }
 150
 151 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 152 {
 153         u32 pos1, pos2;
 154
 155         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 156         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 157
 158         if (pos1 != pos2)
 159                 return true;
 160         else
 161                 return false;
 162 }
 163
 164 /**
 165  * dce_v8_0_vblank_wait - vblank wait asic callback.
 166  *
 167  * @adev: amdgpu_device pointer
 168  * @crtc: crtc to wait for vblank on
 169  *
 170  * Wait for vblank on the requested crtc (evergreen+).
 171  */
 172 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 173 {
 174         unsigned i = 100;
 175
 176         if (crtc >= adev->mode_info.num_crtc)
 177                 return;
 178
 179         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 180                 return;
 181
 182         /* depending on when we hit vblank, we may be close to active; if so,
 183          * wait for another frame.
 184          */
 185         while (dce_v8_0_is_in_vblank(adev, crtc)) {
 186                 if (i++ == 100) {
 187                         i = 0;
 188                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 189                                 break;
 190                 }
 191         }
 192
 193         while (!dce_v8_0_is_in_vblank(adev, crtc)) {
 194                 if (i++ == 100) {
 195                         i = 0;
 196                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 197                                 break;
 198                 }
 199         }
 200 }
 201
 202 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 203 {
 204         if (crtc >= adev->mode_info.num_crtc)
 205                 return 0;
 206         else
 207                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 208 }
 209
 210 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 211 {
 212         unsigned i;
 213
 214         /* Enable pflip interrupts */
 215         for (i = 0; i < adev->mode_info.num_crtc; i++)
 216                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 217 }
 218
 219 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 220 {
 221         unsigned i;
 222
 223         /* Disable pflip interrupts */
 224         for (i = 0; i < adev->mode_info.num_crtc; i++)
 225                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 226 }
 227
 228 /**
 229  * dce_v8_0_page_flip - pageflip callback.
 230  *
 231  * @adev: amdgpu_device pointer
 232  * @crtc_id: crtc to cleanup pageflip on
 233  * @crtc_base: new address of the crtc (GPU MC address)
 234  *
 235  * Triggers the actual pageflip by updating the primary
 236  * surface base address.
 237  */
 238 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
 239                                int crtc_id, u64 crtc_base, bool async)
 240 {
 241         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 242
 243         /* flip at hsync for async, default is vsync */
 244         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 245                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 246         /* update the primary scanout addresses */
 247         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 248                upper_32_bits(crtc_base));
 249         /* writing to the low address triggers the update */
 250         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 251                lower_32_bits(crtc_base));
 252         /* post the write */
 253         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 254 }
 255
 256 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 257                                         u32 *vbl, u32 *position)
 258 {
 259         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 260                 return -EINVAL;
 261
 262         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 263         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 264
 265         return 0;
 266 }
 267
 268 /**
 269  * dce_v8_0_hpd_sense - hpd sense callback.
 270  *
 271  * @adev: amdgpu_device pointer
 272  * @hpd: hpd (hotplug detect) pin
 273  *
 274  * Checks if a digital monitor is connected (evergreen+).
 275  * Returns true if connected, false if not connected.
 276  */
 277 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
 278                                enum amdgpu_hpd_id hpd)
 279 {
 280         bool connected = false;
 281
 282         if (hpd >= adev->mode_info.num_hpd)
 283                 return connected;
 284
 285         if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
 286             DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 287                 connected = true;
 288
 289         return connected;
 290 }
 291
 292 /**
 293  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
 294  *
 295  * @adev: amdgpu_device pointer
 296  * @hpd: hpd (hotplug detect) pin
 297  *
 298  * Set the polarity of the hpd pin (evergreen+).
 299  */
 300 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
 301                                       enum amdgpu_hpd_id hpd)
 302 {
 303         u32 tmp;
 304         bool connected = dce_v8_0_hpd_sense(adev, hpd);
 305
 306         if (hpd >= adev->mode_info.num_hpd)
 307                 return;
 308
 309         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
 310         if (connected)
 311                 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 312         else
 313                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 314         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 315 }
 316
 317 /**
 318  * dce_v8_0_hpd_init - hpd setup callback.
 319  *
 320  * @adev: amdgpu_device pointer
 321  *
 322  * Setup the hpd pins used by the card (evergreen+).
 323  * Enable the pin, set the polarity, and enable the hpd interrupts.
 324  */
 325 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 326 {
 327         struct drm_device *dev = adev->ddev;
 328         struct drm_connector *connector;
 329         u32 tmp;
 330
 331         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 332                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 333
 334                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 335                         continue;
 336
 337                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 338                 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 339                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 340
 341                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 342                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 343                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 344                          * aux dp channel on imac and help (but not completely fix)
 345                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 346                          * also avoid interrupt storms during dpms.
 347                          */
 348                         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 349                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 350                         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 351                         continue;
 352                 }
 353
 354                 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 355                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 356         }
 357 }
 358
 359 /**
 360  * dce_v8_0_hpd_fini - hpd tear down callback.
 361  *
 362  * @adev: amdgpu_device pointer
 363  *
 364  * Tear down the hpd pins used by the card (evergreen+).
 365  * Disable the hpd interrupts.
 366  */
 367 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 368 {
 369         struct drm_device *dev = adev->ddev;
 370         struct drm_connector *connector;
 371         u32 tmp;
 372
 373         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 374                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 375
 376                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 377                         continue;
 378
 379                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 380                 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 381                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 382
 383                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 384         }
 385 }
 386
 387 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 388 {
 389         return mmDC_GPIO_HPD_A;
 390 }
 391
 392 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
 393 {
 394         u32 crtc_hung = 0;
 395         u32 crtc_status[6];
 396         u32 i, j, tmp;
 397
 398         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 399                 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
 400                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 401                         crtc_hung |= (1 << i);
 402                 }
 403         }
 404
 405         for (j = 0; j < 10; j++) {
 406                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 407                         if (crtc_hung & (1 << i)) {
 408                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 409                                 if (tmp != crtc_status[i])
 410                                         crtc_hung &= ~(1 << i);
 411                         }
 412                 }
 413                 if (crtc_hung == 0)
 414                         return false;
 415                 udelay(100);
 416         }
 417
 418         return true;
 419 }
 420
 421 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
 422                                     struct amdgpu_mode_mc_save *save)
 423 {
 424         u32 crtc_enabled, tmp;
 425         int i;
 426
 427         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 428         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 429
 430         /* disable VGA render */
 431         tmp = RREG32(mmVGA_RENDER_CONTROL);
 432         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 433         WREG32(mmVGA_RENDER_CONTROL, tmp);
 434
 435         /* blank the display controllers */
 436         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 437                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 438                                              CRTC_CONTROL, CRTC_MASTER_EN);
 439                 if (crtc_enabled) {
 440 #if 1
 441                         save->crtc_enabled[i] = true;
 442                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 443                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 444                                 /*it is correct only for RGB ; black is 0*/
 445                                 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
 446                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 447                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 448                         }
 449                         mdelay(20);
 450 #else
 451                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 452                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 453                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 454                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 455                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 456                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 457                         save->crtc_enabled[i] = false;
 458                         /* ***** */
 459 #endif
 460                 } else {
 461                         save->crtc_enabled[i] = false;
 462                 }
 463         }
 464 }
 465
 466 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
 467                                       struct amdgpu_mode_mc_save *save)
 468 {
 469         u32 tmp;
 470         int i;
 471
 472         /* update crtc base addresses */
 473         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 474                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 475                        upper_32_bits(adev->mc.vram_start));
 476                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 477                        (u32)adev->mc.vram_start);
 478
 479                 if (save->crtc_enabled[i]) {
 480                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 481                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 482                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 483                 }
 484                 mdelay(20);
 485         }
 486
 487         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 488         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 489
 490         /* Unlock vga access */
 491         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 492         mdelay(1);
 493         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 494 }
 495
 496 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
 497                                           bool render)
 498 {
 499         u32 tmp;
 500
 501         /* Lockout access through VGA aperture*/
 502         tmp = RREG32(mmVGA_HDP_CONTROL);
 503         if (render)
 504                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 505         else
 506                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 507         WREG32(mmVGA_HDP_CONTROL, tmp);
 508
 509         /* disable VGA render */
 510         tmp = RREG32(mmVGA_RENDER_CONTROL);
 511         if (render)
 512                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 513         else
 514                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 515         WREG32(mmVGA_RENDER_CONTROL, tmp);
 516 }
 517
 518 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
 519 {
 520         int num_crtc = 0;
 521
 522         switch (adev->asic_type) {
 523         case CHIP_BONAIRE:
 524         case CHIP_HAWAII:
 525                 num_crtc = 6;
 526                 break;
 527         case CHIP_KAVERI:
 528                 num_crtc = 4;
 529                 break;
 530         case CHIP_KABINI:
 531         case CHIP_MULLINS:
 532                 num_crtc = 2;
 533                 break;
 534         default:
 535                 num_crtc = 0;
 536         }
 537         return num_crtc;
 538 }
 539
 540 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
 541 {
 542         /*Disable VGA render and enabled crtc, if has DCE engine*/
 543         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 544                 u32 tmp;
 545                 int crtc_enabled, i;
 546
 547                 dce_v8_0_set_vga_render_state(adev, false);
 548
 549                 /*Disable crtc*/
 550                 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
 551                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 552                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 553                         if (crtc_enabled) {
 554                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 555                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 556                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 557                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 558                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 559                         }
 560                 }
 561         }
 562 }
 563
 564 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
 565 {
 566         struct drm_device *dev = encoder->dev;
 567         struct amdgpu_device *adev = dev->dev_private;
 568         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 569         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 570         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 571         int bpc = 0;
 572         u32 tmp = 0;
 573         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 574
 575         if (connector) {
 576                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 577                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 578                 dither = amdgpu_connector->dither;
 579         }
 580
 581         /* LVDS/eDP FMT is set up by atom */
 582         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 583                 return;
 584
 585         /* not needed for analog */
 586         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 587             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 588                 return;
 589
 590         if (bpc == 0)
 591                 return;
 592
 593         switch (bpc) {
 594         case 6:
 595                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 596                         /* XXX sort out optimal dither settings */
 597                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 598                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 599                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 600                                 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 601                 else
 602                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 603                         (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 604                 break;
 605         case 8:
 606                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 607                         /* XXX sort out optimal dither settings */
 608                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 609                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 610                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 611                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 612                                 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 613                 else
 614                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 615                         (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 616                 break;
 617         case 10:
 618                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 619                         /* XXX sort out optimal dither settings */
 620                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 621                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 622                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 623                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 624                                 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 625                 else
 626                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 627                         (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 628                 break;
 629         default:
 630                 /* not needed */
 631                 break;
 632         }
 633
 634         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 635 }
 636
 637
 638 /* display watermark setup */
 639 /**
 640  * dce_v8_0_line_buffer_adjust - Set up the line buffer
 641  *
 642  * @adev: amdgpu_device pointer
 643  * @amdgpu_crtc: the selected display controller
 644  * @mode: the current display mode on the selected display
 645  * controller
 646  *
 647  * Setup up the line buffer allocation for
 648  * the selected display controller (CIK).
 649  * Returns the line buffer size in pixels.
 650  */
 651 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
 652                                        struct amdgpu_crtc *amdgpu_crtc,
 653                                        struct drm_display_mode *mode)
 654 {
 655         u32 tmp, buffer_alloc, i;
 656         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 657         /*
 658          * Line Buffer Setup
 659          * There are 6 line buffers, one for each display controllers.
 660          * There are 3 partitions per LB. Select the number of partitions
 661          * to enable based on the display width.  For display widths larger
 662          * than 4096, you need use to use 2 display controllers and combine
 663          * them using the stereo blender.
 664          */
 665         if (amdgpu_crtc->base.enabled && mode) {
 666                 if (mode->crtc_hdisplay < 1920) {
 667                         tmp = 1;
 668                         buffer_alloc = 2;
 669                 } else if (mode->crtc_hdisplay < 2560) {
 670                         tmp = 2;
 671                         buffer_alloc = 2;
 672                 } else if (mode->crtc_hdisplay < 4096) {
 673                         tmp = 0;
 674                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 675                 } else {
 676                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 677                         tmp = 0;
 678                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 679                 }
 680         } else {
 681                 tmp = 1;
 682                 buffer_alloc = 0;
 683         }
 684
 685         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
 686               (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
 687               (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
 688
 689         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 690                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
 691         for (i = 0; i < adev->usec_timeout; i++) {
 692                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 693                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
 694                         break;
 695                 udelay(1);
 696         }
 697
 698         if (amdgpu_crtc->base.enabled && mode) {
 699                 switch (tmp) {
 700                 case 0:
 701                 default:
 702                         return 4096 * 2;
 703                 case 1:
 704                         return 1920 * 2;
 705                 case 2:
 706                         return 2560 * 2;
 707                 }
 708         }
 709
 710         /* controller not enabled, so no lb used */
 711         return 0;
 712 }
 713
 714 /**
 715  * cik_get_number_of_dram_channels - get the number of dram channels
 716  *
 717  * @adev: amdgpu_device pointer
 718  *
 719  * Look up the number of video ram channels (CIK).
 720  * Used for display watermark bandwidth calculations
 721  * Returns the number of dram channels
 722  */
 723 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 724 {
 725         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 726
 727         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 728         case 0:
 729         default:
 730                 return 1;
 731         case 1:
 732                 return 2;
 733         case 2:
 734                 return 4;
 735         case 3:
 736                 return 8;
 737         case 4:
 738                 return 3;
 739         case 5:
 740                 return 6;
 741         case 6:
 742                 return 10;
 743         case 7:
 744                 return 12;
 745         case 8:
 746                 return 16;
 747         }
 748 }
 749
 750 struct dce8_wm_params {
 751         u32 dram_channels; /* number of dram channels */
 752         u32 yclk;          /* bandwidth per dram data pin in kHz */
 753         u32 sclk;          /* engine clock in kHz */
 754         u32 disp_clk;      /* display clock in kHz */
 755         u32 src_width;     /* viewport width */
 756         u32 active_time;   /* active display time in ns */
 757         u32 blank_time;    /* blank time in ns */
 758         bool interlaced;    /* mode is interlaced */
 759         fixed20_12 vsc;    /* vertical scale ratio */
 760         u32 num_heads;     /* number of active crtcs */
 761         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 762         u32 lb_size;       /* line buffer allocated to pipe */
 763         u32 vtaps;         /* vertical scaler taps */
 764 };
 765
 766 /**
 767  * dce_v8_0_dram_bandwidth - get the dram bandwidth
 768  *
 769  * @wm: watermark calculation data
 770  *
 771  * Calculate the raw dram bandwidth (CIK).
 772  * Used for display watermark bandwidth calculations
 773  * Returns the dram bandwidth in MBytes/s
 774  */
 775 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
 776 {
 777         /* Calculate raw DRAM Bandwidth */
 778         fixed20_12 dram_efficiency; /* 0.7 */
 779         fixed20_12 yclk, dram_channels, bandwidth;
 780         fixed20_12 a;
 781
 782         a.full = dfixed_const(1000);
 783         yclk.full = dfixed_const(wm->yclk);
 784         yclk.full = dfixed_div(yclk, a);
 785         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 786         a.full = dfixed_const(10);
 787         dram_efficiency.full = dfixed_const(7);
 788         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 789         bandwidth.full = dfixed_mul(dram_channels, yclk);
 790         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 791
 792         return dfixed_trunc(bandwidth);
 793 }
 794
 795 /**
 796  * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
 797  *
 798  * @wm: watermark calculation data
 799  *
 800  * Calculate the dram bandwidth used for display (CIK).
 801  * Used for display watermark bandwidth calculations
 802  * Returns the dram bandwidth for display in MBytes/s
 803  */
 804 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 805 {
 806         /* Calculate DRAM Bandwidth and the part allocated to display. */
 807         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 808         fixed20_12 yclk, dram_channels, bandwidth;
 809         fixed20_12 a;
 810
 811         a.full = dfixed_const(1000);
 812         yclk.full = dfixed_const(wm->yclk);
 813         yclk.full = dfixed_div(yclk, a);
 814         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 815         a.full = dfixed_const(10);
 816         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 817         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 818         bandwidth.full = dfixed_mul(dram_channels, yclk);
 819         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 820
 821         return dfixed_trunc(bandwidth);
 822 }
 823
 824 /**
 825  * dce_v8_0_data_return_bandwidth - get the data return bandwidth
 826  *
 827  * @wm: watermark calculation data
 828  *
 829  * Calculate the data return bandwidth used for display (CIK).
 830  * Used for display watermark bandwidth calculations
 831  * Returns the data return bandwidth in MBytes/s
 832  */
 833 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
 834 {
 835         /* Calculate the display Data return Bandwidth */
 836         fixed20_12 return_efficiency; /* 0.8 */
 837         fixed20_12 sclk, bandwidth;
 838         fixed20_12 a;
 839
 840         a.full = dfixed_const(1000);
 841         sclk.full = dfixed_const(wm->sclk);
 842         sclk.full = dfixed_div(sclk, a);
 843         a.full = dfixed_const(10);
 844         return_efficiency.full = dfixed_const(8);
 845         return_efficiency.full = dfixed_div(return_efficiency, a);
 846         a.full = dfixed_const(32);
 847         bandwidth.full = dfixed_mul(a, sclk);
 848         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 849
 850         return dfixed_trunc(bandwidth);
 851 }
 852
 853 /**
 854  * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
 855  *
 856  * @wm: watermark calculation data
 857  *
 858  * Calculate the dmif bandwidth used for display (CIK).
 859  * Used for display watermark bandwidth calculations
 860  * Returns the dmif bandwidth in MBytes/s
 861  */
 862 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
 863 {
 864         /* Calculate the DMIF Request Bandwidth */
 865         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 866         fixed20_12 disp_clk, bandwidth;
 867         fixed20_12 a, b;
 868
 869         a.full = dfixed_const(1000);
 870         disp_clk.full = dfixed_const(wm->disp_clk);
 871         disp_clk.full = dfixed_div(disp_clk, a);
 872         a.full = dfixed_const(32);
 873         b.full = dfixed_mul(a, disp_clk);
 874
 875         a.full = dfixed_const(10);
 876         disp_clk_request_efficiency.full = dfixed_const(8);
 877         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 878
 879         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 880
 881         return dfixed_trunc(bandwidth);
 882 }
 883
 884 /**
 885  * dce_v8_0_available_bandwidth - get the min available bandwidth
 886  *
 887  * @wm: watermark calculation data
 888  *
 889  * Calculate the min available bandwidth used for display (CIK).
 890  * Used for display watermark bandwidth calculations
 891  * Returns the min available bandwidth in MBytes/s
 892  */
 893 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
 894 {
 895         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 896         u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
 897         u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
 898         u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
 899
 900         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 901 }
 902
 903 /**
 904  * dce_v8_0_average_bandwidth - get the average available bandwidth
 905  *
 906  * @wm: watermark calculation data
 907  *
 908  * Calculate the average available bandwidth used for display (CIK).
 909  * Used for display watermark bandwidth calculations
 910  * Returns the average available bandwidth in MBytes/s
 911  */
 912 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
 913 {
 914         /* Calculate the display mode Average Bandwidth
 915          * DisplayMode should contain the source and destination dimensions,
 916          * timing, etc.
 917          */
 918         fixed20_12 bpp;
 919         fixed20_12 line_time;
 920         fixed20_12 src_width;
 921         fixed20_12 bandwidth;
 922         fixed20_12 a;
 923
 924         a.full = dfixed_const(1000);
 925         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 926         line_time.full = dfixed_div(line_time, a);
 927         bpp.full = dfixed_const(wm->bytes_per_pixel);
 928         src_width.full = dfixed_const(wm->src_width);
 929         bandwidth.full = dfixed_mul(src_width, bpp);
 930         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 931         bandwidth.full = dfixed_div(bandwidth, line_time);
 932
 933         return dfixed_trunc(bandwidth);
 934 }
 935
 936 /**
 937  * dce_v8_0_latency_watermark - get the latency watermark
 938  *
 939  * @wm: watermark calculation data
 940  *
 941  * Calculate the latency watermark (CIK).
 942  * Used for display watermark bandwidth calculations
 943  * Returns the latency watermark in ns
 944  */
 945 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
 946 {
 947         /* First calculate the latency in ns */
 948         u32 mc_latency = 2000; /* 2000 ns. */
 949         u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
 950         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 951         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 952         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 953         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 954                 (wm->num_heads * cursor_line_pair_return_time);
 955         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 956         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 957         u32 tmp, dmif_size = 12288;
 958         fixed20_12 a, b, c;
 959
 960         if (wm->num_heads == 0)
 961                 return 0;
 962
 963         a.full = dfixed_const(2);
 964         b.full = dfixed_const(1);
 965         if ((wm->vsc.full > a.full) ||
 966             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 967             (wm->vtaps >= 5) ||
 968             ((wm->vsc.full >= a.full) && wm->interlaced))
 969                 max_src_lines_per_dst_line = 4;
 970         else
 971                 max_src_lines_per_dst_line = 2;
 972
 973         a.full = dfixed_const(available_bandwidth);
 974         b.full = dfixed_const(wm->num_heads);
 975         a.full = dfixed_div(a, b);
 976
 977         b.full = dfixed_const(mc_latency + 512);
 978         c.full = dfixed_const(wm->disp_clk);
 979         b.full = dfixed_div(b, c);
 980
 981         c.full = dfixed_const(dmif_size);
 982         b.full = dfixed_div(c, b);
 983
 984         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
 985
 986         b.full = dfixed_const(1000);
 987         c.full = dfixed_const(wm->disp_clk);
 988         b.full = dfixed_div(c, b);
 989         c.full = dfixed_const(wm->bytes_per_pixel);
 990         b.full = dfixed_mul(b, c);
 991
 992         lb_fill_bw = min(tmp, dfixed_trunc(b));
 993
 994         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 995         b.full = dfixed_const(1000);
 996         c.full = dfixed_const(lb_fill_bw);
 997         b.full = dfixed_div(c, b);
 998         a.full = dfixed_div(a, b);
 999         line_fill_time = dfixed_trunc(a);
1000
1001         if (line_fill_time < wm->active_time)
1002                 return latency;
1003         else
1004                 return latency + (line_fill_time - wm->active_time);
1005
1006 }
1007
1008 /**
1009  * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1010  * average and available dram bandwidth
1011  *
1012  * @wm: watermark calculation data
1013  *
1014  * Check if the display average bandwidth fits in the display
1015  * dram bandwidth (CIK).
1016  * Used for display watermark bandwidth calculations
1017  * Returns true if the display fits, false if not.
1018  */
1019 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1020 {
1021         if (dce_v8_0_average_bandwidth(wm) <=
1022             (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1023                 return true;
1024         else
1025                 return false;
1026 }
1027
1028 /**
1029  * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1030  * average and available bandwidth
1031  *
1032  * @wm: watermark calculation data
1033  *
1034  * Check if the display average bandwidth fits in the display
1035  * available bandwidth (CIK).
1036  * Used for display watermark bandwidth calculations
1037  * Returns true if the display fits, false if not.
1038  */
1039 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1040 {
1041         if (dce_v8_0_average_bandwidth(wm) <=
1042             (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1043                 return true;
1044         else
1045                 return false;
1046 }
1047
1048 /**
1049  * dce_v8_0_check_latency_hiding - check latency hiding
1050  *
1051  * @wm: watermark calculation data
1052  *
1053  * Check latency hiding (CIK).
1054  * Used for display watermark bandwidth calculations
1055  * Returns true if the display fits, false if not.
1056  */
1057 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1058 {
1059         u32 lb_partitions = wm->lb_size / wm->src_width;
1060         u32 line_time = wm->active_time + wm->blank_time;
1061         u32 latency_tolerant_lines;
1062         u32 latency_hiding;
1063         fixed20_12 a;
1064
1065         a.full = dfixed_const(1);
1066         if (wm->vsc.full > a.full)
1067                 latency_tolerant_lines = 1;
1068         else {
1069                 if (lb_partitions <= (wm->vtaps + 1))
1070                         latency_tolerant_lines = 1;
1071                 else
1072                         latency_tolerant_lines = 2;
1073         }
1074
1075         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1076
1077         if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1078                 return true;
1079         else
1080                 return false;
1081 }
1082
1083 /**
1084  * dce_v8_0_program_watermarks - program display watermarks
1085  *
1086  * @adev: amdgpu_device pointer
1087  * @amdgpu_crtc: the selected display controller
1088  * @lb_size: line buffer size
1089  * @num_heads: number of display controllers in use
1090  *
1091  * Calculate and program the display watermarks for the
1092  * selected display controller (CIK).
1093  */
1094 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1095                                         struct amdgpu_crtc *amdgpu_crtc,
1096                                         u32 lb_size, u32 num_heads)
1097 {
1098         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1099         struct dce8_wm_params wm_low, wm_high;
1100         u32 pixel_period;
1101         u32 line_time = 0;
1102         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1103         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1104
1105         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1106                 pixel_period = 1000000 / (u32)mode->clock;
1107                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1108
1109                 /* watermark for high clocks */
1110                 if (adev->pm.dpm_enabled) {
1111                         wm_high.yclk =
1112                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1113                         wm_high.sclk =
1114                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1115                 } else {
1116                         wm_high.yclk = adev->pm.current_mclk * 10;
1117                         wm_high.sclk = adev->pm.current_sclk * 10;
1118                 }
1119
1120                 wm_high.disp_clk = mode->clock;
1121                 wm_high.src_width = mode->crtc_hdisplay;
1122                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1123                 wm_high.blank_time = line_time - wm_high.active_time;
1124                 wm_high.interlaced = false;
1125                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1126                         wm_high.interlaced = true;
1127                 wm_high.vsc = amdgpu_crtc->vsc;
1128                 wm_high.vtaps = 1;
1129                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1130                         wm_high.vtaps = 2;
1131                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1132                 wm_high.lb_size = lb_size;
1133                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1134                 wm_high.num_heads = num_heads;
1135
1136                 /* set for high clocks */
1137                 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1138
1139                 /* possibly force display priority to high */
1140                 /* should really do this at mode validation time... */
1141                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1142                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1143                     !dce_v8_0_check_latency_hiding(&wm_high) ||
1144                     (adev->mode_info.disp_priority == 2)) {
1145                         DRM_DEBUG_KMS("force priority to high\n");
1146                 }
1147
1148                 /* watermark for low clocks */
1149                 if (adev->pm.dpm_enabled) {
1150                         wm_low.yclk =
1151                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1152                         wm_low.sclk =
1153                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1154                 } else {
1155                         wm_low.yclk = adev->pm.current_mclk * 10;
1156                         wm_low.sclk = adev->pm.current_sclk * 10;
1157                 }
1158
1159                 wm_low.disp_clk = mode->clock;
1160                 wm_low.src_width = mode->crtc_hdisplay;
1161                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1162                 wm_low.blank_time = line_time - wm_low.active_time;
1163                 wm_low.interlaced = false;
1164                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1165                         wm_low.interlaced = true;
1166                 wm_low.vsc = amdgpu_crtc->vsc;
1167                 wm_low.vtaps = 1;
1168                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1169                         wm_low.vtaps = 2;
1170                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1171                 wm_low.lb_size = lb_size;
1172                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1173                 wm_low.num_heads = num_heads;
1174
1175                 /* set for low clocks */
1176                 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1177
1178                 /* possibly force display priority to high */
1179                 /* should really do this at mode validation time... */
1180                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1181                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1182                     !dce_v8_0_check_latency_hiding(&wm_low) ||
1183                     (adev->mode_info.disp_priority == 2)) {
1184                         DRM_DEBUG_KMS("force priority to high\n");
1185                 }
1186                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1187         }
1188
1189         /* select wm A */
1190         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1191         tmp = wm_mask;
1192         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1193         tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1194         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1195         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1196                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1197                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1198         /* select wm B */
1199         tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1200         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1201         tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1202         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1203         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1204                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1205                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1206         /* restore original selection */
1207         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1208
1209         /* save values for DPM */
1210         amdgpu_crtc->line_time = line_time;
1211         amdgpu_crtc->wm_high = latency_watermark_a;
1212         amdgpu_crtc->wm_low = latency_watermark_b;
1213         /* Save number of lines the linebuffer leads before the scanout */
1214         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1215 }
1216
1217 /**
1218  * dce_v8_0_bandwidth_update - program display watermarks
1219  *
1220  * @adev: amdgpu_device pointer
1221  *
1222  * Calculate and program the display watermarks and line
1223  * buffer allocation (CIK).
1224  */
1225 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1226 {
1227         struct drm_display_mode *mode = NULL;
1228         u32 num_heads = 0, lb_size;
1229         int i;
1230
1231         amdgpu_update_display_priority(adev);
1232
1233         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1234                 if (adev->mode_info.crtcs[i]->base.enabled)
1235                         num_heads++;
1236         }
1237         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1238                 mode = &adev->mode_info.crtcs[i]->base.mode;
1239                 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1240                 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1241                                             lb_size, num_heads);
1242         }
1243 }
1244
1245 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1246 {
1247         int i;
1248         u32 offset, tmp;
1249
1250         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1251                 offset = adev->mode_info.audio.pin[i].offset;
1252                 tmp = RREG32_AUDIO_ENDPT(offset,
1253                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1254                 if (((tmp &
1255                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1256                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1257                         adev->mode_info.audio.pin[i].connected = false;
1258                 else
1259                         adev->mode_info.audio.pin[i].connected = true;
1260         }
1261 }
1262
1263 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1264 {
1265         int i;
1266
1267         dce_v8_0_audio_get_connected_pins(adev);
1268
1269         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1270                 if (adev->mode_info.audio.pin[i].connected)
1271                         return &adev->mode_info.audio.pin[i];
1272         }
1273         DRM_ERROR("No connected audio pins found!\n");
1274         return NULL;
1275 }
1276
1277 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1278 {
1279         struct amdgpu_device *adev = encoder->dev->dev_private;
1280         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1281         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1282         u32 offset;
1283
1284         if (!dig || !dig->afmt || !dig->afmt->pin)
1285                 return;
1286
1287         offset = dig->afmt->offset;
1288
1289         WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1290                (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1291 }
1292
1293 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1294                                                 struct drm_display_mode *mode)
1295 {
1296         struct amdgpu_device *adev = encoder->dev->dev_private;
1297         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1298         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1299         struct drm_connector *connector;
1300         struct amdgpu_connector *amdgpu_connector = NULL;
1301         u32 tmp = 0, offset;
1302
1303         if (!dig || !dig->afmt || !dig->afmt->pin)
1304                 return;
1305
1306         offset = dig->afmt->pin->offset;
1307
1308         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1309                 if (connector->encoder == encoder) {
1310                         amdgpu_connector = to_amdgpu_connector(connector);
1311                         break;
1312                 }
1313         }
1314
1315         if (!amdgpu_connector) {
1316                 DRM_ERROR("Couldn't find encoder's connector\n");
1317                 return;
1318         }
1319
1320         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1321                 if (connector->latency_present[1])
1322                         tmp =
1323                         (connector->video_latency[1] <<
1324                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1325                         (connector->audio_latency[1] <<
1326                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1327                 else
1328                         tmp =
1329                         (0 <<
1330                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1331                         (0 <<
1332                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1333         } else {
1334                 if (connector->latency_present[0])
1335                         tmp =
1336                         (connector->video_latency[0] <<
1337                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1338                         (connector->audio_latency[0] <<
1339                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1340                 else
1341                         tmp =
1342                         (0 <<
1343                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1344                         (0 <<
1345                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1346
1347         }
1348         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1349 }
1350
1351 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1352 {
1353         struct amdgpu_device *adev = encoder->dev->dev_private;
1354         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1355         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1356         struct drm_connector *connector;
1357         struct amdgpu_connector *amdgpu_connector = NULL;
1358         u32 offset, tmp;
1359         u8 *sadb = NULL;
1360         int sad_count;
1361
1362         if (!dig || !dig->afmt || !dig->afmt->pin)
1363                 return;
1364
1365         offset = dig->afmt->pin->offset;
1366
1367         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1368                 if (connector->encoder == encoder) {
1369                         amdgpu_connector = to_amdgpu_connector(connector);
1370                         break;
1371                 }
1372         }
1373
1374         if (!amdgpu_connector) {
1375                 DRM_ERROR("Couldn't find encoder's connector\n");
1376                 return;
1377         }
1378
1379         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1380         if (sad_count < 0) {
1381                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1382                 sad_count = 0;
1383         }
1384
1385         /* program the speaker allocation */
1386         tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1387         tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1388                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1389         /* set HDMI mode */
1390         tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1391         if (sad_count)
1392                 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1393         else
1394                 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1395         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1396
1397         kfree(sadb);
1398 }
1399
1400 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1401 {
1402         struct amdgpu_device *adev = encoder->dev->dev_private;
1403         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1404         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1405         u32 offset;
1406         struct drm_connector *connector;
1407         struct amdgpu_connector *amdgpu_connector = NULL;
1408         struct cea_sad *sads;
1409         int i, sad_count;
1410
1411         static const u16 eld_reg_to_type[][2] = {
1412                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1413                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1414                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1415                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1416                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1417                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1418                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1419                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1420                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1421                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1422                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1423                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1424         };
1425
1426         if (!dig || !dig->afmt || !dig->afmt->pin)
1427                 return;
1428
1429         offset = dig->afmt->pin->offset;
1430
1431         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1432                 if (connector->encoder == encoder) {
1433                         amdgpu_connector = to_amdgpu_connector(connector);
1434                         break;
1435                 }
1436         }
1437
1438         if (!amdgpu_connector) {
1439                 DRM_ERROR("Couldn't find encoder's connector\n");
1440                 return;
1441         }
1442
1443         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1444         if (sad_count <= 0) {
1445                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1446                 return;
1447         }
1448         BUG_ON(!sads);
1449
1450         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1451                 u32 value = 0;
1452                 u8 stereo_freqs = 0;
1453                 int max_channels = -1;
1454                 int j;
1455
1456                 for (j = 0; j < sad_count; j++) {
1457                         struct cea_sad *sad = &sads[j];
1458
1459                         if (sad->format == eld_reg_to_type[i][1]) {
1460                                 if (sad->channels > max_channels) {
1461                                         value = (sad->channels <<
1462                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1463                                                 (sad->byte2 <<
1464                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1465                                                 (sad->freq <<
1466                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1467                                         max_channels = sad->channels;
1468                                 }
1469
1470                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1471                                         stereo_freqs |= sad->freq;
1472                                 else
1473                                         break;
1474                         }
1475                 }
1476
1477                 value |= (stereo_freqs <<
1478                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1479
1480                 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1481         }
1482
1483         kfree(sads);
1484 }
1485
1486 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1487                                   struct amdgpu_audio_pin *pin,
1488                                   bool enable)
1489 {
1490         if (!pin)
1491                 return;
1492
1493         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1494                 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1495 }
1496
1497 static const u32 pin_offsets[7] =
1498 {
1499         (0x1780 - 0x1780),
1500         (0x1786 - 0x1780),
1501         (0x178c - 0x1780),
1502         (0x1792 - 0x1780),
1503         (0x1798 - 0x1780),
1504         (0x179d - 0x1780),
1505         (0x17a4 - 0x1780),
1506 };
1507
1508 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1509 {
1510         int i;
1511
1512         if (!amdgpu_audio)
1513                 return 0;
1514
1515         adev->mode_info.audio.enabled = true;
1516
1517         if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1518                 adev->mode_info.audio.num_pins = 7;
1519         else if ((adev->asic_type == CHIP_KABINI) ||
1520                  (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1521                 adev->mode_info.audio.num_pins = 3;
1522         else if ((adev->asic_type == CHIP_BONAIRE) ||
1523                  (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1524                 adev->mode_info.audio.num_pins = 7;
1525         else
1526                 adev->mode_info.audio.num_pins = 3;
1527
1528         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1529                 adev->mode_info.audio.pin[i].channels = -1;
1530                 adev->mode_info.audio.pin[i].rate = -1;
1531                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1532                 adev->mode_info.audio.pin[i].status_bits = 0;
1533                 adev->mode_info.audio.pin[i].category_code = 0;
1534                 adev->mode_info.audio.pin[i].connected = false;
1535                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1536                 adev->mode_info.audio.pin[i].id = i;
1537                 /* disable audio.  it will be set up later */
1538                 /* XXX remove once we switch to ip funcs */
1539                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1540         }
1541
1542         return 0;
1543 }
1544
1545 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1546 {
1547         int i;
1548
1549         if (!amdgpu_audio)
1550                 return;
1551
1552         if (!adev->mode_info.audio.enabled)
1553                 return;
1554
1555         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1556                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1557
1558         adev->mode_info.audio.enabled = false;
1559 }
1560
1561 /*
1562  * update the N and CTS parameters for a given pixel clock rate
1563  */
1564 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1565 {
1566         struct drm_device *dev = encoder->dev;
1567         struct amdgpu_device *adev = dev->dev_private;
1568         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1569         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1570         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1571         uint32_t offset = dig->afmt->offset;
1572
1573         WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1574         WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1575
1576         WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1577         WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1578
1579         WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1580         WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1581 }
1582
1583 /*
1584  * build a HDMI Video Info Frame
1585  */
1586 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1587                                                void *buffer, size_t size)
1588 {
1589         struct drm_device *dev = encoder->dev;
1590         struct amdgpu_device *adev = dev->dev_private;
1591         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1592         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1593         uint32_t offset = dig->afmt->offset;
1594         uint8_t *frame = buffer + 3;
1595         uint8_t *header = buffer;
1596
1597         WREG32(mmAFMT_AVI_INFO0 + offset,
1598                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1599         WREG32(mmAFMT_AVI_INFO1 + offset,
1600                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1601         WREG32(mmAFMT_AVI_INFO2 + offset,
1602                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1603         WREG32(mmAFMT_AVI_INFO3 + offset,
1604                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1605 }
1606
1607 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1608 {
1609         struct drm_device *dev = encoder->dev;
1610         struct amdgpu_device *adev = dev->dev_private;
1611         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1612         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1613         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1614         u32 dto_phase = 24 * 1000;
1615         u32 dto_modulo = clock;
1616
1617         if (!dig || !dig->afmt)
1618                 return;
1619
1620         /* XXX two dtos; generally use dto0 for hdmi */
1621         /* Express [24MHz / target pixel clock] as an exact rational
1622          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1623          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1624          */
1625         WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1626         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1627         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1628 }
1629
1630 /*
1631  * update the info frames with the data from the current display mode
1632  */
1633 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1634                                   struct drm_display_mode *mode)
1635 {
1636         struct drm_device *dev = encoder->dev;
1637         struct amdgpu_device *adev = dev->dev_private;
1638         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1639         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1640         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1641         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1642         struct hdmi_avi_infoframe frame;
1643         uint32_t offset, val;
1644         ssize_t err;
1645         int bpc = 8;
1646
1647         if (!dig || !dig->afmt)
1648                 return;
1649
1650         /* Silent, r600_hdmi_enable will raise WARN for us */
1651         if (!dig->afmt->enabled)
1652                 return;
1653
1654         offset = dig->afmt->offset;
1655
1656         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1657         if (encoder->crtc) {
1658                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1659                 bpc = amdgpu_crtc->bpc;
1660         }
1661
1662         /* disable audio prior to setting up hw */
1663         dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1664         dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1665
1666         dce_v8_0_audio_set_dto(encoder, mode->clock);
1667
1668         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1669                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1670
1671         WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1672
1673         val = RREG32(mmHDMI_CONTROL + offset);
1674         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1675         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1676
1677         switch (bpc) {
1678         case 0:
1679         case 6:
1680         case 8:
1681         case 16:
1682         default:
1683                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1684                           connector->name, bpc);
1685                 break;
1686         case 10:
1687                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1688                 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1689                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1690                           connector->name);
1691                 break;
1692         case 12:
1693                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1694                 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1695                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1696                           connector->name);
1697                 break;
1698         }
1699
1700         WREG32(mmHDMI_CONTROL + offset, val);
1701
1702         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1703                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1704                HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1705                HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1706
1707         WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1708                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1709                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1710
1711         WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1712                AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1713
1714         WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1715                (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1716
1717         WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1718
1719         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1720                (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1721                (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1722
1723         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1724                AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1725
1726         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1727
1728         if (bpc > 8)
1729                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1730                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1731         else
1732                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1733                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1734                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1735
1736         dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1737
1738         WREG32(mmAFMT_60958_0 + offset,
1739                (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1740
1741         WREG32(mmAFMT_60958_1 + offset,
1742                (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1743
1744         WREG32(mmAFMT_60958_2 + offset,
1745                (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1746                (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1747                (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1748                (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1749                (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1750                (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1751
1752         dce_v8_0_audio_write_speaker_allocation(encoder);
1753
1754
1755         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1756                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1757
1758         dce_v8_0_afmt_audio_select_pin(encoder);
1759         dce_v8_0_audio_write_sad_regs(encoder);
1760         dce_v8_0_audio_write_latency_fields(encoder, mode);
1761
1762         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1763         if (err < 0) {
1764                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1765                 return;
1766         }
1767
1768         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1769         if (err < 0) {
1770                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1771                 return;
1772         }
1773
1774         dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1775
1776         WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1777                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1778                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1779
1780         WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1781                  (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1782                  ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1783
1784         WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1785                   AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1786
1787         WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1788         WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1789         WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1790         WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1791
1792         /* enable audio after setting up hw */
1793         dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1794 }
1795
1796 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1797 {
1798         struct drm_device *dev = encoder->dev;
1799         struct amdgpu_device *adev = dev->dev_private;
1800         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1801         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1802
1803         if (!dig || !dig->afmt)
1804                 return;
1805
1806         /* Silent, r600_hdmi_enable will raise WARN for us */
1807         if (enable && dig->afmt->enabled)
1808                 return;
1809         if (!enable && !dig->afmt->enabled)
1810                 return;
1811
1812         if (!enable && dig->afmt->pin) {
1813                 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1814                 dig->afmt->pin = NULL;
1815         }
1816
1817         dig->afmt->enabled = enable;
1818
1819         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1820                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1821 }
1822
1823 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1824 {
1825         int i;
1826
1827         for (i = 0; i < adev->mode_info.num_dig; i++)
1828                 adev->mode_info.afmt[i] = NULL;
1829
1830         /* DCE8 has audio blocks tied to DIG encoders */
1831         for (i = 0; i < adev->mode_info.num_dig; i++) {
1832                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1833                 if (adev->mode_info.afmt[i]) {
1834                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1835                         adev->mode_info.afmt[i]->id = i;
1836                 } else {
1837                         int j;
1838                         for (j = 0; j < i; j++) {
1839                                 kfree(adev->mode_info.afmt[j]);
1840                                 adev->mode_info.afmt[j] = NULL;
1841                         }
1842                         return -ENOMEM;
1843                 }
1844         }
1845         return 0;
1846 }
1847
1848 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1849 {
1850         int i;
1851
1852         for (i = 0; i < adev->mode_info.num_dig; i++) {
1853                 kfree(adev->mode_info.afmt[i]);
1854                 adev->mode_info.afmt[i] = NULL;
1855         }
1856 }
1857
1858 static const u32 vga_control_regs[6] =
1859 {
1860         mmD1VGA_CONTROL,
1861         mmD2VGA_CONTROL,
1862         mmD3VGA_CONTROL,
1863         mmD4VGA_CONTROL,
1864         mmD5VGA_CONTROL,
1865         mmD6VGA_CONTROL,
1866 };
1867
1868 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1869 {
1870         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1871         struct drm_device *dev = crtc->dev;
1872         struct amdgpu_device *adev = dev->dev_private;
1873         u32 vga_control;
1874
1875         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1876         if (enable)
1877                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1878         else
1879                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1880 }
1881
1882 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1883 {
1884         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1885         struct drm_device *dev = crtc->dev;
1886         struct amdgpu_device *adev = dev->dev_private;
1887
1888         if (enable)
1889                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1890         else
1891                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1892 }
1893
1894 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1895                                      struct drm_framebuffer *fb,
1896                                      int x, int y, int atomic)
1897 {
1898         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1899         struct drm_device *dev = crtc->dev;
1900         struct amdgpu_device *adev = dev->dev_private;
1901         struct amdgpu_framebuffer *amdgpu_fb;
1902         struct drm_framebuffer *target_fb;
1903         struct drm_gem_object *obj;
1904         struct amdgpu_bo *abo;
1905         uint64_t fb_location, tiling_flags;
1906         uint32_t fb_format, fb_pitch_pixels;
1907         u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1908         u32 pipe_config;
1909         u32 viewport_w, viewport_h;
1910         int r;
1911         bool bypass_lut = false;
1912         char *format_name;
1913
1914         /* no fb bound */
1915         if (!atomic && !crtc->primary->fb) {
1916                 DRM_DEBUG_KMS("No FB bound\n");
1917                 return 0;
1918         }
1919
1920         if (atomic) {
1921                 amdgpu_fb = to_amdgpu_framebuffer(fb);
1922                 target_fb = fb;
1923         } else {
1924                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1925                 target_fb = crtc->primary->fb;
1926         }
1927
1928         /* If atomic, assume fb object is pinned & idle & fenced and
1929          * just update base pointers
1930          */
1931         obj = amdgpu_fb->obj;
1932         abo = gem_to_amdgpu_bo(obj);
1933         r = amdgpu_bo_reserve(abo, false);
1934         if (unlikely(r != 0))
1935                 return r;
1936
1937         if (atomic) {
1938                 fb_location = amdgpu_bo_gpu_offset(abo);
1939         } else {
1940                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1941                 if (unlikely(r != 0)) {
1942                         amdgpu_bo_unreserve(abo);
1943                         return -EINVAL;
1944                 }
1945         }
1946
1947         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1948         amdgpu_bo_unreserve(abo);
1949
1950         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1951
1952         switch (target_fb->pixel_format) {
1953         case DRM_FORMAT_C8:
1954                 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1955                              (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1956                 break;
1957         case DRM_FORMAT_XRGB4444:
1958         case DRM_FORMAT_ARGB4444:
1959                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1960                              (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1961 #ifdef __BIG_ENDIAN
1962                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1963 #endif
1964                 break;
1965         case DRM_FORMAT_XRGB1555:
1966         case DRM_FORMAT_ARGB1555:
1967                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1968                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1969 #ifdef __BIG_ENDIAN
1970                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1971 #endif
1972                 break;
1973         case DRM_FORMAT_BGRX5551:
1974         case DRM_FORMAT_BGRA5551:
1975                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1976                              (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1977 #ifdef __BIG_ENDIAN
1978                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1979 #endif
1980                 break;
1981         case DRM_FORMAT_RGB565:
1982                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1983                              (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1984 #ifdef __BIG_ENDIAN
1985                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1986 #endif
1987                 break;
1988         case DRM_FORMAT_XRGB8888:
1989         case DRM_FORMAT_ARGB8888:
1990                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1991                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1992 #ifdef __BIG_ENDIAN
1993                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1994 #endif
1995                 break;
1996         case DRM_FORMAT_XRGB2101010:
1997         case DRM_FORMAT_ARGB2101010:
1998                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1999                              (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2000 #ifdef __BIG_ENDIAN
2001                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2002 #endif
2003                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2004                 bypass_lut = true;
2005                 break;
2006         case DRM_FORMAT_BGRX1010102:
2007         case DRM_FORMAT_BGRA1010102:
2008                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2009                              (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2010 #ifdef __BIG_ENDIAN
2011                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2012 #endif
2013                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2014                 bypass_lut = true;
2015                 break;
2016         default:
2017                 format_name = drm_get_format_name(target_fb->pixel_format);
2018                 DRM_ERROR("Unsupported screen format %s\n", format_name);
2019                 kfree(format_name);
2020                 return -EINVAL;
2021         }
2022
2023         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2024                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2025
2026                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2027                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2028                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2029                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2030                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2031
2032                 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2033                 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2034                 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2035                 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2036                 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2037                 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2038                 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
2039         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2040                 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2041         }
2042
2043         fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2044
2045         dce_v8_0_vga_enable(crtc, false);
2046
2047         /* Make sure surface address is updated at vertical blank rather than
2048          * horizontal blank
2049          */
2050         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2051
2052         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2053                upper_32_bits(fb_location));
2054         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2055                upper_32_bits(fb_location));
2056         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2057                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2058         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2059                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2060         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2061         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2062
2063         /*
2064          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2065          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2066          * retain the full precision throughout the pipeline.
2067          */
2068         WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2069                  (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2070                  ~LUT_10BIT_BYPASS_EN);
2071
2072         if (bypass_lut)
2073                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2074
2075         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2076         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2077         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2078         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2079         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2080         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2081
2082         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2083         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2084
2085         dce_v8_0_grph_enable(crtc, true);
2086
2087         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2088                target_fb->height);
2089
2090         x &= ~3;
2091         y &= ~1;
2092         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2093                (x << 16) | y);
2094         viewport_w = crtc->mode.hdisplay;
2095         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2096         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2097                (viewport_w << 16) | viewport_h);
2098
2099         /* set pageflip to happen anywhere in vblank interval */
2100         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2101
2102         if (!atomic && fb && fb != crtc->primary->fb) {
2103                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2104                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2105                 r = amdgpu_bo_reserve(abo, false);
2106                 if (unlikely(r != 0))
2107                         return r;
2108                 amdgpu_bo_unpin(abo);
2109                 amdgpu_bo_unreserve(abo);
2110         }
2111
2112         /* Bytes per pixel may have changed */
2113         dce_v8_0_bandwidth_update(adev);
2114
2115         return 0;
2116 }
2117
2118 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2119                                     struct drm_display_mode *mode)
2120 {
2121         struct drm_device *dev = crtc->dev;
2122         struct amdgpu_device *adev = dev->dev_private;
2123         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2124
2125         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2126                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2127                        LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2128         else
2129                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2130 }
2131
2132 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2133 {
2134         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2135         struct drm_device *dev = crtc->dev;
2136         struct amdgpu_device *adev = dev->dev_private;
2137         int i;
2138
2139         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2140
2141         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2142                ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2143                 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2144         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2145                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2146         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2147                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2148         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2149                ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2150                 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2151
2152         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2153
2154         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2155         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2156         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2157
2158         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2159         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2160         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2161
2162         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2163         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2164
2165         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2166         for (i = 0; i < 256; i++) {
2167                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2168                        (amdgpu_crtc->lut_r[i] << 20) |
2169                        (amdgpu_crtc->lut_g[i] << 10) |
2170                        (amdgpu_crtc->lut_b[i] << 0));
2171         }
2172
2173         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2174                ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2175                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2176                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2177         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2178                ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2179                 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2180         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2181                ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2182                 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2183         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2184                ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2185                 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2186         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2187         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2188         /* XXX this only needs to be programmed once per crtc at startup,
2189          * not sure where the best place for it is
2190          */
2191         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2192                ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2193 }
2194
2195 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2196 {
2197         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2198         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2199
2200         switch (amdgpu_encoder->encoder_id) {
2201         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2202                 if (dig->linkb)
2203                         return 1;
2204                 else
2205                         return 0;
2206                 break;
2207         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2208                 if (dig->linkb)
2209                         return 3;
2210                 else
2211                         return 2;
2212                 break;
2213         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2214                 if (dig->linkb)
2215                         return 5;
2216                 else
2217                         return 4;
2218                 break;
2219         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2220                 return 6;
2221                 break;
2222         default:
2223                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2224                 return 0;
2225         }
2226 }
2227
2228 /**
2229  * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2230  *
2231  * @crtc: drm crtc
2232  *
2233  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2234  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2235  * monitors a dedicated PPLL must be used.  If a particular board has
2236  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2237  * as there is no need to program the PLL itself.  If we are not able to
2238  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2239  * avoid messing up an existing monitor.
2240  *
2241  * Asic specific PLL information
2242  *
2243  * DCE 8.x
2244  * KB/KV
2245  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2246  * CI
2247  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2248  *
2249  */
2250 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2251 {
2252         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2253         struct drm_device *dev = crtc->dev;
2254         struct amdgpu_device *adev = dev->dev_private;
2255         u32 pll_in_use;
2256         int pll;
2257
2258         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2259                 if (adev->clock.dp_extclk)
2260                         /* skip PPLL programming if using ext clock */
2261                         return ATOM_PPLL_INVALID;
2262                 else {
2263                         /* use the same PPLL for all DP monitors */
2264                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2265                         if (pll != ATOM_PPLL_INVALID)
2266                                 return pll;
2267                 }
2268         } else {
2269                 /* use the same PPLL for all monitors with the same clock */
2270                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2271                 if (pll != ATOM_PPLL_INVALID)
2272                         return pll;
2273         }
2274         /* otherwise, pick one of the plls */
2275         if ((adev->asic_type == CHIP_KABINI) ||
2276             (adev->asic_type == CHIP_MULLINS)) {
2277                 /* KB/ML has PPLL1 and PPLL2 */
2278                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2279                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2280                         return ATOM_PPLL2;
2281                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2282                         return ATOM_PPLL1;
2283                 DRM_ERROR("unable to allocate a PPLL\n");
2284                 return ATOM_PPLL_INVALID;
2285         } else {
2286                 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2287                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2288                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2289                         return ATOM_PPLL2;
2290                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2291                         return ATOM_PPLL1;
2292                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2293                         return ATOM_PPLL0;
2294                 DRM_ERROR("unable to allocate a PPLL\n");
2295                 return ATOM_PPLL_INVALID;
2296         }
2297         return ATOM_PPLL_INVALID;
2298 }
2299
2300 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2301 {
2302         struct amdgpu_device *adev = crtc->dev->dev_private;
2303         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2304         uint32_t cur_lock;
2305
2306         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2307         if (lock)
2308                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2309         else
2310                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2311         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2312 }
2313
2314 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2315 {
2316         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2317         struct amdgpu_device *adev = crtc->dev->dev_private;
2318
2319         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2320                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2321                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2322 }
2323
2324 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2325 {
2326         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2327         struct amdgpu_device *adev = crtc->dev->dev_private;
2328
2329         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2330                upper_32_bits(amdgpu_crtc->cursor_addr));
2331         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2332                lower_32_bits(amdgpu_crtc->cursor_addr));
2333
2334         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2335                    CUR_CONTROL__CURSOR_EN_MASK |
2336                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2337                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2338 }
2339
2340 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2341                                        int x, int y)
2342 {
2343         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2344         struct amdgpu_device *adev = crtc->dev->dev_private;
2345         int xorigin = 0, yorigin = 0;
2346
2347         /* avivo cursor are offset into the total surface */
2348         x += crtc->x;
2349         y += crtc->y;
2350         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2351
2352         if (x < 0) {
2353                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2354                 x = 0;
2355         }
2356         if (y < 0) {
2357                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2358                 y = 0;
2359         }
2360
2361         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2362         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2363         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2364                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2365
2366         amdgpu_crtc->cursor_x = x;
2367         amdgpu_crtc->cursor_y = y;
2368
2369         return 0;
2370 }
2371
2372 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2373                                      int x, int y)
2374 {
2375         int ret;
2376
2377         dce_v8_0_lock_cursor(crtc, true);
2378         ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2379         dce_v8_0_lock_cursor(crtc, false);
2380
2381         return ret;
2382 }
2383
2384 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2385                                      struct drm_file *file_priv,
2386                                      uint32_t handle,
2387                                      uint32_t width,
2388                                      uint32_t height,
2389                                      int32_t hot_x,
2390                                      int32_t hot_y)
2391 {
2392         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2393         struct drm_gem_object *obj;
2394         struct amdgpu_bo *aobj;
2395         int ret;
2396
2397         if (!handle) {
2398                 /* turn off cursor */
2399                 dce_v8_0_hide_cursor(crtc);
2400                 obj = NULL;
2401                 goto unpin;
2402         }
2403
2404         if ((width > amdgpu_crtc->max_cursor_width) ||
2405             (height > amdgpu_crtc->max_cursor_height)) {
2406                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2407                 return -EINVAL;
2408         }
2409
2410         obj = drm_gem_object_lookup(file_priv, handle);
2411         if (!obj) {
2412                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2413                 return -ENOENT;
2414         }
2415
2416         aobj = gem_to_amdgpu_bo(obj);
2417         ret = amdgpu_bo_reserve(aobj, false);
2418         if (ret != 0) {
2419                 drm_gem_object_unreference_unlocked(obj);
2420                 return ret;
2421         }
2422
2423         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2424         amdgpu_bo_unreserve(aobj);
2425         if (ret) {
2426                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2427                 drm_gem_object_unreference_unlocked(obj);
2428                 return ret;
2429         }
2430
2431         amdgpu_crtc->cursor_width = width;
2432         amdgpu_crtc->cursor_height = height;
2433
2434         dce_v8_0_lock_cursor(crtc, true);
2435
2436         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2437             hot_y != amdgpu_crtc->cursor_hot_y) {
2438                 int x, y;
2439
2440                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2441                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2442
2443                 dce_v8_0_cursor_move_locked(crtc, x, y);
2444
2445                 amdgpu_crtc->cursor_hot_x = hot_x;
2446                 amdgpu_crtc->cursor_hot_y = hot_y;
2447         }
2448
2449         dce_v8_0_show_cursor(crtc);
2450         dce_v8_0_lock_cursor(crtc, false);
2451
2452 unpin:
2453         if (amdgpu_crtc->cursor_bo) {
2454                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2455                 ret = amdgpu_bo_reserve(aobj, false);
2456                 if (likely(ret == 0)) {
2457                         amdgpu_bo_unpin(aobj);
2458                         amdgpu_bo_unreserve(aobj);
2459                 }
2460                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2461         }
2462
2463         amdgpu_crtc->cursor_bo = obj;
2464         return 0;
2465 }
2466
2467 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2468 {
2469         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2470
2471         if (amdgpu_crtc->cursor_bo) {
2472                 dce_v8_0_lock_cursor(crtc, true);
2473
2474                 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2475                                             amdgpu_crtc->cursor_y);
2476
2477                 dce_v8_0_show_cursor(crtc);
2478
2479                 dce_v8_0_lock_cursor(crtc, false);
2480         }
2481 }
2482
2483 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2484                                    u16 *blue, uint32_t size)
2485 {
2486         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2487         int i;
2488
2489         /* userspace palettes are always correct as is */
2490         for (i = 0; i < size; i++) {
2491                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2492                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2493                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2494         }
2495         dce_v8_0_crtc_load_lut(crtc);
2496
2497         return 0;
2498 }
2499
2500 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2501 {
2502         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2503
2504         drm_crtc_cleanup(crtc);
2505         kfree(amdgpu_crtc);
2506 }
2507
2508 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2509         .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2510         .cursor_move = dce_v8_0_crtc_cursor_move,
2511         .gamma_set = dce_v8_0_crtc_gamma_set,
2512         .set_config = amdgpu_crtc_set_config,
2513         .destroy = dce_v8_0_crtc_destroy,
2514         .page_flip_target = amdgpu_crtc_page_flip_target,
2515 };
2516
2517 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2518 {
2519         struct drm_device *dev = crtc->dev;
2520         struct amdgpu_device *adev = dev->dev_private;
2521         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2522         unsigned type;
2523
2524         switch (mode) {
2525         case DRM_MODE_DPMS_ON:
2526                 amdgpu_crtc->enabled = true;
2527                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2528                 dce_v8_0_vga_enable(crtc, true);
2529                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2530                 dce_v8_0_vga_enable(crtc, false);
2531                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2532                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2533                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2534                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2535                 drm_crtc_vblank_on(crtc);
2536                 dce_v8_0_crtc_load_lut(crtc);
2537                 break;
2538         case DRM_MODE_DPMS_STANDBY:
2539         case DRM_MODE_DPMS_SUSPEND:
2540         case DRM_MODE_DPMS_OFF:
2541                 drm_crtc_vblank_off(crtc);
2542                 if (amdgpu_crtc->enabled) {
2543                         dce_v8_0_vga_enable(crtc, true);
2544                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2545                         dce_v8_0_vga_enable(crtc, false);
2546                 }
2547                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2548                 amdgpu_crtc->enabled = false;
2549                 break;
2550         }
2551         /* adjust pm to dpms */
2552         amdgpu_pm_compute_clocks(adev);
2553 }
2554
2555 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2556 {
2557         /* disable crtc pair power gating before programming */
2558         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2559         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2560         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2561 }
2562
2563 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2564 {
2565         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2566         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2567 }
2568
2569 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2570 {
2571         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2572         struct drm_device *dev = crtc->dev;
2573         struct amdgpu_device *adev = dev->dev_private;
2574         struct amdgpu_atom_ss ss;
2575         int i;
2576
2577         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2578         if (crtc->primary->fb) {
2579                 int r;
2580                 struct amdgpu_framebuffer *amdgpu_fb;
2581                 struct amdgpu_bo *abo;
2582
2583                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2584                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2585                 r = amdgpu_bo_reserve(abo, false);
2586                 if (unlikely(r))
2587                         DRM_ERROR("failed to reserve abo before unpin\n");
2588                 else {
2589                         amdgpu_bo_unpin(abo);
2590                         amdgpu_bo_unreserve(abo);
2591                 }
2592         }
2593         /* disable the GRPH */
2594         dce_v8_0_grph_enable(crtc, false);
2595
2596         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2597
2598         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2599                 if (adev->mode_info.crtcs[i] &&
2600                     adev->mode_info.crtcs[i]->enabled &&
2601                     i != amdgpu_crtc->crtc_id &&
2602                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2603                         /* one other crtc is using this pll don't turn
2604                          * off the pll
2605                          */
2606                         goto done;
2607                 }
2608         }
2609
2610         switch (amdgpu_crtc->pll_id) {
2611         case ATOM_PPLL1:
2612         case ATOM_PPLL2:
2613                 /* disable the ppll */
2614                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2615                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2616                 break;
2617         case ATOM_PPLL0:
2618                 /* disable the ppll */
2619                 if ((adev->asic_type == CHIP_KAVERI) ||
2620                     (adev->asic_type == CHIP_BONAIRE) ||
2621                     (adev->asic_type == CHIP_HAWAII))
2622                         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2623                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2624                 break;
2625         default:
2626                 break;
2627         }
2628 done:
2629         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2630         amdgpu_crtc->adjusted_clock = 0;
2631         amdgpu_crtc->encoder = NULL;
2632         amdgpu_crtc->connector = NULL;
2633 }
2634
2635 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2636                                   struct drm_display_mode *mode,
2637                                   struct drm_display_mode *adjusted_mode,
2638                                   int x, int y, struct drm_framebuffer *old_fb)
2639 {
2640         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2641
2642         if (!amdgpu_crtc->adjusted_clock)
2643                 return -EINVAL;
2644
2645         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2646         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2647         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2648         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2649         amdgpu_atombios_crtc_scaler_setup(crtc);
2650         dce_v8_0_cursor_reset(crtc);
2651         /* update the hw version fpr dpm */
2652         amdgpu_crtc->hw_mode = *adjusted_mode;
2653
2654         return 0;
2655 }
2656
2657 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2658                                      const struct drm_display_mode *mode,
2659                                      struct drm_display_mode *adjusted_mode)
2660 {
2661         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2662         struct drm_device *dev = crtc->dev;
2663         struct drm_encoder *encoder;
2664
2665         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2666         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2667                 if (encoder->crtc == crtc) {
2668                         amdgpu_crtc->encoder = encoder;
2669                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2670                         break;
2671                 }
2672         }
2673         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2674                 amdgpu_crtc->encoder = NULL;
2675                 amdgpu_crtc->connector = NULL;
2676                 return false;
2677         }
2678         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2679                 return false;
2680         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2681                 return false;
2682         /* pick pll */
2683         amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2684         /* if we can't get a PPLL for a non-DP encoder, fail */
2685         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2686             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2687                 return false;
2688
2689         return true;
2690 }
2691
2692 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2693                                   struct drm_framebuffer *old_fb)
2694 {
2695         return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2696 }
2697
2698 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2699                                          struct drm_framebuffer *fb,
2700                                          int x, int y, enum mode_set_atomic state)
2701 {
2702        return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2703 }
2704
2705 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2706         .dpms = dce_v8_0_crtc_dpms,
2707         .mode_fixup = dce_v8_0_crtc_mode_fixup,
2708         .mode_set = dce_v8_0_crtc_mode_set,
2709         .mode_set_base = dce_v8_0_crtc_set_base,
2710         .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2711         .prepare = dce_v8_0_crtc_prepare,
2712         .commit = dce_v8_0_crtc_commit,
2713         .load_lut = dce_v8_0_crtc_load_lut,
2714         .disable = dce_v8_0_crtc_disable,
2715 };
2716
2717 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2718 {
2719         struct amdgpu_crtc *amdgpu_crtc;
2720         int i;
2721
2722         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2723                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2724         if (amdgpu_crtc == NULL)
2725                 return -ENOMEM;
2726
2727         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2728
2729         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2730         amdgpu_crtc->crtc_id = index;
2731         adev->mode_info.crtcs[index] = amdgpu_crtc;
2732
2733         amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2734         amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2735         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2736         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2737
2738         for (i = 0; i < 256; i++) {
2739                 amdgpu_crtc->lut_r[i] = i << 2;
2740                 amdgpu_crtc->lut_g[i] = i << 2;
2741                 amdgpu_crtc->lut_b[i] = i << 2;
2742         }
2743
2744         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2745
2746         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2747         amdgpu_crtc->adjusted_clock = 0;
2748         amdgpu_crtc->encoder = NULL;
2749         amdgpu_crtc->connector = NULL;
2750         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2751
2752         return 0;
2753 }
2754
2755 static int dce_v8_0_early_init(void *handle)
2756 {
2757         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2758
2759         adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2760         adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2761
2762         dce_v8_0_set_display_funcs(adev);
2763         dce_v8_0_set_irq_funcs(adev);
2764
2765         adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2766
2767         switch (adev->asic_type) {
2768         case CHIP_BONAIRE:
2769         case CHIP_HAWAII:
2770                 adev->mode_info.num_hpd = 6;
2771                 adev->mode_info.num_dig = 6;
2772                 break;
2773         case CHIP_KAVERI:
2774                 adev->mode_info.num_hpd = 6;
2775                 adev->mode_info.num_dig = 7;
2776                 break;
2777         case CHIP_KABINI:
2778         case CHIP_MULLINS:
2779                 adev->mode_info.num_hpd = 6;
2780                 adev->mode_info.num_dig = 6; /* ? */
2781                 break;
2782         default:
2783                 /* FIXME: not supported yet */
2784                 return -EINVAL;
2785         }
2786
2787         return 0;
2788 }
2789
2790 static int dce_v8_0_sw_init(void *handle)
2791 {
2792         int r, i;
2793         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2794
2795         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2796                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2797                 if (r)
2798                         return r;
2799         }
2800
2801         for (i = 8; i < 20; i += 2) {
2802                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2803                 if (r)
2804                         return r;
2805         }
2806
2807         /* HPD hotplug */
2808         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2809         if (r)
2810                 return r;
2811
2812         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2813
2814         adev->ddev->mode_config.async_page_flip = true;
2815
2816         adev->ddev->mode_config.max_width = 16384;
2817         adev->ddev->mode_config.max_height = 16384;
2818
2819         adev->ddev->mode_config.preferred_depth = 24;
2820         adev->ddev->mode_config.prefer_shadow = 1;
2821
2822         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2823
2824         r = amdgpu_modeset_create_props(adev);
2825         if (r)
2826                 return r;
2827
2828         adev->ddev->mode_config.max_width = 16384;
2829         adev->ddev->mode_config.max_height = 16384;
2830
2831         /* allocate crtcs */
2832         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2833                 r = dce_v8_0_crtc_init(adev, i);
2834                 if (r)
2835                         return r;
2836         }
2837
2838         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2839                 amdgpu_print_display_setup(adev->ddev);
2840         else
2841                 return -EINVAL;
2842
2843         /* setup afmt */
2844         r = dce_v8_0_afmt_init(adev);
2845         if (r)
2846                 return r;
2847
2848         r = dce_v8_0_audio_init(adev);
2849         if (r)
2850                 return r;
2851
2852         drm_kms_helper_poll_init(adev->ddev);
2853
2854         adev->mode_info.mode_config_initialized = true;
2855         return 0;
2856 }
2857
2858 static int dce_v8_0_sw_fini(void *handle)
2859 {
2860         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2861
2862         kfree(adev->mode_info.bios_hardcoded_edid);
2863
2864         drm_kms_helper_poll_fini(adev->ddev);
2865
2866         dce_v8_0_audio_fini(adev);
2867
2868         dce_v8_0_afmt_fini(adev);
2869
2870         drm_mode_config_cleanup(adev->ddev);
2871         adev->mode_info.mode_config_initialized = false;
2872
2873         return 0;
2874 }
2875
2876 static int dce_v8_0_hw_init(void *handle)
2877 {
2878         int i;
2879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2880
2881         /* init dig PHYs, disp eng pll */
2882         amdgpu_atombios_encoder_init_dig(adev);
2883         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2884
2885         /* initialize hpd */
2886         dce_v8_0_hpd_init(adev);
2887
2888         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2889                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2890         }
2891
2892         dce_v8_0_pageflip_interrupt_init(adev);
2893
2894         return 0;
2895 }
2896
2897 static int dce_v8_0_hw_fini(void *handle)
2898 {
2899         int i;
2900         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2901
2902         dce_v8_0_hpd_fini(adev);
2903
2904         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2905                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2906         }
2907
2908         dce_v8_0_pageflip_interrupt_fini(adev);
2909
2910         return 0;
2911 }
2912
2913 static int dce_v8_0_suspend(void *handle)
2914 {
2915         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2916
2917         amdgpu_atombios_scratch_regs_save(adev);
2918
2919         return dce_v8_0_hw_fini(handle);
2920 }
2921
2922 static int dce_v8_0_resume(void *handle)
2923 {
2924         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2925         int ret;
2926
2927         ret = dce_v8_0_hw_init(handle);
2928
2929         amdgpu_atombios_scratch_regs_restore(adev);
2930
2931         /* turn on the BL */
2932         if (adev->mode_info.bl_encoder) {
2933                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2934                                                                   adev->mode_info.bl_encoder);
2935                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2936                                                     bl_level);
2937         }
2938
2939         return ret;
2940 }
2941
2942 static bool dce_v8_0_is_idle(void *handle)
2943 {
2944         return true;
2945 }
2946
2947 static int dce_v8_0_wait_for_idle(void *handle)
2948 {
2949         return 0;
2950 }
2951
2952 static int dce_v8_0_soft_reset(void *handle)
2953 {
2954         u32 srbm_soft_reset = 0, tmp;
2955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2956
2957         if (dce_v8_0_is_display_hung(adev))
2958                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2959
2960         if (srbm_soft_reset) {
2961                 tmp = RREG32(mmSRBM_SOFT_RESET);
2962                 tmp |= srbm_soft_reset;
2963                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2964                 WREG32(mmSRBM_SOFT_RESET, tmp);
2965                 tmp = RREG32(mmSRBM_SOFT_RESET);
2966
2967                 udelay(50);
2968
2969                 tmp &= ~srbm_soft_reset;
2970                 WREG32(mmSRBM_SOFT_RESET, tmp);
2971                 tmp = RREG32(mmSRBM_SOFT_RESET);
2972
2973                 /* Wait a little for things to settle down */
2974                 udelay(50);
2975         }
2976         return 0;
2977 }
2978
2979 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2980                                                      int crtc,
2981                                                      enum amdgpu_interrupt_state state)
2982 {
2983         u32 reg_block, lb_interrupt_mask;
2984
2985         if (crtc >= adev->mode_info.num_crtc) {
2986                 DRM_DEBUG("invalid crtc %d\n", crtc);
2987                 return;
2988         }
2989
2990         switch (crtc) {
2991         case 0:
2992                 reg_block = CRTC0_REGISTER_OFFSET;
2993                 break;
2994         case 1:
2995                 reg_block = CRTC1_REGISTER_OFFSET;
2996                 break;
2997         case 2:
2998                 reg_block = CRTC2_REGISTER_OFFSET;
2999                 break;
3000         case 3:
3001                 reg_block = CRTC3_REGISTER_OFFSET;
3002                 break;
3003         case 4:
3004                 reg_block = CRTC4_REGISTER_OFFSET;
3005                 break;
3006         case 5:
3007                 reg_block = CRTC5_REGISTER_OFFSET;
3008                 break;
3009         default:
3010                 DRM_DEBUG("invalid crtc %d\n", crtc);
3011                 return;
3012         }
3013
3014         switch (state) {
3015         case AMDGPU_IRQ_STATE_DISABLE:
3016                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3017                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3018                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3019                 break;
3020         case AMDGPU_IRQ_STATE_ENABLE:
3021                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3022                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3023                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3024                 break;
3025         default:
3026                 break;
3027         }
3028 }
3029
3030 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3031                                                     int crtc,
3032                                                     enum amdgpu_interrupt_state state)
3033 {
3034         u32 reg_block, lb_interrupt_mask;
3035
3036         if (crtc >= adev->mode_info.num_crtc) {
3037                 DRM_DEBUG("invalid crtc %d\n", crtc);
3038                 return;
3039         }
3040
3041         switch (crtc) {
3042         case 0:
3043                 reg_block = CRTC0_REGISTER_OFFSET;
3044                 break;
3045         case 1:
3046                 reg_block = CRTC1_REGISTER_OFFSET;
3047                 break;
3048         case 2:
3049                 reg_block = CRTC2_REGISTER_OFFSET;
3050                 break;
3051         case 3:
3052                 reg_block = CRTC3_REGISTER_OFFSET;
3053                 break;
3054         case 4:
3055                 reg_block = CRTC4_REGISTER_OFFSET;
3056                 break;
3057         case 5:
3058                 reg_block = CRTC5_REGISTER_OFFSET;
3059                 break;
3060         default:
3061                 DRM_DEBUG("invalid crtc %d\n", crtc);
3062                 return;
3063         }
3064
3065         switch (state) {
3066         case AMDGPU_IRQ_STATE_DISABLE:
3067                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3068                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3069                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3070                 break;
3071         case AMDGPU_IRQ_STATE_ENABLE:
3072                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3073                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3074                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3075                 break;
3076         default:
3077                 break;
3078         }
3079 }
3080
3081 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3082                                             struct amdgpu_irq_src *src,
3083                                             unsigned type,
3084                                             enum amdgpu_interrupt_state state)
3085 {
3086         u32 dc_hpd_int_cntl;
3087
3088         if (type >= adev->mode_info.num_hpd) {
3089                 DRM_DEBUG("invalid hdp %d\n", type);
3090                 return 0;
3091         }
3092
3093         switch (state) {
3094         case AMDGPU_IRQ_STATE_DISABLE:
3095                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3096                 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3097                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3098                 break;
3099         case AMDGPU_IRQ_STATE_ENABLE:
3100                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3101                 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3102                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3103                 break;
3104         default:
3105                 break;
3106         }
3107
3108         return 0;
3109 }
3110
3111 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3112                                              struct amdgpu_irq_src *src,
3113                                              unsigned type,
3114                                              enum amdgpu_interrupt_state state)
3115 {
3116         switch (type) {
3117         case AMDGPU_CRTC_IRQ_VBLANK1:
3118                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3119                 break;
3120         case AMDGPU_CRTC_IRQ_VBLANK2:
3121                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3122                 break;
3123         case AMDGPU_CRTC_IRQ_VBLANK3:
3124                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3125                 break;
3126         case AMDGPU_CRTC_IRQ_VBLANK4:
3127                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3128                 break;
3129         case AMDGPU_CRTC_IRQ_VBLANK5:
3130                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3131                 break;
3132         case AMDGPU_CRTC_IRQ_VBLANK6:
3133                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3134                 break;
3135         case AMDGPU_CRTC_IRQ_VLINE1:
3136                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3137                 break;
3138         case AMDGPU_CRTC_IRQ_VLINE2:
3139                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3140                 break;
3141         case AMDGPU_CRTC_IRQ_VLINE3:
3142                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3143                 break;
3144         case AMDGPU_CRTC_IRQ_VLINE4:
3145                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3146                 break;
3147         case AMDGPU_CRTC_IRQ_VLINE5:
3148                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3149                 break;
3150         case AMDGPU_CRTC_IRQ_VLINE6:
3151                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3152                 break;
3153         default:
3154                 break;
3155         }
3156         return 0;
3157 }
3158
3159 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3160                              struct amdgpu_irq_src *source,
3161                              struct amdgpu_iv_entry *entry)
3162 {
3163         unsigned crtc = entry->src_id - 1;
3164         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3165         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3166
3167         switch (entry->src_data) {
3168         case 0: /* vblank */
3169                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3170                         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3171                 else
3172                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3173
3174                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3175                         drm_handle_vblank(adev->ddev, crtc);
3176                 }
3177                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3178                 break;
3179         case 1: /* vline */
3180                 if (disp_int & interrupt_status_offsets[crtc].vline)
3181                         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3182                 else
3183                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3184
3185                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3186                 break;
3187         default:
3188                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3189                 break;
3190         }
3191
3192         return 0;
3193 }
3194
3195 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3196                                                  struct amdgpu_irq_src *src,
3197                                                  unsigned type,
3198                                                  enum amdgpu_interrupt_state state)
3199 {
3200         u32 reg;
3201
3202         if (type >= adev->mode_info.num_crtc) {
3203                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3204                 return -EINVAL;
3205         }
3206
3207         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3208         if (state == AMDGPU_IRQ_STATE_DISABLE)
3209                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3210                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3211         else
3212                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3213                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3214
3215         return 0;
3216 }
3217
3218 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3219                                 struct amdgpu_irq_src *source,
3220                                 struct amdgpu_iv_entry *entry)
3221 {
3222         unsigned long flags;
3223         unsigned crtc_id;
3224         struct amdgpu_crtc *amdgpu_crtc;
3225         struct amdgpu_flip_work *works;
3226
3227         crtc_id = (entry->src_id - 8) >> 1;
3228         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3229
3230         if (crtc_id >= adev->mode_info.num_crtc) {
3231                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3232                 return -EINVAL;
3233         }
3234
3235         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3236             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3237                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3238                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3239
3240         /* IRQ could occur when in initial stage */
3241         if (amdgpu_crtc == NULL)
3242                 return 0;
3243
3244         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3245         works = amdgpu_crtc->pflip_works;
3246         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3247                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3248                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3249                                                 amdgpu_crtc->pflip_status,
3250                                                 AMDGPU_FLIP_SUBMITTED);
3251                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3252                 return 0;
3253         }
3254
3255         /* page flip completed. clean up */
3256         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3257         amdgpu_crtc->pflip_works = NULL;
3258
3259         /* wakeup usersapce */
3260         if (works->event)
3261                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3262
3263         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3264
3265         drm_crtc_vblank_put(&amdgpu_crtc->base);
3266         schedule_work(&works->unpin_work);
3267
3268         return 0;
3269 }
3270
3271 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3272                             struct amdgpu_irq_src *source,
3273                             struct amdgpu_iv_entry *entry)
3274 {
3275         uint32_t disp_int, mask, tmp;
3276         unsigned hpd;
3277
3278         if (entry->src_data >= adev->mode_info.num_hpd) {
3279                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3280                 return 0;
3281         }
3282
3283         hpd = entry->src_data;
3284         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3285         mask = interrupt_status_offsets[hpd].hpd;
3286
3287         if (disp_int & mask) {
3288                 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3289                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3290                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3291                 schedule_work(&adev->hotplug_work);
3292                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3293         }
3294
3295         return 0;
3296
3297 }
3298
3299 static int dce_v8_0_set_clockgating_state(void *handle,
3300                                           enum amd_clockgating_state state)
3301 {
3302         return 0;
3303 }
3304
3305 static int dce_v8_0_set_powergating_state(void *handle,
3306                                           enum amd_powergating_state state)
3307 {
3308         return 0;
3309 }
3310
3311 const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3312         .name = "dce_v8_0",
3313         .early_init = dce_v8_0_early_init,
3314         .late_init = NULL,
3315         .sw_init = dce_v8_0_sw_init,
3316         .sw_fini = dce_v8_0_sw_fini,
3317         .hw_init = dce_v8_0_hw_init,
3318         .hw_fini = dce_v8_0_hw_fini,
3319         .suspend = dce_v8_0_suspend,
3320         .resume = dce_v8_0_resume,
3321         .is_idle = dce_v8_0_is_idle,
3322         .wait_for_idle = dce_v8_0_wait_for_idle,
3323         .soft_reset = dce_v8_0_soft_reset,
3324         .set_clockgating_state = dce_v8_0_set_clockgating_state,
3325         .set_powergating_state = dce_v8_0_set_powergating_state,
3326 };
3327
3328 static void
3329 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3330                           struct drm_display_mode *mode,
3331                           struct drm_display_mode *adjusted_mode)
3332 {
3333         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3334
3335         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3336
3337         /* need to call this here rather than in prepare() since we need some crtc info */
3338         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3339
3340         /* set scaler clears this on some chips */
3341         dce_v8_0_set_interleave(encoder->crtc, mode);
3342
3343         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3344                 dce_v8_0_afmt_enable(encoder, true);
3345                 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3346         }
3347 }
3348
3349 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3350 {
3351         struct amdgpu_device *adev = encoder->dev->dev_private;
3352         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3353         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3354
3355         if ((amdgpu_encoder->active_device &
3356              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3357             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3358              ENCODER_OBJECT_ID_NONE)) {
3359                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3360                 if (dig) {
3361                         dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3362                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3363                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3364                 }
3365         }
3366
3367         amdgpu_atombios_scratch_regs_lock(adev, true);
3368
3369         if (connector) {
3370                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3371
3372                 /* select the clock/data port if it uses a router */
3373                 if (amdgpu_connector->router.cd_valid)
3374                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3375
3376                 /* turn eDP panel on for mode set */
3377                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3378                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3379                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3380         }
3381
3382         /* this is needed for the pll/ss setup to work correctly in some cases */
3383         amdgpu_atombios_encoder_set_crtc_source(encoder);
3384         /* set up the FMT blocks */
3385         dce_v8_0_program_fmt(encoder);
3386 }
3387
3388 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3389 {
3390         struct drm_device *dev = encoder->dev;
3391         struct amdgpu_device *adev = dev->dev_private;
3392
3393         /* need to call this here as we need the crtc set up */
3394         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3395         amdgpu_atombios_scratch_regs_lock(adev, false);
3396 }
3397
3398 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3399 {
3400         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3401         struct amdgpu_encoder_atom_dig *dig;
3402
3403         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3404
3405         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3406                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3407                         dce_v8_0_afmt_enable(encoder, false);
3408                 dig = amdgpu_encoder->enc_priv;
3409                 dig->dig_encoder = -1;
3410         }
3411         amdgpu_encoder->active_device = 0;
3412 }
3413
3414 /* these are handled by the primary encoders */
3415 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3416 {
3417
3418 }
3419
3420 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3421 {
3422
3423 }
3424
3425 static void
3426 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3427                       struct drm_display_mode *mode,
3428                       struct drm_display_mode *adjusted_mode)
3429 {
3430
3431 }
3432
3433 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3434 {
3435
3436 }
3437
3438 static void
3439 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3440 {
3441
3442 }
3443
3444 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3445         .dpms = dce_v8_0_ext_dpms,
3446         .prepare = dce_v8_0_ext_prepare,
3447         .mode_set = dce_v8_0_ext_mode_set,
3448         .commit = dce_v8_0_ext_commit,
3449         .disable = dce_v8_0_ext_disable,
3450         /* no detect for TMDS/LVDS yet */
3451 };
3452
3453 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3454         .dpms = amdgpu_atombios_encoder_dpms,
3455         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3456         .prepare = dce_v8_0_encoder_prepare,
3457         .mode_set = dce_v8_0_encoder_mode_set,
3458         .commit = dce_v8_0_encoder_commit,
3459         .disable = dce_v8_0_encoder_disable,
3460         .detect = amdgpu_atombios_encoder_dig_detect,
3461 };
3462
3463 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3464         .dpms = amdgpu_atombios_encoder_dpms,
3465         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3466         .prepare = dce_v8_0_encoder_prepare,
3467         .mode_set = dce_v8_0_encoder_mode_set,
3468         .commit = dce_v8_0_encoder_commit,
3469         .detect = amdgpu_atombios_encoder_dac_detect,
3470 };
3471
3472 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3473 {
3474         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3475         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3476                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3477         kfree(amdgpu_encoder->enc_priv);
3478         drm_encoder_cleanup(encoder);
3479         kfree(amdgpu_encoder);
3480 }
3481
3482 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3483         .destroy = dce_v8_0_encoder_destroy,
3484 };
3485
3486 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3487                                  uint32_t encoder_enum,
3488                                  uint32_t supported_device,
3489                                  u16 caps)
3490 {
3491         struct drm_device *dev = adev->ddev;
3492         struct drm_encoder *encoder;
3493         struct amdgpu_encoder *amdgpu_encoder;
3494
3495         /* see if we already added it */
3496         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3497                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3498                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3499                         amdgpu_encoder->devices |= supported_device;
3500                         return;
3501                 }
3502
3503         }
3504
3505         /* add a new one */
3506         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3507         if (!amdgpu_encoder)
3508                 return;
3509
3510         encoder = &amdgpu_encoder->base;
3511         switch (adev->mode_info.num_crtc) {
3512         case 1:
3513                 encoder->possible_crtcs = 0x1;
3514                 break;
3515         case 2:
3516         default:
3517                 encoder->possible_crtcs = 0x3;
3518                 break;
3519         case 4:
3520                 encoder->possible_crtcs = 0xf;
3521                 break;
3522         case 6:
3523                 encoder->possible_crtcs = 0x3f;
3524                 break;
3525         }
3526
3527         amdgpu_encoder->enc_priv = NULL;
3528
3529         amdgpu_encoder->encoder_enum = encoder_enum;
3530         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3531         amdgpu_encoder->devices = supported_device;
3532         amdgpu_encoder->rmx_type = RMX_OFF;
3533         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3534         amdgpu_encoder->is_ext_encoder = false;
3535         amdgpu_encoder->caps = caps;
3536
3537         switch (amdgpu_encoder->encoder_id) {
3538         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3539         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3540                 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3541                                  DRM_MODE_ENCODER_DAC, NULL);
3542                 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3543                 break;
3544         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3545         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3546         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3547         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3548         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3549                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3550                         amdgpu_encoder->rmx_type = RMX_FULL;
3551                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3552                                          DRM_MODE_ENCODER_LVDS, NULL);
3553                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3554                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3555                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3556                                          DRM_MODE_ENCODER_DAC, NULL);
3557                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3558                 } else {
3559                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3560                                          DRM_MODE_ENCODER_TMDS, NULL);
3561                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3562                 }
3563                 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3564                 break;
3565         case ENCODER_OBJECT_ID_SI170B:
3566         case ENCODER_OBJECT_ID_CH7303:
3567         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3568         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3569         case ENCODER_OBJECT_ID_TITFP513:
3570         case ENCODER_OBJECT_ID_VT1623:
3571         case ENCODER_OBJECT_ID_HDMI_SI1930:
3572         case ENCODER_OBJECT_ID_TRAVIS:
3573         case ENCODER_OBJECT_ID_NUTMEG:
3574                 /* these are handled by the primary encoders */
3575                 amdgpu_encoder->is_ext_encoder = true;
3576                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3577                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3578                                          DRM_MODE_ENCODER_LVDS, NULL);
3579                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3580                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3581                                          DRM_MODE_ENCODER_DAC, NULL);
3582                 else
3583                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3584                                          DRM_MODE_ENCODER_TMDS, NULL);
3585                 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3586                 break;
3587         }
3588 }
3589
3590 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3591         .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3592         .bandwidth_update = &dce_v8_0_bandwidth_update,
3593         .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3594         .vblank_wait = &dce_v8_0_vblank_wait,
3595         .is_display_hung = &dce_v8_0_is_display_hung,
3596         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3597         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3598         .hpd_sense = &dce_v8_0_hpd_sense,
3599         .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3600         .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3601         .page_flip = &dce_v8_0_page_flip,
3602         .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3603         .add_encoder = &dce_v8_0_encoder_add,
3604         .add_connector = &amdgpu_connector_add,
3605         .stop_mc_access = &dce_v8_0_stop_mc_access,
3606         .resume_mc_access = &dce_v8_0_resume_mc_access,
3607 };
3608
3609 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3610 {
3611         if (adev->mode_info.funcs == NULL)
3612                 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3613 }
3614
3615 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3616         .set = dce_v8_0_set_crtc_interrupt_state,
3617         .process = dce_v8_0_crtc_irq,
3618 };
3619
3620 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3621         .set = dce_v8_0_set_pageflip_interrupt_state,
3622         .process = dce_v8_0_pageflip_irq,
3623 };
3624
3625 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3626         .set = dce_v8_0_set_hpd_interrupt_state,
3627         .process = dce_v8_0_hpd_irq,
3628 };
3629
3630 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3631 {
3632         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3633         adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3634
3635         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3636         adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3637
3638         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3639         adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3640 }