2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
44 #ifdef CONFIG_DRM_AMDGPU_SI
47 #ifdef CONFIG_DRM_AMDGPU_CIK
51 #include "bif/bif_4_1_d.h"
52 #include <linux/pci.h>
53 #include <linux/firmware.h>
55 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
58 static const char *amdgpu_asic_name[] = {
79 bool amdgpu_device_is_px(struct drm_device *dev)
81 struct amdgpu_device *adev = dev->dev_private;
83 if (adev->flags & AMD_IS_PX)
89 * MMIO register access helper functions.
91 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
96 if ((reg * 4) < adev->rmmio_size && !always_indirect)
97 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
101 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
102 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
103 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
104 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
106 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
111 bool always_indirect)
113 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
115 if ((reg * 4) < adev->rmmio_size && !always_indirect)
116 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
120 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
121 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
122 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
123 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
127 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
129 if ((reg * 4) < adev->rio_mem_size)
130 return ioread32(adev->rio_mem + (reg * 4));
132 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
133 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
140 if ((reg * 4) < adev->rio_mem_size)
141 iowrite32(v, adev->rio_mem + (reg * 4));
143 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
144 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
149 * amdgpu_mm_rdoorbell - read a doorbell dword
151 * @adev: amdgpu_device pointer
152 * @index: doorbell index
154 * Returns the value in the doorbell aperture at the
155 * requested doorbell index (CIK).
157 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
159 if (index < adev->doorbell.num_doorbells) {
160 return readl(adev->doorbell.ptr + index);
162 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
168 * amdgpu_mm_wdoorbell - write a doorbell dword
170 * @adev: amdgpu_device pointer
171 * @index: doorbell index
174 * Writes @v to the doorbell aperture at the
175 * requested doorbell index (CIK).
177 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
179 if (index < adev->doorbell.num_doorbells) {
180 writel(v, adev->doorbell.ptr + index);
182 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
187 * amdgpu_invalid_rreg - dummy reg read function
189 * @adev: amdgpu device pointer
190 * @reg: offset of register
192 * Dummy register read function. Used for register blocks
193 * that certain asics don't have (all asics).
194 * Returns the value in the register.
196 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
198 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
204 * amdgpu_invalid_wreg - dummy reg write function
206 * @adev: amdgpu device pointer
207 * @reg: offset of register
208 * @v: value to write to the register
210 * Dummy register read function. Used for register blocks
211 * that certain asics don't have (all asics).
213 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
215 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
221 * amdgpu_block_invalid_rreg - dummy reg read function
223 * @adev: amdgpu device pointer
224 * @block: offset of instance
225 * @reg: offset of register
227 * Dummy register read function. Used for register blocks
228 * that certain asics don't have (all asics).
229 * Returns the value in the register.
231 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
232 uint32_t block, uint32_t reg)
234 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
241 * amdgpu_block_invalid_wreg - dummy reg write function
243 * @adev: amdgpu device pointer
244 * @block: offset of instance
245 * @reg: offset of register
246 * @v: value to write to the register
248 * Dummy register read function. Used for register blocks
249 * that certain asics don't have (all asics).
251 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
253 uint32_t reg, uint32_t v)
255 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
260 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
264 if (adev->vram_scratch.robj == NULL) {
265 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
266 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
267 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
268 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
269 NULL, NULL, &adev->vram_scratch.robj);
275 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
276 if (unlikely(r != 0))
278 r = amdgpu_bo_pin(adev->vram_scratch.robj,
279 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
281 amdgpu_bo_unreserve(adev->vram_scratch.robj);
284 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
285 (void **)&adev->vram_scratch.ptr);
287 amdgpu_bo_unpin(adev->vram_scratch.robj);
288 amdgpu_bo_unreserve(adev->vram_scratch.robj);
293 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
297 if (adev->vram_scratch.robj == NULL) {
300 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
301 if (likely(r == 0)) {
302 amdgpu_bo_kunmap(adev->vram_scratch.robj);
303 amdgpu_bo_unpin(adev->vram_scratch.robj);
304 amdgpu_bo_unreserve(adev->vram_scratch.robj);
306 amdgpu_bo_unref(&adev->vram_scratch.robj);
310 * amdgpu_program_register_sequence - program an array of registers.
312 * @adev: amdgpu_device pointer
313 * @registers: pointer to the register array
314 * @array_size: size of the register array
316 * Programs an array or registers with and and or masks.
317 * This is a helper for setting golden registers.
319 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
320 const u32 *registers,
321 const u32 array_size)
323 u32 tmp, reg, and_mask, or_mask;
329 for (i = 0; i < array_size; i +=3) {
330 reg = registers[i + 0];
331 and_mask = registers[i + 1];
332 or_mask = registers[i + 2];
334 if (and_mask == 0xffffffff) {
345 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
347 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
351 * GPU doorbell aperture helpers function.
354 * amdgpu_doorbell_init - Init doorbell driver information.
356 * @adev: amdgpu_device pointer
358 * Init doorbell driver information (CIK)
359 * Returns 0 on success, error on failure.
361 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
363 /* doorbell bar mapping */
364 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
365 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
367 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
368 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
369 if (adev->doorbell.num_doorbells == 0)
372 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
373 if (adev->doorbell.ptr == NULL) {
376 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
377 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
383 * amdgpu_doorbell_fini - Tear down doorbell driver information.
385 * @adev: amdgpu_device pointer
387 * Tear down doorbell driver information (CIK)
389 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
391 iounmap(adev->doorbell.ptr);
392 adev->doorbell.ptr = NULL;
396 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
399 * @adev: amdgpu_device pointer
400 * @aperture_base: output returning doorbell aperture base physical address
401 * @aperture_size: output returning doorbell aperture size in bytes
402 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
404 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
405 * takes doorbells required for its own rings and reports the setup to amdkfd.
406 * amdgpu reserved doorbells are at the start of the doorbell aperture.
408 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
409 phys_addr_t *aperture_base,
410 size_t *aperture_size,
411 size_t *start_offset)
414 * The first num_doorbells are used by amdgpu.
415 * amdkfd takes whatever's left in the aperture.
417 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
418 *aperture_base = adev->doorbell.base;
419 *aperture_size = adev->doorbell.size;
420 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
430 * Writeback is the the method by which the the GPU updates special pages
431 * in memory with the status of certain GPU events (fences, ring pointers,
436 * amdgpu_wb_fini - Disable Writeback and free memory
438 * @adev: amdgpu_device pointer
440 * Disables Writeback and frees the Writeback memory (all asics).
441 * Used at driver shutdown.
443 static void amdgpu_wb_fini(struct amdgpu_device *adev)
445 if (adev->wb.wb_obj) {
446 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
447 amdgpu_bo_kunmap(adev->wb.wb_obj);
448 amdgpu_bo_unpin(adev->wb.wb_obj);
449 amdgpu_bo_unreserve(adev->wb.wb_obj);
451 amdgpu_bo_unref(&adev->wb.wb_obj);
453 adev->wb.wb_obj = NULL;
458 * amdgpu_wb_init- Init Writeback driver info and allocate memory
460 * @adev: amdgpu_device pointer
462 * Disables Writeback and frees the Writeback memory (all asics).
463 * Used at driver startup.
464 * Returns 0 on success or an -error on failure.
466 static int amdgpu_wb_init(struct amdgpu_device *adev)
470 if (adev->wb.wb_obj == NULL) {
471 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
472 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
475 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
478 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
479 if (unlikely(r != 0)) {
480 amdgpu_wb_fini(adev);
483 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
486 amdgpu_bo_unreserve(adev->wb.wb_obj);
487 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
488 amdgpu_wb_fini(adev);
491 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
492 amdgpu_bo_unreserve(adev->wb.wb_obj);
494 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
495 amdgpu_wb_fini(adev);
499 adev->wb.num_wb = AMDGPU_MAX_WB;
500 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
502 /* clear wb memory */
503 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
510 * amdgpu_wb_get - Allocate a wb entry
512 * @adev: amdgpu_device pointer
515 * Allocate a wb slot for use by the driver (all asics).
516 * Returns 0 on success or -EINVAL on failure.
518 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
520 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
521 if (offset < adev->wb.num_wb) {
522 __set_bit(offset, adev->wb.used);
531 * amdgpu_wb_free - Free a wb entry
533 * @adev: amdgpu_device pointer
536 * Free a wb slot allocated for use by the driver (all asics)
538 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
540 if (wb < adev->wb.num_wb)
541 __clear_bit(wb, adev->wb.used);
545 * amdgpu_vram_location - try to find VRAM location
546 * @adev: amdgpu device structure holding all necessary informations
547 * @mc: memory controller structure holding memory informations
548 * @base: base address at which to put VRAM
550 * Function will place try to place VRAM at base address provided
551 * as parameter (which is so far either PCI aperture address or
552 * for IGP TOM base address).
554 * If there is not enough space to fit the unvisible VRAM in the 32bits
555 * address space then we limit the VRAM size to the aperture.
557 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
558 * this shouldn't be a problem as we are using the PCI aperture as a reference.
559 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
562 * Note: we use mc_vram_size as on some board we need to program the mc to
563 * cover the whole aperture even if VRAM size is inferior to aperture size
564 * Novell bug 204882 + along with lots of ubuntu ones
566 * Note: when limiting vram it's safe to overwritte real_vram_size because
567 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
568 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
571 * Note: IGP TOM addr should be the same as the aperture addr, we don't
572 * explicitly check for that thought.
574 * FIXME: when reducing VRAM size align new size on power of 2.
576 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
578 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
580 mc->vram_start = base;
581 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
582 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
583 mc->real_vram_size = mc->aper_size;
584 mc->mc_vram_size = mc->aper_size;
586 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
587 if (limit && limit < mc->real_vram_size)
588 mc->real_vram_size = limit;
589 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
590 mc->mc_vram_size >> 20, mc->vram_start,
591 mc->vram_end, mc->real_vram_size >> 20);
595 * amdgpu_gtt_location - try to find GTT location
596 * @adev: amdgpu device structure holding all necessary informations
597 * @mc: memory controller structure holding memory informations
599 * Function will place try to place GTT before or after VRAM.
601 * If GTT size is bigger than space left then we ajust GTT size.
602 * Thus function will never fails.
604 * FIXME: when reducing GTT size align new size on power of 2.
606 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
608 u64 size_af, size_bf;
610 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
611 size_bf = mc->vram_start & ~mc->gtt_base_align;
612 if (size_bf > size_af) {
613 if (mc->gtt_size > size_bf) {
614 dev_warn(adev->dev, "limiting GTT\n");
615 mc->gtt_size = size_bf;
617 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
619 if (mc->gtt_size > size_af) {
620 dev_warn(adev->dev, "limiting GTT\n");
621 mc->gtt_size = size_af;
623 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
625 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
626 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
627 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
631 * GPU helpers function.
634 * amdgpu_card_posted - check if the hw has already been initialized
636 * @adev: amdgpu_device pointer
638 * Check if the asic has been initialized (all asics).
639 * Used at driver startup.
640 * Returns true if initialized or false if not.
642 bool amdgpu_card_posted(struct amdgpu_device *adev)
646 /* then check MEM_SIZE, in case the crtcs are off */
647 reg = RREG32(mmCONFIG_MEMSIZE);
656 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
658 if (amdgpu_sriov_vf(adev))
661 if (amdgpu_passthrough(adev)) {
662 /* for FIJI: In whole GPU pass-through virtualization case
663 * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH)
664 * so amdgpu_card_posted return false and driver will incorrectly skip vPost.
665 * but if we force vPost do in pass-through case, the driver reload will hang.
666 * whether doing vPost depends on amdgpu_card_posted if smc version is above
669 if (adev->asic_type == CHIP_FIJI) {
672 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
673 /* force vPost if error occured */
677 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
678 if (fw_ver >= 0x00160e00)
679 return !amdgpu_card_posted(adev);
682 /* in bare-metal case, amdgpu_card_posted return false
683 * after system reboot/boot, and return true if driver
685 * we shouldn't do vPost after driver reload otherwise GPU
688 if (amdgpu_card_posted(adev))
692 /* we assume vPost is neede for all other cases */
697 * amdgpu_dummy_page_init - init dummy page used by the driver
699 * @adev: amdgpu_device pointer
701 * Allocate the dummy page used by the driver (all asics).
702 * This dummy page is used by the driver as a filler for gart entries
703 * when pages are taken out of the GART
704 * Returns 0 on sucess, -ENOMEM on failure.
706 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
708 if (adev->dummy_page.page)
710 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
711 if (adev->dummy_page.page == NULL)
713 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
714 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
715 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
716 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
717 __free_page(adev->dummy_page.page);
718 adev->dummy_page.page = NULL;
725 * amdgpu_dummy_page_fini - free dummy page used by the driver
727 * @adev: amdgpu_device pointer
729 * Frees the dummy page used by the driver (all asics).
731 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
733 if (adev->dummy_page.page == NULL)
735 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
736 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
737 __free_page(adev->dummy_page.page);
738 adev->dummy_page.page = NULL;
742 /* ATOM accessor methods */
744 * ATOM is an interpreted byte code stored in tables in the vbios. The
745 * driver registers callbacks to access registers and the interpreter
746 * in the driver parses the tables and executes then to program specific
747 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
748 * atombios.h, and atom.c
752 * cail_pll_read - read PLL register
754 * @info: atom card_info pointer
755 * @reg: PLL register offset
757 * Provides a PLL register accessor for the atom interpreter (r4xx+).
758 * Returns the value of the PLL register.
760 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
766 * cail_pll_write - write PLL register
768 * @info: atom card_info pointer
769 * @reg: PLL register offset
770 * @val: value to write to the pll register
772 * Provides a PLL register accessor for the atom interpreter (r4xx+).
774 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
780 * cail_mc_read - read MC (Memory Controller) register
782 * @info: atom card_info pointer
783 * @reg: MC register offset
785 * Provides an MC register accessor for the atom interpreter (r4xx+).
786 * Returns the value of the MC register.
788 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
794 * cail_mc_write - write MC (Memory Controller) register
796 * @info: atom card_info pointer
797 * @reg: MC register offset
798 * @val: value to write to the pll register
800 * Provides a MC register accessor for the atom interpreter (r4xx+).
802 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
808 * cail_reg_write - write MMIO register
810 * @info: atom card_info pointer
811 * @reg: MMIO register offset
812 * @val: value to write to the pll register
814 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
816 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
818 struct amdgpu_device *adev = info->dev->dev_private;
824 * cail_reg_read - read MMIO register
826 * @info: atom card_info pointer
827 * @reg: MMIO register offset
829 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
830 * Returns the value of the MMIO register.
832 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
834 struct amdgpu_device *adev = info->dev->dev_private;
842 * cail_ioreg_write - write IO register
844 * @info: atom card_info pointer
845 * @reg: IO register offset
846 * @val: value to write to the pll register
848 * Provides a IO register accessor for the atom interpreter (r4xx+).
850 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
852 struct amdgpu_device *adev = info->dev->dev_private;
858 * cail_ioreg_read - read IO register
860 * @info: atom card_info pointer
861 * @reg: IO register offset
863 * Provides an IO register accessor for the atom interpreter (r4xx+).
864 * Returns the value of the IO register.
866 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
868 struct amdgpu_device *adev = info->dev->dev_private;
876 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
878 * @adev: amdgpu_device pointer
880 * Frees the driver info and register access callbacks for the ATOM
881 * interpreter (r4xx+).
882 * Called at driver shutdown.
884 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
886 if (adev->mode_info.atom_context) {
887 kfree(adev->mode_info.atom_context->scratch);
888 kfree(adev->mode_info.atom_context->iio);
890 kfree(adev->mode_info.atom_context);
891 adev->mode_info.atom_context = NULL;
892 kfree(adev->mode_info.atom_card_info);
893 adev->mode_info.atom_card_info = NULL;
897 * amdgpu_atombios_init - init the driver info and callbacks for atombios
899 * @adev: amdgpu_device pointer
901 * Initializes the driver info and register access callbacks for the
902 * ATOM interpreter (r4xx+).
903 * Returns 0 on sucess, -ENOMEM on failure.
904 * Called at driver startup.
906 static int amdgpu_atombios_init(struct amdgpu_device *adev)
908 struct card_info *atom_card_info =
909 kzalloc(sizeof(struct card_info), GFP_KERNEL);
914 adev->mode_info.atom_card_info = atom_card_info;
915 atom_card_info->dev = adev->ddev;
916 atom_card_info->reg_read = cail_reg_read;
917 atom_card_info->reg_write = cail_reg_write;
918 /* needed for iio ops */
920 atom_card_info->ioreg_read = cail_ioreg_read;
921 atom_card_info->ioreg_write = cail_ioreg_write;
923 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
924 atom_card_info->ioreg_read = cail_reg_read;
925 atom_card_info->ioreg_write = cail_reg_write;
927 atom_card_info->mc_read = cail_mc_read;
928 atom_card_info->mc_write = cail_mc_write;
929 atom_card_info->pll_read = cail_pll_read;
930 atom_card_info->pll_write = cail_pll_write;
932 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
933 if (!adev->mode_info.atom_context) {
934 amdgpu_atombios_fini(adev);
938 mutex_init(&adev->mode_info.atom_context->mutex);
939 amdgpu_atombios_scratch_regs_init(adev);
940 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
944 /* if we get transitioned to only one device, take VGA back */
946 * amdgpu_vga_set_decode - enable/disable vga decode
948 * @cookie: amdgpu_device pointer
949 * @state: enable/disable vga decode
951 * Enable/disable vga decode (all asics).
952 * Returns VGA resource flags.
954 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
956 struct amdgpu_device *adev = cookie;
957 amdgpu_asic_set_vga_state(adev, state);
959 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
960 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
962 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
966 * amdgpu_check_pot_argument - check that argument is a power of two
968 * @arg: value to check
970 * Validates that a certain argument is a power of two (all asics).
971 * Returns true if argument is valid.
973 static bool amdgpu_check_pot_argument(int arg)
975 return (arg & (arg - 1)) == 0;
979 * amdgpu_check_arguments - validate module params
981 * @adev: amdgpu_device pointer
983 * Validates certain module parameters and updates
984 * the associated values used by the driver (all asics).
986 static void amdgpu_check_arguments(struct amdgpu_device *adev)
988 if (amdgpu_sched_jobs < 4) {
989 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
991 amdgpu_sched_jobs = 4;
992 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
993 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
995 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
998 if (amdgpu_gart_size != -1) {
999 /* gtt size must be greater or equal to 32M */
1000 if (amdgpu_gart_size < 32) {
1001 dev_warn(adev->dev, "gart size (%d) too small\n",
1003 amdgpu_gart_size = -1;
1007 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1008 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1013 if (amdgpu_vm_size < 1) {
1014 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1020 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1022 if (amdgpu_vm_size > 1024) {
1023 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1028 /* defines number of bits in page table versus page directory,
1029 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1030 * page table and the remaining bits are in the page directory */
1031 if (amdgpu_vm_block_size == -1) {
1033 /* Total bits covered by PD + PTs */
1034 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1036 /* Make sure the PD is 4K in size up to 8GB address space.
1037 Above that split equal between PD and PTs */
1038 if (amdgpu_vm_size <= 8)
1039 amdgpu_vm_block_size = bits - 9;
1041 amdgpu_vm_block_size = (bits + 3) / 2;
1043 } else if (amdgpu_vm_block_size < 9) {
1044 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1045 amdgpu_vm_block_size);
1046 amdgpu_vm_block_size = 9;
1049 if (amdgpu_vm_block_size > 24 ||
1050 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1051 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1052 amdgpu_vm_block_size);
1053 amdgpu_vm_block_size = 9;
1058 * amdgpu_switcheroo_set_state - set switcheroo state
1060 * @pdev: pci dev pointer
1061 * @state: vga_switcheroo state
1063 * Callback for the switcheroo driver. Suspends or resumes the
1064 * the asics before or after it is powered up using ACPI methods.
1066 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1068 struct drm_device *dev = pci_get_drvdata(pdev);
1070 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1073 if (state == VGA_SWITCHEROO_ON) {
1074 unsigned d3_delay = dev->pdev->d3_delay;
1076 printk(KERN_INFO "amdgpu: switched on\n");
1077 /* don't suspend or resume card normally */
1078 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1080 amdgpu_device_resume(dev, true, true);
1082 dev->pdev->d3_delay = d3_delay;
1084 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1085 drm_kms_helper_poll_enable(dev);
1087 printk(KERN_INFO "amdgpu: switched off\n");
1088 drm_kms_helper_poll_disable(dev);
1089 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1090 amdgpu_device_suspend(dev, true, true);
1091 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1096 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1098 * @pdev: pci dev pointer
1100 * Callback for the switcheroo driver. Check of the switcheroo
1101 * state can be changed.
1102 * Returns true if the state can be changed, false if not.
1104 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1106 struct drm_device *dev = pci_get_drvdata(pdev);
1109 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1110 * locking inversion with the driver load path. And the access here is
1111 * completely racy anyway. So don't bother with locking for now.
1113 return dev->open_count == 0;
1116 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1117 .set_gpu_state = amdgpu_switcheroo_set_state,
1119 .can_switch = amdgpu_switcheroo_can_switch,
1122 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1123 enum amd_ip_block_type block_type,
1124 enum amd_clockgating_state state)
1128 for (i = 0; i < adev->num_ip_blocks; i++) {
1129 if (!adev->ip_block_status[i].valid)
1131 if (adev->ip_blocks[i].type == block_type) {
1132 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1142 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1143 enum amd_ip_block_type block_type,
1144 enum amd_powergating_state state)
1148 for (i = 0; i < adev->num_ip_blocks; i++) {
1149 if (!adev->ip_block_status[i].valid)
1151 if (adev->ip_blocks[i].type == block_type) {
1152 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1162 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1163 enum amd_ip_block_type block_type)
1167 for (i = 0; i < adev->num_ip_blocks; i++) {
1168 if (!adev->ip_block_status[i].valid)
1170 if (adev->ip_blocks[i].type == block_type) {
1171 r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1181 bool amdgpu_is_idle(struct amdgpu_device *adev,
1182 enum amd_ip_block_type block_type)
1186 for (i = 0; i < adev->num_ip_blocks; i++) {
1187 if (!adev->ip_block_status[i].valid)
1189 if (adev->ip_blocks[i].type == block_type)
1190 return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1196 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1197 struct amdgpu_device *adev,
1198 enum amd_ip_block_type type)
1202 for (i = 0; i < adev->num_ip_blocks; i++)
1203 if (adev->ip_blocks[i].type == type)
1204 return &adev->ip_blocks[i];
1210 * amdgpu_ip_block_version_cmp
1212 * @adev: amdgpu_device pointer
1213 * @type: enum amd_ip_block_type
1214 * @major: major version
1215 * @minor: minor version
1217 * return 0 if equal or greater
1218 * return 1 if smaller or the ip_block doesn't exist
1220 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1221 enum amd_ip_block_type type,
1222 u32 major, u32 minor)
1224 const struct amdgpu_ip_block_version *ip_block;
1225 ip_block = amdgpu_get_ip_block(adev, type);
1227 if (ip_block && ((ip_block->major > major) ||
1228 ((ip_block->major == major) &&
1229 (ip_block->minor >= minor))))
1235 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1237 adev->enable_virtual_display = false;
1239 if (amdgpu_virtual_display) {
1240 struct drm_device *ddev = adev->ddev;
1241 const char *pci_address_name = pci_name(ddev->pdev);
1242 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1244 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1245 pciaddstr_tmp = pciaddstr;
1246 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1247 pciaddname = strsep(&pciaddname_tmp, ",");
1248 if (!strcmp(pci_address_name, pciaddname)) {
1252 adev->enable_virtual_display = true;
1255 res = kstrtol(pciaddname_tmp, 10,
1263 adev->mode_info.num_crtc = num_crtc;
1265 adev->mode_info.num_crtc = 1;
1271 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1272 amdgpu_virtual_display, pci_address_name,
1273 adev->enable_virtual_display, adev->mode_info.num_crtc);
1279 static int amdgpu_early_init(struct amdgpu_device *adev)
1283 amdgpu_device_enable_virtual_display(adev);
1285 switch (adev->asic_type) {
1289 case CHIP_POLARIS11:
1290 case CHIP_POLARIS10:
1293 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1294 adev->family = AMDGPU_FAMILY_CZ;
1296 adev->family = AMDGPU_FAMILY_VI;
1298 r = vi_set_ip_blocks(adev);
1302 #ifdef CONFIG_DRM_AMDGPU_SI
1308 adev->family = AMDGPU_FAMILY_SI;
1309 r = si_set_ip_blocks(adev);
1314 #ifdef CONFIG_DRM_AMDGPU_CIK
1320 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1321 adev->family = AMDGPU_FAMILY_CI;
1323 adev->family = AMDGPU_FAMILY_KV;
1325 r = cik_set_ip_blocks(adev);
1331 /* FIXME: not supported yet */
1335 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1336 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1337 if (adev->ip_block_status == NULL)
1340 if (adev->ip_blocks == NULL) {
1341 DRM_ERROR("No IP blocks found!\n");
1345 for (i = 0; i < adev->num_ip_blocks; i++) {
1346 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1347 DRM_ERROR("disabled ip block: %d\n", i);
1348 adev->ip_block_status[i].valid = false;
1350 if (adev->ip_blocks[i].funcs->early_init) {
1351 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1353 adev->ip_block_status[i].valid = false;
1355 DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1358 adev->ip_block_status[i].valid = true;
1361 adev->ip_block_status[i].valid = true;
1366 adev->cg_flags &= amdgpu_cg_mask;
1367 adev->pg_flags &= amdgpu_pg_mask;
1372 static int amdgpu_init(struct amdgpu_device *adev)
1376 for (i = 0; i < adev->num_ip_blocks; i++) {
1377 if (!adev->ip_block_status[i].valid)
1379 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1381 DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1384 adev->ip_block_status[i].sw = true;
1385 /* need to do gmc hw init early so we can allocate gpu mem */
1386 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1387 r = amdgpu_vram_scratch_init(adev);
1389 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1392 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1394 DRM_ERROR("hw_init %d failed %d\n", i, r);
1397 r = amdgpu_wb_init(adev);
1399 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1402 adev->ip_block_status[i].hw = true;
1406 for (i = 0; i < adev->num_ip_blocks; i++) {
1407 if (!adev->ip_block_status[i].sw)
1409 /* gmc hw init is done early */
1410 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1412 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1414 DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1417 adev->ip_block_status[i].hw = true;
1423 static int amdgpu_late_init(struct amdgpu_device *adev)
1427 for (i = 0; i < adev->num_ip_blocks; i++) {
1428 if (!adev->ip_block_status[i].valid)
1430 if (adev->ip_blocks[i].funcs->late_init) {
1431 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1433 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1436 adev->ip_block_status[i].late_initialized = true;
1438 /* skip CG for VCE/UVD, it's handled specially */
1439 if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
1440 adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
1441 /* enable clockgating to save power */
1442 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1445 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1446 adev->ip_blocks[i].funcs->name, r);
1455 static int amdgpu_fini(struct amdgpu_device *adev)
1459 /* need to disable SMC first */
1460 for (i = 0; i < adev->num_ip_blocks; i++) {
1461 if (!adev->ip_block_status[i].hw)
1463 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) {
1464 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1465 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1466 AMD_CG_STATE_UNGATE);
1468 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1469 adev->ip_blocks[i].funcs->name, r);
1472 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1473 /* XXX handle errors */
1475 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1476 adev->ip_blocks[i].funcs->name, r);
1478 adev->ip_block_status[i].hw = false;
1483 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1484 if (!adev->ip_block_status[i].hw)
1486 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1487 amdgpu_wb_fini(adev);
1488 amdgpu_vram_scratch_fini(adev);
1490 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1491 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1492 AMD_CG_STATE_UNGATE);
1494 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1497 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1498 /* XXX handle errors */
1500 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1502 adev->ip_block_status[i].hw = false;
1505 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1506 if (!adev->ip_block_status[i].sw)
1508 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1509 /* XXX handle errors */
1511 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1513 adev->ip_block_status[i].sw = false;
1514 adev->ip_block_status[i].valid = false;
1517 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1518 if (!adev->ip_block_status[i].late_initialized)
1520 if (adev->ip_blocks[i].funcs->late_fini)
1521 adev->ip_blocks[i].funcs->late_fini((void *)adev);
1522 adev->ip_block_status[i].late_initialized = false;
1528 static int amdgpu_suspend(struct amdgpu_device *adev)
1532 /* ungate SMC block first */
1533 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1534 AMD_CG_STATE_UNGATE);
1536 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1539 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1540 if (!adev->ip_block_status[i].valid)
1542 /* ungate blocks so that suspend can properly shut them down */
1543 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1544 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1545 AMD_CG_STATE_UNGATE);
1547 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1550 /* XXX handle errors */
1551 r = adev->ip_blocks[i].funcs->suspend(adev);
1552 /* XXX handle errors */
1554 DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1561 static int amdgpu_resume(struct amdgpu_device *adev)
1565 for (i = 0; i < adev->num_ip_blocks; i++) {
1566 if (!adev->ip_block_status[i].valid)
1568 r = adev->ip_blocks[i].funcs->resume(adev);
1570 DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1578 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1580 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1581 adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1585 * amdgpu_device_init - initialize the driver
1587 * @adev: amdgpu_device pointer
1588 * @pdev: drm dev pointer
1589 * @pdev: pci dev pointer
1590 * @flags: driver flags
1592 * Initializes the driver info and hw (all asics).
1593 * Returns 0 for success or an error on failure.
1594 * Called at driver startup.
1596 int amdgpu_device_init(struct amdgpu_device *adev,
1597 struct drm_device *ddev,
1598 struct pci_dev *pdev,
1602 bool runtime = false;
1605 adev->shutdown = false;
1606 adev->dev = &pdev->dev;
1609 adev->flags = flags;
1610 adev->asic_type = flags & AMD_ASIC_MASK;
1611 adev->is_atom_bios = false;
1612 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1613 adev->mc.gtt_size = 512 * 1024 * 1024;
1614 adev->accel_working = false;
1615 adev->num_rings = 0;
1616 adev->mman.buffer_funcs = NULL;
1617 adev->mman.buffer_funcs_ring = NULL;
1618 adev->vm_manager.vm_pte_funcs = NULL;
1619 adev->vm_manager.vm_pte_num_rings = 0;
1620 adev->gart.gart_funcs = NULL;
1621 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1623 adev->smc_rreg = &amdgpu_invalid_rreg;
1624 adev->smc_wreg = &amdgpu_invalid_wreg;
1625 adev->pcie_rreg = &amdgpu_invalid_rreg;
1626 adev->pcie_wreg = &amdgpu_invalid_wreg;
1627 adev->pciep_rreg = &amdgpu_invalid_rreg;
1628 adev->pciep_wreg = &amdgpu_invalid_wreg;
1629 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1630 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1631 adev->didt_rreg = &amdgpu_invalid_rreg;
1632 adev->didt_wreg = &amdgpu_invalid_wreg;
1633 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1634 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1635 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1636 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1639 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1640 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1641 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1643 /* mutex initialization are all done here so we
1644 * can recall function without having locking issues */
1645 mutex_init(&adev->vm_manager.lock);
1646 atomic_set(&adev->irq.ih.lock, 0);
1647 mutex_init(&adev->pm.mutex);
1648 mutex_init(&adev->gfx.gpu_clock_mutex);
1649 mutex_init(&adev->srbm_mutex);
1650 mutex_init(&adev->grbm_idx_mutex);
1651 mutex_init(&adev->mn_lock);
1652 hash_init(adev->mn_hash);
1654 amdgpu_check_arguments(adev);
1656 /* Registers mapping */
1657 /* TODO: block userspace mapping of io register */
1658 spin_lock_init(&adev->mmio_idx_lock);
1659 spin_lock_init(&adev->smc_idx_lock);
1660 spin_lock_init(&adev->pcie_idx_lock);
1661 spin_lock_init(&adev->uvd_ctx_idx_lock);
1662 spin_lock_init(&adev->didt_idx_lock);
1663 spin_lock_init(&adev->gc_cac_idx_lock);
1664 spin_lock_init(&adev->audio_endpt_idx_lock);
1665 spin_lock_init(&adev->mm_stats.lock);
1667 INIT_LIST_HEAD(&adev->shadow_list);
1668 mutex_init(&adev->shadow_list_lock);
1670 INIT_LIST_HEAD(&adev->gtt_list);
1671 spin_lock_init(&adev->gtt_list_lock);
1673 if (adev->asic_type >= CHIP_BONAIRE) {
1674 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1675 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1677 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1678 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1681 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1682 if (adev->rmmio == NULL) {
1685 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1686 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1688 if (adev->asic_type >= CHIP_BONAIRE)
1689 /* doorbell bar mapping */
1690 amdgpu_doorbell_init(adev);
1692 /* io port mapping */
1693 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1694 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1695 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1696 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1700 if (adev->rio_mem == NULL)
1701 DRM_ERROR("Unable to find PCI I/O BAR\n");
1703 /* early init functions */
1704 r = amdgpu_early_init(adev);
1708 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1709 /* this will fail for cards that aren't VGA class devices, just
1711 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1713 if (amdgpu_runtime_pm == 1)
1715 if (amdgpu_device_is_px(ddev))
1717 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1719 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1722 if (!amdgpu_get_bios(adev)) {
1726 /* Must be an ATOMBIOS */
1727 if (!adev->is_atom_bios) {
1728 dev_err(adev->dev, "Expecting atombios for GPU\n");
1732 r = amdgpu_atombios_init(adev);
1734 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1738 /* detect if we are with an SRIOV vbios */
1739 amdgpu_device_detect_sriov_bios(adev);
1741 /* Post card if necessary */
1742 if (amdgpu_vpost_needed(adev)) {
1744 dev_err(adev->dev, "no vBIOS found\n");
1748 DRM_INFO("GPU posting now...\n");
1749 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1751 dev_err(adev->dev, "gpu post error!\n");
1755 DRM_INFO("GPU post is not needed\n");
1758 /* Initialize clocks */
1759 r = amdgpu_atombios_get_clock_info(adev);
1761 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1764 /* init i2c buses */
1765 amdgpu_atombios_i2c_init(adev);
1768 r = amdgpu_fence_driver_init(adev);
1770 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1774 /* init the mode config */
1775 drm_mode_config_init(adev->ddev);
1777 r = amdgpu_init(adev);
1779 dev_err(adev->dev, "amdgpu_init failed\n");
1784 adev->accel_working = true;
1786 /* Initialize the buffer migration limit. */
1787 if (amdgpu_moverate >= 0)
1788 max_MBps = amdgpu_moverate;
1790 max_MBps = 8; /* Allow 8 MB/s. */
1791 /* Get a log2 for easy divisions. */
1792 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1794 amdgpu_fbdev_init(adev);
1796 r = amdgpu_ib_pool_init(adev);
1798 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1802 r = amdgpu_ib_ring_tests(adev);
1804 DRM_ERROR("ib ring test failed (%d).\n", r);
1806 r = amdgpu_gem_debugfs_init(adev);
1808 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1811 r = amdgpu_debugfs_regs_init(adev);
1813 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1816 r = amdgpu_debugfs_firmware_init(adev);
1818 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1822 if ((amdgpu_testing & 1)) {
1823 if (adev->accel_working)
1824 amdgpu_test_moves(adev);
1826 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1828 if ((amdgpu_testing & 2)) {
1829 if (adev->accel_working)
1830 amdgpu_test_syncing(adev);
1832 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1834 if (amdgpu_benchmarking) {
1835 if (adev->accel_working)
1836 amdgpu_benchmark(adev, amdgpu_benchmarking);
1838 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1841 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1842 * explicit gating rather than handling it automatically.
1844 r = amdgpu_late_init(adev);
1846 dev_err(adev->dev, "amdgpu_late_init failed\n");
1854 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1858 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1861 * amdgpu_device_fini - tear down the driver
1863 * @adev: amdgpu_device pointer
1865 * Tear down the driver info (all asics).
1866 * Called at driver shutdown.
1868 void amdgpu_device_fini(struct amdgpu_device *adev)
1872 DRM_INFO("amdgpu: finishing device.\n");
1873 adev->shutdown = true;
1874 drm_crtc_force_disable_all(adev->ddev);
1875 /* evict vram memory */
1876 amdgpu_bo_evict_vram(adev);
1877 amdgpu_ib_pool_fini(adev);
1878 amdgpu_fence_driver_fini(adev);
1879 amdgpu_fbdev_fini(adev);
1880 r = amdgpu_fini(adev);
1881 kfree(adev->ip_block_status);
1882 adev->ip_block_status = NULL;
1883 adev->accel_working = false;
1884 /* free i2c buses */
1885 amdgpu_i2c_fini(adev);
1886 amdgpu_atombios_fini(adev);
1889 vga_switcheroo_unregister_client(adev->pdev);
1890 if (adev->flags & AMD_IS_PX)
1891 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1892 vga_client_register(adev->pdev, NULL, NULL, NULL);
1894 pci_iounmap(adev->pdev, adev->rio_mem);
1895 adev->rio_mem = NULL;
1896 iounmap(adev->rmmio);
1898 if (adev->asic_type >= CHIP_BONAIRE)
1899 amdgpu_doorbell_fini(adev);
1900 amdgpu_debugfs_regs_cleanup(adev);
1901 amdgpu_debugfs_remove_files(adev);
1909 * amdgpu_device_suspend - initiate device suspend
1911 * @pdev: drm dev pointer
1912 * @state: suspend state
1914 * Puts the hw in the suspend state (all asics).
1915 * Returns 0 for success or an error on failure.
1916 * Called at driver suspend.
1918 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1920 struct amdgpu_device *adev;
1921 struct drm_crtc *crtc;
1922 struct drm_connector *connector;
1925 if (dev == NULL || dev->dev_private == NULL) {
1929 adev = dev->dev_private;
1931 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1934 drm_kms_helper_poll_disable(dev);
1936 /* turn off display hw */
1937 drm_modeset_lock_all(dev);
1938 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1939 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1941 drm_modeset_unlock_all(dev);
1943 /* unpin the front buffers and cursors */
1944 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1945 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1946 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1947 struct amdgpu_bo *robj;
1949 if (amdgpu_crtc->cursor_bo) {
1950 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1951 r = amdgpu_bo_reserve(aobj, false);
1953 amdgpu_bo_unpin(aobj);
1954 amdgpu_bo_unreserve(aobj);
1958 if (rfb == NULL || rfb->obj == NULL) {
1961 robj = gem_to_amdgpu_bo(rfb->obj);
1962 /* don't unpin kernel fb objects */
1963 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1964 r = amdgpu_bo_reserve(robj, false);
1966 amdgpu_bo_unpin(robj);
1967 amdgpu_bo_unreserve(robj);
1971 /* evict vram memory */
1972 amdgpu_bo_evict_vram(adev);
1974 amdgpu_fence_driver_suspend(adev);
1976 r = amdgpu_suspend(adev);
1978 /* evict remaining vram memory */
1979 amdgpu_bo_evict_vram(adev);
1981 pci_save_state(dev->pdev);
1983 /* Shut down the device */
1984 pci_disable_device(dev->pdev);
1985 pci_set_power_state(dev->pdev, PCI_D3hot);
1987 r = amdgpu_asic_reset(adev);
1989 DRM_ERROR("amdgpu asic reset failed\n");
1994 amdgpu_fbdev_set_suspend(adev, 1);
2001 * amdgpu_device_resume - initiate device resume
2003 * @pdev: drm dev pointer
2005 * Bring the hw back to operating state (all asics).
2006 * Returns 0 for success or an error on failure.
2007 * Called at driver resume.
2009 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2011 struct drm_connector *connector;
2012 struct amdgpu_device *adev = dev->dev_private;
2013 struct drm_crtc *crtc;
2016 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2023 pci_set_power_state(dev->pdev, PCI_D0);
2024 pci_restore_state(dev->pdev);
2025 r = pci_enable_device(dev->pdev);
2034 if (!amdgpu_card_posted(adev) || !resume) {
2035 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2037 DRM_ERROR("amdgpu asic init failed\n");
2040 r = amdgpu_resume(adev);
2042 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2044 amdgpu_fence_driver_resume(adev);
2047 r = amdgpu_ib_ring_tests(adev);
2049 DRM_ERROR("ib ring test failed (%d).\n", r);
2052 r = amdgpu_late_init(adev);
2057 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2058 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2060 if (amdgpu_crtc->cursor_bo) {
2061 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2062 r = amdgpu_bo_reserve(aobj, false);
2064 r = amdgpu_bo_pin(aobj,
2065 AMDGPU_GEM_DOMAIN_VRAM,
2066 &amdgpu_crtc->cursor_addr);
2068 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2069 amdgpu_bo_unreserve(aobj);
2074 /* blat the mode back in */
2076 drm_helper_resume_force_mode(dev);
2077 /* turn on display hw */
2078 drm_modeset_lock_all(dev);
2079 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2080 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2082 drm_modeset_unlock_all(dev);
2085 drm_kms_helper_poll_enable(dev);
2088 * Most of the connector probing functions try to acquire runtime pm
2089 * refs to ensure that the GPU is powered on when connector polling is
2090 * performed. Since we're calling this from a runtime PM callback,
2091 * trying to acquire rpm refs will cause us to deadlock.
2093 * Since we're guaranteed to be holding the rpm lock, it's safe to
2094 * temporarily disable the rpm helpers so this doesn't deadlock us.
2097 dev->dev->power.disable_depth++;
2099 drm_helper_hpd_irq_event(dev);
2101 dev->dev->power.disable_depth--;
2105 amdgpu_fbdev_set_suspend(adev, 0);
2112 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2115 bool asic_hang = false;
2117 for (i = 0; i < adev->num_ip_blocks; i++) {
2118 if (!adev->ip_block_status[i].valid)
2120 if (adev->ip_blocks[i].funcs->check_soft_reset)
2121 adev->ip_block_status[i].hang =
2122 adev->ip_blocks[i].funcs->check_soft_reset(adev);
2123 if (adev->ip_block_status[i].hang) {
2124 DRM_INFO("IP block:%d is hang!\n", i);
2131 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2135 for (i = 0; i < adev->num_ip_blocks; i++) {
2136 if (!adev->ip_block_status[i].valid)
2138 if (adev->ip_block_status[i].hang &&
2139 adev->ip_blocks[i].funcs->pre_soft_reset) {
2140 r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
2149 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2153 for (i = 0; i < adev->num_ip_blocks; i++) {
2154 if (!adev->ip_block_status[i].valid)
2156 if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
2157 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
2158 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
2159 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
2160 if (adev->ip_block_status[i].hang) {
2161 DRM_INFO("Some block need full reset!\n");
2169 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2173 for (i = 0; i < adev->num_ip_blocks; i++) {
2174 if (!adev->ip_block_status[i].valid)
2176 if (adev->ip_block_status[i].hang &&
2177 adev->ip_blocks[i].funcs->soft_reset) {
2178 r = adev->ip_blocks[i].funcs->soft_reset(adev);
2187 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2191 for (i = 0; i < adev->num_ip_blocks; i++) {
2192 if (!adev->ip_block_status[i].valid)
2194 if (adev->ip_block_status[i].hang &&
2195 adev->ip_blocks[i].funcs->post_soft_reset)
2196 r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
2204 bool amdgpu_need_backup(struct amdgpu_device *adev)
2206 if (adev->flags & AMD_IS_APU)
2209 return amdgpu_lockup_timeout > 0 ? true : false;
2212 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2213 struct amdgpu_ring *ring,
2214 struct amdgpu_bo *bo,
2215 struct fence **fence)
2223 r = amdgpu_bo_reserve(bo, false);
2226 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2227 /* if bo has been evicted, then no need to recover */
2228 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2229 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2232 DRM_ERROR("recover page table failed!\n");
2237 amdgpu_bo_unreserve(bo);
2242 * amdgpu_gpu_reset - reset the asic
2244 * @adev: amdgpu device pointer
2246 * Attempt the reset the GPU if it has hung (all asics).
2247 * Returns 0 for success or an error on failure.
2249 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2253 bool need_full_reset;
2255 if (!amdgpu_check_soft_reset(adev)) {
2256 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2260 atomic_inc(&adev->gpu_reset_counter);
2263 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2265 /* block scheduler */
2266 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2267 struct amdgpu_ring *ring = adev->rings[i];
2271 kthread_park(ring->sched.thread);
2272 amd_sched_hw_job_reset(&ring->sched);
2274 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2275 amdgpu_fence_driver_force_completion(adev);
2277 need_full_reset = amdgpu_need_full_reset(adev);
2279 if (!need_full_reset) {
2280 amdgpu_pre_soft_reset(adev);
2281 r = amdgpu_soft_reset(adev);
2282 amdgpu_post_soft_reset(adev);
2283 if (r || amdgpu_check_soft_reset(adev)) {
2284 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2285 need_full_reset = true;
2289 if (need_full_reset) {
2291 amdgpu_atombios_scratch_regs_save(adev);
2292 r = amdgpu_suspend(adev);
2295 /* Disable fb access */
2296 if (adev->mode_info.num_crtc) {
2297 struct amdgpu_mode_mc_save save;
2298 amdgpu_display_stop_mc_access(adev, &save);
2299 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2302 r = amdgpu_asic_reset(adev);
2304 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2307 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2308 r = amdgpu_resume(adev);
2310 /* restore scratch */
2311 amdgpu_atombios_scratch_regs_restore(adev);
2314 amdgpu_irq_gpu_reset_resume_helper(adev);
2315 if (need_full_reset && amdgpu_need_backup(adev)) {
2316 r = amdgpu_ttm_recover_gart(adev);
2318 DRM_ERROR("gart recovery failed!!!\n");
2320 r = amdgpu_ib_ring_tests(adev);
2322 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2323 r = amdgpu_suspend(adev);
2324 need_full_reset = true;
2328 * recovery vm page tables, since we cannot depend on VRAM is
2329 * consistent after gpu full reset.
2331 if (need_full_reset && amdgpu_need_backup(adev)) {
2332 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2333 struct amdgpu_bo *bo, *tmp;
2334 struct fence *fence = NULL, *next = NULL;
2336 DRM_INFO("recover vram bo from shadow\n");
2337 mutex_lock(&adev->shadow_list_lock);
2338 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2339 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2341 r = fence_wait(fence, false);
2343 WARN(r, "recovery from shadow isn't comleted\n");
2351 mutex_unlock(&adev->shadow_list_lock);
2353 r = fence_wait(fence, false);
2355 WARN(r, "recovery from shadow isn't comleted\n");
2359 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2360 struct amdgpu_ring *ring = adev->rings[i];
2364 amd_sched_job_recovery(&ring->sched);
2365 kthread_unpark(ring->sched.thread);
2368 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2369 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2370 if (adev->rings[i]) {
2371 kthread_unpark(adev->rings[i]->sched.thread);
2376 drm_helper_resume_force_mode(adev->ddev);
2378 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2380 /* bad news, how to tell it to userspace ? */
2381 dev_info(adev->dev, "GPU reset failed\n");
2387 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2392 if (amdgpu_pcie_gen_cap)
2393 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2395 if (amdgpu_pcie_lane_cap)
2396 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2398 /* covers APUs as well */
2399 if (pci_is_root_bus(adev->pdev->bus)) {
2400 if (adev->pm.pcie_gen_mask == 0)
2401 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2402 if (adev->pm.pcie_mlw_mask == 0)
2403 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2407 if (adev->pm.pcie_gen_mask == 0) {
2408 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2410 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2411 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2412 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2414 if (mask & DRM_PCIE_SPEED_25)
2415 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2416 if (mask & DRM_PCIE_SPEED_50)
2417 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2418 if (mask & DRM_PCIE_SPEED_80)
2419 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2421 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2424 if (adev->pm.pcie_mlw_mask == 0) {
2425 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2429 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2430 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2431 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2432 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2433 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2434 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2435 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2438 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2439 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2440 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2441 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2442 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2443 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2446 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2447 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2448 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2449 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2450 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2453 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2454 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2455 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2456 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2459 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2460 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2461 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2464 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2465 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2468 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2474 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2482 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2483 const struct drm_info_list *files,
2488 for (i = 0; i < adev->debugfs_count; i++) {
2489 if (adev->debugfs[i].files == files) {
2490 /* Already registered */
2495 i = adev->debugfs_count + 1;
2496 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2497 DRM_ERROR("Reached maximum number of debugfs components.\n");
2498 DRM_ERROR("Report so we increase "
2499 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2502 adev->debugfs[adev->debugfs_count].files = files;
2503 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2504 adev->debugfs_count = i;
2505 #if defined(CONFIG_DEBUG_FS)
2506 drm_debugfs_create_files(files, nfiles,
2507 adev->ddev->control->debugfs_root,
2508 adev->ddev->control);
2509 drm_debugfs_create_files(files, nfiles,
2510 adev->ddev->primary->debugfs_root,
2511 adev->ddev->primary);
2516 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2518 #if defined(CONFIG_DEBUG_FS)
2521 for (i = 0; i < adev->debugfs_count; i++) {
2522 drm_debugfs_remove_files(adev->debugfs[i].files,
2523 adev->debugfs[i].num_files,
2524 adev->ddev->control);
2525 drm_debugfs_remove_files(adev->debugfs[i].files,
2526 adev->debugfs[i].num_files,
2527 adev->ddev->primary);
2532 #if defined(CONFIG_DEBUG_FS)
2534 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2535 size_t size, loff_t *pos)
2537 struct amdgpu_device *adev = f->f_inode->i_private;
2540 bool pm_pg_lock, use_bank;
2541 unsigned instance_bank, sh_bank, se_bank;
2543 if (size & 0x3 || *pos & 0x3)
2546 /* are we reading registers for which a PG lock is necessary? */
2547 pm_pg_lock = (*pos >> 23) & 1;
2549 if (*pos & (1ULL << 62)) {
2550 se_bank = (*pos >> 24) & 0x3FF;
2551 sh_bank = (*pos >> 34) & 0x3FF;
2552 instance_bank = (*pos >> 44) & 0x3FF;
2561 if (sh_bank >= adev->gfx.config.max_sh_per_se ||
2562 se_bank >= adev->gfx.config.max_shader_engines)
2564 mutex_lock(&adev->grbm_idx_mutex);
2565 amdgpu_gfx_select_se_sh(adev, se_bank,
2566 sh_bank, instance_bank);
2570 mutex_lock(&adev->pm.mutex);
2575 if (*pos > adev->rmmio_size)
2578 value = RREG32(*pos >> 2);
2579 r = put_user(value, (uint32_t *)buf);
2593 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2594 mutex_unlock(&adev->grbm_idx_mutex);
2598 mutex_unlock(&adev->pm.mutex);
2603 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2604 size_t size, loff_t *pos)
2606 struct amdgpu_device *adev = f->f_inode->i_private;
2610 if (size & 0x3 || *pos & 0x3)
2616 if (*pos > adev->rmmio_size)
2619 r = get_user(value, (uint32_t *)buf);
2623 WREG32(*pos >> 2, value);
2634 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2635 size_t size, loff_t *pos)
2637 struct amdgpu_device *adev = f->f_inode->i_private;
2641 if (size & 0x3 || *pos & 0x3)
2647 value = RREG32_PCIE(*pos >> 2);
2648 r = put_user(value, (uint32_t *)buf);
2661 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2662 size_t size, loff_t *pos)
2664 struct amdgpu_device *adev = f->f_inode->i_private;
2668 if (size & 0x3 || *pos & 0x3)
2674 r = get_user(value, (uint32_t *)buf);
2678 WREG32_PCIE(*pos >> 2, value);
2689 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2690 size_t size, loff_t *pos)
2692 struct amdgpu_device *adev = f->f_inode->i_private;
2696 if (size & 0x3 || *pos & 0x3)
2702 value = RREG32_DIDT(*pos >> 2);
2703 r = put_user(value, (uint32_t *)buf);
2716 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2717 size_t size, loff_t *pos)
2719 struct amdgpu_device *adev = f->f_inode->i_private;
2723 if (size & 0x3 || *pos & 0x3)
2729 r = get_user(value, (uint32_t *)buf);
2733 WREG32_DIDT(*pos >> 2, value);
2744 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2745 size_t size, loff_t *pos)
2747 struct amdgpu_device *adev = f->f_inode->i_private;
2751 if (size & 0x3 || *pos & 0x3)
2757 value = RREG32_SMC(*pos);
2758 r = put_user(value, (uint32_t *)buf);
2771 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2772 size_t size, loff_t *pos)
2774 struct amdgpu_device *adev = f->f_inode->i_private;
2778 if (size & 0x3 || *pos & 0x3)
2784 r = get_user(value, (uint32_t *)buf);
2788 WREG32_SMC(*pos, value);
2799 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2800 size_t size, loff_t *pos)
2802 struct amdgpu_device *adev = f->f_inode->i_private;
2805 uint32_t *config, no_regs = 0;
2807 if (size & 0x3 || *pos & 0x3)
2810 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
2814 /* version, increment each time something is added */
2815 config[no_regs++] = 2;
2816 config[no_regs++] = adev->gfx.config.max_shader_engines;
2817 config[no_regs++] = adev->gfx.config.max_tile_pipes;
2818 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2819 config[no_regs++] = adev->gfx.config.max_sh_per_se;
2820 config[no_regs++] = adev->gfx.config.max_backends_per_se;
2821 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2822 config[no_regs++] = adev->gfx.config.max_gprs;
2823 config[no_regs++] = adev->gfx.config.max_gs_threads;
2824 config[no_regs++] = adev->gfx.config.max_hw_contexts;
2825 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2826 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2827 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2828 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2829 config[no_regs++] = adev->gfx.config.num_tile_pipes;
2830 config[no_regs++] = adev->gfx.config.backend_enable_mask;
2831 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2832 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2833 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2834 config[no_regs++] = adev->gfx.config.num_gpus;
2835 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2836 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2837 config[no_regs++] = adev->gfx.config.gb_addr_config;
2838 config[no_regs++] = adev->gfx.config.num_rbs;
2841 config[no_regs++] = adev->rev_id;
2842 config[no_regs++] = adev->pg_flags;
2843 config[no_regs++] = adev->cg_flags;
2846 config[no_regs++] = adev->family;
2847 config[no_regs++] = adev->external_rev_id;
2849 while (size && (*pos < no_regs * 4)) {
2852 value = config[*pos >> 2];
2853 r = put_user(value, (uint32_t *)buf);
2869 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
2870 size_t size, loff_t *pos)
2872 struct amdgpu_device *adev = f->f_inode->i_private;
2876 if (size != 4 || *pos & 0x3)
2879 /* convert offset to sensor number */
2882 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
2883 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
2888 r = put_user(value, (int32_t *)buf);
2893 static const struct file_operations amdgpu_debugfs_regs_fops = {
2894 .owner = THIS_MODULE,
2895 .read = amdgpu_debugfs_regs_read,
2896 .write = amdgpu_debugfs_regs_write,
2897 .llseek = default_llseek
2899 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2900 .owner = THIS_MODULE,
2901 .read = amdgpu_debugfs_regs_didt_read,
2902 .write = amdgpu_debugfs_regs_didt_write,
2903 .llseek = default_llseek
2905 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2906 .owner = THIS_MODULE,
2907 .read = amdgpu_debugfs_regs_pcie_read,
2908 .write = amdgpu_debugfs_regs_pcie_write,
2909 .llseek = default_llseek
2911 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2912 .owner = THIS_MODULE,
2913 .read = amdgpu_debugfs_regs_smc_read,
2914 .write = amdgpu_debugfs_regs_smc_write,
2915 .llseek = default_llseek
2918 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
2919 .owner = THIS_MODULE,
2920 .read = amdgpu_debugfs_gca_config_read,
2921 .llseek = default_llseek
2924 static const struct file_operations amdgpu_debugfs_sensors_fops = {
2925 .owner = THIS_MODULE,
2926 .read = amdgpu_debugfs_sensor_read,
2927 .llseek = default_llseek
2930 static const struct file_operations *debugfs_regs[] = {
2931 &amdgpu_debugfs_regs_fops,
2932 &amdgpu_debugfs_regs_didt_fops,
2933 &amdgpu_debugfs_regs_pcie_fops,
2934 &amdgpu_debugfs_regs_smc_fops,
2935 &amdgpu_debugfs_gca_config_fops,
2936 &amdgpu_debugfs_sensors_fops,
2939 static const char *debugfs_regs_names[] = {
2944 "amdgpu_gca_config",
2948 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2950 struct drm_minor *minor = adev->ddev->primary;
2951 struct dentry *ent, *root = minor->debugfs_root;
2954 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2955 ent = debugfs_create_file(debugfs_regs_names[i],
2956 S_IFREG | S_IRUGO, root,
2957 adev, debugfs_regs[i]);
2959 for (j = 0; j < i; j++) {
2960 debugfs_remove(adev->debugfs_regs[i]);
2961 adev->debugfs_regs[i] = NULL;
2963 return PTR_ERR(ent);
2967 i_size_write(ent->d_inode, adev->rmmio_size);
2968 adev->debugfs_regs[i] = ent;
2974 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2978 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2979 if (adev->debugfs_regs[i]) {
2980 debugfs_remove(adev->debugfs_regs[i]);
2981 adev->debugfs_regs[i] = NULL;
2986 int amdgpu_debugfs_init(struct drm_minor *minor)
2991 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2995 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2999 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }