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drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag v3
[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_device.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
41 #include "atom.h"
42 #include "amdgpu_atombios.h"
43 #include "amd_pcie.h"
44 #ifdef CONFIG_DRM_AMDGPU_SI
45 #include "si.h"
46 #endif
47 #ifdef CONFIG_DRM_AMDGPU_CIK
48 #include "cik.h"
49 #endif
50 #include "vi.h"
51 #include "bif/bif_4_1_d.h"
52 #include <linux/pci.h>
53 #include <linux/firmware.h>
54
55 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
57
58 static const char *amdgpu_asic_name[] = {
59         "TAHITI",
60         "PITCAIRN",
61         "VERDE",
62         "OLAND",
63         "HAINAN",
64         "BONAIRE",
65         "KAVERI",
66         "KABINI",
67         "HAWAII",
68         "MULLINS",
69         "TOPAZ",
70         "TONGA",
71         "FIJI",
72         "CARRIZO",
73         "STONEY",
74         "POLARIS10",
75         "POLARIS11",
76         "LAST",
77 };
78
79 bool amdgpu_device_is_px(struct drm_device *dev)
80 {
81         struct amdgpu_device *adev = dev->dev_private;
82
83         if (adev->flags & AMD_IS_PX)
84                 return true;
85         return false;
86 }
87
88 /*
89  * MMIO register access helper functions.
90  */
91 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
92                         bool always_indirect)
93 {
94         uint32_t ret;
95
96         if ((reg * 4) < adev->rmmio_size && !always_indirect)
97                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
98         else {
99                 unsigned long flags;
100
101                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
102                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
103                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
104                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
105         }
106         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
107         return ret;
108 }
109
110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
111                     bool always_indirect)
112 {
113         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
114
115         if ((reg * 4) < adev->rmmio_size && !always_indirect)
116                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
117         else {
118                 unsigned long flags;
119
120                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
121                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
122                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
123                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
124         }
125 }
126
127 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
128 {
129         if ((reg * 4) < adev->rio_mem_size)
130                 return ioread32(adev->rio_mem + (reg * 4));
131         else {
132                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
133                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
134         }
135 }
136
137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
138 {
139
140         if ((reg * 4) < adev->rio_mem_size)
141                 iowrite32(v, adev->rio_mem + (reg * 4));
142         else {
143                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
144                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
145         }
146 }
147
148 /**
149  * amdgpu_mm_rdoorbell - read a doorbell dword
150  *
151  * @adev: amdgpu_device pointer
152  * @index: doorbell index
153  *
154  * Returns the value in the doorbell aperture at the
155  * requested doorbell index (CIK).
156  */
157 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
158 {
159         if (index < adev->doorbell.num_doorbells) {
160                 return readl(adev->doorbell.ptr + index);
161         } else {
162                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
163                 return 0;
164         }
165 }
166
167 /**
168  * amdgpu_mm_wdoorbell - write a doorbell dword
169  *
170  * @adev: amdgpu_device pointer
171  * @index: doorbell index
172  * @v: value to write
173  *
174  * Writes @v to the doorbell aperture at the
175  * requested doorbell index (CIK).
176  */
177 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
178 {
179         if (index < adev->doorbell.num_doorbells) {
180                 writel(v, adev->doorbell.ptr + index);
181         } else {
182                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
183         }
184 }
185
186 /**
187  * amdgpu_invalid_rreg - dummy reg read function
188  *
189  * @adev: amdgpu device pointer
190  * @reg: offset of register
191  *
192  * Dummy register read function.  Used for register blocks
193  * that certain asics don't have (all asics).
194  * Returns the value in the register.
195  */
196 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
197 {
198         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
199         BUG();
200         return 0;
201 }
202
203 /**
204  * amdgpu_invalid_wreg - dummy reg write function
205  *
206  * @adev: amdgpu device pointer
207  * @reg: offset of register
208  * @v: value to write to the register
209  *
210  * Dummy register read function.  Used for register blocks
211  * that certain asics don't have (all asics).
212  */
213 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
214 {
215         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
216                   reg, v);
217         BUG();
218 }
219
220 /**
221  * amdgpu_block_invalid_rreg - dummy reg read function
222  *
223  * @adev: amdgpu device pointer
224  * @block: offset of instance
225  * @reg: offset of register
226  *
227  * Dummy register read function.  Used for register blocks
228  * that certain asics don't have (all asics).
229  * Returns the value in the register.
230  */
231 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
232                                           uint32_t block, uint32_t reg)
233 {
234         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
235                   reg, block);
236         BUG();
237         return 0;
238 }
239
240 /**
241  * amdgpu_block_invalid_wreg - dummy reg write function
242  *
243  * @adev: amdgpu device pointer
244  * @block: offset of instance
245  * @reg: offset of register
246  * @v: value to write to the register
247  *
248  * Dummy register read function.  Used for register blocks
249  * that certain asics don't have (all asics).
250  */
251 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
252                                       uint32_t block,
253                                       uint32_t reg, uint32_t v)
254 {
255         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
256                   reg, block, v);
257         BUG();
258 }
259
260 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
261 {
262         int r;
263
264         if (adev->vram_scratch.robj == NULL) {
265                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
266                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
267                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
268                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
269                                      NULL, NULL, &adev->vram_scratch.robj);
270                 if (r) {
271                         return r;
272                 }
273         }
274
275         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
276         if (unlikely(r != 0))
277                 return r;
278         r = amdgpu_bo_pin(adev->vram_scratch.robj,
279                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
280         if (r) {
281                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
282                 return r;
283         }
284         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
285                                 (void **)&adev->vram_scratch.ptr);
286         if (r)
287                 amdgpu_bo_unpin(adev->vram_scratch.robj);
288         amdgpu_bo_unreserve(adev->vram_scratch.robj);
289
290         return r;
291 }
292
293 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
294 {
295         int r;
296
297         if (adev->vram_scratch.robj == NULL) {
298                 return;
299         }
300         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
301         if (likely(r == 0)) {
302                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
303                 amdgpu_bo_unpin(adev->vram_scratch.robj);
304                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
305         }
306         amdgpu_bo_unref(&adev->vram_scratch.robj);
307 }
308
309 /**
310  * amdgpu_program_register_sequence - program an array of registers.
311  *
312  * @adev: amdgpu_device pointer
313  * @registers: pointer to the register array
314  * @array_size: size of the register array
315  *
316  * Programs an array or registers with and and or masks.
317  * This is a helper for setting golden registers.
318  */
319 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
320                                       const u32 *registers,
321                                       const u32 array_size)
322 {
323         u32 tmp, reg, and_mask, or_mask;
324         int i;
325
326         if (array_size % 3)
327                 return;
328
329         for (i = 0; i < array_size; i +=3) {
330                 reg = registers[i + 0];
331                 and_mask = registers[i + 1];
332                 or_mask = registers[i + 2];
333
334                 if (and_mask == 0xffffffff) {
335                         tmp = or_mask;
336                 } else {
337                         tmp = RREG32(reg);
338                         tmp &= ~and_mask;
339                         tmp |= or_mask;
340                 }
341                 WREG32(reg, tmp);
342         }
343 }
344
345 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
346 {
347         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
348 }
349
350 /*
351  * GPU doorbell aperture helpers function.
352  */
353 /**
354  * amdgpu_doorbell_init - Init doorbell driver information.
355  *
356  * @adev: amdgpu_device pointer
357  *
358  * Init doorbell driver information (CIK)
359  * Returns 0 on success, error on failure.
360  */
361 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
362 {
363         /* doorbell bar mapping */
364         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
365         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
366
367         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
368                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
369         if (adev->doorbell.num_doorbells == 0)
370                 return -EINVAL;
371
372         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
373         if (adev->doorbell.ptr == NULL) {
374                 return -ENOMEM;
375         }
376         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
377         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
378
379         return 0;
380 }
381
382 /**
383  * amdgpu_doorbell_fini - Tear down doorbell driver information.
384  *
385  * @adev: amdgpu_device pointer
386  *
387  * Tear down doorbell driver information (CIK)
388  */
389 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
390 {
391         iounmap(adev->doorbell.ptr);
392         adev->doorbell.ptr = NULL;
393 }
394
395 /**
396  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
397  *                                setup amdkfd
398  *
399  * @adev: amdgpu_device pointer
400  * @aperture_base: output returning doorbell aperture base physical address
401  * @aperture_size: output returning doorbell aperture size in bytes
402  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
403  *
404  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
405  * takes doorbells required for its own rings and reports the setup to amdkfd.
406  * amdgpu reserved doorbells are at the start of the doorbell aperture.
407  */
408 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
409                                 phys_addr_t *aperture_base,
410                                 size_t *aperture_size,
411                                 size_t *start_offset)
412 {
413         /*
414          * The first num_doorbells are used by amdgpu.
415          * amdkfd takes whatever's left in the aperture.
416          */
417         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
418                 *aperture_base = adev->doorbell.base;
419                 *aperture_size = adev->doorbell.size;
420                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
421         } else {
422                 *aperture_base = 0;
423                 *aperture_size = 0;
424                 *start_offset = 0;
425         }
426 }
427
428 /*
429  * amdgpu_wb_*()
430  * Writeback is the the method by which the the GPU updates special pages
431  * in memory with the status of certain GPU events (fences, ring pointers,
432  * etc.).
433  */
434
435 /**
436  * amdgpu_wb_fini - Disable Writeback and free memory
437  *
438  * @adev: amdgpu_device pointer
439  *
440  * Disables Writeback and frees the Writeback memory (all asics).
441  * Used at driver shutdown.
442  */
443 static void amdgpu_wb_fini(struct amdgpu_device *adev)
444 {
445         if (adev->wb.wb_obj) {
446                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
447                         amdgpu_bo_kunmap(adev->wb.wb_obj);
448                         amdgpu_bo_unpin(adev->wb.wb_obj);
449                         amdgpu_bo_unreserve(adev->wb.wb_obj);
450                 }
451                 amdgpu_bo_unref(&adev->wb.wb_obj);
452                 adev->wb.wb = NULL;
453                 adev->wb.wb_obj = NULL;
454         }
455 }
456
457 /**
458  * amdgpu_wb_init- Init Writeback driver info and allocate memory
459  *
460  * @adev: amdgpu_device pointer
461  *
462  * Disables Writeback and frees the Writeback memory (all asics).
463  * Used at driver startup.
464  * Returns 0 on success or an -error on failure.
465  */
466 static int amdgpu_wb_init(struct amdgpu_device *adev)
467 {
468         int r;
469
470         if (adev->wb.wb_obj == NULL) {
471                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
472                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
473                                      &adev->wb.wb_obj);
474                 if (r) {
475                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
476                         return r;
477                 }
478                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
479                 if (unlikely(r != 0)) {
480                         amdgpu_wb_fini(adev);
481                         return r;
482                 }
483                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
484                                 &adev->wb.gpu_addr);
485                 if (r) {
486                         amdgpu_bo_unreserve(adev->wb.wb_obj);
487                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
488                         amdgpu_wb_fini(adev);
489                         return r;
490                 }
491                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
492                 amdgpu_bo_unreserve(adev->wb.wb_obj);
493                 if (r) {
494                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
495                         amdgpu_wb_fini(adev);
496                         return r;
497                 }
498
499                 adev->wb.num_wb = AMDGPU_MAX_WB;
500                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
501
502                 /* clear wb memory */
503                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
504         }
505
506         return 0;
507 }
508
509 /**
510  * amdgpu_wb_get - Allocate a wb entry
511  *
512  * @adev: amdgpu_device pointer
513  * @wb: wb index
514  *
515  * Allocate a wb slot for use by the driver (all asics).
516  * Returns 0 on success or -EINVAL on failure.
517  */
518 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
519 {
520         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
521         if (offset < adev->wb.num_wb) {
522                 __set_bit(offset, adev->wb.used);
523                 *wb = offset;
524                 return 0;
525         } else {
526                 return -EINVAL;
527         }
528 }
529
530 /**
531  * amdgpu_wb_free - Free a wb entry
532  *
533  * @adev: amdgpu_device pointer
534  * @wb: wb index
535  *
536  * Free a wb slot allocated for use by the driver (all asics)
537  */
538 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
539 {
540         if (wb < adev->wb.num_wb)
541                 __clear_bit(wb, adev->wb.used);
542 }
543
544 /**
545  * amdgpu_vram_location - try to find VRAM location
546  * @adev: amdgpu device structure holding all necessary informations
547  * @mc: memory controller structure holding memory informations
548  * @base: base address at which to put VRAM
549  *
550  * Function will place try to place VRAM at base address provided
551  * as parameter (which is so far either PCI aperture address or
552  * for IGP TOM base address).
553  *
554  * If there is not enough space to fit the unvisible VRAM in the 32bits
555  * address space then we limit the VRAM size to the aperture.
556  *
557  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
558  * this shouldn't be a problem as we are using the PCI aperture as a reference.
559  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
560  * not IGP.
561  *
562  * Note: we use mc_vram_size as on some board we need to program the mc to
563  * cover the whole aperture even if VRAM size is inferior to aperture size
564  * Novell bug 204882 + along with lots of ubuntu ones
565  *
566  * Note: when limiting vram it's safe to overwritte real_vram_size because
567  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
568  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
569  * ones)
570  *
571  * Note: IGP TOM addr should be the same as the aperture addr, we don't
572  * explicitly check for that thought.
573  *
574  * FIXME: when reducing VRAM size align new size on power of 2.
575  */
576 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
577 {
578         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
579
580         mc->vram_start = base;
581         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
582                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
583                 mc->real_vram_size = mc->aper_size;
584                 mc->mc_vram_size = mc->aper_size;
585         }
586         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
587         if (limit && limit < mc->real_vram_size)
588                 mc->real_vram_size = limit;
589         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
590                         mc->mc_vram_size >> 20, mc->vram_start,
591                         mc->vram_end, mc->real_vram_size >> 20);
592 }
593
594 /**
595  * amdgpu_gtt_location - try to find GTT location
596  * @adev: amdgpu device structure holding all necessary informations
597  * @mc: memory controller structure holding memory informations
598  *
599  * Function will place try to place GTT before or after VRAM.
600  *
601  * If GTT size is bigger than space left then we ajust GTT size.
602  * Thus function will never fails.
603  *
604  * FIXME: when reducing GTT size align new size on power of 2.
605  */
606 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
607 {
608         u64 size_af, size_bf;
609
610         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
611         size_bf = mc->vram_start & ~mc->gtt_base_align;
612         if (size_bf > size_af) {
613                 if (mc->gtt_size > size_bf) {
614                         dev_warn(adev->dev, "limiting GTT\n");
615                         mc->gtt_size = size_bf;
616                 }
617                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
618         } else {
619                 if (mc->gtt_size > size_af) {
620                         dev_warn(adev->dev, "limiting GTT\n");
621                         mc->gtt_size = size_af;
622                 }
623                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
624         }
625         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
626         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
627                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
628 }
629
630 /*
631  * GPU helpers function.
632  */
633 /**
634  * amdgpu_card_posted - check if the hw has already been initialized
635  *
636  * @adev: amdgpu_device pointer
637  *
638  * Check if the asic has been initialized (all asics).
639  * Used at driver startup.
640  * Returns true if initialized or false if not.
641  */
642 bool amdgpu_card_posted(struct amdgpu_device *adev)
643 {
644         uint32_t reg;
645
646         /* then check MEM_SIZE, in case the crtcs are off */
647         reg = RREG32(mmCONFIG_MEMSIZE);
648
649         if (reg)
650                 return true;
651
652         return false;
653
654 }
655
656 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
657 {
658         if (amdgpu_sriov_vf(adev))
659                 return false;
660
661         if (amdgpu_passthrough(adev)) {
662                 /* for FIJI: In whole GPU pass-through virtualization case
663                  * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH)
664                  * so amdgpu_card_posted return false and driver will incorrectly skip vPost.
665                  * but if we force vPost do in pass-through case, the driver reload will hang.
666                  * whether doing vPost depends on amdgpu_card_posted if smc version is above
667                  * 00160e00 for FIJI.
668                  */
669                 if (adev->asic_type == CHIP_FIJI) {
670                         int err;
671                         uint32_t fw_ver;
672                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
673                         /* force vPost if error occured */
674                         if (err)
675                                 return true;
676
677                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
678                         if (fw_ver >= 0x00160e00)
679                                 return !amdgpu_card_posted(adev);
680                 }
681         } else {
682                 /* in bare-metal case, amdgpu_card_posted return false
683                  * after system reboot/boot, and return true if driver
684                  * reloaded.
685                  * we shouldn't do vPost after driver reload otherwise GPU
686                  * could hang.
687                  */
688                 if (amdgpu_card_posted(adev))
689                         return false;
690         }
691
692         /* we assume vPost is neede for all other cases */
693         return true;
694 }
695
696 /**
697  * amdgpu_dummy_page_init - init dummy page used by the driver
698  *
699  * @adev: amdgpu_device pointer
700  *
701  * Allocate the dummy page used by the driver (all asics).
702  * This dummy page is used by the driver as a filler for gart entries
703  * when pages are taken out of the GART
704  * Returns 0 on sucess, -ENOMEM on failure.
705  */
706 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
707 {
708         if (adev->dummy_page.page)
709                 return 0;
710         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
711         if (adev->dummy_page.page == NULL)
712                 return -ENOMEM;
713         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
714                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
715         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
716                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
717                 __free_page(adev->dummy_page.page);
718                 adev->dummy_page.page = NULL;
719                 return -ENOMEM;
720         }
721         return 0;
722 }
723
724 /**
725  * amdgpu_dummy_page_fini - free dummy page used by the driver
726  *
727  * @adev: amdgpu_device pointer
728  *
729  * Frees the dummy page used by the driver (all asics).
730  */
731 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
732 {
733         if (adev->dummy_page.page == NULL)
734                 return;
735         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
736                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
737         __free_page(adev->dummy_page.page);
738         adev->dummy_page.page = NULL;
739 }
740
741
742 /* ATOM accessor methods */
743 /*
744  * ATOM is an interpreted byte code stored in tables in the vbios.  The
745  * driver registers callbacks to access registers and the interpreter
746  * in the driver parses the tables and executes then to program specific
747  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
748  * atombios.h, and atom.c
749  */
750
751 /**
752  * cail_pll_read - read PLL register
753  *
754  * @info: atom card_info pointer
755  * @reg: PLL register offset
756  *
757  * Provides a PLL register accessor for the atom interpreter (r4xx+).
758  * Returns the value of the PLL register.
759  */
760 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
761 {
762         return 0;
763 }
764
765 /**
766  * cail_pll_write - write PLL register
767  *
768  * @info: atom card_info pointer
769  * @reg: PLL register offset
770  * @val: value to write to the pll register
771  *
772  * Provides a PLL register accessor for the atom interpreter (r4xx+).
773  */
774 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
775 {
776
777 }
778
779 /**
780  * cail_mc_read - read MC (Memory Controller) register
781  *
782  * @info: atom card_info pointer
783  * @reg: MC register offset
784  *
785  * Provides an MC register accessor for the atom interpreter (r4xx+).
786  * Returns the value of the MC register.
787  */
788 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
789 {
790         return 0;
791 }
792
793 /**
794  * cail_mc_write - write MC (Memory Controller) register
795  *
796  * @info: atom card_info pointer
797  * @reg: MC register offset
798  * @val: value to write to the pll register
799  *
800  * Provides a MC register accessor for the atom interpreter (r4xx+).
801  */
802 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
803 {
804
805 }
806
807 /**
808  * cail_reg_write - write MMIO register
809  *
810  * @info: atom card_info pointer
811  * @reg: MMIO register offset
812  * @val: value to write to the pll register
813  *
814  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
815  */
816 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
817 {
818         struct amdgpu_device *adev = info->dev->dev_private;
819
820         WREG32(reg, val);
821 }
822
823 /**
824  * cail_reg_read - read MMIO register
825  *
826  * @info: atom card_info pointer
827  * @reg: MMIO register offset
828  *
829  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
830  * Returns the value of the MMIO register.
831  */
832 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
833 {
834         struct amdgpu_device *adev = info->dev->dev_private;
835         uint32_t r;
836
837         r = RREG32(reg);
838         return r;
839 }
840
841 /**
842  * cail_ioreg_write - write IO register
843  *
844  * @info: atom card_info pointer
845  * @reg: IO register offset
846  * @val: value to write to the pll register
847  *
848  * Provides a IO register accessor for the atom interpreter (r4xx+).
849  */
850 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
851 {
852         struct amdgpu_device *adev = info->dev->dev_private;
853
854         WREG32_IO(reg, val);
855 }
856
857 /**
858  * cail_ioreg_read - read IO register
859  *
860  * @info: atom card_info pointer
861  * @reg: IO register offset
862  *
863  * Provides an IO register accessor for the atom interpreter (r4xx+).
864  * Returns the value of the IO register.
865  */
866 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
867 {
868         struct amdgpu_device *adev = info->dev->dev_private;
869         uint32_t r;
870
871         r = RREG32_IO(reg);
872         return r;
873 }
874
875 /**
876  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
877  *
878  * @adev: amdgpu_device pointer
879  *
880  * Frees the driver info and register access callbacks for the ATOM
881  * interpreter (r4xx+).
882  * Called at driver shutdown.
883  */
884 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
885 {
886         if (adev->mode_info.atom_context) {
887                 kfree(adev->mode_info.atom_context->scratch);
888                 kfree(adev->mode_info.atom_context->iio);
889         }
890         kfree(adev->mode_info.atom_context);
891         adev->mode_info.atom_context = NULL;
892         kfree(adev->mode_info.atom_card_info);
893         adev->mode_info.atom_card_info = NULL;
894 }
895
896 /**
897  * amdgpu_atombios_init - init the driver info and callbacks for atombios
898  *
899  * @adev: amdgpu_device pointer
900  *
901  * Initializes the driver info and register access callbacks for the
902  * ATOM interpreter (r4xx+).
903  * Returns 0 on sucess, -ENOMEM on failure.
904  * Called at driver startup.
905  */
906 static int amdgpu_atombios_init(struct amdgpu_device *adev)
907 {
908         struct card_info *atom_card_info =
909             kzalloc(sizeof(struct card_info), GFP_KERNEL);
910
911         if (!atom_card_info)
912                 return -ENOMEM;
913
914         adev->mode_info.atom_card_info = atom_card_info;
915         atom_card_info->dev = adev->ddev;
916         atom_card_info->reg_read = cail_reg_read;
917         atom_card_info->reg_write = cail_reg_write;
918         /* needed for iio ops */
919         if (adev->rio_mem) {
920                 atom_card_info->ioreg_read = cail_ioreg_read;
921                 atom_card_info->ioreg_write = cail_ioreg_write;
922         } else {
923                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
924                 atom_card_info->ioreg_read = cail_reg_read;
925                 atom_card_info->ioreg_write = cail_reg_write;
926         }
927         atom_card_info->mc_read = cail_mc_read;
928         atom_card_info->mc_write = cail_mc_write;
929         atom_card_info->pll_read = cail_pll_read;
930         atom_card_info->pll_write = cail_pll_write;
931
932         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
933         if (!adev->mode_info.atom_context) {
934                 amdgpu_atombios_fini(adev);
935                 return -ENOMEM;
936         }
937
938         mutex_init(&adev->mode_info.atom_context->mutex);
939         amdgpu_atombios_scratch_regs_init(adev);
940         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
941         return 0;
942 }
943
944 /* if we get transitioned to only one device, take VGA back */
945 /**
946  * amdgpu_vga_set_decode - enable/disable vga decode
947  *
948  * @cookie: amdgpu_device pointer
949  * @state: enable/disable vga decode
950  *
951  * Enable/disable vga decode (all asics).
952  * Returns VGA resource flags.
953  */
954 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
955 {
956         struct amdgpu_device *adev = cookie;
957         amdgpu_asic_set_vga_state(adev, state);
958         if (state)
959                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
960                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
961         else
962                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
963 }
964
965 /**
966  * amdgpu_check_pot_argument - check that argument is a power of two
967  *
968  * @arg: value to check
969  *
970  * Validates that a certain argument is a power of two (all asics).
971  * Returns true if argument is valid.
972  */
973 static bool amdgpu_check_pot_argument(int arg)
974 {
975         return (arg & (arg - 1)) == 0;
976 }
977
978 /**
979  * amdgpu_check_arguments - validate module params
980  *
981  * @adev: amdgpu_device pointer
982  *
983  * Validates certain module parameters and updates
984  * the associated values used by the driver (all asics).
985  */
986 static void amdgpu_check_arguments(struct amdgpu_device *adev)
987 {
988         if (amdgpu_sched_jobs < 4) {
989                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
990                          amdgpu_sched_jobs);
991                 amdgpu_sched_jobs = 4;
992         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
993                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
994                          amdgpu_sched_jobs);
995                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
996         }
997
998         if (amdgpu_gart_size != -1) {
999                 /* gtt size must be greater or equal to 32M */
1000                 if (amdgpu_gart_size < 32) {
1001                         dev_warn(adev->dev, "gart size (%d) too small\n",
1002                                  amdgpu_gart_size);
1003                         amdgpu_gart_size = -1;
1004                 }
1005         }
1006
1007         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1008                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1009                          amdgpu_vm_size);
1010                 amdgpu_vm_size = 8;
1011         }
1012
1013         if (amdgpu_vm_size < 1) {
1014                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1015                          amdgpu_vm_size);
1016                 amdgpu_vm_size = 8;
1017         }
1018
1019         /*
1020          * Max GPUVM size for Cayman, SI and CI are 40 bits.
1021          */
1022         if (amdgpu_vm_size > 1024) {
1023                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1024                          amdgpu_vm_size);
1025                 amdgpu_vm_size = 8;
1026         }
1027
1028         /* defines number of bits in page table versus page directory,
1029          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1030          * page table and the remaining bits are in the page directory */
1031         if (amdgpu_vm_block_size == -1) {
1032
1033                 /* Total bits covered by PD + PTs */
1034                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1035
1036                 /* Make sure the PD is 4K in size up to 8GB address space.
1037                    Above that split equal between PD and PTs */
1038                 if (amdgpu_vm_size <= 8)
1039                         amdgpu_vm_block_size = bits - 9;
1040                 else
1041                         amdgpu_vm_block_size = (bits + 3) / 2;
1042
1043         } else if (amdgpu_vm_block_size < 9) {
1044                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1045                          amdgpu_vm_block_size);
1046                 amdgpu_vm_block_size = 9;
1047         }
1048
1049         if (amdgpu_vm_block_size > 24 ||
1050             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1051                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1052                          amdgpu_vm_block_size);
1053                 amdgpu_vm_block_size = 9;
1054         }
1055 }
1056
1057 /**
1058  * amdgpu_switcheroo_set_state - set switcheroo state
1059  *
1060  * @pdev: pci dev pointer
1061  * @state: vga_switcheroo state
1062  *
1063  * Callback for the switcheroo driver.  Suspends or resumes the
1064  * the asics before or after it is powered up using ACPI methods.
1065  */
1066 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1067 {
1068         struct drm_device *dev = pci_get_drvdata(pdev);
1069
1070         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1071                 return;
1072
1073         if (state == VGA_SWITCHEROO_ON) {
1074                 unsigned d3_delay = dev->pdev->d3_delay;
1075
1076                 printk(KERN_INFO "amdgpu: switched on\n");
1077                 /* don't suspend or resume card normally */
1078                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1079
1080                 amdgpu_device_resume(dev, true, true);
1081
1082                 dev->pdev->d3_delay = d3_delay;
1083
1084                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1085                 drm_kms_helper_poll_enable(dev);
1086         } else {
1087                 printk(KERN_INFO "amdgpu: switched off\n");
1088                 drm_kms_helper_poll_disable(dev);
1089                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1090                 amdgpu_device_suspend(dev, true, true);
1091                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1092         }
1093 }
1094
1095 /**
1096  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1097  *
1098  * @pdev: pci dev pointer
1099  *
1100  * Callback for the switcheroo driver.  Check of the switcheroo
1101  * state can be changed.
1102  * Returns true if the state can be changed, false if not.
1103  */
1104 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1105 {
1106         struct drm_device *dev = pci_get_drvdata(pdev);
1107
1108         /*
1109         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1110         * locking inversion with the driver load path. And the access here is
1111         * completely racy anyway. So don't bother with locking for now.
1112         */
1113         return dev->open_count == 0;
1114 }
1115
1116 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1117         .set_gpu_state = amdgpu_switcheroo_set_state,
1118         .reprobe = NULL,
1119         .can_switch = amdgpu_switcheroo_can_switch,
1120 };
1121
1122 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1123                                   enum amd_ip_block_type block_type,
1124                                   enum amd_clockgating_state state)
1125 {
1126         int i, r = 0;
1127
1128         for (i = 0; i < adev->num_ip_blocks; i++) {
1129                 if (!adev->ip_block_status[i].valid)
1130                         continue;
1131                 if (adev->ip_blocks[i].type == block_type) {
1132                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1133                                                                             state);
1134                         if (r)
1135                                 return r;
1136                         break;
1137                 }
1138         }
1139         return r;
1140 }
1141
1142 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1143                                   enum amd_ip_block_type block_type,
1144                                   enum amd_powergating_state state)
1145 {
1146         int i, r = 0;
1147
1148         for (i = 0; i < adev->num_ip_blocks; i++) {
1149                 if (!adev->ip_block_status[i].valid)
1150                         continue;
1151                 if (adev->ip_blocks[i].type == block_type) {
1152                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1153                                                                             state);
1154                         if (r)
1155                                 return r;
1156                         break;
1157                 }
1158         }
1159         return r;
1160 }
1161
1162 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1163                          enum amd_ip_block_type block_type)
1164 {
1165         int i, r;
1166
1167         for (i = 0; i < adev->num_ip_blocks; i++) {
1168                 if (!adev->ip_block_status[i].valid)
1169                         continue;
1170                 if (adev->ip_blocks[i].type == block_type) {
1171                         r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1172                         if (r)
1173                                 return r;
1174                         break;
1175                 }
1176         }
1177         return 0;
1178
1179 }
1180
1181 bool amdgpu_is_idle(struct amdgpu_device *adev,
1182                     enum amd_ip_block_type block_type)
1183 {
1184         int i;
1185
1186         for (i = 0; i < adev->num_ip_blocks; i++) {
1187                 if (!adev->ip_block_status[i].valid)
1188                         continue;
1189                 if (adev->ip_blocks[i].type == block_type)
1190                         return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1191         }
1192         return true;
1193
1194 }
1195
1196 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1197                                         struct amdgpu_device *adev,
1198                                         enum amd_ip_block_type type)
1199 {
1200         int i;
1201
1202         for (i = 0; i < adev->num_ip_blocks; i++)
1203                 if (adev->ip_blocks[i].type == type)
1204                         return &adev->ip_blocks[i];
1205
1206         return NULL;
1207 }
1208
1209 /**
1210  * amdgpu_ip_block_version_cmp
1211  *
1212  * @adev: amdgpu_device pointer
1213  * @type: enum amd_ip_block_type
1214  * @major: major version
1215  * @minor: minor version
1216  *
1217  * return 0 if equal or greater
1218  * return 1 if smaller or the ip_block doesn't exist
1219  */
1220 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1221                                 enum amd_ip_block_type type,
1222                                 u32 major, u32 minor)
1223 {
1224         const struct amdgpu_ip_block_version *ip_block;
1225         ip_block = amdgpu_get_ip_block(adev, type);
1226
1227         if (ip_block && ((ip_block->major > major) ||
1228                         ((ip_block->major == major) &&
1229                         (ip_block->minor >= minor))))
1230                 return 0;
1231
1232         return 1;
1233 }
1234
1235 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1236 {
1237         adev->enable_virtual_display = false;
1238
1239         if (amdgpu_virtual_display) {
1240                 struct drm_device *ddev = adev->ddev;
1241                 const char *pci_address_name = pci_name(ddev->pdev);
1242                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1243
1244                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1245                 pciaddstr_tmp = pciaddstr;
1246                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1247                         pciaddname = strsep(&pciaddname_tmp, ",");
1248                         if (!strcmp(pci_address_name, pciaddname)) {
1249                                 long num_crtc;
1250                                 int res = -1;
1251
1252                                 adev->enable_virtual_display = true;
1253
1254                                 if (pciaddname_tmp)
1255                                         res = kstrtol(pciaddname_tmp, 10,
1256                                                       &num_crtc);
1257
1258                                 if (!res) {
1259                                         if (num_crtc < 1)
1260                                                 num_crtc = 1;
1261                                         if (num_crtc > 6)
1262                                                 num_crtc = 6;
1263                                         adev->mode_info.num_crtc = num_crtc;
1264                                 } else {
1265                                         adev->mode_info.num_crtc = 1;
1266                                 }
1267                                 break;
1268                         }
1269                 }
1270
1271                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1272                          amdgpu_virtual_display, pci_address_name,
1273                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1274
1275                 kfree(pciaddstr);
1276         }
1277 }
1278
1279 static int amdgpu_early_init(struct amdgpu_device *adev)
1280 {
1281         int i, r;
1282
1283         amdgpu_device_enable_virtual_display(adev);
1284
1285         switch (adev->asic_type) {
1286         case CHIP_TOPAZ:
1287         case CHIP_TONGA:
1288         case CHIP_FIJI:
1289         case CHIP_POLARIS11:
1290         case CHIP_POLARIS10:
1291         case CHIP_CARRIZO:
1292         case CHIP_STONEY:
1293                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1294                         adev->family = AMDGPU_FAMILY_CZ;
1295                 else
1296                         adev->family = AMDGPU_FAMILY_VI;
1297
1298                 r = vi_set_ip_blocks(adev);
1299                 if (r)
1300                         return r;
1301                 break;
1302 #ifdef CONFIG_DRM_AMDGPU_SI
1303         case CHIP_VERDE:
1304         case CHIP_TAHITI:
1305         case CHIP_PITCAIRN:
1306         case CHIP_OLAND:
1307         case CHIP_HAINAN:
1308                 adev->family = AMDGPU_FAMILY_SI;
1309                 r = si_set_ip_blocks(adev);
1310                 if (r)
1311                         return r;
1312                 break;
1313 #endif
1314 #ifdef CONFIG_DRM_AMDGPU_CIK
1315         case CHIP_BONAIRE:
1316         case CHIP_HAWAII:
1317         case CHIP_KAVERI:
1318         case CHIP_KABINI:
1319         case CHIP_MULLINS:
1320                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1321                         adev->family = AMDGPU_FAMILY_CI;
1322                 else
1323                         adev->family = AMDGPU_FAMILY_KV;
1324
1325                 r = cik_set_ip_blocks(adev);
1326                 if (r)
1327                         return r;
1328                 break;
1329 #endif
1330         default:
1331                 /* FIXME: not supported yet */
1332                 return -EINVAL;
1333         }
1334
1335         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1336                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1337         if (adev->ip_block_status == NULL)
1338                 return -ENOMEM;
1339
1340         if (adev->ip_blocks == NULL) {
1341                 DRM_ERROR("No IP blocks found!\n");
1342                 return r;
1343         }
1344
1345         for (i = 0; i < adev->num_ip_blocks; i++) {
1346                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1347                         DRM_ERROR("disabled ip block: %d\n", i);
1348                         adev->ip_block_status[i].valid = false;
1349                 } else {
1350                         if (adev->ip_blocks[i].funcs->early_init) {
1351                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1352                                 if (r == -ENOENT) {
1353                                         adev->ip_block_status[i].valid = false;
1354                                 } else if (r) {
1355                                         DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1356                                         return r;
1357                                 } else {
1358                                         adev->ip_block_status[i].valid = true;
1359                                 }
1360                         } else {
1361                                 adev->ip_block_status[i].valid = true;
1362                         }
1363                 }
1364         }
1365
1366         adev->cg_flags &= amdgpu_cg_mask;
1367         adev->pg_flags &= amdgpu_pg_mask;
1368
1369         return 0;
1370 }
1371
1372 static int amdgpu_init(struct amdgpu_device *adev)
1373 {
1374         int i, r;
1375
1376         for (i = 0; i < adev->num_ip_blocks; i++) {
1377                 if (!adev->ip_block_status[i].valid)
1378                         continue;
1379                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1380                 if (r) {
1381                         DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1382                         return r;
1383                 }
1384                 adev->ip_block_status[i].sw = true;
1385                 /* need to do gmc hw init early so we can allocate gpu mem */
1386                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1387                         r = amdgpu_vram_scratch_init(adev);
1388                         if (r) {
1389                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1390                                 return r;
1391                         }
1392                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1393                         if (r) {
1394                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1395                                 return r;
1396                         }
1397                         r = amdgpu_wb_init(adev);
1398                         if (r) {
1399                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1400                                 return r;
1401                         }
1402                         adev->ip_block_status[i].hw = true;
1403                 }
1404         }
1405
1406         for (i = 0; i < adev->num_ip_blocks; i++) {
1407                 if (!adev->ip_block_status[i].sw)
1408                         continue;
1409                 /* gmc hw init is done early */
1410                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1411                         continue;
1412                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1413                 if (r) {
1414                         DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1415                         return r;
1416                 }
1417                 adev->ip_block_status[i].hw = true;
1418         }
1419
1420         return 0;
1421 }
1422
1423 static int amdgpu_late_init(struct amdgpu_device *adev)
1424 {
1425         int i = 0, r;
1426
1427         for (i = 0; i < adev->num_ip_blocks; i++) {
1428                 if (!adev->ip_block_status[i].valid)
1429                         continue;
1430                 if (adev->ip_blocks[i].funcs->late_init) {
1431                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1432                         if (r) {
1433                                 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1434                                 return r;
1435                         }
1436                         adev->ip_block_status[i].late_initialized = true;
1437                 }
1438                 /* skip CG for VCE/UVD, it's handled specially */
1439                 if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
1440                     adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
1441                         /* enable clockgating to save power */
1442                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1443                                                                             AMD_CG_STATE_GATE);
1444                         if (r) {
1445                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1446                                           adev->ip_blocks[i].funcs->name, r);
1447                                 return r;
1448                         }
1449                 }
1450         }
1451
1452         return 0;
1453 }
1454
1455 static int amdgpu_fini(struct amdgpu_device *adev)
1456 {
1457         int i, r;
1458
1459         /* need to disable SMC first */
1460         for (i = 0; i < adev->num_ip_blocks; i++) {
1461                 if (!adev->ip_block_status[i].hw)
1462                         continue;
1463                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) {
1464                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1465                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1466                                                                             AMD_CG_STATE_UNGATE);
1467                         if (r) {
1468                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1469                                           adev->ip_blocks[i].funcs->name, r);
1470                                 return r;
1471                         }
1472                         r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1473                         /* XXX handle errors */
1474                         if (r) {
1475                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1476                                           adev->ip_blocks[i].funcs->name, r);
1477                         }
1478                         adev->ip_block_status[i].hw = false;
1479                         break;
1480                 }
1481         }
1482
1483         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1484                 if (!adev->ip_block_status[i].hw)
1485                         continue;
1486                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1487                         amdgpu_wb_fini(adev);
1488                         amdgpu_vram_scratch_fini(adev);
1489                 }
1490                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1491                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1492                                                                     AMD_CG_STATE_UNGATE);
1493                 if (r) {
1494                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1495                         return r;
1496                 }
1497                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1498                 /* XXX handle errors */
1499                 if (r) {
1500                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1501                 }
1502                 adev->ip_block_status[i].hw = false;
1503         }
1504
1505         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1506                 if (!adev->ip_block_status[i].sw)
1507                         continue;
1508                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1509                 /* XXX handle errors */
1510                 if (r) {
1511                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1512                 }
1513                 adev->ip_block_status[i].sw = false;
1514                 adev->ip_block_status[i].valid = false;
1515         }
1516
1517         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1518                 if (!adev->ip_block_status[i].late_initialized)
1519                         continue;
1520                 if (adev->ip_blocks[i].funcs->late_fini)
1521                         adev->ip_blocks[i].funcs->late_fini((void *)adev);
1522                 adev->ip_block_status[i].late_initialized = false;
1523         }
1524
1525         return 0;
1526 }
1527
1528 static int amdgpu_suspend(struct amdgpu_device *adev)
1529 {
1530         int i, r;
1531
1532         /* ungate SMC block first */
1533         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1534                                          AMD_CG_STATE_UNGATE);
1535         if (r) {
1536                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1537         }
1538
1539         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1540                 if (!adev->ip_block_status[i].valid)
1541                         continue;
1542                 /* ungate blocks so that suspend can properly shut them down */
1543                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1544                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1545                                                                             AMD_CG_STATE_UNGATE);
1546                         if (r) {
1547                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1548                         }
1549                 }
1550                 /* XXX handle errors */
1551                 r = adev->ip_blocks[i].funcs->suspend(adev);
1552                 /* XXX handle errors */
1553                 if (r) {
1554                         DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1555                 }
1556         }
1557
1558         return 0;
1559 }
1560
1561 static int amdgpu_resume(struct amdgpu_device *adev)
1562 {
1563         int i, r;
1564
1565         for (i = 0; i < adev->num_ip_blocks; i++) {
1566                 if (!adev->ip_block_status[i].valid)
1567                         continue;
1568                 r = adev->ip_blocks[i].funcs->resume(adev);
1569                 if (r) {
1570                         DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1571                         return r;
1572                 }
1573         }
1574
1575         return 0;
1576 }
1577
1578 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1579 {
1580         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1581                 adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1582 }
1583
1584 /**
1585  * amdgpu_device_init - initialize the driver
1586  *
1587  * @adev: amdgpu_device pointer
1588  * @pdev: drm dev pointer
1589  * @pdev: pci dev pointer
1590  * @flags: driver flags
1591  *
1592  * Initializes the driver info and hw (all asics).
1593  * Returns 0 for success or an error on failure.
1594  * Called at driver startup.
1595  */
1596 int amdgpu_device_init(struct amdgpu_device *adev,
1597                        struct drm_device *ddev,
1598                        struct pci_dev *pdev,
1599                        uint32_t flags)
1600 {
1601         int r, i;
1602         bool runtime = false;
1603         u32 max_MBps;
1604
1605         adev->shutdown = false;
1606         adev->dev = &pdev->dev;
1607         adev->ddev = ddev;
1608         adev->pdev = pdev;
1609         adev->flags = flags;
1610         adev->asic_type = flags & AMD_ASIC_MASK;
1611         adev->is_atom_bios = false;
1612         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1613         adev->mc.gtt_size = 512 * 1024 * 1024;
1614         adev->accel_working = false;
1615         adev->num_rings = 0;
1616         adev->mman.buffer_funcs = NULL;
1617         adev->mman.buffer_funcs_ring = NULL;
1618         adev->vm_manager.vm_pte_funcs = NULL;
1619         adev->vm_manager.vm_pte_num_rings = 0;
1620         adev->gart.gart_funcs = NULL;
1621         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1622
1623         adev->smc_rreg = &amdgpu_invalid_rreg;
1624         adev->smc_wreg = &amdgpu_invalid_wreg;
1625         adev->pcie_rreg = &amdgpu_invalid_rreg;
1626         adev->pcie_wreg = &amdgpu_invalid_wreg;
1627         adev->pciep_rreg = &amdgpu_invalid_rreg;
1628         adev->pciep_wreg = &amdgpu_invalid_wreg;
1629         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1630         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1631         adev->didt_rreg = &amdgpu_invalid_rreg;
1632         adev->didt_wreg = &amdgpu_invalid_wreg;
1633         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1634         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1635         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1636         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1637
1638
1639         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1640                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1641                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1642
1643         /* mutex initialization are all done here so we
1644          * can recall function without having locking issues */
1645         mutex_init(&adev->vm_manager.lock);
1646         atomic_set(&adev->irq.ih.lock, 0);
1647         mutex_init(&adev->pm.mutex);
1648         mutex_init(&adev->gfx.gpu_clock_mutex);
1649         mutex_init(&adev->srbm_mutex);
1650         mutex_init(&adev->grbm_idx_mutex);
1651         mutex_init(&adev->mn_lock);
1652         hash_init(adev->mn_hash);
1653
1654         amdgpu_check_arguments(adev);
1655
1656         /* Registers mapping */
1657         /* TODO: block userspace mapping of io register */
1658         spin_lock_init(&adev->mmio_idx_lock);
1659         spin_lock_init(&adev->smc_idx_lock);
1660         spin_lock_init(&adev->pcie_idx_lock);
1661         spin_lock_init(&adev->uvd_ctx_idx_lock);
1662         spin_lock_init(&adev->didt_idx_lock);
1663         spin_lock_init(&adev->gc_cac_idx_lock);
1664         spin_lock_init(&adev->audio_endpt_idx_lock);
1665         spin_lock_init(&adev->mm_stats.lock);
1666
1667         INIT_LIST_HEAD(&adev->shadow_list);
1668         mutex_init(&adev->shadow_list_lock);
1669
1670         INIT_LIST_HEAD(&adev->gtt_list);
1671         spin_lock_init(&adev->gtt_list_lock);
1672
1673         if (adev->asic_type >= CHIP_BONAIRE) {
1674                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1675                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1676         } else {
1677                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1678                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1679         }
1680
1681         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1682         if (adev->rmmio == NULL) {
1683                 return -ENOMEM;
1684         }
1685         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1686         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1687
1688         if (adev->asic_type >= CHIP_BONAIRE)
1689                 /* doorbell bar mapping */
1690                 amdgpu_doorbell_init(adev);
1691
1692         /* io port mapping */
1693         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1694                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1695                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1696                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1697                         break;
1698                 }
1699         }
1700         if (adev->rio_mem == NULL)
1701                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1702
1703         /* early init functions */
1704         r = amdgpu_early_init(adev);
1705         if (r)
1706                 return r;
1707
1708         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1709         /* this will fail for cards that aren't VGA class devices, just
1710          * ignore it */
1711         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1712
1713         if (amdgpu_runtime_pm == 1)
1714                 runtime = true;
1715         if (amdgpu_device_is_px(ddev))
1716                 runtime = true;
1717         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1718         if (runtime)
1719                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1720
1721         /* Read BIOS */
1722         if (!amdgpu_get_bios(adev)) {
1723                 r = -EINVAL;
1724                 goto failed;
1725         }
1726         /* Must be an ATOMBIOS */
1727         if (!adev->is_atom_bios) {
1728                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1729                 r = -EINVAL;
1730                 goto failed;
1731         }
1732         r = amdgpu_atombios_init(adev);
1733         if (r) {
1734                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1735                 goto failed;
1736         }
1737
1738         /* detect if we are with an SRIOV vbios */
1739         amdgpu_device_detect_sriov_bios(adev);
1740
1741         /* Post card if necessary */
1742         if (amdgpu_vpost_needed(adev)) {
1743                 if (!adev->bios) {
1744                         dev_err(adev->dev, "no vBIOS found\n");
1745                         r = -EINVAL;
1746                         goto failed;
1747                 }
1748                 DRM_INFO("GPU posting now...\n");
1749                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1750                 if (r) {
1751                         dev_err(adev->dev, "gpu post error!\n");
1752                         goto failed;
1753                 }
1754         } else {
1755                 DRM_INFO("GPU post is not needed\n");
1756         }
1757
1758         /* Initialize clocks */
1759         r = amdgpu_atombios_get_clock_info(adev);
1760         if (r) {
1761                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1762                 goto failed;
1763         }
1764         /* init i2c buses */
1765         amdgpu_atombios_i2c_init(adev);
1766
1767         /* Fence driver */
1768         r = amdgpu_fence_driver_init(adev);
1769         if (r) {
1770                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1771                 goto failed;
1772         }
1773
1774         /* init the mode config */
1775         drm_mode_config_init(adev->ddev);
1776
1777         r = amdgpu_init(adev);
1778         if (r) {
1779                 dev_err(adev->dev, "amdgpu_init failed\n");
1780                 amdgpu_fini(adev);
1781                 goto failed;
1782         }
1783
1784         adev->accel_working = true;
1785
1786         /* Initialize the buffer migration limit. */
1787         if (amdgpu_moverate >= 0)
1788                 max_MBps = amdgpu_moverate;
1789         else
1790                 max_MBps = 8; /* Allow 8 MB/s. */
1791         /* Get a log2 for easy divisions. */
1792         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1793
1794         amdgpu_fbdev_init(adev);
1795
1796         r = amdgpu_ib_pool_init(adev);
1797         if (r) {
1798                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1799                 goto failed;
1800         }
1801
1802         r = amdgpu_ib_ring_tests(adev);
1803         if (r)
1804                 DRM_ERROR("ib ring test failed (%d).\n", r);
1805
1806         r = amdgpu_gem_debugfs_init(adev);
1807         if (r) {
1808                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1809         }
1810
1811         r = amdgpu_debugfs_regs_init(adev);
1812         if (r) {
1813                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1814         }
1815
1816         r = amdgpu_debugfs_firmware_init(adev);
1817         if (r) {
1818                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1819                 return r;
1820         }
1821
1822         if ((amdgpu_testing & 1)) {
1823                 if (adev->accel_working)
1824                         amdgpu_test_moves(adev);
1825                 else
1826                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1827         }
1828         if ((amdgpu_testing & 2)) {
1829                 if (adev->accel_working)
1830                         amdgpu_test_syncing(adev);
1831                 else
1832                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1833         }
1834         if (amdgpu_benchmarking) {
1835                 if (adev->accel_working)
1836                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1837                 else
1838                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1839         }
1840
1841         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1842          * explicit gating rather than handling it automatically.
1843          */
1844         r = amdgpu_late_init(adev);
1845         if (r) {
1846                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1847                 goto failed;
1848         }
1849
1850         return 0;
1851
1852 failed:
1853         if (runtime)
1854                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1855         return r;
1856 }
1857
1858 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1859
1860 /**
1861  * amdgpu_device_fini - tear down the driver
1862  *
1863  * @adev: amdgpu_device pointer
1864  *
1865  * Tear down the driver info (all asics).
1866  * Called at driver shutdown.
1867  */
1868 void amdgpu_device_fini(struct amdgpu_device *adev)
1869 {
1870         int r;
1871
1872         DRM_INFO("amdgpu: finishing device.\n");
1873         adev->shutdown = true;
1874         drm_crtc_force_disable_all(adev->ddev);
1875         /* evict vram memory */
1876         amdgpu_bo_evict_vram(adev);
1877         amdgpu_ib_pool_fini(adev);
1878         amdgpu_fence_driver_fini(adev);
1879         amdgpu_fbdev_fini(adev);
1880         r = amdgpu_fini(adev);
1881         kfree(adev->ip_block_status);
1882         adev->ip_block_status = NULL;
1883         adev->accel_working = false;
1884         /* free i2c buses */
1885         amdgpu_i2c_fini(adev);
1886         amdgpu_atombios_fini(adev);
1887         kfree(adev->bios);
1888         adev->bios = NULL;
1889         vga_switcheroo_unregister_client(adev->pdev);
1890         if (adev->flags & AMD_IS_PX)
1891                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1892         vga_client_register(adev->pdev, NULL, NULL, NULL);
1893         if (adev->rio_mem)
1894                 pci_iounmap(adev->pdev, adev->rio_mem);
1895         adev->rio_mem = NULL;
1896         iounmap(adev->rmmio);
1897         adev->rmmio = NULL;
1898         if (adev->asic_type >= CHIP_BONAIRE)
1899                 amdgpu_doorbell_fini(adev);
1900         amdgpu_debugfs_regs_cleanup(adev);
1901         amdgpu_debugfs_remove_files(adev);
1902 }
1903
1904
1905 /*
1906  * Suspend & resume.
1907  */
1908 /**
1909  * amdgpu_device_suspend - initiate device suspend
1910  *
1911  * @pdev: drm dev pointer
1912  * @state: suspend state
1913  *
1914  * Puts the hw in the suspend state (all asics).
1915  * Returns 0 for success or an error on failure.
1916  * Called at driver suspend.
1917  */
1918 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1919 {
1920         struct amdgpu_device *adev;
1921         struct drm_crtc *crtc;
1922         struct drm_connector *connector;
1923         int r;
1924
1925         if (dev == NULL || dev->dev_private == NULL) {
1926                 return -ENODEV;
1927         }
1928
1929         adev = dev->dev_private;
1930
1931         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1932                 return 0;
1933
1934         drm_kms_helper_poll_disable(dev);
1935
1936         /* turn off display hw */
1937         drm_modeset_lock_all(dev);
1938         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1939                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1940         }
1941         drm_modeset_unlock_all(dev);
1942
1943         /* unpin the front buffers and cursors */
1944         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1945                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1946                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1947                 struct amdgpu_bo *robj;
1948
1949                 if (amdgpu_crtc->cursor_bo) {
1950                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1951                         r = amdgpu_bo_reserve(aobj, false);
1952                         if (r == 0) {
1953                                 amdgpu_bo_unpin(aobj);
1954                                 amdgpu_bo_unreserve(aobj);
1955                         }
1956                 }
1957
1958                 if (rfb == NULL || rfb->obj == NULL) {
1959                         continue;
1960                 }
1961                 robj = gem_to_amdgpu_bo(rfb->obj);
1962                 /* don't unpin kernel fb objects */
1963                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1964                         r = amdgpu_bo_reserve(robj, false);
1965                         if (r == 0) {
1966                                 amdgpu_bo_unpin(robj);
1967                                 amdgpu_bo_unreserve(robj);
1968                         }
1969                 }
1970         }
1971         /* evict vram memory */
1972         amdgpu_bo_evict_vram(adev);
1973
1974         amdgpu_fence_driver_suspend(adev);
1975
1976         r = amdgpu_suspend(adev);
1977
1978         /* evict remaining vram memory */
1979         amdgpu_bo_evict_vram(adev);
1980
1981         pci_save_state(dev->pdev);
1982         if (suspend) {
1983                 /* Shut down the device */
1984                 pci_disable_device(dev->pdev);
1985                 pci_set_power_state(dev->pdev, PCI_D3hot);
1986         } else {
1987                 r = amdgpu_asic_reset(adev);
1988                 if (r)
1989                         DRM_ERROR("amdgpu asic reset failed\n");
1990         }
1991
1992         if (fbcon) {
1993                 console_lock();
1994                 amdgpu_fbdev_set_suspend(adev, 1);
1995                 console_unlock();
1996         }
1997         return 0;
1998 }
1999
2000 /**
2001  * amdgpu_device_resume - initiate device resume
2002  *
2003  * @pdev: drm dev pointer
2004  *
2005  * Bring the hw back to operating state (all asics).
2006  * Returns 0 for success or an error on failure.
2007  * Called at driver resume.
2008  */
2009 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2010 {
2011         struct drm_connector *connector;
2012         struct amdgpu_device *adev = dev->dev_private;
2013         struct drm_crtc *crtc;
2014         int r;
2015
2016         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2017                 return 0;
2018
2019         if (fbcon)
2020                 console_lock();
2021
2022         if (resume) {
2023                 pci_set_power_state(dev->pdev, PCI_D0);
2024                 pci_restore_state(dev->pdev);
2025                 r = pci_enable_device(dev->pdev);
2026                 if (r) {
2027                         if (fbcon)
2028                                 console_unlock();
2029                         return r;
2030                 }
2031         }
2032
2033         /* post card */
2034         if (!amdgpu_card_posted(adev) || !resume) {
2035                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2036                 if (r)
2037                         DRM_ERROR("amdgpu asic init failed\n");
2038         }
2039
2040         r = amdgpu_resume(adev);
2041         if (r)
2042                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2043
2044         amdgpu_fence_driver_resume(adev);
2045
2046         if (resume) {
2047                 r = amdgpu_ib_ring_tests(adev);
2048                 if (r)
2049                         DRM_ERROR("ib ring test failed (%d).\n", r);
2050         }
2051
2052         r = amdgpu_late_init(adev);
2053         if (r)
2054                 return r;
2055
2056         /* pin cursors */
2057         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2058                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2059
2060                 if (amdgpu_crtc->cursor_bo) {
2061                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2062                         r = amdgpu_bo_reserve(aobj, false);
2063                         if (r == 0) {
2064                                 r = amdgpu_bo_pin(aobj,
2065                                                   AMDGPU_GEM_DOMAIN_VRAM,
2066                                                   &amdgpu_crtc->cursor_addr);
2067                                 if (r != 0)
2068                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2069                                 amdgpu_bo_unreserve(aobj);
2070                         }
2071                 }
2072         }
2073
2074         /* blat the mode back in */
2075         if (fbcon) {
2076                 drm_helper_resume_force_mode(dev);
2077                 /* turn on display hw */
2078                 drm_modeset_lock_all(dev);
2079                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2080                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2081                 }
2082                 drm_modeset_unlock_all(dev);
2083         }
2084
2085         drm_kms_helper_poll_enable(dev);
2086
2087         /*
2088          * Most of the connector probing functions try to acquire runtime pm
2089          * refs to ensure that the GPU is powered on when connector polling is
2090          * performed. Since we're calling this from a runtime PM callback,
2091          * trying to acquire rpm refs will cause us to deadlock.
2092          *
2093          * Since we're guaranteed to be holding the rpm lock, it's safe to
2094          * temporarily disable the rpm helpers so this doesn't deadlock us.
2095          */
2096 #ifdef CONFIG_PM
2097         dev->dev->power.disable_depth++;
2098 #endif
2099         drm_helper_hpd_irq_event(dev);
2100 #ifdef CONFIG_PM
2101         dev->dev->power.disable_depth--;
2102 #endif
2103
2104         if (fbcon) {
2105                 amdgpu_fbdev_set_suspend(adev, 0);
2106                 console_unlock();
2107         }
2108
2109         return 0;
2110 }
2111
2112 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2113 {
2114         int i;
2115         bool asic_hang = false;
2116
2117         for (i = 0; i < adev->num_ip_blocks; i++) {
2118                 if (!adev->ip_block_status[i].valid)
2119                         continue;
2120                 if (adev->ip_blocks[i].funcs->check_soft_reset)
2121                         adev->ip_block_status[i].hang =
2122                                 adev->ip_blocks[i].funcs->check_soft_reset(adev);
2123                 if (adev->ip_block_status[i].hang) {
2124                         DRM_INFO("IP block:%d is hang!\n", i);
2125                         asic_hang = true;
2126                 }
2127         }
2128         return asic_hang;
2129 }
2130
2131 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2132 {
2133         int i, r = 0;
2134
2135         for (i = 0; i < adev->num_ip_blocks; i++) {
2136                 if (!adev->ip_block_status[i].valid)
2137                         continue;
2138                 if (adev->ip_block_status[i].hang &&
2139                     adev->ip_blocks[i].funcs->pre_soft_reset) {
2140                         r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
2141                         if (r)
2142                                 return r;
2143                 }
2144         }
2145
2146         return 0;
2147 }
2148
2149 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2150 {
2151         int i;
2152
2153         for (i = 0; i < adev->num_ip_blocks; i++) {
2154                 if (!adev->ip_block_status[i].valid)
2155                         continue;
2156                 if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
2157                     (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
2158                     (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
2159                     (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
2160                         if (adev->ip_block_status[i].hang) {
2161                                 DRM_INFO("Some block need full reset!\n");
2162                                 return true;
2163                         }
2164                 }
2165         }
2166         return false;
2167 }
2168
2169 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2170 {
2171         int i, r = 0;
2172
2173         for (i = 0; i < adev->num_ip_blocks; i++) {
2174                 if (!adev->ip_block_status[i].valid)
2175                         continue;
2176                 if (adev->ip_block_status[i].hang &&
2177                     adev->ip_blocks[i].funcs->soft_reset) {
2178                         r = adev->ip_blocks[i].funcs->soft_reset(adev);
2179                         if (r)
2180                                 return r;
2181                 }
2182         }
2183
2184         return 0;
2185 }
2186
2187 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2188 {
2189         int i, r = 0;
2190
2191         for (i = 0; i < adev->num_ip_blocks; i++) {
2192                 if (!adev->ip_block_status[i].valid)
2193                         continue;
2194                 if (adev->ip_block_status[i].hang &&
2195                     adev->ip_blocks[i].funcs->post_soft_reset)
2196                         r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
2197                 if (r)
2198                         return r;
2199         }
2200
2201         return 0;
2202 }
2203
2204 bool amdgpu_need_backup(struct amdgpu_device *adev)
2205 {
2206         if (adev->flags & AMD_IS_APU)
2207                 return false;
2208
2209         return amdgpu_lockup_timeout > 0 ? true : false;
2210 }
2211
2212 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2213                                            struct amdgpu_ring *ring,
2214                                            struct amdgpu_bo *bo,
2215                                            struct fence **fence)
2216 {
2217         uint32_t domain;
2218         int r;
2219
2220        if (!bo->shadow)
2221                return 0;
2222
2223        r = amdgpu_bo_reserve(bo, false);
2224        if (r)
2225                return r;
2226        domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2227        /* if bo has been evicted, then no need to recover */
2228        if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2229                r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2230                                                  NULL, fence, true);
2231                if (r) {
2232                        DRM_ERROR("recover page table failed!\n");
2233                        goto err;
2234                }
2235        }
2236 err:
2237        amdgpu_bo_unreserve(bo);
2238        return r;
2239 }
2240
2241 /**
2242  * amdgpu_gpu_reset - reset the asic
2243  *
2244  * @adev: amdgpu device pointer
2245  *
2246  * Attempt the reset the GPU if it has hung (all asics).
2247  * Returns 0 for success or an error on failure.
2248  */
2249 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2250 {
2251         int i, r;
2252         int resched;
2253         bool need_full_reset;
2254
2255         if (!amdgpu_check_soft_reset(adev)) {
2256                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2257                 return 0;
2258         }
2259
2260         atomic_inc(&adev->gpu_reset_counter);
2261
2262         /* block TTM */
2263         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2264
2265         /* block scheduler */
2266         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2267                 struct amdgpu_ring *ring = adev->rings[i];
2268
2269                 if (!ring)
2270                         continue;
2271                 kthread_park(ring->sched.thread);
2272                 amd_sched_hw_job_reset(&ring->sched);
2273         }
2274         /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2275         amdgpu_fence_driver_force_completion(adev);
2276
2277         need_full_reset = amdgpu_need_full_reset(adev);
2278
2279         if (!need_full_reset) {
2280                 amdgpu_pre_soft_reset(adev);
2281                 r = amdgpu_soft_reset(adev);
2282                 amdgpu_post_soft_reset(adev);
2283                 if (r || amdgpu_check_soft_reset(adev)) {
2284                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2285                         need_full_reset = true;
2286                 }
2287         }
2288
2289         if (need_full_reset) {
2290                 /* save scratch */
2291                 amdgpu_atombios_scratch_regs_save(adev);
2292                 r = amdgpu_suspend(adev);
2293
2294 retry:
2295                 /* Disable fb access */
2296                 if (adev->mode_info.num_crtc) {
2297                         struct amdgpu_mode_mc_save save;
2298                         amdgpu_display_stop_mc_access(adev, &save);
2299                         amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2300                 }
2301
2302                 r = amdgpu_asic_reset(adev);
2303                 /* post card */
2304                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2305
2306                 if (!r) {
2307                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2308                         r = amdgpu_resume(adev);
2309                 }
2310                 /* restore scratch */
2311                 amdgpu_atombios_scratch_regs_restore(adev);
2312         }
2313         if (!r) {
2314                 amdgpu_irq_gpu_reset_resume_helper(adev);
2315                 if (need_full_reset && amdgpu_need_backup(adev)) {
2316                         r = amdgpu_ttm_recover_gart(adev);
2317                         if (r)
2318                                 DRM_ERROR("gart recovery failed!!!\n");
2319                 }
2320                 r = amdgpu_ib_ring_tests(adev);
2321                 if (r) {
2322                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2323                         r = amdgpu_suspend(adev);
2324                         need_full_reset = true;
2325                         goto retry;
2326                 }
2327                 /**
2328                  * recovery vm page tables, since we cannot depend on VRAM is
2329                  * consistent after gpu full reset.
2330                  */
2331                 if (need_full_reset && amdgpu_need_backup(adev)) {
2332                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2333                         struct amdgpu_bo *bo, *tmp;
2334                         struct fence *fence = NULL, *next = NULL;
2335
2336                         DRM_INFO("recover vram bo from shadow\n");
2337                         mutex_lock(&adev->shadow_list_lock);
2338                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2339                                 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2340                                 if (fence) {
2341                                         r = fence_wait(fence, false);
2342                                         if (r) {
2343                                                 WARN(r, "recovery from shadow isn't comleted\n");
2344                                                 break;
2345                                         }
2346                                 }
2347
2348                                 fence_put(fence);
2349                                 fence = next;
2350                         }
2351                         mutex_unlock(&adev->shadow_list_lock);
2352                         if (fence) {
2353                                 r = fence_wait(fence, false);
2354                                 if (r)
2355                                         WARN(r, "recovery from shadow isn't comleted\n");
2356                         }
2357                         fence_put(fence);
2358                 }
2359                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2360                         struct amdgpu_ring *ring = adev->rings[i];
2361                         if (!ring)
2362                                 continue;
2363
2364                         amd_sched_job_recovery(&ring->sched);
2365                         kthread_unpark(ring->sched.thread);
2366                 }
2367         } else {
2368                 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2369                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2370                         if (adev->rings[i]) {
2371                                 kthread_unpark(adev->rings[i]->sched.thread);
2372                         }
2373                 }
2374         }
2375
2376         drm_helper_resume_force_mode(adev->ddev);
2377
2378         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2379         if (r) {
2380                 /* bad news, how to tell it to userspace ? */
2381                 dev_info(adev->dev, "GPU reset failed\n");
2382         }
2383
2384         return r;
2385 }
2386
2387 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2388 {
2389         u32 mask;
2390         int ret;
2391
2392         if (amdgpu_pcie_gen_cap)
2393                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2394
2395         if (amdgpu_pcie_lane_cap)
2396                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2397
2398         /* covers APUs as well */
2399         if (pci_is_root_bus(adev->pdev->bus)) {
2400                 if (adev->pm.pcie_gen_mask == 0)
2401                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2402                 if (adev->pm.pcie_mlw_mask == 0)
2403                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2404                 return;
2405         }
2406
2407         if (adev->pm.pcie_gen_mask == 0) {
2408                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2409                 if (!ret) {
2410                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2411                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2412                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2413
2414                         if (mask & DRM_PCIE_SPEED_25)
2415                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2416                         if (mask & DRM_PCIE_SPEED_50)
2417                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2418                         if (mask & DRM_PCIE_SPEED_80)
2419                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2420                 } else {
2421                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2422                 }
2423         }
2424         if (adev->pm.pcie_mlw_mask == 0) {
2425                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2426                 if (!ret) {
2427                         switch (mask) {
2428                         case 32:
2429                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2430                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2431                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2432                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2433                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2434                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2435                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2436                                 break;
2437                         case 16:
2438                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2439                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2440                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2441                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2442                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2443                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2444                                 break;
2445                         case 12:
2446                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2447                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2448                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2449                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2450                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2451                                 break;
2452                         case 8:
2453                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2454                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2455                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2456                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2457                                 break;
2458                         case 4:
2459                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2460                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2461                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2462                                 break;
2463                         case 2:
2464                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2465                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2466                                 break;
2467                         case 1:
2468                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2469                                 break;
2470                         default:
2471                                 break;
2472                         }
2473                 } else {
2474                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2475                 }
2476         }
2477 }
2478
2479 /*
2480  * Debugfs
2481  */
2482 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2483                              const struct drm_info_list *files,
2484                              unsigned nfiles)
2485 {
2486         unsigned i;
2487
2488         for (i = 0; i < adev->debugfs_count; i++) {
2489                 if (adev->debugfs[i].files == files) {
2490                         /* Already registered */
2491                         return 0;
2492                 }
2493         }
2494
2495         i = adev->debugfs_count + 1;
2496         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2497                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2498                 DRM_ERROR("Report so we increase "
2499                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2500                 return -EINVAL;
2501         }
2502         adev->debugfs[adev->debugfs_count].files = files;
2503         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2504         adev->debugfs_count = i;
2505 #if defined(CONFIG_DEBUG_FS)
2506         drm_debugfs_create_files(files, nfiles,
2507                                  adev->ddev->control->debugfs_root,
2508                                  adev->ddev->control);
2509         drm_debugfs_create_files(files, nfiles,
2510                                  adev->ddev->primary->debugfs_root,
2511                                  adev->ddev->primary);
2512 #endif
2513         return 0;
2514 }
2515
2516 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2517 {
2518 #if defined(CONFIG_DEBUG_FS)
2519         unsigned i;
2520
2521         for (i = 0; i < adev->debugfs_count; i++) {
2522                 drm_debugfs_remove_files(adev->debugfs[i].files,
2523                                          adev->debugfs[i].num_files,
2524                                          adev->ddev->control);
2525                 drm_debugfs_remove_files(adev->debugfs[i].files,
2526                                          adev->debugfs[i].num_files,
2527                                          adev->ddev->primary);
2528         }
2529 #endif
2530 }
2531
2532 #if defined(CONFIG_DEBUG_FS)
2533
2534 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2535                                         size_t size, loff_t *pos)
2536 {
2537         struct amdgpu_device *adev = f->f_inode->i_private;
2538         ssize_t result = 0;
2539         int r;
2540         bool pm_pg_lock, use_bank;
2541         unsigned instance_bank, sh_bank, se_bank;
2542
2543         if (size & 0x3 || *pos & 0x3)
2544                 return -EINVAL;
2545
2546         /* are we reading registers for which a PG lock is necessary? */
2547         pm_pg_lock = (*pos >> 23) & 1;
2548
2549         if (*pos & (1ULL << 62)) {
2550                 se_bank = (*pos >> 24) & 0x3FF;
2551                 sh_bank = (*pos >> 34) & 0x3FF;
2552                 instance_bank = (*pos >> 44) & 0x3FF;
2553                 use_bank = 1;
2554         } else {
2555                 use_bank = 0;
2556         }
2557
2558         *pos &= 0x3FFFF;
2559
2560         if (use_bank) {
2561                 if (sh_bank >= adev->gfx.config.max_sh_per_se ||
2562                     se_bank >= adev->gfx.config.max_shader_engines)
2563                         return -EINVAL;
2564                 mutex_lock(&adev->grbm_idx_mutex);
2565                 amdgpu_gfx_select_se_sh(adev, se_bank,
2566                                         sh_bank, instance_bank);
2567         }
2568
2569         if (pm_pg_lock)
2570                 mutex_lock(&adev->pm.mutex);
2571
2572         while (size) {
2573                 uint32_t value;
2574
2575                 if (*pos > adev->rmmio_size)
2576                         goto end;
2577
2578                 value = RREG32(*pos >> 2);
2579                 r = put_user(value, (uint32_t *)buf);
2580                 if (r) {
2581                         result = r;
2582                         goto end;
2583                 }
2584
2585                 result += 4;
2586                 buf += 4;
2587                 *pos += 4;
2588                 size -= 4;
2589         }
2590
2591 end:
2592         if (use_bank) {
2593                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2594                 mutex_unlock(&adev->grbm_idx_mutex);
2595         }
2596
2597         if (pm_pg_lock)
2598                 mutex_unlock(&adev->pm.mutex);
2599
2600         return result;
2601 }
2602
2603 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2604                                          size_t size, loff_t *pos)
2605 {
2606         struct amdgpu_device *adev = f->f_inode->i_private;
2607         ssize_t result = 0;
2608         int r;
2609
2610         if (size & 0x3 || *pos & 0x3)
2611                 return -EINVAL;
2612
2613         while (size) {
2614                 uint32_t value;
2615
2616                 if (*pos > adev->rmmio_size)
2617                         return result;
2618
2619                 r = get_user(value, (uint32_t *)buf);
2620                 if (r)
2621                         return r;
2622
2623                 WREG32(*pos >> 2, value);
2624
2625                 result += 4;
2626                 buf += 4;
2627                 *pos += 4;
2628                 size -= 4;
2629         }
2630
2631         return result;
2632 }
2633
2634 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2635                                         size_t size, loff_t *pos)
2636 {
2637         struct amdgpu_device *adev = f->f_inode->i_private;
2638         ssize_t result = 0;
2639         int r;
2640
2641         if (size & 0x3 || *pos & 0x3)
2642                 return -EINVAL;
2643
2644         while (size) {
2645                 uint32_t value;
2646
2647                 value = RREG32_PCIE(*pos >> 2);
2648                 r = put_user(value, (uint32_t *)buf);
2649                 if (r)
2650                         return r;
2651
2652                 result += 4;
2653                 buf += 4;
2654                 *pos += 4;
2655                 size -= 4;
2656         }
2657
2658         return result;
2659 }
2660
2661 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2662                                          size_t size, loff_t *pos)
2663 {
2664         struct amdgpu_device *adev = f->f_inode->i_private;
2665         ssize_t result = 0;
2666         int r;
2667
2668         if (size & 0x3 || *pos & 0x3)
2669                 return -EINVAL;
2670
2671         while (size) {
2672                 uint32_t value;
2673
2674                 r = get_user(value, (uint32_t *)buf);
2675                 if (r)
2676                         return r;
2677
2678                 WREG32_PCIE(*pos >> 2, value);
2679
2680                 result += 4;
2681                 buf += 4;
2682                 *pos += 4;
2683                 size -= 4;
2684         }
2685
2686         return result;
2687 }
2688
2689 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2690                                         size_t size, loff_t *pos)
2691 {
2692         struct amdgpu_device *adev = f->f_inode->i_private;
2693         ssize_t result = 0;
2694         int r;
2695
2696         if (size & 0x3 || *pos & 0x3)
2697                 return -EINVAL;
2698
2699         while (size) {
2700                 uint32_t value;
2701
2702                 value = RREG32_DIDT(*pos >> 2);
2703                 r = put_user(value, (uint32_t *)buf);
2704                 if (r)
2705                         return r;
2706
2707                 result += 4;
2708                 buf += 4;
2709                 *pos += 4;
2710                 size -= 4;
2711         }
2712
2713         return result;
2714 }
2715
2716 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2717                                          size_t size, loff_t *pos)
2718 {
2719         struct amdgpu_device *adev = f->f_inode->i_private;
2720         ssize_t result = 0;
2721         int r;
2722
2723         if (size & 0x3 || *pos & 0x3)
2724                 return -EINVAL;
2725
2726         while (size) {
2727                 uint32_t value;
2728
2729                 r = get_user(value, (uint32_t *)buf);
2730                 if (r)
2731                         return r;
2732
2733                 WREG32_DIDT(*pos >> 2, value);
2734
2735                 result += 4;
2736                 buf += 4;
2737                 *pos += 4;
2738                 size -= 4;
2739         }
2740
2741         return result;
2742 }
2743
2744 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2745                                         size_t size, loff_t *pos)
2746 {
2747         struct amdgpu_device *adev = f->f_inode->i_private;
2748         ssize_t result = 0;
2749         int r;
2750
2751         if (size & 0x3 || *pos & 0x3)
2752                 return -EINVAL;
2753
2754         while (size) {
2755                 uint32_t value;
2756
2757                 value = RREG32_SMC(*pos);
2758                 r = put_user(value, (uint32_t *)buf);
2759                 if (r)
2760                         return r;
2761
2762                 result += 4;
2763                 buf += 4;
2764                 *pos += 4;
2765                 size -= 4;
2766         }
2767
2768         return result;
2769 }
2770
2771 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2772                                          size_t size, loff_t *pos)
2773 {
2774         struct amdgpu_device *adev = f->f_inode->i_private;
2775         ssize_t result = 0;
2776         int r;
2777
2778         if (size & 0x3 || *pos & 0x3)
2779                 return -EINVAL;
2780
2781         while (size) {
2782                 uint32_t value;
2783
2784                 r = get_user(value, (uint32_t *)buf);
2785                 if (r)
2786                         return r;
2787
2788                 WREG32_SMC(*pos, value);
2789
2790                 result += 4;
2791                 buf += 4;
2792                 *pos += 4;
2793                 size -= 4;
2794         }
2795
2796         return result;
2797 }
2798
2799 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2800                                         size_t size, loff_t *pos)
2801 {
2802         struct amdgpu_device *adev = f->f_inode->i_private;
2803         ssize_t result = 0;
2804         int r;
2805         uint32_t *config, no_regs = 0;
2806
2807         if (size & 0x3 || *pos & 0x3)
2808                 return -EINVAL;
2809
2810         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
2811         if (!config)
2812                 return -ENOMEM;
2813
2814         /* version, increment each time something is added */
2815         config[no_regs++] = 2;
2816         config[no_regs++] = adev->gfx.config.max_shader_engines;
2817         config[no_regs++] = adev->gfx.config.max_tile_pipes;
2818         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2819         config[no_regs++] = adev->gfx.config.max_sh_per_se;
2820         config[no_regs++] = adev->gfx.config.max_backends_per_se;
2821         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2822         config[no_regs++] = adev->gfx.config.max_gprs;
2823         config[no_regs++] = adev->gfx.config.max_gs_threads;
2824         config[no_regs++] = adev->gfx.config.max_hw_contexts;
2825         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2826         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2827         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2828         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2829         config[no_regs++] = adev->gfx.config.num_tile_pipes;
2830         config[no_regs++] = adev->gfx.config.backend_enable_mask;
2831         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2832         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2833         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2834         config[no_regs++] = adev->gfx.config.num_gpus;
2835         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2836         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2837         config[no_regs++] = adev->gfx.config.gb_addr_config;
2838         config[no_regs++] = adev->gfx.config.num_rbs;
2839
2840         /* rev==1 */
2841         config[no_regs++] = adev->rev_id;
2842         config[no_regs++] = adev->pg_flags;
2843         config[no_regs++] = adev->cg_flags;
2844
2845         /* rev==2 */
2846         config[no_regs++] = adev->family;
2847         config[no_regs++] = adev->external_rev_id;
2848
2849         while (size && (*pos < no_regs * 4)) {
2850                 uint32_t value;
2851
2852                 value = config[*pos >> 2];
2853                 r = put_user(value, (uint32_t *)buf);
2854                 if (r) {
2855                         kfree(config);
2856                         return r;
2857                 }
2858
2859                 result += 4;
2860                 buf += 4;
2861                 *pos += 4;
2862                 size -= 4;
2863         }
2864
2865         kfree(config);
2866         return result;
2867 }
2868
2869 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
2870                                         size_t size, loff_t *pos)
2871 {
2872         struct amdgpu_device *adev = f->f_inode->i_private;
2873         int idx, r;
2874         int32_t value;
2875
2876         if (size != 4 || *pos & 0x3)
2877                 return -EINVAL;
2878
2879         /* convert offset to sensor number */
2880         idx = *pos >> 2;
2881
2882         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
2883                 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
2884         else
2885                 return -EINVAL;
2886
2887         if (!r)
2888                 r = put_user(value, (int32_t *)buf);
2889
2890         return !r ? 4 : r;
2891 }
2892
2893 static const struct file_operations amdgpu_debugfs_regs_fops = {
2894         .owner = THIS_MODULE,
2895         .read = amdgpu_debugfs_regs_read,
2896         .write = amdgpu_debugfs_regs_write,
2897         .llseek = default_llseek
2898 };
2899 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2900         .owner = THIS_MODULE,
2901         .read = amdgpu_debugfs_regs_didt_read,
2902         .write = amdgpu_debugfs_regs_didt_write,
2903         .llseek = default_llseek
2904 };
2905 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2906         .owner = THIS_MODULE,
2907         .read = amdgpu_debugfs_regs_pcie_read,
2908         .write = amdgpu_debugfs_regs_pcie_write,
2909         .llseek = default_llseek
2910 };
2911 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2912         .owner = THIS_MODULE,
2913         .read = amdgpu_debugfs_regs_smc_read,
2914         .write = amdgpu_debugfs_regs_smc_write,
2915         .llseek = default_llseek
2916 };
2917
2918 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
2919         .owner = THIS_MODULE,
2920         .read = amdgpu_debugfs_gca_config_read,
2921         .llseek = default_llseek
2922 };
2923
2924 static const struct file_operations amdgpu_debugfs_sensors_fops = {
2925         .owner = THIS_MODULE,
2926         .read = amdgpu_debugfs_sensor_read,
2927         .llseek = default_llseek
2928 };
2929
2930 static const struct file_operations *debugfs_regs[] = {
2931         &amdgpu_debugfs_regs_fops,
2932         &amdgpu_debugfs_regs_didt_fops,
2933         &amdgpu_debugfs_regs_pcie_fops,
2934         &amdgpu_debugfs_regs_smc_fops,
2935         &amdgpu_debugfs_gca_config_fops,
2936         &amdgpu_debugfs_sensors_fops,
2937 };
2938
2939 static const char *debugfs_regs_names[] = {
2940         "amdgpu_regs",
2941         "amdgpu_regs_didt",
2942         "amdgpu_regs_pcie",
2943         "amdgpu_regs_smc",
2944         "amdgpu_gca_config",
2945         "amdgpu_sensors",
2946 };
2947
2948 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2949 {
2950         struct drm_minor *minor = adev->ddev->primary;
2951         struct dentry *ent, *root = minor->debugfs_root;
2952         unsigned i, j;
2953
2954         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2955                 ent = debugfs_create_file(debugfs_regs_names[i],
2956                                           S_IFREG | S_IRUGO, root,
2957                                           adev, debugfs_regs[i]);
2958                 if (IS_ERR(ent)) {
2959                         for (j = 0; j < i; j++) {
2960                                 debugfs_remove(adev->debugfs_regs[i]);
2961                                 adev->debugfs_regs[i] = NULL;
2962                         }
2963                         return PTR_ERR(ent);
2964                 }
2965
2966                 if (!i)
2967                         i_size_write(ent->d_inode, adev->rmmio_size);
2968                 adev->debugfs_regs[i] = ent;
2969         }
2970
2971         return 0;
2972 }
2973
2974 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2975 {
2976         unsigned i;
2977
2978         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2979                 if (adev->debugfs_regs[i]) {
2980                         debugfs_remove(adev->debugfs_regs[i]);
2981                         adev->debugfs_regs[i] = NULL;
2982                 }
2983         }
2984 }
2985
2986 int amdgpu_debugfs_init(struct drm_minor *minor)
2987 {
2988         return 0;
2989 }
2990
2991 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2992 {
2993 }
2994 #else
2995 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2996 {
2997         return 0;
2998 }
2999 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
3000 #endif
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