2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/list.h>
25 #include <linux/slab.h>
26 #include <linux/pci.h>
27 #include <linux/acpi.h>
29 #include <linux/firmware.h>
30 #include <drm/amdgpu_drm.h>
32 #include "cgs_linux.h"
34 #include "amdgpu_ucode.h"
36 struct amdgpu_cgs_device {
37 struct cgs_device base;
38 struct amdgpu_device *adev;
41 #define CGS_FUNC_ADEV \
42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev
45 static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
46 uint64_t *mc_start, uint64_t *mc_size,
51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
52 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
54 *mc_size = adev->mc.visible_vram_size;
55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
59 *mc_start = adev->mc.visible_vram_size;
60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
65 *mc_start = adev->mc.gtt_start;
66 *mc_size = adev->mc.gtt_size;
67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
76 static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
78 uint64_t min_offset, uint64_t max_offset,
79 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
84 struct page *kmem_page = vmalloc_to_page(kmem);
85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
92 ret = amdgpu_bo_reserve(bo, false);
93 if (unlikely(ret != 0))
96 /* pin buffer into GTT */
97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
98 min_offset, max_offset, mcaddr);
99 amdgpu_bo_unreserve(bo);
101 *kmem_handle = (cgs_handle_t)bo;
105 static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
110 int r = amdgpu_bo_reserve(obj, false);
111 if (likely(r == 0)) {
112 amdgpu_bo_unpin(obj);
113 amdgpu_bo_unreserve(obj);
115 amdgpu_bo_unref(&obj);
121 static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
122 enum cgs_gpu_mem_type type,
123 uint64_t size, uint64_t align,
124 uint64_t min_offset, uint64_t max_offset,
125 cgs_handle_t *handle)
131 struct amdgpu_bo *obj;
132 struct ttm_placement placement;
133 struct ttm_place place;
135 if (min_offset > max_offset) {
140 /* fail if the alignment is not a power of 2 */
141 if (((align != 1) && (align & (align - 1)))
142 || size == 0 || align == 0)
147 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
148 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
149 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
150 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
151 domain = AMDGPU_GEM_DOMAIN_VRAM;
152 if (max_offset > adev->mc.real_vram_size)
154 place.fpfn = min_offset >> PAGE_SHIFT;
155 place.lpfn = max_offset >> PAGE_SHIFT;
156 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
159 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
160 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
161 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
162 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
163 domain = AMDGPU_GEM_DOMAIN_VRAM;
164 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
166 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
168 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
169 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
174 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
175 domain = AMDGPU_GEM_DOMAIN_GTT;
176 place.fpfn = min_offset >> PAGE_SHIFT;
177 place.lpfn = max_offset >> PAGE_SHIFT;
178 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
180 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
181 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
182 domain = AMDGPU_GEM_DOMAIN_GTT;
183 place.fpfn = min_offset >> PAGE_SHIFT;
184 place.lpfn = max_offset >> PAGE_SHIFT;
185 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
186 TTM_PL_FLAG_UNCACHED;
195 placement.placement = &place;
196 placement.num_placement = 1;
197 placement.busy_placement = &place;
198 placement.num_busy_placement = 1;
200 ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
202 NULL, &placement, NULL,
205 DRM_ERROR("(%d) bo create failed\n", ret);
208 *handle = (cgs_handle_t)obj;
213 static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
215 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
218 int r = amdgpu_bo_reserve(obj, false);
219 if (likely(r == 0)) {
220 amdgpu_bo_kunmap(obj);
221 amdgpu_bo_unpin(obj);
222 amdgpu_bo_unreserve(obj);
224 amdgpu_bo_unref(&obj);
230 static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
234 u64 min_offset, max_offset;
235 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
237 WARN_ON_ONCE(obj->placement.num_placement > 1);
239 min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
240 max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
242 r = amdgpu_bo_reserve(obj, false);
243 if (unlikely(r != 0))
245 r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT,
246 min_offset, max_offset, mcaddr);
247 amdgpu_bo_unreserve(obj);
251 static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
254 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
255 r = amdgpu_bo_reserve(obj, false);
256 if (unlikely(r != 0))
258 r = amdgpu_bo_unpin(obj);
259 amdgpu_bo_unreserve(obj);
263 static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
267 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
268 r = amdgpu_bo_reserve(obj, false);
269 if (unlikely(r != 0))
271 r = amdgpu_bo_kmap(obj, map);
272 amdgpu_bo_unreserve(obj);
276 static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
279 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
280 r = amdgpu_bo_reserve(obj, false);
281 if (unlikely(r != 0))
283 amdgpu_bo_kunmap(obj);
284 amdgpu_bo_unreserve(obj);
288 static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
291 return RREG32(offset);
294 static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
298 WREG32(offset, value);
301 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
302 enum cgs_ind_reg space,
307 case CGS_IND_REG__MMIO:
308 return RREG32_IDX(index);
309 case CGS_IND_REG__PCIE:
310 return RREG32_PCIE(index);
311 case CGS_IND_REG__SMC:
312 return RREG32_SMC(index);
313 case CGS_IND_REG__UVD_CTX:
314 return RREG32_UVD_CTX(index);
315 case CGS_IND_REG__DIDT:
316 return RREG32_DIDT(index);
317 case CGS_IND_REG_GC_CAC:
318 return RREG32_GC_CAC(index);
319 case CGS_IND_REG__AUDIO_ENDPT:
320 DRM_ERROR("audio endpt register access not implemented.\n");
323 WARN(1, "Invalid indirect register space");
327 static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
328 enum cgs_ind_reg space,
329 unsigned index, uint32_t value)
333 case CGS_IND_REG__MMIO:
334 return WREG32_IDX(index, value);
335 case CGS_IND_REG__PCIE:
336 return WREG32_PCIE(index, value);
337 case CGS_IND_REG__SMC:
338 return WREG32_SMC(index, value);
339 case CGS_IND_REG__UVD_CTX:
340 return WREG32_UVD_CTX(index, value);
341 case CGS_IND_REG__DIDT:
342 return WREG32_DIDT(index, value);
343 case CGS_IND_REG_GC_CAC:
344 return WREG32_GC_CAC(index, value);
345 case CGS_IND_REG__AUDIO_ENDPT:
346 DRM_ERROR("audio endpt register access not implemented.\n");
349 WARN(1, "Invalid indirect register space");
352 static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
356 int ret = pci_read_config_byte(adev->pdev, addr, &val);
357 if (WARN(ret, "pci_read_config_byte error"))
362 static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
366 int ret = pci_read_config_word(adev->pdev, addr, &val);
367 if (WARN(ret, "pci_read_config_word error"))
372 static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
377 int ret = pci_read_config_dword(adev->pdev, addr, &val);
378 if (WARN(ret, "pci_read_config_dword error"))
383 static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
387 int ret = pci_write_config_byte(adev->pdev, addr, value);
388 WARN(ret, "pci_write_config_byte error");
391 static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
395 int ret = pci_write_config_word(adev->pdev, addr, value);
396 WARN(ret, "pci_write_config_word error");
399 static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
403 int ret = pci_write_config_dword(adev->pdev, addr, value);
404 WARN(ret, "pci_write_config_dword error");
408 static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
409 enum cgs_resource_type resource_type,
412 uint64_t *resource_base)
416 if (resource_base == NULL)
419 switch (resource_type) {
420 case CGS_RESOURCE_TYPE_MMIO:
421 if (adev->rmmio_size == 0)
423 if ((offset + size) > adev->rmmio_size)
425 *resource_base = adev->rmmio_base;
427 case CGS_RESOURCE_TYPE_DOORBELL:
428 if (adev->doorbell.size == 0)
430 if ((offset + size) > adev->doorbell.size)
432 *resource_base = adev->doorbell.base;
434 case CGS_RESOURCE_TYPE_FB:
435 case CGS_RESOURCE_TYPE_IO:
436 case CGS_RESOURCE_TYPE_ROM:
442 static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
443 unsigned table, uint16_t *size,
444 uint8_t *frev, uint8_t *crev)
449 if (amdgpu_atom_parse_data_header(
450 adev->mode_info.atom_context, table, size,
451 frev, crev, &data_start))
452 return (uint8_t*)adev->mode_info.atom_context->bios +
458 static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
459 uint8_t *frev, uint8_t *crev)
463 if (amdgpu_atom_parse_cmd_header(
464 adev->mode_info.atom_context, table,
471 static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
476 return amdgpu_atom_execute_table(
477 adev->mode_info.atom_context, table, args);
480 static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
486 static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
492 static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
499 static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
500 enum cgs_clock clock, unsigned freq)
506 static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
507 enum cgs_engine engine, int powered)
515 static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
516 enum cgs_clock clock,
517 struct cgs_clock_limits *limits)
523 static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
524 const uint32_t *voltages)
526 DRM_ERROR("not implemented");
530 struct cgs_irq_params {
532 cgs_irq_source_set_func_t set;
533 cgs_irq_handler_func_t handler;
537 static int cgs_set_irq_state(struct amdgpu_device *adev,
538 struct amdgpu_irq_src *src,
540 enum amdgpu_interrupt_state state)
542 struct cgs_irq_params *irq_params =
543 (struct cgs_irq_params *)src->data;
546 if (!irq_params->set)
548 return irq_params->set(irq_params->private_data,
554 static int cgs_process_irq(struct amdgpu_device *adev,
555 struct amdgpu_irq_src *source,
556 struct amdgpu_iv_entry *entry)
558 struct cgs_irq_params *irq_params =
559 (struct cgs_irq_params *)source->data;
562 if (!irq_params->handler)
564 return irq_params->handler(irq_params->private_data,
569 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
570 .set = cgs_set_irq_state,
571 .process = cgs_process_irq,
574 static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id,
576 cgs_irq_source_set_func_t set,
577 cgs_irq_handler_func_t handler,
582 struct cgs_irq_params *irq_params;
583 struct amdgpu_irq_src *source =
584 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
588 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
593 source->num_types = num_types;
594 source->funcs = &cgs_irq_funcs;
595 irq_params->src_id = src_id;
596 irq_params->set = set;
597 irq_params->handler = handler;
598 irq_params->private_data = private_data;
599 source->data = (void *)irq_params;
600 ret = amdgpu_irq_add_id(adev, src_id, source);
609 static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
612 return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
615 static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
618 return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
621 static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
622 enum amd_ip_block_type block_type,
623 enum amd_clockgating_state state)
628 for (i = 0; i < adev->num_ip_blocks; i++) {
629 if (!adev->ip_block_status[i].valid)
632 if (adev->ip_blocks[i].type == block_type) {
633 r = adev->ip_blocks[i].funcs->set_clockgating_state(
642 static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
643 enum amd_ip_block_type block_type,
644 enum amd_powergating_state state)
649 for (i = 0; i < adev->num_ip_blocks; i++) {
650 if (!adev->ip_block_status[i].valid)
653 if (adev->ip_blocks[i].type == block_type) {
654 r = adev->ip_blocks[i].funcs->set_powergating_state(
664 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
667 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
670 case CGS_UCODE_ID_SDMA0:
671 result = AMDGPU_UCODE_ID_SDMA0;
673 case CGS_UCODE_ID_SDMA1:
674 result = AMDGPU_UCODE_ID_SDMA1;
676 case CGS_UCODE_ID_CP_CE:
677 result = AMDGPU_UCODE_ID_CP_CE;
679 case CGS_UCODE_ID_CP_PFP:
680 result = AMDGPU_UCODE_ID_CP_PFP;
682 case CGS_UCODE_ID_CP_ME:
683 result = AMDGPU_UCODE_ID_CP_ME;
685 case CGS_UCODE_ID_CP_MEC:
686 case CGS_UCODE_ID_CP_MEC_JT1:
687 result = AMDGPU_UCODE_ID_CP_MEC1;
689 case CGS_UCODE_ID_CP_MEC_JT2:
690 if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11
691 || adev->asic_type == CHIP_POLARIS10)
692 result = AMDGPU_UCODE_ID_CP_MEC2;
694 result = AMDGPU_UCODE_ID_CP_MEC1;
696 case CGS_UCODE_ID_RLC_G:
697 result = AMDGPU_UCODE_ID_RLC_G;
700 DRM_ERROR("Firmware type not supported\n");
705 static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
708 if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
709 release_firmware(adev->pm.fw);
712 /* cannot release other firmware because they are not created by cgs */
716 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
717 enum cgs_ucode_id type)
723 case CGS_UCODE_ID_SDMA0:
724 fw_version = adev->sdma.instance[0].fw_version;
726 case CGS_UCODE_ID_SDMA1:
727 fw_version = adev->sdma.instance[1].fw_version;
729 case CGS_UCODE_ID_CP_CE:
730 fw_version = adev->gfx.ce_fw_version;
732 case CGS_UCODE_ID_CP_PFP:
733 fw_version = adev->gfx.pfp_fw_version;
735 case CGS_UCODE_ID_CP_ME:
736 fw_version = adev->gfx.me_fw_version;
738 case CGS_UCODE_ID_CP_MEC:
739 fw_version = adev->gfx.mec_fw_version;
741 case CGS_UCODE_ID_CP_MEC_JT1:
742 fw_version = adev->gfx.mec_fw_version;
744 case CGS_UCODE_ID_CP_MEC_JT2:
745 fw_version = adev->gfx.mec_fw_version;
747 case CGS_UCODE_ID_RLC_G:
748 fw_version = adev->gfx.rlc_fw_version;
751 DRM_ERROR("firmware type %d do not have version\n", type);
757 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
758 enum cgs_ucode_id type,
759 struct cgs_firmware_info *info)
763 if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
766 const struct gfx_firmware_header_v1_0 *header;
767 enum AMDGPU_UCODE_ID id;
768 struct amdgpu_firmware_info *ucode;
770 id = fw_type_convert(cgs_device, type);
771 ucode = &adev->firmware.ucode[id];
772 if (ucode->fw == NULL)
775 gpu_addr = ucode->mc_addr;
776 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
777 data_size = le32_to_cpu(header->header.ucode_size_bytes);
779 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
780 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
781 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
782 data_size = le32_to_cpu(header->jt_size) << 2;
784 info->mc_addr = gpu_addr;
785 info->image_size = data_size;
786 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
787 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
788 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
790 char fw_name[30] = {0};
793 uint32_t ucode_start_address;
795 const struct smc_firmware_header_v1_0 *hdr;
798 switch (adev->asic_type) {
800 strcpy(fw_name, "amdgpu/topaz_smc.bin");
803 strcpy(fw_name, "amdgpu/tonga_smc.bin");
806 strcpy(fw_name, "amdgpu/fiji_smc.bin");
809 if (type == CGS_UCODE_ID_SMU)
810 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
811 else if (type == CGS_UCODE_ID_SMU_SK)
812 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
815 if (type == CGS_UCODE_ID_SMU)
816 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
817 else if (type == CGS_UCODE_ID_SMU_SK)
818 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
821 DRM_ERROR("SMC firmware not supported\n");
825 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
827 DRM_ERROR("Failed to request firmware\n");
831 err = amdgpu_ucode_validate(adev->pm.fw);
833 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
834 release_firmware(adev->pm.fw);
840 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
841 amdgpu_ucode_print_smc_hdr(&hdr->header);
842 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
843 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
844 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
845 src = (const uint8_t *)(adev->pm.fw->data +
846 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
848 info->version = adev->pm.fw_version;
849 info->image_size = ucode_size;
850 info->ucode_start_address = ucode_start_address;
851 info->kptr = (void *)src;
856 static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
857 struct cgs_system_info *sys_info)
861 if (NULL == sys_info)
864 if (sizeof(struct cgs_system_info) != sys_info->size)
867 switch (sys_info->info_id) {
868 case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
869 sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
871 case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
872 sys_info->value = adev->pm.pcie_gen_mask;
874 case CGS_SYSTEM_INFO_PCIE_MLW:
875 sys_info->value = adev->pm.pcie_mlw_mask;
877 case CGS_SYSTEM_INFO_PCIE_DEV:
878 sys_info->value = adev->pdev->device;
880 case CGS_SYSTEM_INFO_PCIE_REV:
881 sys_info->value = adev->pdev->revision;
883 case CGS_SYSTEM_INFO_CG_FLAGS:
884 sys_info->value = adev->cg_flags;
886 case CGS_SYSTEM_INFO_PG_FLAGS:
887 sys_info->value = adev->pg_flags;
889 case CGS_SYSTEM_INFO_GFX_CU_INFO:
890 sys_info->value = adev->gfx.cu_info.number;
892 case CGS_SYSTEM_INFO_GFX_SE_INFO:
893 sys_info->value = adev->gfx.config.max_shader_engines;
895 case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:
896 sys_info->value = adev->pdev->subsystem_device;
898 case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
899 sys_info->value = adev->pdev->subsystem_vendor;
908 static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
909 struct cgs_display_info *info)
912 struct amdgpu_crtc *amdgpu_crtc;
913 struct drm_device *ddev = adev->ddev;
914 struct drm_crtc *crtc;
915 uint32_t line_time_us, vblank_lines;
916 struct cgs_mode_info *mode_info;
921 mode_info = info->mode_info;
923 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
924 list_for_each_entry(crtc,
925 &ddev->mode_config.crtc_list, head) {
926 amdgpu_crtc = to_amdgpu_crtc(crtc);
928 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
929 info->display_count++;
931 if (mode_info != NULL &&
932 crtc->enabled && amdgpu_crtc->enabled &&
933 amdgpu_crtc->hw_mode.clock) {
934 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
935 amdgpu_crtc->hw_mode.clock;
936 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
937 amdgpu_crtc->hw_mode.crtc_vdisplay +
938 (amdgpu_crtc->v_border * 2);
939 mode_info->vblank_time_us = vblank_lines * line_time_us;
940 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
941 mode_info->ref_clock = adev->clock.spll.reference_freq;
951 static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
955 adev->pm.dpm_enabled = enabled;
960 /** \brief evaluate acpi namespace object, handle or pathname must be valid
962 * \param info input/output arguments for the control method
966 #if defined(CONFIG_ACPI)
967 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
968 struct cgs_acpi_method_info *info)
972 struct acpi_object_list input;
973 struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
974 union acpi_object *params, *obj;
975 uint8_t name[5] = {'\0'};
976 struct cgs_acpi_method_argument *argument;
981 handle = ACPI_HANDLE(&adev->pdev->dev);
985 memset(&input, 0, sizeof(struct acpi_object_list));
987 /* validate input info */
988 if (info->size != sizeof(struct cgs_acpi_method_info))
991 input.count = info->input_count;
992 if (info->input_count > 0) {
993 if (info->pinput_argument == NULL)
995 argument = info->pinput_argument;
996 for (i = 0; i < info->input_count; i++) {
997 if (((argument->type == ACPI_TYPE_STRING) ||
998 (argument->type == ACPI_TYPE_BUFFER)) &&
999 (argument->pointer == NULL))
1005 if (info->output_count > 0) {
1006 if (info->poutput_argument == NULL)
1008 argument = info->poutput_argument;
1009 for (i = 0; i < info->output_count; i++) {
1010 if (((argument->type == ACPI_TYPE_STRING) ||
1011 (argument->type == ACPI_TYPE_BUFFER))
1012 && (argument->pointer == NULL))
1018 /* The path name passed to acpi_evaluate_object should be null terminated */
1019 if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
1020 strncpy(name, (char *)&(info->name), sizeof(uint32_t));
1024 /* parse input parameters */
1025 if (input.count > 0) {
1026 input.pointer = params =
1027 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
1031 argument = info->pinput_argument;
1033 for (i = 0; i < input.count; i++) {
1034 params->type = argument->type;
1035 switch (params->type) {
1036 case ACPI_TYPE_INTEGER:
1037 params->integer.value = argument->value;
1039 case ACPI_TYPE_STRING:
1040 params->string.length = argument->data_length;
1041 params->string.pointer = argument->pointer;
1043 case ACPI_TYPE_BUFFER:
1044 params->buffer.length = argument->data_length;
1045 params->buffer.pointer = argument->pointer;
1055 /* parse output info */
1056 count = info->output_count;
1057 argument = info->poutput_argument;
1059 /* evaluate the acpi method */
1060 status = acpi_evaluate_object(handle, name, &input, &output);
1062 if (ACPI_FAILURE(status)) {
1067 /* return the output info */
1068 obj = output.pointer;
1071 if ((obj->type != ACPI_TYPE_PACKAGE) ||
1072 (obj->package.count != count)) {
1076 params = obj->package.elements;
1080 if (params == NULL) {
1085 for (i = 0; i < count; i++) {
1086 if (argument->type != params->type) {
1090 switch (params->type) {
1091 case ACPI_TYPE_INTEGER:
1092 argument->value = params->integer.value;
1094 case ACPI_TYPE_STRING:
1095 if ((params->string.length != argument->data_length) ||
1096 (params->string.pointer == NULL)) {
1100 strncpy(argument->pointer,
1101 params->string.pointer,
1102 params->string.length);
1104 case ACPI_TYPE_BUFFER:
1105 if (params->buffer.pointer == NULL) {
1109 memcpy(argument->pointer,
1110 params->buffer.pointer,
1111 argument->data_length);
1124 kfree((void *)input.pointer);
1128 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
1129 struct cgs_acpi_method_info *info)
1135 static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
1136 uint32_t acpi_method,
1137 uint32_t acpi_function,
1138 void *pinput, void *poutput,
1139 uint32_t output_count,
1140 uint32_t input_size,
1141 uint32_t output_size)
1143 struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
1144 struct cgs_acpi_method_argument acpi_output = {0};
1145 struct cgs_acpi_method_info info = {0};
1147 acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
1148 acpi_input[0].data_length = sizeof(uint32_t);
1149 acpi_input[0].value = acpi_function;
1151 acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
1152 acpi_input[1].data_length = input_size;
1153 acpi_input[1].pointer = pinput;
1155 acpi_output.type = CGS_ACPI_TYPE_BUFFER;
1156 acpi_output.data_length = output_size;
1157 acpi_output.pointer = poutput;
1159 info.size = sizeof(struct cgs_acpi_method_info);
1160 info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
1161 info.input_count = 2;
1162 info.name = acpi_method;
1163 info.pinput_argument = acpi_input;
1164 info.output_count = output_count;
1165 info.poutput_argument = &acpi_output;
1167 return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
1170 static const struct cgs_ops amdgpu_cgs_ops = {
1171 amdgpu_cgs_gpu_mem_info,
1172 amdgpu_cgs_gmap_kmem,
1173 amdgpu_cgs_gunmap_kmem,
1174 amdgpu_cgs_alloc_gpu_mem,
1175 amdgpu_cgs_free_gpu_mem,
1176 amdgpu_cgs_gmap_gpu_mem,
1177 amdgpu_cgs_gunmap_gpu_mem,
1178 amdgpu_cgs_kmap_gpu_mem,
1179 amdgpu_cgs_kunmap_gpu_mem,
1180 amdgpu_cgs_read_register,
1181 amdgpu_cgs_write_register,
1182 amdgpu_cgs_read_ind_register,
1183 amdgpu_cgs_write_ind_register,
1184 amdgpu_cgs_read_pci_config_byte,
1185 amdgpu_cgs_read_pci_config_word,
1186 amdgpu_cgs_read_pci_config_dword,
1187 amdgpu_cgs_write_pci_config_byte,
1188 amdgpu_cgs_write_pci_config_word,
1189 amdgpu_cgs_write_pci_config_dword,
1190 amdgpu_cgs_get_pci_resource,
1191 amdgpu_cgs_atom_get_data_table,
1192 amdgpu_cgs_atom_get_cmd_table_revs,
1193 amdgpu_cgs_atom_exec_cmd_table,
1194 amdgpu_cgs_create_pm_request,
1195 amdgpu_cgs_destroy_pm_request,
1196 amdgpu_cgs_set_pm_request,
1197 amdgpu_cgs_pm_request_clock,
1198 amdgpu_cgs_pm_request_engine,
1199 amdgpu_cgs_pm_query_clock_limits,
1200 amdgpu_cgs_set_camera_voltages,
1201 amdgpu_cgs_get_firmware_info,
1202 amdgpu_cgs_rel_firmware,
1203 amdgpu_cgs_set_powergating_state,
1204 amdgpu_cgs_set_clockgating_state,
1205 amdgpu_cgs_get_active_displays_info,
1206 amdgpu_cgs_notify_dpm_enabled,
1207 amdgpu_cgs_call_acpi_method,
1208 amdgpu_cgs_query_system_info,
1211 static const struct cgs_os_ops amdgpu_cgs_os_ops = {
1212 amdgpu_cgs_add_irq_source,
1217 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
1219 struct amdgpu_cgs_device *cgs_device =
1220 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
1223 DRM_ERROR("Couldn't allocate CGS device structure\n");
1227 cgs_device->base.ops = &amdgpu_cgs_ops;
1228 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
1229 cgs_device->adev = adev;
1231 return (struct cgs_device *)cgs_device;
1234 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)