drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  89
  90 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
  91 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
  92 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
  93 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
  94 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
  95 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
  96
  97 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  98 {
  99         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 100         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
 101         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 102         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 103         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 104         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 105         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 106         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 107         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 108         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 109         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 110         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 111         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 112         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 113         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 114         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 115 };
 116
 117 static const u32 golden_settings_tonga_a11[] =
 118 {
 119         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 120         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 121         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 122         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 123         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 124         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 125         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 126         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 127         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 128         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 129         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 130         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 131         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 132         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 133         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 134 };
 135
 136 static const u32 tonga_golden_common_all[] =
 137 {
 138         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 139         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 140         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 141         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 142         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 143         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 144         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 145         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 146 };
 147
 148 static const u32 tonga_mgcg_cgcg_init[] =
 149 {
 150         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 151         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 152         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 153         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 154         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 155         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 156         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 157         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 158         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 159         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 160         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 161         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 162         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 163         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 164         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 165         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 166         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 167         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 168         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 169         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 170         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 171         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 172         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 173         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 174         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 175         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 176         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 177         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 178         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 179         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 180         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 181         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 182         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 183         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 184         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 185         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 186         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 187         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 188         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 189         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 190         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 191         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 192         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 193         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 194         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 195         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 196         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 197         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 198         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 199         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 200         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 201         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 202         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 203         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 204         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 205         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 206         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 207         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 208         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 209         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 210         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 211         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 212         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 213         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 214         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 215         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 216         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 217         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 218         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 219         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 220         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 221         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 222         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 223         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 224         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 225 };
 226
 227 static const u32 fiji_golden_common_all[] =
 228 {
 229         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 230         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 231         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 232         mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
 233         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 234         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 235         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 236         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 237 };
 238
 239 static const u32 golden_settings_fiji_a10[] =
 240 {
 241         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 242         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 243         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 244         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
 245         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 246         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 247         mmTCC_CTRL, 0x00100000, 0xf30fff7f,
 248         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 249         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
 250         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
 251 };
 252
 253 static const u32 fiji_mgcg_cgcg_init[] =
 254 {
 255         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
 256         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 257         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 258         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 259         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 260         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 261         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 262         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 263         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 264         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 265         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 266         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 267         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 268         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 269         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 270         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 271         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 272         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 273         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 274         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 275         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 276         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 277         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 278         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 279         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 280         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 281         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 282         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 283         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 284         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 285         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 286         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 287         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 288         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 289         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 290 };
 291
 292 static const u32 golden_settings_iceland_a11[] =
 293 {
 294         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 295         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 296         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 297         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 298         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 299         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 300         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 301         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 302         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 303         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 304         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 305         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 306         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 307         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 308         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 309 };
 310
 311 static const u32 iceland_golden_common_all[] =
 312 {
 313         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 314         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 315         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 316         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 317         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 318         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 319         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 320         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 321 };
 322
 323 static const u32 iceland_mgcg_cgcg_init[] =
 324 {
 325         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 326         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 327         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 328         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 329         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 330         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 331         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 332         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 333         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 334         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 335         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 336         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 337         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 338         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 339         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 340         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 341         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 342         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 343         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 344         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 345         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 346         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 347         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 348         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 349         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 350         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 351         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 352         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 353         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 354         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 355         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 356         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 357         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 358         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 359         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 360         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 361         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 362         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 363         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 364         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 365         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 366         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 367         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 368         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 369         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 370         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 371         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 372         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 373         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 374         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 375         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 376         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 377         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 378         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 379         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 380         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 381         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 382         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 383         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 384         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 385         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 386         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 387         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 388         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 389 };
 390
 391 static const u32 cz_golden_settings_a11[] =
 392 {
 393         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 394         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 395         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 396         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 397         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 398         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 399         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 400         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 401         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 402         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 403 };
 404
 405 static const u32 cz_golden_common_all[] =
 406 {
 407         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 408         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 409         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 410         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 411         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 412         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 413         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 414         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 415 };
 416
 417 static const u32 cz_mgcg_cgcg_init[] =
 418 {
 419         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 420         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 421         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 422         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 423         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 424         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 425         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 426         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 427         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 428         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 429         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 430         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 431         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 432         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 433         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 434         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 435         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 436         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 437         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 438         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 439         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 440         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 441         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 442         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 443         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 444         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 445         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 446         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 447         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 448         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 449         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 450         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 451         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 452         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 453         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 454         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 455         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 456         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 457         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 458         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 459         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 460         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 461         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 462         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 463         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 464         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 465         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 466         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 467         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 468         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 469         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 470         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 471         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 472         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 473         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 474         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 475         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 476         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 477         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 478         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 479         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 480         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 481         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 482         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 483         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 484         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 485         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 486         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 487         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 488         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 489         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 490         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 491         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 492         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 493         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 494 };
 495
 496 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 497 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 498 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 499
 500 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 501 {
 502         switch (adev->asic_type) {
 503         case CHIP_TOPAZ:
 504                 amdgpu_program_register_sequence(adev,
 505                                                  iceland_mgcg_cgcg_init,
 506                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 507                 amdgpu_program_register_sequence(adev,
 508                                                  golden_settings_iceland_a11,
 509                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 510                 amdgpu_program_register_sequence(adev,
 511                                                  iceland_golden_common_all,
 512                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 513                 break;
 514         case CHIP_FIJI:
 515                 amdgpu_program_register_sequence(adev,
 516                                                  fiji_mgcg_cgcg_init,
 517                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 518                 amdgpu_program_register_sequence(adev,
 519                                                  golden_settings_fiji_a10,
 520                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 521                 amdgpu_program_register_sequence(adev,
 522                                                  fiji_golden_common_all,
 523                                                  (const u32)ARRAY_SIZE(fiji_golden_common_all));
 524                 break;
 525
 526         case CHIP_TONGA:
 527                 amdgpu_program_register_sequence(adev,
 528                                                  tonga_mgcg_cgcg_init,
 529                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 530                 amdgpu_program_register_sequence(adev,
 531                                                  golden_settings_tonga_a11,
 532                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 533                 amdgpu_program_register_sequence(adev,
 534                                                  tonga_golden_common_all,
 535                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 536                 break;
 537         case CHIP_CARRIZO:
 538                 amdgpu_program_register_sequence(adev,
 539                                                  cz_mgcg_cgcg_init,
 540                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 541                 amdgpu_program_register_sequence(adev,
 542                                                  cz_golden_settings_a11,
 543                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 544                 amdgpu_program_register_sequence(adev,
 545                                                  cz_golden_common_all,
 546                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 547                 break;
 548         default:
 549                 break;
 550         }
 551 }
 552
 553 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 554 {
 555         int i;
 556
 557         adev->gfx.scratch.num_reg = 7;
 558         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 559         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 560                 adev->gfx.scratch.free[i] = true;
 561                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 562         }
 563 }
 564
 565 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 566 {
 567         struct amdgpu_device *adev = ring->adev;
 568         uint32_t scratch;
 569         uint32_t tmp = 0;
 570         unsigned i;
 571         int r;
 572
 573         r = amdgpu_gfx_scratch_get(adev, &scratch);
 574         if (r) {
 575                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 576                 return r;
 577         }
 578         WREG32(scratch, 0xCAFEDEAD);
 579         r = amdgpu_ring_lock(ring, 3);
 580         if (r) {
 581                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 582                           ring->idx, r);
 583                 amdgpu_gfx_scratch_free(adev, scratch);
 584                 return r;
 585         }
 586         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 587         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 588         amdgpu_ring_write(ring, 0xDEADBEEF);
 589         amdgpu_ring_unlock_commit(ring);
 590
 591         for (i = 0; i < adev->usec_timeout; i++) {
 592                 tmp = RREG32(scratch);
 593                 if (tmp == 0xDEADBEEF)
 594                         break;
 595                 DRM_UDELAY(1);
 596         }
 597         if (i < adev->usec_timeout) {
 598                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 599                          ring->idx, i);
 600         } else {
 601                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 602                           ring->idx, scratch, tmp);
 603                 r = -EINVAL;
 604         }
 605         amdgpu_gfx_scratch_free(adev, scratch);
 606         return r;
 607 }
 608
 609 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 610 {
 611         struct amdgpu_device *adev = ring->adev;
 612         struct amdgpu_ib ib;
 613         struct fence *f = NULL;
 614         uint32_t scratch;
 615         uint32_t tmp = 0;
 616         unsigned i;
 617         int r;
 618
 619         r = amdgpu_gfx_scratch_get(adev, &scratch);
 620         if (r) {
 621                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 622                 return r;
 623         }
 624         WREG32(scratch, 0xCAFEDEAD);
 625         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 626         if (r) {
 627                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 628                 goto err1;
 629         }
 630         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 631         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 632         ib.ptr[2] = 0xDEADBEEF;
 633         ib.length_dw = 3;
 634
 635         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 636                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 637                                                  &f);
 638         if (r)
 639                 goto err2;
 640
 641         r = fence_wait(f, false);
 642         if (r) {
 643                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 644                 goto err2;
 645         }
 646         for (i = 0; i < adev->usec_timeout; i++) {
 647                 tmp = RREG32(scratch);
 648                 if (tmp == 0xDEADBEEF)
 649                         break;
 650                 DRM_UDELAY(1);
 651         }
 652         if (i < adev->usec_timeout) {
 653                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 654                          ring->idx, i);
 655                 goto err2;
 656         } else {
 657                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 658                           scratch, tmp);
 659                 r = -EINVAL;
 660         }
 661 err2:
 662         amdgpu_ib_free(adev, &ib);
 663 err1:
 664         amdgpu_gfx_scratch_free(adev, scratch);
 665         return r;
 666 }
 667
 668 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 669 {
 670         const char *chip_name;
 671         char fw_name[30];
 672         int err;
 673         struct amdgpu_firmware_info *info = NULL;
 674         const struct common_firmware_header *header = NULL;
 675         const struct gfx_firmware_header_v1_0 *cp_hdr;
 676
 677         DRM_DEBUG("\n");
 678
 679         switch (adev->asic_type) {
 680         case CHIP_TOPAZ:
 681                 chip_name = "topaz";
 682                 break;
 683         case CHIP_TONGA:
 684                 chip_name = "tonga";
 685                 break;
 686         case CHIP_CARRIZO:
 687                 chip_name = "carrizo";
 688                 break;
 689         case CHIP_FIJI:
 690                 chip_name = "fiji";
 691                 break;
 692         default:
 693                 BUG();
 694         }
 695
 696         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 697         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 698         if (err)
 699                 goto out;
 700         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 701         if (err)
 702                 goto out;
 703         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 704         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 705         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 706
 707         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 708         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 709         if (err)
 710                 goto out;
 711         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 712         if (err)
 713                 goto out;
 714         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 715         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 716         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 717
 718         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 719         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 720         if (err)
 721                 goto out;
 722         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 723         if (err)
 724                 goto out;
 725         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 726         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 727         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 728
 729         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 730         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 731         if (err)
 732                 goto out;
 733         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 734         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 735         adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 736         adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 737
 738         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 739         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 740         if (err)
 741                 goto out;
 742         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 743         if (err)
 744                 goto out;
 745         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 746         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 747         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 748
 749         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 750         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 751         if (!err) {
 752                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 753                 if (err)
 754                         goto out;
 755                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 756                                                 adev->gfx.mec2_fw->data;
 757                 adev->gfx.mec2_fw_version = le32_to_cpu(
 758                                                 cp_hdr->header.ucode_version);
 759                 adev->gfx.mec2_feature_version = le32_to_cpu(
 760                                                 cp_hdr->ucode_feature_version);
 761         } else {
 762                 err = 0;
 763                 adev->gfx.mec2_fw = NULL;
 764         }
 765
 766         if (adev->firmware.smu_load) {
 767                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 768                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 769                 info->fw = adev->gfx.pfp_fw;
 770                 header = (const struct common_firmware_header *)info->fw->data;
 771                 adev->firmware.fw_size +=
 772                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 773
 774                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 775                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 776                 info->fw = adev->gfx.me_fw;
 777                 header = (const struct common_firmware_header *)info->fw->data;
 778                 adev->firmware.fw_size +=
 779                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 780
 781                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 782                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 783                 info->fw = adev->gfx.ce_fw;
 784                 header = (const struct common_firmware_header *)info->fw->data;
 785                 adev->firmware.fw_size +=
 786                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 787
 788                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 789                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 790                 info->fw = adev->gfx.rlc_fw;
 791                 header = (const struct common_firmware_header *)info->fw->data;
 792                 adev->firmware.fw_size +=
 793                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 794
 795                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 796                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 797                 info->fw = adev->gfx.mec_fw;
 798                 header = (const struct common_firmware_header *)info->fw->data;
 799                 adev->firmware.fw_size +=
 800                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 801
 802                 if (adev->gfx.mec2_fw) {
 803                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 804                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 805                         info->fw = adev->gfx.mec2_fw;
 806                         header = (const struct common_firmware_header *)info->fw->data;
 807                         adev->firmware.fw_size +=
 808                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 809                 }
 810
 811         }
 812
 813 out:
 814         if (err) {
 815                 dev_err(adev->dev,
 816                         "gfx8: Failed to load firmware \"%s\"\n",
 817                         fw_name);
 818                 release_firmware(adev->gfx.pfp_fw);
 819                 adev->gfx.pfp_fw = NULL;
 820                 release_firmware(adev->gfx.me_fw);
 821                 adev->gfx.me_fw = NULL;
 822                 release_firmware(adev->gfx.ce_fw);
 823                 adev->gfx.ce_fw = NULL;
 824                 release_firmware(adev->gfx.rlc_fw);
 825                 adev->gfx.rlc_fw = NULL;
 826                 release_firmware(adev->gfx.mec_fw);
 827                 adev->gfx.mec_fw = NULL;
 828                 release_firmware(adev->gfx.mec2_fw);
 829                 adev->gfx.mec2_fw = NULL;
 830         }
 831         return err;
 832 }
 833
 834 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 835 {
 836         int r;
 837
 838         if (adev->gfx.mec.hpd_eop_obj) {
 839                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 840                 if (unlikely(r != 0))
 841                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 842                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 843                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 844
 845                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 846                 adev->gfx.mec.hpd_eop_obj = NULL;
 847         }
 848 }
 849
 850 #define MEC_HPD_SIZE 2048
 851
 852 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 853 {
 854         int r;
 855         u32 *hpd;
 856
 857         /*
 858          * we assign only 1 pipe because all other pipes will
 859          * be handled by KFD
 860          */
 861         adev->gfx.mec.num_mec = 1;
 862         adev->gfx.mec.num_pipe = 1;
 863         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 864
 865         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 866                 r = amdgpu_bo_create(adev,
 867                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 868                                      PAGE_SIZE, true,
 869                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
 870                                      &adev->gfx.mec.hpd_eop_obj);
 871                 if (r) {
 872                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 873                         return r;
 874                 }
 875         }
 876
 877         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 878         if (unlikely(r != 0)) {
 879                 gfx_v8_0_mec_fini(adev);
 880                 return r;
 881         }
 882         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 883                           &adev->gfx.mec.hpd_eop_gpu_addr);
 884         if (r) {
 885                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 886                 gfx_v8_0_mec_fini(adev);
 887                 return r;
 888         }
 889         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 890         if (r) {
 891                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 892                 gfx_v8_0_mec_fini(adev);
 893                 return r;
 894         }
 895
 896         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 897
 898         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 899         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 900
 901         return 0;
 902 }
 903
 904 static int gfx_v8_0_sw_init(void *handle)
 905 {
 906         int i, r;
 907         struct amdgpu_ring *ring;
 908         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 909
 910         /* EOP Event */
 911         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
 912         if (r)
 913                 return r;
 914
 915         /* Privileged reg */
 916         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
 917         if (r)
 918                 return r;
 919
 920         /* Privileged inst */
 921         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
 922         if (r)
 923                 return r;
 924
 925         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 926
 927         gfx_v8_0_scratch_init(adev);
 928
 929         r = gfx_v8_0_init_microcode(adev);
 930         if (r) {
 931                 DRM_ERROR("Failed to load gfx firmware!\n");
 932                 return r;
 933         }
 934
 935         r = gfx_v8_0_mec_init(adev);
 936         if (r) {
 937                 DRM_ERROR("Failed to init MEC BOs!\n");
 938                 return r;
 939         }
 940
 941         r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
 942         if (r) {
 943                 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
 944                 return r;
 945         }
 946
 947         /* set up the gfx ring */
 948         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 949                 ring = &adev->gfx.gfx_ring[i];
 950                 ring->ring_obj = NULL;
 951                 sprintf(ring->name, "gfx");
 952                 /* no gfx doorbells on iceland */
 953                 if (adev->asic_type != CHIP_TOPAZ) {
 954                         ring->use_doorbell = true;
 955                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
 956                 }
 957
 958                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 959                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 960                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
 961                                      AMDGPU_RING_TYPE_GFX);
 962                 if (r)
 963                         return r;
 964         }
 965
 966         /* set up the compute queues */
 967         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 968                 unsigned irq_type;
 969
 970                 /* max 32 queues per MEC */
 971                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
 972                         DRM_ERROR("Too many (%d) compute rings!\n", i);
 973                         break;
 974                 }
 975                 ring = &adev->gfx.compute_ring[i];
 976                 ring->ring_obj = NULL;
 977                 ring->use_doorbell = true;
 978                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
 979                 ring->me = 1; /* first MEC */
 980                 ring->pipe = i / 8;
 981                 ring->queue = i % 8;
 982                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
 983                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
 984                 /* type-2 packets are deprecated on MEC, use type-3 instead */
 985                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 986                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 987                                      &adev->gfx.eop_irq, irq_type,
 988                                      AMDGPU_RING_TYPE_COMPUTE);
 989                 if (r)
 990                         return r;
 991         }
 992
 993         /* reserve GDS, GWS and OA resource for gfx */
 994         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
 995                         PAGE_SIZE, true,
 996                         AMDGPU_GEM_DOMAIN_GDS, 0,
 997                         NULL, &adev->gds.gds_gfx_bo);
 998         if (r)
 999                 return r;
1000
1001         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1002                 PAGE_SIZE, true,
1003                 AMDGPU_GEM_DOMAIN_GWS, 0,
1004                 NULL, &adev->gds.gws_gfx_bo);
1005         if (r)
1006                 return r;
1007
1008         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1009                         PAGE_SIZE, true,
1010                         AMDGPU_GEM_DOMAIN_OA, 0,
1011                         NULL, &adev->gds.oa_gfx_bo);
1012         if (r)
1013                 return r;
1014
1015         adev->gfx.ce_ram_size = 0x8000;
1016
1017         return 0;
1018 }
1019
1020 static int gfx_v8_0_sw_fini(void *handle)
1021 {
1022         int i;
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1026         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1027         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1028
1029         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1030                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1031         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1032                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1033
1034         amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
1035
1036         gfx_v8_0_mec_fini(adev);
1037
1038         return 0;
1039 }
1040
1041 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1042 {
1043         const u32 num_tile_mode_states = 32;
1044         const u32 num_secondary_tile_mode_states = 16;
1045         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1046
1047         switch (adev->gfx.config.mem_row_size_in_kb) {
1048         case 1:
1049                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1050                 break;
1051         case 2:
1052         default:
1053                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1054                 break;
1055         case 4:
1056                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1057                 break;
1058         }
1059
1060         switch (adev->asic_type) {
1061         case CHIP_TOPAZ:
1062                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1063                         switch (reg_offset) {
1064                         case 0:
1065                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1067                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1068                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069                                 break;
1070                         case 1:
1071                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1072                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1073                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1074                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1075                                 break;
1076                         case 2:
1077                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1078                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1079                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1080                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1081                                 break;
1082                         case 3:
1083                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1084                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1085                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1086                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1087                                 break;
1088                         case 4:
1089                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1090                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1091                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1092                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1093                                 break;
1094                         case 5:
1095                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1097                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1098                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1099                                 break;
1100                         case 6:
1101                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1102                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1103                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1104                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1105                                 break;
1106                         case 8:
1107                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1108                                                 PIPE_CONFIG(ADDR_SURF_P2));
1109                                 break;
1110                         case 9:
1111                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1112                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1113                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1114                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1115                                 break;
1116                         case 10:
1117                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1118                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1119                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1120                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1121                                 break;
1122                         case 11:
1123                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1124                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1125                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1126                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1127                                 break;
1128                         case 13:
1129                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1130                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1131                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1132                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1133                                 break;
1134                         case 14:
1135                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1136                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1137                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1139                                 break;
1140                         case 15:
1141                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1142                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1143                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1144                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1145                                 break;
1146                         case 16:
1147                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1148                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1149                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1150                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1151                                 break;
1152                         case 18:
1153                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1154                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1155                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1156                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1157                                 break;
1158                         case 19:
1159                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1160                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1161                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1162                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1163                                 break;
1164                         case 20:
1165                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1166                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1167                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1168                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1169                                 break;
1170                         case 21:
1171                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1172                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1173                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1174                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1175                                 break;
1176                         case 22:
1177                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1178                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1179                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1180                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1181                                 break;
1182                         case 24:
1183                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1184                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1185                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1186                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1187                                 break;
1188                         case 25:
1189                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1190                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1191                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1192                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1193                                 break;
1194                         case 26:
1195                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1196                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1197                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1198                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1199                                 break;
1200                         case 27:
1201                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1202                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1203                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1204                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1205                                 break;
1206                         case 28:
1207                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1208                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1209                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1210                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1211                                 break;
1212                         case 29:
1213                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1214                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1215                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1216                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1217                                 break;
1218                         case 7:
1219                         case 12:
1220                         case 17:
1221                         case 23:
1222                                 /* unused idx */
1223                                 continue;
1224                         default:
1225                                 gb_tile_moden = 0;
1226                                 break;
1227                         };
1228                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1229                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1230                 }
1231                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1232                         switch (reg_offset) {
1233                         case 0:
1234                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1235                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1236                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1237                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1238                                 break;
1239                         case 1:
1240                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1241                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1242                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1243                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1244                                 break;
1245                         case 2:
1246                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1247                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1248                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1249                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1250                                 break;
1251                         case 3:
1252                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1253                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1254                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1255                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1256                                 break;
1257                         case 4:
1258                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1259                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1260                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1261                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1262                                 break;
1263                         case 5:
1264                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1265                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1266                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1267                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1268                                 break;
1269                         case 6:
1270                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1271                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1272                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1273                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1274                                 break;
1275                         case 8:
1276                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1277                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1278                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1279                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1280                                 break;
1281                         case 9:
1282                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1283                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1284                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1285                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1286                                 break;
1287                         case 10:
1288                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1289                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1290                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1291                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1292                                 break;
1293                         case 11:
1294                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1295                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1296                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1297                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1298                                 break;
1299                         case 12:
1300                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1301                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1302                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1303                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1304                                 break;
1305                         case 13:
1306                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1307                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1308                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1309                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1310                                 break;
1311                         case 14:
1312                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1313                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1314                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1315                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1316                                 break;
1317                         case 7:
1318                                 /* unused idx */
1319                                 continue;
1320                         default:
1321                                 gb_tile_moden = 0;
1322                                 break;
1323                         };
1324                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1325                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1326                 }
1327         case CHIP_FIJI:
1328         case CHIP_TONGA:
1329                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1330                         switch (reg_offset) {
1331                         case 0:
1332                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1333                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1334                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1335                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1336                                 break;
1337                         case 1:
1338                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1339                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1340                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1341                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1342                                 break;
1343                         case 2:
1344                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1345                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1346                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1347                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1348                                 break;
1349                         case 3:
1350                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1351                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1352                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1353                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1354                                 break;
1355                         case 4:
1356                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1357                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1358                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1359                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1360                                 break;
1361                         case 5:
1362                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1363                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1364                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1365                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1366                                 break;
1367                         case 6:
1368                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1369                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1370                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1371                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1372                                 break;
1373                         case 7:
1374                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1375                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1376                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1377                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1378                                 break;
1379                         case 8:
1380                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1381                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1382                                 break;
1383                         case 9:
1384                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1385                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1386                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1387                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1388                                 break;
1389                         case 10:
1390                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1392                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1393                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1394                                 break;
1395                         case 11:
1396                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1397                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1398                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1399                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1400                                 break;
1401                         case 12:
1402                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1403                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1404                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1405                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1406                                 break;
1407                         case 13:
1408                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1409                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1410                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1411                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1412                                 break;
1413                         case 14:
1414                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1416                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1417                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1418                                 break;
1419                         case 15:
1420                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1421                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1422                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1423                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1424                                 break;
1425                         case 16:
1426                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1427                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1428                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1429                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1430                                 break;
1431                         case 17:
1432                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1433                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1434                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1435                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1436                                 break;
1437                         case 18:
1438                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1439                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1440                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1441                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1442                                 break;
1443                         case 19:
1444                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1445                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1446                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1447                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1448                                 break;
1449                         case 20:
1450                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1451                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1452                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1453                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1454                                 break;
1455                         case 21:
1456                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1457                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1458                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1459                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1460                                 break;
1461                         case 22:
1462                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1463                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1464                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1465                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1466                                 break;
1467                         case 23:
1468                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1469                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1470                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1471                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472                                 break;
1473                         case 24:
1474                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1475                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1476                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1477                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1478                                 break;
1479                         case 25:
1480                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1481                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1482                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1483                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1484                                 break;
1485                         case 26:
1486                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1487                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1488                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1489                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1490                                 break;
1491                         case 27:
1492                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1493                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1494                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1495                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1496                                 break;
1497                         case 28:
1498                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1499                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1500                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1501                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1502                                 break;
1503                         case 29:
1504                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1505                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1506                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1507                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1508                                 break;
1509                         case 30:
1510                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1511                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1512                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1513                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1514                                 break;
1515                         default:
1516                                 gb_tile_moden = 0;
1517                                 break;
1518                         };
1519                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1520                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1521                 }
1522                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1523                         switch (reg_offset) {
1524                         case 0:
1525                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1527                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1529                                 break;
1530                         case 1:
1531                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1532                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1533                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1534                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1535                                 break;
1536                         case 2:
1537                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1538                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1539                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1541                                 break;
1542                         case 3:
1543                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1544                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1545                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1546                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1547                                 break;
1548                         case 4:
1549                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1550                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1551                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1552                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1553                                 break;
1554                         case 5:
1555                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1556                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1557                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1558                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1559                                 break;
1560                         case 6:
1561                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1563                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1564                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1565                                 break;
1566                         case 8:
1567                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1568                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1569                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1570                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1571                                 break;
1572                         case 9:
1573                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1574                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1575                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1576                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1577                                 break;
1578                         case 10:
1579                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1580                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1581                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1582                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1583                                 break;
1584                         case 11:
1585                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1586                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1587                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1588                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1589                                 break;
1590                         case 12:
1591                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1592                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1593                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1594                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1595                                 break;
1596                         case 13:
1597                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1598                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1599                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1600                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1601                                 break;
1602                         case 14:
1603                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1604                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1605                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1606                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1607                                 break;
1608                         case 7:
1609                                 /* unused idx */
1610                                 continue;
1611                         default:
1612                                 gb_tile_moden = 0;
1613                                 break;
1614                         };
1615                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1616                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1617                 }
1618                 break;
1619         case CHIP_CARRIZO:
1620         default:
1621                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1622                         switch (reg_offset) {
1623                         case 0:
1624                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1625                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1626                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1627                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1628                                 break;
1629                         case 1:
1630                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1631                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1632                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1633                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1634                                 break;
1635                         case 2:
1636                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1637                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1638                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1639                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1640                                 break;
1641                         case 3:
1642                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1643                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1644                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1645                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1646                                 break;
1647                         case 4:
1648                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1649                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1650                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1651                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1652                                 break;
1653                         case 5:
1654                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1655                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1656                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1657                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1658                                 break;
1659                         case 6:
1660                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1661                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1662                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1663                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1664                                 break;
1665                         case 8:
1666                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1667                                                 PIPE_CONFIG(ADDR_SURF_P2));
1668                                 break;
1669                         case 9:
1670                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1671                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1672                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1673                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1674                                 break;
1675                         case 10:
1676                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1677                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1678                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1679                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1680                                 break;
1681                         case 11:
1682                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1683                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1684                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1685                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1686                                 break;
1687                         case 13:
1688                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1689                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1690                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1691                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1692                                 break;
1693                         case 14:
1694                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1695                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1696                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1697                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1698                                 break;
1699                         case 15:
1700                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1701                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1702                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1703                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1704                                 break;
1705                         case 16:
1706                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1707                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1708                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1709                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1710                                 break;
1711                         case 18:
1712                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1713                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1714                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1715                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1716                                 break;
1717                         case 19:
1718                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1719                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1720                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1721                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1722                                 break;
1723                         case 20:
1724                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1725                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1726                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1727                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1728                                 break;
1729                         case 21:
1730                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1731                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1732                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1733                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1734                                 break;
1735                         case 22:
1736                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1737                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1738                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1739                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1740                                 break;
1741                         case 24:
1742                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1743                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1744                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1745                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1746                                 break;
1747                         case 25:
1748                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1749                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1750                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1751                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1752                                 break;
1753                         case 26:
1754                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1755                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1756                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1757                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1758                                 break;
1759                         case 27:
1760                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1761                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1762                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1763                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1764                                 break;
1765                         case 28:
1766                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1767                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1768                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1769                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1770                                 break;
1771                         case 29:
1772                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1773                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1774                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1775                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1776                                 break;
1777                         case 7:
1778                         case 12:
1779                         case 17:
1780                         case 23:
1781                                 /* unused idx */
1782                                 continue;
1783                         default:
1784                                 gb_tile_moden = 0;
1785                                 break;
1786                         };
1787                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1788                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1789                 }
1790                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1791                         switch (reg_offset) {
1792                         case 0:
1793                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1794                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1795                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1796                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1797                                 break;
1798                         case 1:
1799                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1800                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1801                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1802                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1803                                 break;
1804                         case 2:
1805                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1806                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1807                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1808                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1809                                 break;
1810                         case 3:
1811                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1812                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1813                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1814                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1815                                 break;
1816                         case 4:
1817                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1818                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1819                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1820                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1821                                 break;
1822                         case 5:
1823                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1824                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1825                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1826                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1827                                 break;
1828                         case 6:
1829                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1830                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1831                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1832                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1833                                 break;
1834                         case 8:
1835                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1836                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1837                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1838                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1839                                 break;
1840                         case 9:
1841                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1842                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1843                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1844                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1845                                 break;
1846                         case 10:
1847                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1848                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1849                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1850                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1851                                 break;
1852                         case 11:
1853                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1854                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1855                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1856                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1857                                 break;
1858                         case 12:
1859                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1860                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1861                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1862                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1863                                 break;
1864                         case 13:
1865                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1866                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1867                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1868                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1869                                 break;
1870                         case 14:
1871                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1872                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1873                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1874                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1875                                 break;
1876                         case 7:
1877                                 /* unused idx */
1878                                 continue;
1879                         default:
1880                                 gb_tile_moden = 0;
1881                                 break;
1882                         };
1883                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1884                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1885                 }
1886         }
1887 }
1888
1889 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1890 {
1891         u32 i, mask = 0;
1892
1893         for (i = 0; i < bit_width; i++) {
1894                 mask <<= 1;
1895                 mask |= 1;
1896         }
1897         return mask;
1898 }
1899
1900 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1901 {
1902         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1903
1904         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1905                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1906                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1907         } else if (se_num == 0xffffffff) {
1908                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1909                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1910         } else if (sh_num == 0xffffffff) {
1911                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1912                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1913         } else {
1914                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1915                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1916         }
1917         WREG32(mmGRBM_GFX_INDEX, data);
1918 }
1919
1920 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1921                                     u32 max_rb_num_per_se,
1922                                     u32 sh_per_se)
1923 {
1924         u32 data, mask;
1925
1926         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1927         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1928
1929         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1930
1931         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1932
1933         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1934
1935         return data & mask;
1936 }
1937
1938 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1939                               u32 se_num, u32 sh_per_se,
1940                               u32 max_rb_num_per_se)
1941 {
1942         int i, j;
1943         u32 data, mask;
1944         u32 disabled_rbs = 0;
1945         u32 enabled_rbs = 0;
1946
1947         mutex_lock(&adev->grbm_idx_mutex);
1948         for (i = 0; i < se_num; i++) {
1949                 for (j = 0; j < sh_per_se; j++) {
1950                         gfx_v8_0_select_se_sh(adev, i, j);
1951                         data = gfx_v8_0_get_rb_disabled(adev,
1952                                               max_rb_num_per_se, sh_per_se);
1953                         disabled_rbs |= data << ((i * sh_per_se + j) *
1954                                                  RB_BITMAP_WIDTH_PER_SH);
1955                 }
1956         }
1957         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1958         mutex_unlock(&adev->grbm_idx_mutex);
1959
1960         mask = 1;
1961         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1962                 if (!(disabled_rbs & mask))
1963                         enabled_rbs |= mask;
1964                 mask <<= 1;
1965         }
1966
1967         adev->gfx.config.backend_enable_mask = enabled_rbs;
1968
1969         mutex_lock(&adev->grbm_idx_mutex);
1970         for (i = 0; i < se_num; i++) {
1971                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1972                 data = 0;
1973                 for (j = 0; j < sh_per_se; j++) {
1974                         switch (enabled_rbs & 3) {
1975                         case 0:
1976                                 if (j == 0)
1977                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
1978                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1979                                 else
1980                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
1981                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1982                                 break;
1983                         case 1:
1984                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
1985                                          (i * sh_per_se + j) * 2);
1986                                 break;
1987                         case 2:
1988                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
1989                                          (i * sh_per_se + j) * 2);
1990                                 break;
1991                         case 3:
1992                         default:
1993                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
1994                                          (i * sh_per_se + j) * 2);
1995                                 break;
1996                         }
1997                         enabled_rbs >>= 2;
1998                 }
1999                 WREG32(mmPA_SC_RASTER_CONFIG, data);
2000         }
2001         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2002         mutex_unlock(&adev->grbm_idx_mutex);
2003 }
2004
2005 /**
2006  * gmc_v8_0_init_compute_vmid - gart enable
2007  *
2008  * @rdev: amdgpu_device pointer
2009  *
2010  * Initialize compute vmid sh_mem registers
2011  *
2012  */
2013 #define DEFAULT_SH_MEM_BASES    (0x6000)
2014 #define FIRST_COMPUTE_VMID      (8)
2015 #define LAST_COMPUTE_VMID       (16)
2016 static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2017 {
2018         int i;
2019         uint32_t sh_mem_config;
2020         uint32_t sh_mem_bases;
2021
2022         /*
2023          * Configure apertures:
2024          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2025          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2026          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2027          */
2028         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2029
2030         sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2031                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2032                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2033                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2034                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2035                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2036
2037         mutex_lock(&adev->srbm_mutex);
2038         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2039                 vi_srbm_select(adev, 0, 0, 0, i);
2040                 /* CP and shaders */
2041                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2042                 WREG32(mmSH_MEM_APE1_BASE, 1);
2043                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2044                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2045         }
2046         vi_srbm_select(adev, 0, 0, 0, 0);
2047         mutex_unlock(&adev->srbm_mutex);
2048 }
2049
2050 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2051 {
2052         u32 gb_addr_config;
2053         u32 mc_shared_chmap, mc_arb_ramcfg;
2054         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
2055         u32 tmp;
2056         int i;
2057
2058         switch (adev->asic_type) {
2059         case CHIP_TOPAZ:
2060                 adev->gfx.config.max_shader_engines = 1;
2061                 adev->gfx.config.max_tile_pipes = 2;
2062                 adev->gfx.config.max_cu_per_sh = 6;
2063                 adev->gfx.config.max_sh_per_se = 1;
2064                 adev->gfx.config.max_backends_per_se = 2;
2065                 adev->gfx.config.max_texture_channel_caches = 2;
2066                 adev->gfx.config.max_gprs = 256;
2067                 adev->gfx.config.max_gs_threads = 32;
2068                 adev->gfx.config.max_hw_contexts = 8;
2069
2070                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2071                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2072                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2073                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2074                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
2075                 break;
2076         case CHIP_FIJI:
2077                 adev->gfx.config.max_shader_engines = 4;
2078                 adev->gfx.config.max_tile_pipes = 16;
2079                 adev->gfx.config.max_cu_per_sh = 16;
2080                 adev->gfx.config.max_sh_per_se = 1;
2081                 adev->gfx.config.max_backends_per_se = 4;
2082                 adev->gfx.config.max_texture_channel_caches = 8;
2083                 adev->gfx.config.max_gprs = 256;
2084                 adev->gfx.config.max_gs_threads = 32;
2085                 adev->gfx.config.max_hw_contexts = 8;
2086
2087                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2088                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2089                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2090                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2091                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2092                 break;
2093         case CHIP_TONGA:
2094                 adev->gfx.config.max_shader_engines = 4;
2095                 adev->gfx.config.max_tile_pipes = 8;
2096                 adev->gfx.config.max_cu_per_sh = 8;
2097                 adev->gfx.config.max_sh_per_se = 1;
2098                 adev->gfx.config.max_backends_per_se = 2;
2099                 adev->gfx.config.max_texture_channel_caches = 8;
2100                 adev->gfx.config.max_gprs = 256;
2101                 adev->gfx.config.max_gs_threads = 32;
2102                 adev->gfx.config.max_hw_contexts = 8;
2103
2104                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2105                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2106                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2107                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2108                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2109                 break;
2110         case CHIP_CARRIZO:
2111                 adev->gfx.config.max_shader_engines = 1;
2112                 adev->gfx.config.max_tile_pipes = 2;
2113                 adev->gfx.config.max_sh_per_se = 1;
2114                 adev->gfx.config.max_backends_per_se = 2;
2115
2116                 switch (adev->pdev->revision) {
2117                 case 0xc4:
2118                 case 0x84:
2119                 case 0xc8:
2120                 case 0xcc:
2121                         /* B10 */
2122                         adev->gfx.config.max_cu_per_sh = 8;
2123                         break;
2124                 case 0xc5:
2125                 case 0x81:
2126                 case 0x85:
2127                 case 0xc9:
2128                 case 0xcd:
2129                         /* B8 */
2130                         adev->gfx.config.max_cu_per_sh = 6;
2131                         break;
2132                 case 0xc6:
2133                 case 0xca:
2134                 case 0xce:
2135                         /* B6 */
2136                         adev->gfx.config.max_cu_per_sh = 6;
2137                         break;
2138                 case 0xc7:
2139                 case 0x87:
2140                 case 0xcb:
2141                 default:
2142                         /* B4 */
2143                         adev->gfx.config.max_cu_per_sh = 4;
2144                         break;
2145                 }
2146
2147                 adev->gfx.config.max_texture_channel_caches = 2;
2148                 adev->gfx.config.max_gprs = 256;
2149                 adev->gfx.config.max_gs_threads = 32;
2150                 adev->gfx.config.max_hw_contexts = 8;
2151
2152                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2153                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2154                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2155                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2156                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
2157                 break;
2158         default:
2159                 adev->gfx.config.max_shader_engines = 2;
2160                 adev->gfx.config.max_tile_pipes = 4;
2161                 adev->gfx.config.max_cu_per_sh = 2;
2162                 adev->gfx.config.max_sh_per_se = 1;
2163                 adev->gfx.config.max_backends_per_se = 2;
2164                 adev->gfx.config.max_texture_channel_caches = 4;
2165                 adev->gfx.config.max_gprs = 256;
2166                 adev->gfx.config.max_gs_threads = 32;
2167                 adev->gfx.config.max_hw_contexts = 8;
2168
2169                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2170                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2171                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2172                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2173                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2174                 break;
2175         }
2176
2177         tmp = RREG32(mmGRBM_CNTL);
2178         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2179         WREG32(mmGRBM_CNTL, tmp);
2180
2181         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2182         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2183         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2184
2185         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2186         adev->gfx.config.mem_max_burst_length_bytes = 256;
2187         if (adev->flags & AMD_IS_APU) {
2188                 /* Get memory bank mapping mode. */
2189                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2190                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2191                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2192
2193                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2194                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2195                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2196
2197                 /* Validate settings in case only one DIMM installed. */
2198                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2199                         dimm00_addr_map = 0;
2200                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2201                         dimm01_addr_map = 0;
2202                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2203                         dimm10_addr_map = 0;
2204                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2205                         dimm11_addr_map = 0;
2206
2207                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2208                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2209                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2210                         adev->gfx.config.mem_row_size_in_kb = 2;
2211                 else
2212                         adev->gfx.config.mem_row_size_in_kb = 1;
2213         } else {
2214                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2215                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2216                 if (adev->gfx.config.mem_row_size_in_kb > 4)
2217                         adev->gfx.config.mem_row_size_in_kb = 4;
2218         }
2219
2220         adev->gfx.config.shader_engine_tile_size = 32;
2221         adev->gfx.config.num_gpus = 1;
2222         adev->gfx.config.multi_gpu_tile_size = 64;
2223
2224         /* fix up row size */
2225         switch (adev->gfx.config.mem_row_size_in_kb) {
2226         case 1:
2227         default:
2228                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2229                 break;
2230         case 2:
2231                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2232                 break;
2233         case 4:
2234                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2235                 break;
2236         }
2237         adev->gfx.config.gb_addr_config = gb_addr_config;
2238
2239         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2240         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2241         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2242         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2243                gb_addr_config & 0x70);
2244         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2245                gb_addr_config & 0x70);
2246         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2247         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2248         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2249
2250         gfx_v8_0_tiling_mode_table_init(adev);
2251
2252         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2253                                  adev->gfx.config.max_sh_per_se,
2254                                  adev->gfx.config.max_backends_per_se);
2255
2256         /* XXX SH_MEM regs */
2257         /* where to put LDS, scratch, GPUVM in FSA64 space */
2258         mutex_lock(&adev->srbm_mutex);
2259         for (i = 0; i < 16; i++) {
2260                 vi_srbm_select(adev, 0, 0, 0, i);
2261                 /* CP and shaders */
2262                 if (i == 0) {
2263                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2264                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2265                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2266                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2267                         WREG32(mmSH_MEM_CONFIG, tmp);
2268                 } else {
2269                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2270                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2271                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2272                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2273                         WREG32(mmSH_MEM_CONFIG, tmp);
2274                 }
2275
2276                 WREG32(mmSH_MEM_APE1_BASE, 1);
2277                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2278                 WREG32(mmSH_MEM_BASES, 0);
2279         }
2280         vi_srbm_select(adev, 0, 0, 0, 0);
2281         mutex_unlock(&adev->srbm_mutex);
2282
2283         gmc_v8_0_init_compute_vmid(adev);
2284
2285         mutex_lock(&adev->grbm_idx_mutex);
2286         /*
2287          * making sure that the following register writes will be broadcasted
2288          * to all the shaders
2289          */
2290         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2291
2292         WREG32(mmPA_SC_FIFO_SIZE,
2293                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2294                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2295                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2296                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2297                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2298                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2299                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2300                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2301         mutex_unlock(&adev->grbm_idx_mutex);
2302
2303 }
2304
2305 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2306 {
2307         u32 i, j, k;
2308         u32 mask;
2309
2310         mutex_lock(&adev->grbm_idx_mutex);
2311         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2312                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2313                         gfx_v8_0_select_se_sh(adev, i, j);
2314                         for (k = 0; k < adev->usec_timeout; k++) {
2315                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2316                                         break;
2317                                 udelay(1);
2318                         }
2319                 }
2320         }
2321         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2322         mutex_unlock(&adev->grbm_idx_mutex);
2323
2324         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2325                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2326                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2327                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2328         for (k = 0; k < adev->usec_timeout; k++) {
2329                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2330                         break;
2331                 udelay(1);
2332         }
2333 }
2334
2335 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2336                                                bool enable)
2337 {
2338         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2339
2340         if (enable) {
2341                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2342                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2343                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2344                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2345         } else {
2346                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2347                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2348                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2349                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2350         }
2351         WREG32(mmCP_INT_CNTL_RING0, tmp);
2352 }
2353
2354 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2355 {
2356         u32 tmp = RREG32(mmRLC_CNTL);
2357
2358         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2359         WREG32(mmRLC_CNTL, tmp);
2360
2361         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2362
2363         gfx_v8_0_wait_for_rlc_serdes(adev);
2364 }
2365
2366 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2367 {
2368         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2369
2370         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2371         WREG32(mmGRBM_SOFT_RESET, tmp);
2372         udelay(50);
2373         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2374         WREG32(mmGRBM_SOFT_RESET, tmp);
2375         udelay(50);
2376 }
2377
2378 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2379 {
2380         u32 tmp = RREG32(mmRLC_CNTL);
2381
2382         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2383         WREG32(mmRLC_CNTL, tmp);
2384
2385         /* carrizo do enable cp interrupt after cp inited */
2386         if (adev->asic_type != CHIP_CARRIZO)
2387                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2388
2389         udelay(50);
2390 }
2391
2392 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2393 {
2394         const struct rlc_firmware_header_v2_0 *hdr;
2395         const __le32 *fw_data;
2396         unsigned i, fw_size;
2397
2398         if (!adev->gfx.rlc_fw)
2399                 return -EINVAL;
2400
2401         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2402         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2403
2404         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2405                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2406         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2407
2408         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2409         for (i = 0; i < fw_size; i++)
2410                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2411         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2412
2413         return 0;
2414 }
2415
2416 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2417 {
2418         int r;
2419
2420         gfx_v8_0_rlc_stop(adev);
2421
2422         /* disable CG */
2423         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2424
2425         /* disable PG */
2426         WREG32(mmRLC_PG_CNTL, 0);
2427
2428         gfx_v8_0_rlc_reset(adev);
2429
2430         if (!adev->firmware.smu_load) {
2431                 /* legacy rlc firmware loading */
2432                 r = gfx_v8_0_rlc_load_microcode(adev);
2433                 if (r)
2434                         return r;
2435         } else {
2436                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2437                                                 AMDGPU_UCODE_ID_RLC_G);
2438                 if (r)
2439                         return -EINVAL;
2440         }
2441
2442         gfx_v8_0_rlc_start(adev);
2443
2444         return 0;
2445 }
2446
2447 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2448 {
2449         int i;
2450         u32 tmp = RREG32(mmCP_ME_CNTL);
2451
2452         if (enable) {
2453                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2454                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2455                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2456         } else {
2457                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2458                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2459                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2460                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2461                         adev->gfx.gfx_ring[i].ready = false;
2462         }
2463         WREG32(mmCP_ME_CNTL, tmp);
2464         udelay(50);
2465 }
2466
2467 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2468 {
2469         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2470         const struct gfx_firmware_header_v1_0 *ce_hdr;
2471         const struct gfx_firmware_header_v1_0 *me_hdr;
2472         const __le32 *fw_data;
2473         unsigned i, fw_size;
2474
2475         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2476                 return -EINVAL;
2477
2478         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2479                 adev->gfx.pfp_fw->data;
2480         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2481                 adev->gfx.ce_fw->data;
2482         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2483                 adev->gfx.me_fw->data;
2484
2485         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2486         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2487         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2488
2489         gfx_v8_0_cp_gfx_enable(adev, false);
2490
2491         /* PFP */
2492         fw_data = (const __le32 *)
2493                 (adev->gfx.pfp_fw->data +
2494                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2495         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2496         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2497         for (i = 0; i < fw_size; i++)
2498                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2499         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2500
2501         /* CE */
2502         fw_data = (const __le32 *)
2503                 (adev->gfx.ce_fw->data +
2504                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2505         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2506         WREG32(mmCP_CE_UCODE_ADDR, 0);
2507         for (i = 0; i < fw_size; i++)
2508                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2509         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2510
2511         /* ME */
2512         fw_data = (const __le32 *)
2513                 (adev->gfx.me_fw->data +
2514                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2515         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2516         WREG32(mmCP_ME_RAM_WADDR, 0);
2517         for (i = 0; i < fw_size; i++)
2518                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2519         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2520
2521         return 0;
2522 }
2523
2524 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2525 {
2526         u32 count = 0;
2527         const struct cs_section_def *sect = NULL;
2528         const struct cs_extent_def *ext = NULL;
2529
2530         /* begin clear state */
2531         count += 2;
2532         /* context control state */
2533         count += 3;
2534
2535         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2536                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2537                         if (sect->id == SECT_CONTEXT)
2538                                 count += 2 + ext->reg_count;
2539                         else
2540                                 return 0;
2541                 }
2542         }
2543         /* pa_sc_raster_config/pa_sc_raster_config1 */
2544         count += 4;
2545         /* end clear state */
2546         count += 2;
2547         /* clear state */
2548         count += 2;
2549
2550         return count;
2551 }
2552
2553 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2554 {
2555         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2556         const struct cs_section_def *sect = NULL;
2557         const struct cs_extent_def *ext = NULL;
2558         int r, i;
2559
2560         /* init the CP */
2561         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2562         WREG32(mmCP_ENDIAN_SWAP, 0);
2563         WREG32(mmCP_DEVICE_ID, 1);
2564
2565         gfx_v8_0_cp_gfx_enable(adev, true);
2566
2567         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2568         if (r) {
2569                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2570                 return r;
2571         }
2572
2573         /* clear state buffer */
2574         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2575         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2576
2577         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2578         amdgpu_ring_write(ring, 0x80000000);
2579         amdgpu_ring_write(ring, 0x80000000);
2580
2581         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2582                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2583                         if (sect->id == SECT_CONTEXT) {
2584                                 amdgpu_ring_write(ring,
2585                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2586                                                ext->reg_count));
2587                                 amdgpu_ring_write(ring,
2588                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2589                                 for (i = 0; i < ext->reg_count; i++)
2590                                         amdgpu_ring_write(ring, ext->extent[i]);
2591                         }
2592                 }
2593         }
2594
2595         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2596         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2597         switch (adev->asic_type) {
2598         case CHIP_TONGA:
2599         case CHIP_FIJI:
2600                 amdgpu_ring_write(ring, 0x16000012);
2601                 amdgpu_ring_write(ring, 0x0000002A);
2602                 break;
2603         case CHIP_TOPAZ:
2604         case CHIP_CARRIZO:
2605                 amdgpu_ring_write(ring, 0x00000002);
2606                 amdgpu_ring_write(ring, 0x00000000);
2607                 break;
2608         default:
2609                 BUG();
2610         }
2611
2612         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2613         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2614
2615         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2616         amdgpu_ring_write(ring, 0);
2617
2618         /* init the CE partitions */
2619         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2620         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2621         amdgpu_ring_write(ring, 0x8000);
2622         amdgpu_ring_write(ring, 0x8000);
2623
2624         amdgpu_ring_unlock_commit(ring);
2625
2626         return 0;
2627 }
2628
2629 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2630 {
2631         struct amdgpu_ring *ring;
2632         u32 tmp;
2633         u32 rb_bufsz;
2634         u64 rb_addr, rptr_addr;
2635         int r;
2636
2637         /* Set the write pointer delay */
2638         WREG32(mmCP_RB_WPTR_DELAY, 0);
2639
2640         /* set the RB to use vmid 0 */
2641         WREG32(mmCP_RB_VMID, 0);
2642
2643         /* Set ring buffer size */
2644         ring = &adev->gfx.gfx_ring[0];
2645         rb_bufsz = order_base_2(ring->ring_size / 8);
2646         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2647         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2648         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2649         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2650 #ifdef __BIG_ENDIAN
2651         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2652 #endif
2653         WREG32(mmCP_RB0_CNTL, tmp);
2654
2655         /* Initialize the ring buffer's read and write pointers */
2656         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2657         ring->wptr = 0;
2658         WREG32(mmCP_RB0_WPTR, ring->wptr);
2659
2660         /* set the wb address wether it's enabled or not */
2661         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2662         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2663         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2664
2665         mdelay(1);
2666         WREG32(mmCP_RB0_CNTL, tmp);
2667
2668         rb_addr = ring->gpu_addr >> 8;
2669         WREG32(mmCP_RB0_BASE, rb_addr);
2670         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2671
2672         /* no gfx doorbells on iceland */
2673         if (adev->asic_type != CHIP_TOPAZ) {
2674                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2675                 if (ring->use_doorbell) {
2676                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2677                                             DOORBELL_OFFSET, ring->doorbell_index);
2678                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2679                                             DOORBELL_EN, 1);
2680                 } else {
2681                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2682                                             DOORBELL_EN, 0);
2683                 }
2684                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2685
2686                 if (adev->asic_type == CHIP_TONGA) {
2687                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2688                                             DOORBELL_RANGE_LOWER,
2689                                             AMDGPU_DOORBELL_GFX_RING0);
2690                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2691
2692                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2693                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2694                 }
2695
2696         }
2697
2698         /* start the ring */
2699         gfx_v8_0_cp_gfx_start(adev);
2700         ring->ready = true;
2701         r = amdgpu_ring_test_ring(ring);
2702         if (r) {
2703                 ring->ready = false;
2704                 return r;
2705         }
2706
2707         return 0;
2708 }
2709
2710 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2711 {
2712         int i;
2713
2714         if (enable) {
2715                 WREG32(mmCP_MEC_CNTL, 0);
2716         } else {
2717                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2718                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2719                         adev->gfx.compute_ring[i].ready = false;
2720         }
2721         udelay(50);
2722 }
2723
2724 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2725 {
2726         gfx_v8_0_cp_compute_enable(adev, true);
2727
2728         return 0;
2729 }
2730
2731 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2732 {
2733         const struct gfx_firmware_header_v1_0 *mec_hdr;
2734         const __le32 *fw_data;
2735         unsigned i, fw_size;
2736
2737         if (!adev->gfx.mec_fw)
2738                 return -EINVAL;
2739
2740         gfx_v8_0_cp_compute_enable(adev, false);
2741
2742         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2743         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2744
2745         fw_data = (const __le32 *)
2746                 (adev->gfx.mec_fw->data +
2747                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2748         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2749
2750         /* MEC1 */
2751         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2752         for (i = 0; i < fw_size; i++)
2753                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2754         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2755
2756         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2757         if (adev->gfx.mec2_fw) {
2758                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2759
2760                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2761                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2762
2763                 fw_data = (const __le32 *)
2764                         (adev->gfx.mec2_fw->data +
2765                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2766                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2767
2768                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2769                 for (i = 0; i < fw_size; i++)
2770                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2771                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2772         }
2773
2774         return 0;
2775 }
2776
2777 struct vi_mqd {
2778         uint32_t header;  /* ordinal0 */
2779         uint32_t compute_dispatch_initiator;  /* ordinal1 */
2780         uint32_t compute_dim_x;  /* ordinal2 */
2781         uint32_t compute_dim_y;  /* ordinal3 */
2782         uint32_t compute_dim_z;  /* ordinal4 */
2783         uint32_t compute_start_x;  /* ordinal5 */
2784         uint32_t compute_start_y;  /* ordinal6 */
2785         uint32_t compute_start_z;  /* ordinal7 */
2786         uint32_t compute_num_thread_x;  /* ordinal8 */
2787         uint32_t compute_num_thread_y;  /* ordinal9 */
2788         uint32_t compute_num_thread_z;  /* ordinal10 */
2789         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
2790         uint32_t compute_perfcount_enable;  /* ordinal12 */
2791         uint32_t compute_pgm_lo;  /* ordinal13 */
2792         uint32_t compute_pgm_hi;  /* ordinal14 */
2793         uint32_t compute_tba_lo;  /* ordinal15 */
2794         uint32_t compute_tba_hi;  /* ordinal16 */
2795         uint32_t compute_tma_lo;  /* ordinal17 */
2796         uint32_t compute_tma_hi;  /* ordinal18 */
2797         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
2798         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
2799         uint32_t compute_vmid;  /* ordinal21 */
2800         uint32_t compute_resource_limits;  /* ordinal22 */
2801         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
2802         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
2803         uint32_t compute_tmpring_size;  /* ordinal25 */
2804         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
2805         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
2806         uint32_t compute_restart_x;  /* ordinal28 */
2807         uint32_t compute_restart_y;  /* ordinal29 */
2808         uint32_t compute_restart_z;  /* ordinal30 */
2809         uint32_t compute_thread_trace_enable;  /* ordinal31 */
2810         uint32_t compute_misc_reserved;  /* ordinal32 */
2811         uint32_t compute_dispatch_id;  /* ordinal33 */
2812         uint32_t compute_threadgroup_id;  /* ordinal34 */
2813         uint32_t compute_relaunch;  /* ordinal35 */
2814         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
2815         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
2816         uint32_t compute_wave_restore_control;  /* ordinal38 */
2817         uint32_t reserved9;  /* ordinal39 */
2818         uint32_t reserved10;  /* ordinal40 */
2819         uint32_t reserved11;  /* ordinal41 */
2820         uint32_t reserved12;  /* ordinal42 */
2821         uint32_t reserved13;  /* ordinal43 */
2822         uint32_t reserved14;  /* ordinal44 */
2823         uint32_t reserved15;  /* ordinal45 */
2824         uint32_t reserved16;  /* ordinal46 */
2825         uint32_t reserved17;  /* ordinal47 */
2826         uint32_t reserved18;  /* ordinal48 */
2827         uint32_t reserved19;  /* ordinal49 */
2828         uint32_t reserved20;  /* ordinal50 */
2829         uint32_t reserved21;  /* ordinal51 */
2830         uint32_t reserved22;  /* ordinal52 */
2831         uint32_t reserved23;  /* ordinal53 */
2832         uint32_t reserved24;  /* ordinal54 */
2833         uint32_t reserved25;  /* ordinal55 */
2834         uint32_t reserved26;  /* ordinal56 */
2835         uint32_t reserved27;  /* ordinal57 */
2836         uint32_t reserved28;  /* ordinal58 */
2837         uint32_t reserved29;  /* ordinal59 */
2838         uint32_t reserved30;  /* ordinal60 */
2839         uint32_t reserved31;  /* ordinal61 */
2840         uint32_t reserved32;  /* ordinal62 */
2841         uint32_t reserved33;  /* ordinal63 */
2842         uint32_t reserved34;  /* ordinal64 */
2843         uint32_t compute_user_data_0;  /* ordinal65 */
2844         uint32_t compute_user_data_1;  /* ordinal66 */
2845         uint32_t compute_user_data_2;  /* ordinal67 */
2846         uint32_t compute_user_data_3;  /* ordinal68 */
2847         uint32_t compute_user_data_4;  /* ordinal69 */
2848         uint32_t compute_user_data_5;  /* ordinal70 */
2849         uint32_t compute_user_data_6;  /* ordinal71 */
2850         uint32_t compute_user_data_7;  /* ordinal72 */
2851         uint32_t compute_user_data_8;  /* ordinal73 */
2852         uint32_t compute_user_data_9;  /* ordinal74 */
2853         uint32_t compute_user_data_10;  /* ordinal75 */
2854         uint32_t compute_user_data_11;  /* ordinal76 */
2855         uint32_t compute_user_data_12;  /* ordinal77 */
2856         uint32_t compute_user_data_13;  /* ordinal78 */
2857         uint32_t compute_user_data_14;  /* ordinal79 */
2858         uint32_t compute_user_data_15;  /* ordinal80 */
2859         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
2860         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
2861         uint32_t reserved35;  /* ordinal83 */
2862         uint32_t reserved36;  /* ordinal84 */
2863         uint32_t reserved37;  /* ordinal85 */
2864         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
2865         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
2866         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
2867         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
2868         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
2869         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
2870         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
2871         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
2872         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
2873         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
2874         uint32_t reserved38;  /* ordinal96 */
2875         uint32_t reserved39;  /* ordinal97 */
2876         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
2877         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
2878         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
2879         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
2880         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
2881         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
2882         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
2883         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
2884         uint32_t reserved40;  /* ordinal106 */
2885         uint32_t reserved41;  /* ordinal107 */
2886         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
2887         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
2888         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
2889         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
2890         uint32_t reserved42;  /* ordinal112 */
2891         uint32_t reserved43;  /* ordinal113 */
2892         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
2893         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
2894         uint32_t cp_packet_id_lo;  /* ordinal116 */
2895         uint32_t cp_packet_id_hi;  /* ordinal117 */
2896         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
2897         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
2898         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
2899         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
2900         uint32_t gds_save_mask_lo;  /* ordinal122 */
2901         uint32_t gds_save_mask_hi;  /* ordinal123 */
2902         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
2903         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
2904         uint32_t reserved44;  /* ordinal126 */
2905         uint32_t reserved45;  /* ordinal127 */
2906         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
2907         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
2908         uint32_t cp_hqd_active;  /* ordinal130 */
2909         uint32_t cp_hqd_vmid;  /* ordinal131 */
2910         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
2911         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
2912         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
2913         uint32_t cp_hqd_quantum;  /* ordinal135 */
2914         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
2915         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
2916         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
2917         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
2918         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
2919         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
2920         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
2921         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
2922         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
2923         uint32_t cp_hqd_pq_control;  /* ordinal145 */
2924         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
2925         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
2926         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
2927         uint32_t cp_hqd_ib_control;  /* ordinal149 */
2928         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
2929         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
2930         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
2931         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
2932         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
2933         uint32_t cp_hqd_msg_type;  /* ordinal155 */
2934         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
2935         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
2936         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
2937         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
2938         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
2939         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
2940         uint32_t cp_mqd_control;  /* ordinal162 */
2941         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
2942         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
2943         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
2944         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
2945         uint32_t cp_hqd_eop_control;  /* ordinal167 */
2946         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
2947         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
2948         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
2949         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
2950         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
2951         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
2952         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
2953         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
2954         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
2955         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
2956         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
2957         uint32_t cp_hqd_error;  /* ordinal179 */
2958         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
2959         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
2960         uint32_t reserved46;  /* ordinal182 */
2961         uint32_t reserved47;  /* ordinal183 */
2962         uint32_t reserved48;  /* ordinal184 */
2963         uint32_t reserved49;  /* ordinal185 */
2964         uint32_t reserved50;  /* ordinal186 */
2965         uint32_t reserved51;  /* ordinal187 */
2966         uint32_t reserved52;  /* ordinal188 */
2967         uint32_t reserved53;  /* ordinal189 */
2968         uint32_t reserved54;  /* ordinal190 */
2969         uint32_t reserved55;  /* ordinal191 */
2970         uint32_t iqtimer_pkt_header;  /* ordinal192 */
2971         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
2972         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
2973         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
2974         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
2975         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
2976         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
2977         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
2978         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
2979         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
2980         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
2981         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
2982         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
2983         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
2984         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
2985         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
2986         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
2987         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
2988         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
2989         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
2990         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
2991         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
2992         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
2993         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
2994         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
2995         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
2996         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
2997         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
2998         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
2999         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
3000         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
3001         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
3002         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
3003         uint32_t reserved56;  /* ordinal225 */
3004         uint32_t reserved57;  /* ordinal226 */
3005         uint32_t reserved58;  /* ordinal227 */
3006         uint32_t set_resources_header;  /* ordinal228 */
3007         uint32_t set_resources_dw1;  /* ordinal229 */
3008         uint32_t set_resources_dw2;  /* ordinal230 */
3009         uint32_t set_resources_dw3;  /* ordinal231 */
3010         uint32_t set_resources_dw4;  /* ordinal232 */
3011         uint32_t set_resources_dw5;  /* ordinal233 */
3012         uint32_t set_resources_dw6;  /* ordinal234 */
3013         uint32_t set_resources_dw7;  /* ordinal235 */
3014         uint32_t reserved59;  /* ordinal236 */
3015         uint32_t reserved60;  /* ordinal237 */
3016         uint32_t reserved61;  /* ordinal238 */
3017         uint32_t reserved62;  /* ordinal239 */
3018         uint32_t reserved63;  /* ordinal240 */
3019         uint32_t reserved64;  /* ordinal241 */
3020         uint32_t reserved65;  /* ordinal242 */
3021         uint32_t reserved66;  /* ordinal243 */
3022         uint32_t reserved67;  /* ordinal244 */
3023         uint32_t reserved68;  /* ordinal245 */
3024         uint32_t reserved69;  /* ordinal246 */
3025         uint32_t reserved70;  /* ordinal247 */
3026         uint32_t reserved71;  /* ordinal248 */
3027         uint32_t reserved72;  /* ordinal249 */
3028         uint32_t reserved73;  /* ordinal250 */
3029         uint32_t reserved74;  /* ordinal251 */
3030         uint32_t reserved75;  /* ordinal252 */
3031         uint32_t reserved76;  /* ordinal253 */
3032         uint32_t reserved77;  /* ordinal254 */
3033         uint32_t reserved78;  /* ordinal255 */
3034
3035         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3036 };
3037
3038 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3039 {
3040         int i, r;
3041
3042         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3043                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3044
3045                 if (ring->mqd_obj) {
3046                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3047                         if (unlikely(r != 0))
3048                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3049
3050                         amdgpu_bo_unpin(ring->mqd_obj);
3051                         amdgpu_bo_unreserve(ring->mqd_obj);
3052
3053                         amdgpu_bo_unref(&ring->mqd_obj);
3054                         ring->mqd_obj = NULL;
3055                 }
3056         }
3057 }
3058
3059 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3060 {
3061         int r, i, j;
3062         u32 tmp;
3063         bool use_doorbell = true;
3064         u64 hqd_gpu_addr;
3065         u64 mqd_gpu_addr;
3066         u64 eop_gpu_addr;
3067         u64 wb_gpu_addr;
3068         u32 *buf;
3069         struct vi_mqd *mqd;
3070
3071         /* init the pipes */
3072         mutex_lock(&adev->srbm_mutex);
3073         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3074                 int me = (i < 4) ? 1 : 2;
3075                 int pipe = (i < 4) ? i : (i - 4);
3076
3077                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3078                 eop_gpu_addr >>= 8;
3079
3080                 vi_srbm_select(adev, me, pipe, 0, 0);
3081
3082                 /* write the EOP addr */
3083                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3084                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3085
3086                 /* set the VMID assigned */
3087                 WREG32(mmCP_HQD_VMID, 0);
3088
3089                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3090                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3091                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3092                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
3093                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3094         }
3095         vi_srbm_select(adev, 0, 0, 0, 0);
3096         mutex_unlock(&adev->srbm_mutex);
3097
3098         /* init the queues.  Just two for now. */
3099         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3100                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3101
3102                 if (ring->mqd_obj == NULL) {
3103                         r = amdgpu_bo_create(adev,
3104                                              sizeof(struct vi_mqd),
3105                                              PAGE_SIZE, true,
3106                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3107                                              &ring->mqd_obj);
3108                         if (r) {
3109                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3110                                 return r;
3111                         }
3112                 }
3113
3114                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3115                 if (unlikely(r != 0)) {
3116                         gfx_v8_0_cp_compute_fini(adev);
3117                         return r;
3118                 }
3119                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3120                                   &mqd_gpu_addr);
3121                 if (r) {
3122                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3123                         gfx_v8_0_cp_compute_fini(adev);
3124                         return r;
3125                 }
3126                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3127                 if (r) {
3128                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3129                         gfx_v8_0_cp_compute_fini(adev);
3130                         return r;
3131                 }
3132
3133                 /* init the mqd struct */
3134                 memset(buf, 0, sizeof(struct vi_mqd));
3135
3136                 mqd = (struct vi_mqd *)buf;
3137                 mqd->header = 0xC0310800;
3138                 mqd->compute_pipelinestat_enable = 0x00000001;
3139                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3140                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3141                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3142                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3143                 mqd->compute_misc_reserved = 0x00000003;
3144
3145                 mutex_lock(&adev->srbm_mutex);
3146                 vi_srbm_select(adev, ring->me,
3147                                ring->pipe,
3148                                ring->queue, 0);
3149
3150                 /* disable wptr polling */
3151                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3152                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3153                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3154
3155                 mqd->cp_hqd_eop_base_addr_lo =
3156                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
3157                 mqd->cp_hqd_eop_base_addr_hi =
3158                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3159
3160                 /* enable doorbell? */
3161                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3162                 if (use_doorbell) {
3163                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3164                 } else {
3165                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3166                 }
3167                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3168                 mqd->cp_hqd_pq_doorbell_control = tmp;
3169
3170                 /* disable the queue if it's active */
3171                 mqd->cp_hqd_dequeue_request = 0;
3172                 mqd->cp_hqd_pq_rptr = 0;
3173                 mqd->cp_hqd_pq_wptr= 0;
3174                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3175                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3176                         for (j = 0; j < adev->usec_timeout; j++) {
3177                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3178                                         break;
3179                                 udelay(1);
3180                         }
3181                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3182                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3183                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3184                 }
3185
3186                 /* set the pointer to the MQD */
3187                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3188                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3189                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3190                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3191
3192                 /* set MQD vmid to 0 */
3193                 tmp = RREG32(mmCP_MQD_CONTROL);
3194                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3195                 WREG32(mmCP_MQD_CONTROL, tmp);
3196                 mqd->cp_mqd_control = tmp;
3197
3198                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3199                 hqd_gpu_addr = ring->gpu_addr >> 8;
3200                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3201                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3202                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3203                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3204
3205                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3206                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3207                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3208                                     (order_base_2(ring->ring_size / 4) - 1));
3209                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3210                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3211 #ifdef __BIG_ENDIAN
3212                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3213 #endif
3214                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3215                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3216                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3217                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3218                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3219                 mqd->cp_hqd_pq_control = tmp;
3220
3221                 /* set the wb address wether it's enabled or not */
3222                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3223                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3224                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3225                         upper_32_bits(wb_gpu_addr) & 0xffff;
3226                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3227                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3228                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3229                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3230
3231                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3232                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3233                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3234                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3235                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3236                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3237                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3238
3239                 /* enable the doorbell if requested */
3240                 if (use_doorbell) {
3241                         if (adev->asic_type == CHIP_CARRIZO) {
3242                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3243                                        AMDGPU_DOORBELL_KIQ << 2);
3244                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3245                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3246                         }
3247                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3248                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3249                                             DOORBELL_OFFSET, ring->doorbell_index);
3250                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3251                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3252                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3253                         mqd->cp_hqd_pq_doorbell_control = tmp;
3254
3255                 } else {
3256                         mqd->cp_hqd_pq_doorbell_control = 0;
3257                 }
3258                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3259                        mqd->cp_hqd_pq_doorbell_control);
3260
3261                 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3262                 ring->wptr = 0;
3263                 mqd->cp_hqd_pq_wptr = ring->wptr;
3264                 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3265                 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3266
3267                 /* set the vmid for the queue */
3268                 mqd->cp_hqd_vmid = 0;
3269                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3270
3271                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3272                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3273                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3274                 mqd->cp_hqd_persistent_state = tmp;
3275
3276                 /* activate the queue */
3277                 mqd->cp_hqd_active = 1;
3278                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3279
3280                 vi_srbm_select(adev, 0, 0, 0, 0);
3281                 mutex_unlock(&adev->srbm_mutex);
3282
3283                 amdgpu_bo_kunmap(ring->mqd_obj);
3284                 amdgpu_bo_unreserve(ring->mqd_obj);
3285         }
3286
3287         if (use_doorbell) {
3288                 tmp = RREG32(mmCP_PQ_STATUS);
3289                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3290                 WREG32(mmCP_PQ_STATUS, tmp);
3291         }
3292
3293         r = gfx_v8_0_cp_compute_start(adev);
3294         if (r)
3295                 return r;
3296
3297         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3298                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3299
3300                 ring->ready = true;
3301                 r = amdgpu_ring_test_ring(ring);
3302                 if (r)
3303                         ring->ready = false;
3304         }
3305
3306         return 0;
3307 }
3308
3309 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3310 {
3311         int r;
3312
3313         if (adev->asic_type != CHIP_CARRIZO)
3314                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3315
3316         if (!adev->firmware.smu_load) {
3317                 /* legacy firmware loading */
3318                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3319                 if (r)
3320                         return r;
3321
3322                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3323                 if (r)
3324                         return r;
3325         } else {
3326                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3327                                                 AMDGPU_UCODE_ID_CP_CE);
3328                 if (r)
3329                         return -EINVAL;
3330
3331                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3332                                                 AMDGPU_UCODE_ID_CP_PFP);
3333                 if (r)
3334                         return -EINVAL;
3335
3336                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3337                                                 AMDGPU_UCODE_ID_CP_ME);
3338                 if (r)
3339                         return -EINVAL;
3340
3341                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3342                                                 AMDGPU_UCODE_ID_CP_MEC1);
3343                 if (r)
3344                         return -EINVAL;
3345         }
3346
3347         r = gfx_v8_0_cp_gfx_resume(adev);
3348         if (r)
3349                 return r;
3350
3351         r = gfx_v8_0_cp_compute_resume(adev);
3352         if (r)
3353                 return r;
3354
3355         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3356
3357         return 0;
3358 }
3359
3360 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3361 {
3362         gfx_v8_0_cp_gfx_enable(adev, enable);
3363         gfx_v8_0_cp_compute_enable(adev, enable);
3364 }
3365
3366 static int gfx_v8_0_hw_init(void *handle)
3367 {
3368         int r;
3369         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3370
3371         gfx_v8_0_init_golden_registers(adev);
3372
3373         gfx_v8_0_gpu_init(adev);
3374
3375         r = gfx_v8_0_rlc_resume(adev);
3376         if (r)
3377                 return r;
3378
3379         r = gfx_v8_0_cp_resume(adev);
3380         if (r)
3381                 return r;
3382
3383         return r;
3384 }
3385
3386 static int gfx_v8_0_hw_fini(void *handle)
3387 {
3388         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3389
3390         gfx_v8_0_cp_enable(adev, false);
3391         gfx_v8_0_rlc_stop(adev);
3392         gfx_v8_0_cp_compute_fini(adev);
3393
3394         return 0;
3395 }
3396
3397 static int gfx_v8_0_suspend(void *handle)
3398 {
3399         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3400
3401         return gfx_v8_0_hw_fini(adev);
3402 }
3403
3404 static int gfx_v8_0_resume(void *handle)
3405 {
3406         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3407
3408         return gfx_v8_0_hw_init(adev);
3409 }
3410
3411 static bool gfx_v8_0_is_idle(void *handle)
3412 {
3413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3414
3415         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3416                 return false;
3417         else
3418                 return true;
3419 }
3420
3421 static int gfx_v8_0_wait_for_idle(void *handle)
3422 {
3423         unsigned i;
3424         u32 tmp;
3425         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3426
3427         for (i = 0; i < adev->usec_timeout; i++) {
3428                 /* read MC_STATUS */
3429                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3430
3431                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3432                         return 0;
3433                 udelay(1);
3434         }
3435         return -ETIMEDOUT;
3436 }
3437
3438 static void gfx_v8_0_print_status(void *handle)
3439 {
3440         int i;
3441         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3442
3443         dev_info(adev->dev, "GFX 8.x registers\n");
3444         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
3445                  RREG32(mmGRBM_STATUS));
3446         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
3447                  RREG32(mmGRBM_STATUS2));
3448         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
3449                  RREG32(mmGRBM_STATUS_SE0));
3450         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
3451                  RREG32(mmGRBM_STATUS_SE1));
3452         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
3453                  RREG32(mmGRBM_STATUS_SE2));
3454         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
3455                  RREG32(mmGRBM_STATUS_SE3));
3456         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3457         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
3458                  RREG32(mmCP_STALLED_STAT1));
3459         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
3460                  RREG32(mmCP_STALLED_STAT2));
3461         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
3462                  RREG32(mmCP_STALLED_STAT3));
3463         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
3464                  RREG32(mmCP_CPF_BUSY_STAT));
3465         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
3466                  RREG32(mmCP_CPF_STALLED_STAT1));
3467         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3468         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3469         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
3470                  RREG32(mmCP_CPC_STALLED_STAT1));
3471         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3472
3473         for (i = 0; i < 32; i++) {
3474                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
3475                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3476         }
3477         for (i = 0; i < 16; i++) {
3478                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
3479                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3480         }
3481         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3482                 dev_info(adev->dev, "  se: %d\n", i);
3483                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3484                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
3485                          RREG32(mmPA_SC_RASTER_CONFIG));
3486                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
3487                          RREG32(mmPA_SC_RASTER_CONFIG_1));
3488         }
3489         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3490
3491         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
3492                  RREG32(mmGB_ADDR_CONFIG));
3493         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
3494                  RREG32(mmHDP_ADDR_CONFIG));
3495         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
3496                  RREG32(mmDMIF_ADDR_CALC));
3497         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
3498                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3499         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
3500                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3501         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3502                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
3503         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3504                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3505         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3506                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3507
3508         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
3509                  RREG32(mmCP_MEQ_THRESHOLDS));
3510         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
3511                  RREG32(mmSX_DEBUG_1));
3512         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
3513                  RREG32(mmTA_CNTL_AUX));
3514         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
3515                  RREG32(mmSPI_CONFIG_CNTL));
3516         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
3517                  RREG32(mmSQ_CONFIG));
3518         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
3519                  RREG32(mmDB_DEBUG));
3520         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
3521                  RREG32(mmDB_DEBUG2));
3522         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
3523                  RREG32(mmDB_DEBUG3));
3524         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
3525                  RREG32(mmCB_HW_CONTROL));
3526         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
3527                  RREG32(mmSPI_CONFIG_CNTL_1));
3528         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
3529                  RREG32(mmPA_SC_FIFO_SIZE));
3530         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
3531                  RREG32(mmVGT_NUM_INSTANCES));
3532         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
3533                  RREG32(mmCP_PERFMON_CNTL));
3534         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3535                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3536         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
3537                  RREG32(mmVGT_CACHE_INVALIDATION));
3538         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
3539                  RREG32(mmVGT_GS_VERTEX_REUSE));
3540         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3541                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3542         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
3543                  RREG32(mmPA_CL_ENHANCE));
3544         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
3545                  RREG32(mmPA_SC_ENHANCE));
3546
3547         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
3548                  RREG32(mmCP_ME_CNTL));
3549         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
3550                  RREG32(mmCP_MAX_CONTEXT));
3551         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
3552                  RREG32(mmCP_ENDIAN_SWAP));
3553         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
3554                  RREG32(mmCP_DEVICE_ID));
3555
3556         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
3557                  RREG32(mmCP_SEM_WAIT_TIMER));
3558
3559         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
3560                  RREG32(mmCP_RB_WPTR_DELAY));
3561         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
3562                  RREG32(mmCP_RB_VMID));
3563         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3564                  RREG32(mmCP_RB0_CNTL));
3565         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
3566                  RREG32(mmCP_RB0_WPTR));
3567         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
3568                  RREG32(mmCP_RB0_RPTR_ADDR));
3569         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3570                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
3571         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3572                  RREG32(mmCP_RB0_CNTL));
3573         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
3574                  RREG32(mmCP_RB0_BASE));
3575         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
3576                  RREG32(mmCP_RB0_BASE_HI));
3577         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
3578                  RREG32(mmCP_MEC_CNTL));
3579         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
3580                  RREG32(mmCP_CPF_DEBUG));
3581
3582         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
3583                  RREG32(mmSCRATCH_ADDR));
3584         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
3585                  RREG32(mmSCRATCH_UMSK));
3586
3587         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
3588                  RREG32(mmCP_INT_CNTL_RING0));
3589         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3590                  RREG32(mmRLC_LB_CNTL));
3591         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
3592                  RREG32(mmRLC_CNTL));
3593         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
3594                  RREG32(mmRLC_CGCG_CGLS_CTRL));
3595         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
3596                  RREG32(mmRLC_LB_CNTR_INIT));
3597         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
3598                  RREG32(mmRLC_LB_CNTR_MAX));
3599         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
3600                  RREG32(mmRLC_LB_INIT_CU_MASK));
3601         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
3602                  RREG32(mmRLC_LB_PARAMS));
3603         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3604                  RREG32(mmRLC_LB_CNTL));
3605         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
3606                  RREG32(mmRLC_MC_CNTL));
3607         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
3608                  RREG32(mmRLC_UCODE_CNTL));
3609
3610         mutex_lock(&adev->srbm_mutex);
3611         for (i = 0; i < 16; i++) {
3612                 vi_srbm_select(adev, 0, 0, 0, i);
3613                 dev_info(adev->dev, "  VM %d:\n", i);
3614                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
3615                          RREG32(mmSH_MEM_CONFIG));
3616                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
3617                          RREG32(mmSH_MEM_APE1_BASE));
3618                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
3619                          RREG32(mmSH_MEM_APE1_LIMIT));
3620                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
3621                          RREG32(mmSH_MEM_BASES));
3622         }
3623         vi_srbm_select(adev, 0, 0, 0, 0);
3624         mutex_unlock(&adev->srbm_mutex);
3625 }
3626
3627 static int gfx_v8_0_soft_reset(void *handle)
3628 {
3629         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3630         u32 tmp;
3631         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3632
3633         /* GRBM_STATUS */
3634         tmp = RREG32(mmGRBM_STATUS);
3635         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3636                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3637                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3638                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3639                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3640                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3641                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3642                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3643                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3644                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3645         }
3646
3647         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3648                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3649                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3650                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3651                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3652         }
3653
3654         /* GRBM_STATUS2 */
3655         tmp = RREG32(mmGRBM_STATUS2);
3656         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3657                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3658                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3659
3660         /* SRBM_STATUS */
3661         tmp = RREG32(mmSRBM_STATUS);
3662         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3663                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3664                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3665
3666         if (grbm_soft_reset || srbm_soft_reset) {
3667                 gfx_v8_0_print_status((void *)adev);
3668                 /* stop the rlc */
3669                 gfx_v8_0_rlc_stop(adev);
3670
3671                 /* Disable GFX parsing/prefetching */
3672                 gfx_v8_0_cp_gfx_enable(adev, false);
3673
3674                 /* Disable MEC parsing/prefetching */
3675                 /* XXX todo */
3676
3677                 if (grbm_soft_reset) {
3678                         tmp = RREG32(mmGRBM_SOFT_RESET);
3679                         tmp |= grbm_soft_reset;
3680                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3681                         WREG32(mmGRBM_SOFT_RESET, tmp);
3682                         tmp = RREG32(mmGRBM_SOFT_RESET);
3683
3684                         udelay(50);
3685
3686                         tmp &= ~grbm_soft_reset;
3687                         WREG32(mmGRBM_SOFT_RESET, tmp);
3688                         tmp = RREG32(mmGRBM_SOFT_RESET);
3689                 }
3690
3691                 if (srbm_soft_reset) {
3692                         tmp = RREG32(mmSRBM_SOFT_RESET);
3693                         tmp |= srbm_soft_reset;
3694                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3695                         WREG32(mmSRBM_SOFT_RESET, tmp);
3696                         tmp = RREG32(mmSRBM_SOFT_RESET);
3697
3698                         udelay(50);
3699
3700                         tmp &= ~srbm_soft_reset;
3701                         WREG32(mmSRBM_SOFT_RESET, tmp);
3702                         tmp = RREG32(mmSRBM_SOFT_RESET);
3703                 }
3704                 /* Wait a little for things to settle down */
3705                 udelay(50);
3706                 gfx_v8_0_print_status((void *)adev);
3707         }
3708         return 0;
3709 }
3710
3711 /**
3712  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3713  *
3714  * @adev: amdgpu_device pointer
3715  *
3716  * Fetches a GPU clock counter snapshot.
3717  * Returns the 64 bit clock counter snapshot.
3718  */
3719 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3720 {
3721         uint64_t clock;
3722
3723         mutex_lock(&adev->gfx.gpu_clock_mutex);
3724         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3725         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3726                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3727         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3728         return clock;
3729 }
3730
3731 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3732                                           uint32_t vmid,
3733                                           uint32_t gds_base, uint32_t gds_size,
3734                                           uint32_t gws_base, uint32_t gws_size,
3735                                           uint32_t oa_base, uint32_t oa_size)
3736 {
3737         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3738         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3739
3740         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3741         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3742
3743         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3744         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3745
3746         /* GDS Base */
3747         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3748         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3749                                 WRITE_DATA_DST_SEL(0)));
3750         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3751         amdgpu_ring_write(ring, 0);
3752         amdgpu_ring_write(ring, gds_base);
3753
3754         /* GDS Size */
3755         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3756         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3757                                 WRITE_DATA_DST_SEL(0)));
3758         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3759         amdgpu_ring_write(ring, 0);
3760         amdgpu_ring_write(ring, gds_size);
3761
3762         /* GWS */
3763         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3764         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3765                                 WRITE_DATA_DST_SEL(0)));
3766         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3767         amdgpu_ring_write(ring, 0);
3768         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3769
3770         /* OA */
3771         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3772         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3773                                 WRITE_DATA_DST_SEL(0)));
3774         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3775         amdgpu_ring_write(ring, 0);
3776         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3777 }
3778
3779 static int gfx_v8_0_early_init(void *handle)
3780 {
3781         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3782
3783         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3784         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3785         gfx_v8_0_set_ring_funcs(adev);
3786         gfx_v8_0_set_irq_funcs(adev);
3787         gfx_v8_0_set_gds_init(adev);
3788
3789         return 0;
3790 }
3791
3792 static int gfx_v8_0_set_powergating_state(void *handle,
3793                                           enum amd_powergating_state state)
3794 {
3795         return 0;
3796 }
3797
3798 static int gfx_v8_0_set_clockgating_state(void *handle,
3799                                           enum amd_clockgating_state state)
3800 {
3801         return 0;
3802 }
3803
3804 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3805 {
3806         u32 rptr;
3807
3808         rptr = ring->adev->wb.wb[ring->rptr_offs];
3809
3810         return rptr;
3811 }
3812
3813 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3814 {
3815         struct amdgpu_device *adev = ring->adev;
3816         u32 wptr;
3817
3818         if (ring->use_doorbell)
3819                 /* XXX check if swapping is necessary on BE */
3820                 wptr = ring->adev->wb.wb[ring->wptr_offs];
3821         else
3822                 wptr = RREG32(mmCP_RB0_WPTR);
3823
3824         return wptr;
3825 }
3826
3827 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3828 {
3829         struct amdgpu_device *adev = ring->adev;
3830
3831         if (ring->use_doorbell) {
3832                 /* XXX check if swapping is necessary on BE */
3833                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3834                 WDOORBELL32(ring->doorbell_index, ring->wptr);
3835         } else {
3836                 WREG32(mmCP_RB0_WPTR, ring->wptr);
3837                 (void)RREG32(mmCP_RB0_WPTR);
3838         }
3839 }
3840
3841 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3842 {
3843         u32 ref_and_mask, reg_mem_engine;
3844
3845         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3846                 switch (ring->me) {
3847                 case 1:
3848                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3849                         break;
3850                 case 2:
3851                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3852                         break;
3853                 default:
3854                         return;
3855                 }
3856                 reg_mem_engine = 0;
3857         } else {
3858                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3859                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3860         }
3861
3862         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3863         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3864                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
3865                                  reg_mem_engine));
3866         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3867         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3868         amdgpu_ring_write(ring, ref_and_mask);
3869         amdgpu_ring_write(ring, ref_and_mask);
3870         amdgpu_ring_write(ring, 0x20); /* poll interval */
3871 }
3872
3873 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3874                                   struct amdgpu_ib *ib)
3875 {
3876         bool need_ctx_switch = ring->current_ctx != ib->ctx;
3877         u32 header, control = 0;
3878         u32 next_rptr = ring->wptr + 5;
3879
3880         /* drop the CE preamble IB for the same context */
3881         if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
3882                 return;
3883
3884         if (need_ctx_switch)
3885                 next_rptr += 2;
3886
3887         next_rptr += 4;
3888         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3889         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3890         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3891         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3892         amdgpu_ring_write(ring, next_rptr);
3893
3894         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3895         if (need_ctx_switch) {
3896                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3897                 amdgpu_ring_write(ring, 0);
3898         }
3899
3900         if (ib->flags & AMDGPU_IB_FLAG_CE)
3901                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3902         else
3903                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3904
3905         control |= ib->length_dw |
3906                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3907
3908         amdgpu_ring_write(ring, header);
3909         amdgpu_ring_write(ring,
3910 #ifdef __BIG_ENDIAN
3911                           (2 << 0) |
3912 #endif
3913                           (ib->gpu_addr & 0xFFFFFFFC));
3914         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3915         amdgpu_ring_write(ring, control);
3916 }
3917
3918 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3919                                   struct amdgpu_ib *ib)
3920 {
3921         u32 header, control = 0;
3922         u32 next_rptr = ring->wptr + 5;
3923
3924         control |= INDIRECT_BUFFER_VALID;
3925
3926         next_rptr += 4;
3927         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3928         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3929         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3930         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3931         amdgpu_ring_write(ring, next_rptr);
3932
3933         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3934
3935         control |= ib->length_dw |
3936                            (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3937
3938         amdgpu_ring_write(ring, header);
3939         amdgpu_ring_write(ring,
3940 #ifdef __BIG_ENDIAN
3941                                           (2 << 0) |
3942 #endif
3943                                           (ib->gpu_addr & 0xFFFFFFFC));
3944         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3945         amdgpu_ring_write(ring, control);
3946 }
3947
3948 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3949                                          u64 seq, unsigned flags)
3950 {
3951         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3952         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3953
3954         /* EVENT_WRITE_EOP - flush caches, send int */
3955         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3956         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3957                                  EOP_TC_ACTION_EN |
3958                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3959                                  EVENT_INDEX(5)));
3960         amdgpu_ring_write(ring, addr & 0xfffffffc);
3961         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3962                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3963         amdgpu_ring_write(ring, lower_32_bits(seq));
3964         amdgpu_ring_write(ring, upper_32_bits(seq));
3965 }
3966
3967 /**
3968  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3969  *
3970  * @ring: amdgpu ring buffer object
3971  * @semaphore: amdgpu semaphore object
3972  * @emit_wait: Is this a sempahore wait?
3973  *
3974  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3975  * from running ahead of semaphore waits.
3976  */
3977 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3978                                          struct amdgpu_semaphore *semaphore,
3979                                          bool emit_wait)
3980 {
3981         uint64_t addr = semaphore->gpu_addr;
3982         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3983
3984         if (ring->adev->asic_type == CHIP_TOPAZ ||
3985             ring->adev->asic_type == CHIP_TONGA ||
3986             ring->adev->asic_type == CHIP_FIJI)
3987                 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3988                 return false;
3989         else {
3990                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3991                 amdgpu_ring_write(ring, lower_32_bits(addr));
3992                 amdgpu_ring_write(ring, upper_32_bits(addr));
3993                 amdgpu_ring_write(ring, sel);
3994         }
3995
3996         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3997                 /* Prevent the PFP from running ahead of the semaphore wait */
3998                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3999                 amdgpu_ring_write(ring, 0x0);
4000         }
4001
4002         return true;
4003 }
4004
4005 static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
4006 {
4007         struct amdgpu_device *adev = ring->adev;
4008         u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
4009
4010         /* instruct DE to set a magic number */
4011         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4012         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4013                                                          WRITE_DATA_DST_SEL(5)));
4014         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4015         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4016         amdgpu_ring_write(ring, 1);
4017
4018         /* let CE wait till condition satisfied */
4019         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4020         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4021                                                          WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4022                                                          WAIT_REG_MEM_FUNCTION(3) |  /* == */
4023                                                          WAIT_REG_MEM_ENGINE(2)));   /* ce */
4024         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4025         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4026         amdgpu_ring_write(ring, 1);
4027         amdgpu_ring_write(ring, 0xffffffff);
4028         amdgpu_ring_write(ring, 4); /* poll interval */
4029
4030         /* instruct CE to reset wb of ce_sync to zero */
4031         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4032         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4033                                                          WRITE_DATA_DST_SEL(5) |
4034                                                          WR_CONFIRM));
4035         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4036         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4037         amdgpu_ring_write(ring, 0);
4038 }
4039
4040 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4041                                         unsigned vm_id, uint64_t pd_addr)
4042 {
4043         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4044
4045         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4046         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4047                                  WRITE_DATA_DST_SEL(0)));
4048         if (vm_id < 8) {
4049                 amdgpu_ring_write(ring,
4050                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4051         } else {
4052                 amdgpu_ring_write(ring,
4053                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4054         }
4055         amdgpu_ring_write(ring, 0);
4056         amdgpu_ring_write(ring, pd_addr >> 12);
4057
4058         /* bits 0-15 are the VM contexts0-15 */
4059         /* invalidate the cache */
4060         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4061         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4062                                  WRITE_DATA_DST_SEL(0)));
4063         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4064         amdgpu_ring_write(ring, 0);
4065         amdgpu_ring_write(ring, 1 << vm_id);
4066
4067         /* wait for the invalidate to complete */
4068         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4069         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4070                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
4071                                  WAIT_REG_MEM_ENGINE(0))); /* me */
4072         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4073         amdgpu_ring_write(ring, 0);
4074         amdgpu_ring_write(ring, 0); /* ref */
4075         amdgpu_ring_write(ring, 0); /* mask */
4076         amdgpu_ring_write(ring, 0x20); /* poll interval */
4077
4078         /* compute doesn't have PFP */
4079         if (usepfp) {
4080                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4081                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4082                 amdgpu_ring_write(ring, 0x0);
4083
4084                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4085                 gfx_v8_0_ce_sync_me(ring);
4086         }
4087 }
4088
4089 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
4090 {
4091         if (gfx_v8_0_is_idle(ring->adev)) {
4092                 amdgpu_ring_lockup_update(ring);
4093                 return false;
4094         }
4095         return amdgpu_ring_test_lockup(ring);
4096 }
4097
4098 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4099 {
4100         return ring->adev->wb.wb[ring->rptr_offs];
4101 }
4102
4103 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4104 {
4105         return ring->adev->wb.wb[ring->wptr_offs];
4106 }
4107
4108 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4109 {
4110         struct amdgpu_device *adev = ring->adev;
4111
4112         /* XXX check if swapping is necessary on BE */
4113         adev->wb.wb[ring->wptr_offs] = ring->wptr;
4114         WDOORBELL32(ring->doorbell_index, ring->wptr);
4115 }
4116
4117 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4118                                              u64 addr, u64 seq,
4119                                              unsigned flags)
4120 {
4121         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4122         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4123
4124         /* RELEASE_MEM - flush caches, send int */
4125         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4126         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4127                                  EOP_TC_ACTION_EN |
4128                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4129                                  EVENT_INDEX(5)));
4130         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4131         amdgpu_ring_write(ring, addr & 0xfffffffc);
4132         amdgpu_ring_write(ring, upper_32_bits(addr));
4133         amdgpu_ring_write(ring, lower_32_bits(seq));
4134         amdgpu_ring_write(ring, upper_32_bits(seq));
4135 }
4136
4137 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4138                                                  enum amdgpu_interrupt_state state)
4139 {
4140         u32 cp_int_cntl;
4141
4142         switch (state) {
4143         case AMDGPU_IRQ_STATE_DISABLE:
4144                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4145                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4146                                             TIME_STAMP_INT_ENABLE, 0);
4147                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4148                 break;
4149         case AMDGPU_IRQ_STATE_ENABLE:
4150                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4151                 cp_int_cntl =
4152                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4153                                       TIME_STAMP_INT_ENABLE, 1);
4154                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4155                 break;
4156         default:
4157                 break;
4158         }
4159 }
4160
4161 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4162                                                      int me, int pipe,
4163                                                      enum amdgpu_interrupt_state state)
4164 {
4165         u32 mec_int_cntl, mec_int_cntl_reg;
4166
4167         /*
4168          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4169          * handles the setting of interrupts for this specific pipe. All other
4170          * pipes' interrupts are set by amdkfd.
4171          */
4172
4173         if (me == 1) {
4174                 switch (pipe) {
4175                 case 0:
4176                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4177                         break;
4178                 default:
4179                         DRM_DEBUG("invalid pipe %d\n", pipe);
4180                         return;
4181                 }
4182         } else {
4183                 DRM_DEBUG("invalid me %d\n", me);
4184                 return;
4185         }
4186
4187         switch (state) {
4188         case AMDGPU_IRQ_STATE_DISABLE:
4189                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4190                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4191                                              TIME_STAMP_INT_ENABLE, 0);
4192                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4193                 break;
4194         case AMDGPU_IRQ_STATE_ENABLE:
4195                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4196                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4197                                              TIME_STAMP_INT_ENABLE, 1);
4198                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4199                 break;
4200         default:
4201                 break;
4202         }
4203 }
4204
4205 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4206                                              struct amdgpu_irq_src *source,
4207                                              unsigned type,
4208                                              enum amdgpu_interrupt_state state)
4209 {
4210         u32 cp_int_cntl;
4211
4212         switch (state) {
4213         case AMDGPU_IRQ_STATE_DISABLE:
4214                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4215                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4216                                             PRIV_REG_INT_ENABLE, 0);
4217                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4218                 break;
4219         case AMDGPU_IRQ_STATE_ENABLE:
4220                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4221                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4222                                             PRIV_REG_INT_ENABLE, 0);
4223                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4224                 break;
4225         default:
4226                 break;
4227         }
4228
4229         return 0;
4230 }
4231
4232 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4233                                               struct amdgpu_irq_src *source,
4234                                               unsigned type,
4235                                               enum amdgpu_interrupt_state state)
4236 {
4237         u32 cp_int_cntl;
4238
4239         switch (state) {
4240         case AMDGPU_IRQ_STATE_DISABLE:
4241                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4242                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4243                                             PRIV_INSTR_INT_ENABLE, 0);
4244                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4245                 break;
4246         case AMDGPU_IRQ_STATE_ENABLE:
4247                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4248                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4249                                             PRIV_INSTR_INT_ENABLE, 1);
4250                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4251                 break;
4252         default:
4253                 break;
4254         }
4255
4256         return 0;
4257 }
4258
4259 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4260                                             struct amdgpu_irq_src *src,
4261                                             unsigned type,
4262                                             enum amdgpu_interrupt_state state)
4263 {
4264         switch (type) {
4265         case AMDGPU_CP_IRQ_GFX_EOP:
4266                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4267                 break;
4268         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4269                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4270                 break;
4271         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4272                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4273                 break;
4274         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4275                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4276                 break;
4277         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4278                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4279                 break;
4280         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4281                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4282                 break;
4283         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4284                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4285                 break;
4286         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4287                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4288                 break;
4289         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4290                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4291                 break;
4292         default:
4293                 break;
4294         }
4295         return 0;
4296 }
4297
4298 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4299                             struct amdgpu_irq_src *source,
4300                             struct amdgpu_iv_entry *entry)
4301 {
4302         int i;
4303         u8 me_id, pipe_id, queue_id;
4304         struct amdgpu_ring *ring;
4305
4306         DRM_DEBUG("IH: CP EOP\n");
4307         me_id = (entry->ring_id & 0x0c) >> 2;
4308         pipe_id = (entry->ring_id & 0x03) >> 0;
4309         queue_id = (entry->ring_id & 0x70) >> 4;
4310
4311         switch (me_id) {
4312         case 0:
4313                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4314                 break;
4315         case 1:
4316         case 2:
4317                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4318                         ring = &adev->gfx.compute_ring[i];
4319                         /* Per-queue interrupt is supported for MEC starting from VI.
4320                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4321                           */
4322                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4323                                 amdgpu_fence_process(ring);
4324                 }
4325                 break;
4326         }
4327         return 0;
4328 }
4329
4330 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4331                                  struct amdgpu_irq_src *source,
4332                                  struct amdgpu_iv_entry *entry)
4333 {
4334         DRM_ERROR("Illegal register access in command stream\n");
4335         schedule_work(&adev->reset_work);
4336         return 0;
4337 }
4338
4339 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4340                                   struct amdgpu_irq_src *source,
4341                                   struct amdgpu_iv_entry *entry)
4342 {
4343         DRM_ERROR("Illegal instruction in command stream\n");
4344         schedule_work(&adev->reset_work);
4345         return 0;
4346 }
4347
4348 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4349         .early_init = gfx_v8_0_early_init,
4350         .late_init = NULL,
4351         .sw_init = gfx_v8_0_sw_init,
4352         .sw_fini = gfx_v8_0_sw_fini,
4353         .hw_init = gfx_v8_0_hw_init,
4354         .hw_fini = gfx_v8_0_hw_fini,
4355         .suspend = gfx_v8_0_suspend,
4356         .resume = gfx_v8_0_resume,
4357         .is_idle = gfx_v8_0_is_idle,
4358         .wait_for_idle = gfx_v8_0_wait_for_idle,
4359         .soft_reset = gfx_v8_0_soft_reset,
4360         .print_status = gfx_v8_0_print_status,
4361         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4362         .set_powergating_state = gfx_v8_0_set_powergating_state,
4363 };
4364
4365 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4366         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4367         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4368         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4369         .parse_cs = NULL,
4370         .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4371         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4372         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4373         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4374         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4375         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4376         .test_ring = gfx_v8_0_ring_test_ring,
4377         .test_ib = gfx_v8_0_ring_test_ib,
4378         .is_lockup = gfx_v8_0_ring_is_lockup,
4379 };
4380
4381 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4382         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4383         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4384         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4385         .parse_cs = NULL,
4386         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4387         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4388         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4389         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4390         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4391         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4392         .test_ring = gfx_v8_0_ring_test_ring,
4393         .test_ib = gfx_v8_0_ring_test_ib,
4394         .is_lockup = gfx_v8_0_ring_is_lockup,
4395 };
4396
4397 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4398 {
4399         int i;
4400
4401         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4402                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4403
4404         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4405                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4406 }
4407
4408 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4409         .set = gfx_v8_0_set_eop_interrupt_state,
4410         .process = gfx_v8_0_eop_irq,
4411 };
4412
4413 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4414         .set = gfx_v8_0_set_priv_reg_fault_state,
4415         .process = gfx_v8_0_priv_reg_irq,
4416 };
4417
4418 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4419         .set = gfx_v8_0_set_priv_inst_fault_state,
4420         .process = gfx_v8_0_priv_inst_irq,
4421 };
4422
4423 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4424 {
4425         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4426         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4427
4428         adev->gfx.priv_reg_irq.num_types = 1;
4429         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4430
4431         adev->gfx.priv_inst_irq.num_types = 1;
4432         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4433 }
4434
4435 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4436 {
4437         /* init asci gds info */
4438         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4439         adev->gds.gws.total_size = 64;
4440         adev->gds.oa.total_size = 16;
4441
4442         if (adev->gds.mem.total_size == 64 * 1024) {
4443                 adev->gds.mem.gfx_partition_size = 4096;
4444                 adev->gds.mem.cs_partition_size = 4096;
4445
4446                 adev->gds.gws.gfx_partition_size = 4;
4447                 adev->gds.gws.cs_partition_size = 4;
4448
4449                 adev->gds.oa.gfx_partition_size = 4;
4450                 adev->gds.oa.cs_partition_size = 1;
4451         } else {
4452                 adev->gds.mem.gfx_partition_size = 1024;
4453                 adev->gds.mem.cs_partition_size = 1024;
4454
4455                 adev->gds.gws.gfx_partition_size = 16;
4456                 adev->gds.gws.cs_partition_size = 16;
4457
4458                 adev->gds.oa.gfx_partition_size = 4;
4459                 adev->gds.oa.cs_partition_size = 4;
4460         }
4461 }
4462
4463 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4464                 u32 se, u32 sh)
4465 {
4466         u32 mask = 0, tmp, tmp1;
4467         int i;
4468
4469         gfx_v8_0_select_se_sh(adev, se, sh);
4470         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4471         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4472         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4473
4474         tmp &= 0xffff0000;
4475
4476         tmp |= tmp1;
4477         tmp >>= 16;
4478
4479         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4480                 mask <<= 1;
4481                 mask |= 1;
4482         }
4483
4484         return (~tmp) & mask;
4485 }
4486
4487 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4488                                                  struct amdgpu_cu_info *cu_info)
4489 {
4490         int i, j, k, counter, active_cu_number = 0;
4491         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4492
4493         if (!adev || !cu_info)
4494                 return -EINVAL;
4495
4496         mutex_lock(&adev->grbm_idx_mutex);
4497         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4498                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4499                         mask = 1;
4500                         ao_bitmap = 0;
4501                         counter = 0;
4502                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4503                         cu_info->bitmap[i][j] = bitmap;
4504
4505                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4506                                 if (bitmap & mask) {
4507                                         if (counter < 2)
4508                                                 ao_bitmap |= mask;
4509                                         counter ++;
4510                                 }
4511                                 mask <<= 1;
4512                         }
4513                         active_cu_number += counter;
4514                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4515                 }
4516         }
4517
4518         cu_info->number = active_cu_number;
4519         cu_info->ao_cu_mask = ao_cu_mask;
4520         mutex_unlock(&adev->grbm_idx_mutex);
4521         return 0;
4522 }