drivers/rtc/rtc-davinci.c

   1 /*
   2  * DaVinci Power Management and Real Time Clock Driver for TI platforms
   3  *
   4  * Copyright (C) 2009 Texas Instruments, Inc
   5  *
   6  * Author: Miguel Aguilar <[email protected]>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/delay.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/rtc.h>
  29 #include <linux/bcd.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/io.h>
  32 #include <linux/slab.h>
  33
  34 /*
  35  * The DaVinci RTC is a simple RTC with the following
  36  * Sec: 0 - 59 : BCD count
  37  * Min: 0 - 59 : BCD count
  38  * Hour: 0 - 23 : BCD count
  39  * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
  40  */
  41
  42 /* PRTC interface registers */
  43 #define DAVINCI_PRTCIF_PID              0x00
  44 #define PRTCIF_CTLR                     0x04
  45 #define PRTCIF_LDATA                    0x08
  46 #define PRTCIF_UDATA                    0x0C
  47 #define PRTCIF_INTEN                    0x10
  48 #define PRTCIF_INTFLG                   0x14
  49
  50 /* PRTCIF_CTLR bit fields */
  51 #define PRTCIF_CTLR_BUSY                BIT(31)
  52 #define PRTCIF_CTLR_SIZE                BIT(25)
  53 #define PRTCIF_CTLR_DIR                 BIT(24)
  54 #define PRTCIF_CTLR_BENU_MSB            BIT(23)
  55 #define PRTCIF_CTLR_BENU_3RD_BYTE       BIT(22)
  56 #define PRTCIF_CTLR_BENU_2ND_BYTE       BIT(21)
  57 #define PRTCIF_CTLR_BENU_LSB            BIT(20)
  58 #define PRTCIF_CTLR_BENU_MASK           (0x00F00000)
  59 #define PRTCIF_CTLR_BENL_MSB            BIT(19)
  60 #define PRTCIF_CTLR_BENL_3RD_BYTE       BIT(18)
  61 #define PRTCIF_CTLR_BENL_2ND_BYTE       BIT(17)
  62 #define PRTCIF_CTLR_BENL_LSB            BIT(16)
  63 #define PRTCIF_CTLR_BENL_MASK           (0x000F0000)
  64
  65 /* PRTCIF_INTEN bit fields */
  66 #define PRTCIF_INTEN_RTCSS              BIT(1)
  67 #define PRTCIF_INTEN_RTCIF              BIT(0)
  68 #define PRTCIF_INTEN_MASK               (PRTCIF_INTEN_RTCSS \
  69                                         | PRTCIF_INTEN_RTCIF)
  70
  71 /* PRTCIF_INTFLG bit fields */
  72 #define PRTCIF_INTFLG_RTCSS             BIT(1)
  73 #define PRTCIF_INTFLG_RTCIF             BIT(0)
  74 #define PRTCIF_INTFLG_MASK              (PRTCIF_INTFLG_RTCSS \
  75                                         | PRTCIF_INTFLG_RTCIF)
  76
  77 /* PRTC subsystem registers */
  78 #define PRTCSS_RTC_INTC_EXTENA1         (0x0C)
  79 #define PRTCSS_RTC_CTRL                 (0x10)
  80 #define PRTCSS_RTC_WDT                  (0x11)
  81 #define PRTCSS_RTC_TMR0                 (0x12)
  82 #define PRTCSS_RTC_TMR1                 (0x13)
  83 #define PRTCSS_RTC_CCTRL                (0x14)
  84 #define PRTCSS_RTC_SEC                  (0x15)
  85 #define PRTCSS_RTC_MIN                  (0x16)
  86 #define PRTCSS_RTC_HOUR                 (0x17)
  87 #define PRTCSS_RTC_DAY0                 (0x18)
  88 #define PRTCSS_RTC_DAY1                 (0x19)
  89 #define PRTCSS_RTC_AMIN                 (0x1A)
  90 #define PRTCSS_RTC_AHOUR                (0x1B)
  91 #define PRTCSS_RTC_ADAY0                (0x1C)
  92 #define PRTCSS_RTC_ADAY1                (0x1D)
  93 #define PRTCSS_RTC_CLKC_CNT             (0x20)
  94
  95 /* PRTCSS_RTC_INTC_EXTENA1 */
  96 #define PRTCSS_RTC_INTC_EXTENA1_MASK    (0x07)
  97
  98 /* PRTCSS_RTC_CTRL bit fields */
  99 #define PRTCSS_RTC_CTRL_WDTBUS          BIT(7)
 100 #define PRTCSS_RTC_CTRL_WEN             BIT(6)
 101 #define PRTCSS_RTC_CTRL_WDRT            BIT(5)
 102 #define PRTCSS_RTC_CTRL_WDTFLG          BIT(4)
 103 #define PRTCSS_RTC_CTRL_TE              BIT(3)
 104 #define PRTCSS_RTC_CTRL_TIEN            BIT(2)
 105 #define PRTCSS_RTC_CTRL_TMRFLG          BIT(1)
 106 #define PRTCSS_RTC_CTRL_TMMD            BIT(0)
 107
 108 /* PRTCSS_RTC_CCTRL bit fields */
 109 #define PRTCSS_RTC_CCTRL_CALBUSY        BIT(7)
 110 #define PRTCSS_RTC_CCTRL_DAEN           BIT(5)
 111 #define PRTCSS_RTC_CCTRL_HAEN           BIT(4)
 112 #define PRTCSS_RTC_CCTRL_MAEN           BIT(3)
 113 #define PRTCSS_RTC_CCTRL_ALMFLG         BIT(2)
 114 #define PRTCSS_RTC_CCTRL_AIEN           BIT(1)
 115 #define PRTCSS_RTC_CCTRL_CAEN           BIT(0)
 116
 117 static DEFINE_SPINLOCK(davinci_rtc_lock);
 118
 119 struct davinci_rtc {
 120         struct rtc_device               *rtc;
 121         void __iomem                    *base;
 122         resource_size_t                 pbase;
 123         size_t                          base_size;
 124         int                             irq;
 125 };
 126
 127 static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
 128                                u32 val, u32 addr)
 129 {
 130         writel(val, davinci_rtc->base + addr);
 131 }
 132
 133 static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
 134 {
 135         return readl(davinci_rtc->base + addr);
 136 }
 137
 138 static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
 139 {
 140         while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
 141                 cpu_relax();
 142 }
 143
 144 static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
 145                                unsigned long val, u8 addr)
 146 {
 147         rtcif_wait(davinci_rtc);
 148
 149         rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
 150         rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
 151
 152         rtcif_wait(davinci_rtc);
 153 }
 154
 155 static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
 156 {
 157         rtcif_wait(davinci_rtc);
 158
 159         rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
 160                     PRTCIF_CTLR);
 161
 162         rtcif_wait(davinci_rtc);
 163
 164         return rtcif_read(davinci_rtc, PRTCIF_LDATA);
 165 }
 166
 167 static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
 168 {
 169         while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
 170                PRTCSS_RTC_CCTRL_CALBUSY)
 171                 cpu_relax();
 172 }
 173
 174 static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
 175 {
 176         struct davinci_rtc *davinci_rtc = class_dev;
 177         unsigned long events = 0;
 178         u32 irq_flg;
 179         u8 alm_irq, tmr_irq;
 180         u8 rtc_ctrl, rtc_cctrl;
 181         int ret = IRQ_NONE;
 182
 183         irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
 184                   PRTCIF_INTFLG_RTCSS;
 185
 186         alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
 187                   PRTCSS_RTC_CCTRL_ALMFLG;
 188
 189         tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
 190                   PRTCSS_RTC_CTRL_TMRFLG;
 191
 192         if (irq_flg) {
 193                 if (alm_irq) {
 194                         events |= RTC_IRQF | RTC_AF;
 195                         rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
 196                         rtc_cctrl |=  PRTCSS_RTC_CCTRL_ALMFLG;
 197                         rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
 198                 } else if (tmr_irq) {
 199                         events |= RTC_IRQF | RTC_PF;
 200                         rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
 201                         rtc_ctrl |=  PRTCSS_RTC_CTRL_TMRFLG;
 202                         rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
 203                 }
 204
 205                 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
 206                                     PRTCIF_INTFLG);
 207                 rtc_update_irq(davinci_rtc->rtc, 1, events);
 208
 209                 ret = IRQ_HANDLED;
 210         }
 211
 212         return ret;
 213 }
 214
 215 static int
 216 davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
 217 {
 218         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 219         u8 rtc_ctrl;
 220         unsigned long flags;
 221         int ret = 0;
 222
 223         spin_lock_irqsave(&davinci_rtc_lock, flags);
 224
 225         rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
 226
 227         switch (cmd) {
 228         case RTC_WIE_ON:
 229                 rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
 230                 break;
 231         case RTC_WIE_OFF:
 232                 rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
 233                 break;
 234         case RTC_UIE_OFF:
 235         case RTC_UIE_ON:
 236                 ret = -ENOTTY;
 237                 break;
 238         default:
 239                 ret = -ENOIOCTLCMD;
 240         }
 241
 242         rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
 243
 244         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 245
 246         return ret;
 247 }
 248
 249 static int convertfromdays(u16 days, struct rtc_time *tm)
 250 {
 251         int tmp_days, year, mon;
 252
 253         for (year = 2000;; year++) {
 254                 tmp_days = rtc_year_days(1, 12, year);
 255                 if (days >= tmp_days)
 256                         days -= tmp_days;
 257                 else {
 258                         for (mon = 0;; mon++) {
 259                                 tmp_days = rtc_month_days(mon, year);
 260                                 if (days >= tmp_days) {
 261                                         days -= tmp_days;
 262                                 } else {
 263                                         tm->tm_year = year - 1900;
 264                                         tm->tm_mon = mon;
 265                                         tm->tm_mday = days + 1;
 266                                         break;
 267                                 }
 268                         }
 269                         break;
 270                 }
 271         }
 272         return 0;
 273 }
 274
 275 static int convert2days(u16 *days, struct rtc_time *tm)
 276 {
 277         int i;
 278         *days = 0;
 279
 280         /* epoch == 1900 */
 281         if (tm->tm_year < 100 || tm->tm_year > 199)
 282                 return -EINVAL;
 283
 284         for (i = 2000; i < 1900 + tm->tm_year; i++)
 285                 *days += rtc_year_days(1, 12, i);
 286
 287         *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
 288
 289         return 0;
 290 }
 291
 292 static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
 293 {
 294         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 295         u16 days = 0;
 296         u8 day0, day1;
 297         unsigned long flags;
 298
 299         spin_lock_irqsave(&davinci_rtc_lock, flags);
 300
 301         davinci_rtcss_calendar_wait(davinci_rtc);
 302         tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
 303
 304         davinci_rtcss_calendar_wait(davinci_rtc);
 305         tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
 306
 307         davinci_rtcss_calendar_wait(davinci_rtc);
 308         tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
 309
 310         davinci_rtcss_calendar_wait(davinci_rtc);
 311         day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
 312
 313         davinci_rtcss_calendar_wait(davinci_rtc);
 314         day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
 315
 316         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 317
 318         days |= day1;
 319         days <<= 8;
 320         days |= day0;
 321
 322         if (convertfromdays(days, tm) < 0)
 323                 return -EINVAL;
 324
 325         return 0;
 326 }
 327
 328 static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
 329 {
 330         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 331         u16 days;
 332         u8 rtc_cctrl;
 333         unsigned long flags;
 334
 335         if (convert2days(&days, tm) < 0)
 336                 return -EINVAL;
 337
 338         spin_lock_irqsave(&davinci_rtc_lock, flags);
 339
 340         davinci_rtcss_calendar_wait(davinci_rtc);
 341         rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
 342
 343         davinci_rtcss_calendar_wait(davinci_rtc);
 344         rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
 345
 346         davinci_rtcss_calendar_wait(davinci_rtc);
 347         rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
 348
 349         davinci_rtcss_calendar_wait(davinci_rtc);
 350         rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
 351
 352         davinci_rtcss_calendar_wait(davinci_rtc);
 353         rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
 354
 355         rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
 356         rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
 357         rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
 358
 359         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 360
 361         return 0;
 362 }
 363
 364 static int davinci_rtc_alarm_irq_enable(struct device *dev,
 365                                         unsigned int enabled)
 366 {
 367         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 368         unsigned long flags;
 369         u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
 370
 371         spin_lock_irqsave(&davinci_rtc_lock, flags);
 372
 373         if (enabled)
 374                 rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
 375                              PRTCSS_RTC_CCTRL_HAEN |
 376                              PRTCSS_RTC_CCTRL_MAEN |
 377                              PRTCSS_RTC_CCTRL_ALMFLG |
 378                              PRTCSS_RTC_CCTRL_AIEN;
 379         else
 380                 rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
 381
 382         davinci_rtcss_calendar_wait(davinci_rtc);
 383         rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
 384
 385         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 386
 387         return 0;
 388 }
 389
 390 static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 391 {
 392         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 393         u16 days = 0;
 394         u8 day0, day1;
 395         unsigned long flags;
 396
 397         spin_lock_irqsave(&davinci_rtc_lock, flags);
 398
 399         davinci_rtcss_calendar_wait(davinci_rtc);
 400         alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
 401
 402         davinci_rtcss_calendar_wait(davinci_rtc);
 403         alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
 404
 405         davinci_rtcss_calendar_wait(davinci_rtc);
 406         day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
 407
 408         davinci_rtcss_calendar_wait(davinci_rtc);
 409         day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
 410
 411         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 412         days |= day1;
 413         days <<= 8;
 414         days |= day0;
 415
 416         if (convertfromdays(days, &alm->time) < 0)
 417                 return -EINVAL;
 418
 419         alm->pending = !!(rtcss_read(davinci_rtc,
 420                           PRTCSS_RTC_CCTRL) &
 421                         PRTCSS_RTC_CCTRL_AIEN);
 422         alm->enabled = alm->pending && device_may_wakeup(dev);
 423
 424         return 0;
 425 }
 426
 427 static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 428 {
 429         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 430         unsigned long flags;
 431         u16 days;
 432
 433         if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
 434             && alm->time.tm_year < 0) {
 435                 struct rtc_time tm;
 436                 unsigned long now, then;
 437
 438                 davinci_rtc_read_time(dev, &tm);
 439                 rtc_tm_to_time(&tm, &now);
 440
 441                 alm->time.tm_mday = tm.tm_mday;
 442                 alm->time.tm_mon = tm.tm_mon;
 443                 alm->time.tm_year = tm.tm_year;
 444                 rtc_tm_to_time(&alm->time, &then);
 445
 446                 if (then < now) {
 447                         rtc_time_to_tm(now + 24 * 60 * 60, &tm);
 448                         alm->time.tm_mday = tm.tm_mday;
 449                         alm->time.tm_mon = tm.tm_mon;
 450                         alm->time.tm_year = tm.tm_year;
 451                 }
 452         }
 453
 454         if (convert2days(&days, &alm->time) < 0)
 455                 return -EINVAL;
 456
 457         spin_lock_irqsave(&davinci_rtc_lock, flags);
 458
 459         davinci_rtcss_calendar_wait(davinci_rtc);
 460         rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
 461
 462         davinci_rtcss_calendar_wait(davinci_rtc);
 463         rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
 464
 465         davinci_rtcss_calendar_wait(davinci_rtc);
 466         rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
 467
 468         davinci_rtcss_calendar_wait(davinci_rtc);
 469         rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
 470
 471         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 472
 473         return 0;
 474 }
 475
 476 static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
 477 {
 478         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 479         unsigned long flags;
 480         u8 rtc_ctrl;
 481
 482         spin_lock_irqsave(&davinci_rtc_lock, flags);
 483
 484         rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
 485
 486         if (enabled) {
 487                 while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
 488                        & PRTCSS_RTC_CTRL_WDTBUS)
 489                         cpu_relax();
 490
 491                 rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
 492                 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
 493
 494                 rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
 495
 496                 rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
 497                             PRTCSS_RTC_CTRL_TMMD |
 498                             PRTCSS_RTC_CTRL_TMRFLG;
 499         } else
 500                 rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
 501
 502         rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
 503
 504         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 505
 506         return 0;
 507 }
 508
 509 static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
 510 {
 511         struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
 512         unsigned long flags;
 513         u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
 514
 515         spin_lock_irqsave(&davinci_rtc_lock, flags);
 516
 517         rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
 518         rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
 519
 520         spin_unlock_irqrestore(&davinci_rtc_lock, flags);
 521
 522         return 0;
 523 }
 524
 525 static struct rtc_class_ops davinci_rtc_ops = {
 526         .ioctl                  = davinci_rtc_ioctl,
 527         .read_time              = davinci_rtc_read_time,
 528         .set_time               = davinci_rtc_set_time,
 529         .alarm_irq_enable       = davinci_rtc_alarm_irq_enable,
 530         .read_alarm             = davinci_rtc_read_alarm,
 531         .set_alarm              = davinci_rtc_set_alarm,
 532         .irq_set_state          = davinci_rtc_irq_set_state,
 533         .irq_set_freq           = davinci_rtc_irq_set_freq,
 534 };
 535
 536 static int __init davinci_rtc_probe(struct platform_device *pdev)
 537 {
 538         struct device *dev = &pdev->dev;
 539         struct davinci_rtc *davinci_rtc;
 540         struct resource *res, *mem;
 541         int ret = 0;
 542
 543         davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
 544         if (!davinci_rtc) {
 545                 dev_dbg(dev, "could not allocate memory for private data\n");
 546                 return -ENOMEM;
 547         }
 548
 549         davinci_rtc->irq = platform_get_irq(pdev, 0);
 550         if (davinci_rtc->irq < 0) {
 551                 dev_err(dev, "no RTC irq\n");
 552                 ret = davinci_rtc->irq;
 553                 goto fail1;
 554         }
 555
 556         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 557         if (!res) {
 558                 dev_err(dev, "no mem resource\n");
 559                 ret = -EINVAL;
 560                 goto fail1;
 561         }
 562
 563         davinci_rtc->pbase = res->start;
 564         davinci_rtc->base_size = resource_size(res);
 565
 566         mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
 567                                  pdev->name);
 568         if (!mem) {
 569                 dev_err(dev, "RTC registers at %08x are not free\n",
 570                         davinci_rtc->pbase);
 571                 ret = -EBUSY;
 572                 goto fail1;
 573         }
 574
 575         davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
 576         if (!davinci_rtc->base) {
 577                 dev_err(dev, "unable to ioremap MEM resource\n");
 578                 ret = -ENOMEM;
 579                 goto fail2;
 580         }
 581
 582         davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
 583                                     &davinci_rtc_ops, THIS_MODULE);
 584         if (IS_ERR(davinci_rtc->rtc)) {
 585                 dev_err(dev, "unable to register RTC device, err %ld\n",
 586                                 PTR_ERR(davinci_rtc->rtc));
 587                 goto fail3;
 588         }
 589
 590         rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
 591         rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
 592         rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
 593
 594         rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
 595         rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
 596
 597         ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
 598                           IRQF_DISABLED, "davinci_rtc", davinci_rtc);
 599         if (ret < 0) {
 600                 dev_err(dev, "unable to register davinci RTC interrupt\n");
 601                 goto fail4;
 602         }
 603
 604         /* Enable interrupts */
 605         rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
 606         rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
 607                             PRTCSS_RTC_INTC_EXTENA1);
 608
 609         rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
 610
 611         platform_set_drvdata(pdev, davinci_rtc);
 612
 613         device_init_wakeup(&pdev->dev, 0);
 614
 615         return 0;
 616
 617 fail4:
 618         rtc_device_unregister(davinci_rtc->rtc);
 619 fail3:
 620         iounmap(davinci_rtc->base);
 621 fail2:
 622         release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
 623 fail1:
 624         kfree(davinci_rtc);
 625
 626         return ret;
 627 }
 628
 629 static int __devexit davinci_rtc_remove(struct platform_device *pdev)
 630 {
 631         struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
 632
 633         device_init_wakeup(&pdev->dev, 0);
 634
 635         rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
 636
 637         free_irq(davinci_rtc->irq, davinci_rtc);
 638
 639         rtc_device_unregister(davinci_rtc->rtc);
 640
 641         iounmap(davinci_rtc->base);
 642         release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
 643
 644         platform_set_drvdata(pdev, NULL);
 645
 646         kfree(davinci_rtc);
 647
 648         return 0;
 649 }
 650
 651 static struct platform_driver davinci_rtc_driver = {
 652         .probe          = davinci_rtc_probe,
 653         .remove         = __devexit_p(davinci_rtc_remove),
 654         .driver         = {
 655                 .name = "rtc_davinci",
 656                 .owner = THIS_MODULE,
 657         },
 658 };
 659
 660 static int __init rtc_init(void)
 661 {
 662         return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
 663 }
 664 module_init(rtc_init);
 665
 666 static void __exit rtc_exit(void)
 667 {
 668         platform_driver_unregister(&davinci_rtc_driver);
 669 }
 670 module_exit(rtc_exit);
 671
 672 MODULE_AUTHOR("Miguel Aguilar <[email protected]>");
 673 MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
 674 MODULE_LICENSE("GPL");