drivers/net/phy/micrel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/micrel.c
   4  *
   5  * Driver for Micrel PHYs
   6  *
   7  * Author: David J. Choi
   8  *
   9  * Copyright (c) 2010-2013 Micrel, Inc.
  10  * Copyright (c) 2014 Johan Hovold <[email protected]>
  11  *
  12  * Support : Micrel Phys:
  13  *              Giga phys: ksz9021, ksz9031, ksz9131
  14  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15  *                         ksz8021, ksz8031, ksz8051,
  16  *                         ksz8081, ksz8091,
  17  *                         ksz8061,
  18  *              Switch : ksz8873, ksz886x
  19  *                       ksz9477
  20  */
  21
  22 #include <linux/bitfield.h>
  23 #include <linux/ethtool_netlink.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/phy.h>
  27 #include <linux/micrel_phy.h>
  28 #include <linux/of.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31 #include <linux/ptp_clock_kernel.h>
  32 #include <linux/ptp_clock.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/net_tstamp.h>
  35
  36 /* Operation Mode Strap Override */
  37 #define MII_KSZPHY_OMSO                         0x16
  38 #define KSZPHY_OMSO_FACTORY_TEST                BIT(15)
  39 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  40 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  41 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  42 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  43
  44 /* general Interrupt control/status reg in vendor specific block. */
  45 #define MII_KSZPHY_INTCS                        0x1B
  46 #define KSZPHY_INTCS_JABBER                     BIT(15)
  47 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  48 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  49 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  50 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  51 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  52 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  53 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  54 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  55                                                 KSZPHY_INTCS_LINK_DOWN)
  56 #define KSZPHY_INTCS_LINK_DOWN_STATUS           BIT(2)
  57 #define KSZPHY_INTCS_LINK_UP_STATUS             BIT(0)
  58 #define KSZPHY_INTCS_STATUS                     (KSZPHY_INTCS_LINK_DOWN_STATUS |\
  59                                                  KSZPHY_INTCS_LINK_UP_STATUS)
  60
  61 /* LinkMD Control/Status */
  62 #define KSZ8081_LMD                             0x1d
  63 #define KSZ8081_LMD_ENABLE_TEST                 BIT(15)
  64 #define KSZ8081_LMD_STAT_NORMAL                 0
  65 #define KSZ8081_LMD_STAT_OPEN                   1
  66 #define KSZ8081_LMD_STAT_SHORT                  2
  67 #define KSZ8081_LMD_STAT_FAIL                   3
  68 #define KSZ8081_LMD_STAT_MASK                   GENMASK(14, 13)
  69 /* Short cable (<10 meter) has been detected by LinkMD */
  70 #define KSZ8081_LMD_SHORT_INDICATOR             BIT(12)
  71 #define KSZ8081_LMD_DELTA_TIME_MASK             GENMASK(8, 0)
  72
  73 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
  74 #define LAN8814_INTC                            0x18
  75 #define LAN8814_INTS                            0x1B
  76
  77 #define LAN8814_INT_LINK_DOWN                   BIT(2)
  78 #define LAN8814_INT_LINK_UP                     BIT(0)
  79 #define LAN8814_INT_LINK                        (LAN8814_INT_LINK_UP |\
  80                                                  LAN8814_INT_LINK_DOWN)
  81
  82 #define LAN8814_INTR_CTRL_REG                   0x34
  83 #define LAN8814_INTR_CTRL_REG_POLARITY          BIT(1)
  84 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE       BIT(0)
  85
  86 /* Represents 1ppm adjustment in 2^32 format with
  87  * each nsec contains 4 clock cycles.
  88  * The value is calculated as following: (1/1000000)/((2^-32)/4)
  89  */
  90 #define LAN8814_1PPM_FORMAT                     17179
  91
  92 #define PTP_RX_MOD                              0x024F
  93 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
  94 #define PTP_RX_TIMESTAMP_EN                     0x024D
  95 #define PTP_TX_TIMESTAMP_EN                     0x028D
  96
  97 #define PTP_TIMESTAMP_EN_SYNC_                  BIT(0)
  98 #define PTP_TIMESTAMP_EN_DREQ_                  BIT(1)
  99 #define PTP_TIMESTAMP_EN_PDREQ_                 BIT(2)
 100 #define PTP_TIMESTAMP_EN_PDRES_                 BIT(3)
 101
 102 #define PTP_RX_LATENCY_1000                     0x0224
 103 #define PTP_TX_LATENCY_1000                     0x0225
 104
 105 #define PTP_RX_LATENCY_100                      0x0222
 106 #define PTP_TX_LATENCY_100                      0x0223
 107
 108 #define PTP_RX_LATENCY_10                       0x0220
 109 #define PTP_TX_LATENCY_10                       0x0221
 110
 111 #define PTP_TX_PARSE_L2_ADDR_EN                 0x0284
 112 #define PTP_RX_PARSE_L2_ADDR_EN                 0x0244
 113
 114 #define PTP_TX_PARSE_IP_ADDR_EN                 0x0285
 115 #define PTP_RX_PARSE_IP_ADDR_EN                 0x0245
 116 #define LTC_HARD_RESET                          0x023F
 117 #define LTC_HARD_RESET_                         BIT(0)
 118
 119 #define TSU_HARD_RESET                          0x02C1
 120 #define TSU_HARD_RESET_                         BIT(0)
 121
 122 #define PTP_CMD_CTL                             0x0200
 123 #define PTP_CMD_CTL_PTP_DISABLE_                BIT(0)
 124 #define PTP_CMD_CTL_PTP_ENABLE_                 BIT(1)
 125 #define PTP_CMD_CTL_PTP_CLOCK_READ_             BIT(3)
 126 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_             BIT(4)
 127 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_           BIT(5)
 128 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_          BIT(6)
 129
 130 #define PTP_CLOCK_SET_SEC_MID                   0x0206
 131 #define PTP_CLOCK_SET_SEC_LO                    0x0207
 132 #define PTP_CLOCK_SET_NS_HI                     0x0208
 133 #define PTP_CLOCK_SET_NS_LO                     0x0209
 134
 135 #define PTP_CLOCK_READ_SEC_MID                  0x022A
 136 #define PTP_CLOCK_READ_SEC_LO                   0x022B
 137 #define PTP_CLOCK_READ_NS_HI                    0x022C
 138 #define PTP_CLOCK_READ_NS_LO                    0x022D
 139
 140 #define PTP_OPERATING_MODE                      0x0241
 141 #define PTP_OPERATING_MODE_STANDALONE_          BIT(0)
 142
 143 #define PTP_TX_MOD                              0x028F
 144 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_       BIT(12)
 145 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 146
 147 #define PTP_RX_PARSE_CONFIG                     0x0242
 148 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 149 #define PTP_RX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 150 #define PTP_RX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 151
 152 #define PTP_TX_PARSE_CONFIG                     0x0282
 153 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 154 #define PTP_TX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 155 #define PTP_TX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 156
 157 #define PTP_CLOCK_RATE_ADJ_HI                   0x020C
 158 #define PTP_CLOCK_RATE_ADJ_LO                   0x020D
 159 #define PTP_CLOCK_RATE_ADJ_DIR_                 BIT(15)
 160
 161 #define PTP_LTC_STEP_ADJ_HI                     0x0212
 162 #define PTP_LTC_STEP_ADJ_LO                     0x0213
 163 #define PTP_LTC_STEP_ADJ_DIR_                   BIT(15)
 164
 165 #define LAN8814_INTR_STS_REG                    0x0033
 166 #define LAN8814_INTR_STS_REG_1588_TSU0_         BIT(0)
 167 #define LAN8814_INTR_STS_REG_1588_TSU1_         BIT(1)
 168 #define LAN8814_INTR_STS_REG_1588_TSU2_         BIT(2)
 169 #define LAN8814_INTR_STS_REG_1588_TSU3_         BIT(3)
 170
 171 #define PTP_CAP_INFO                            0x022A
 172 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)    (((reg_val) & 0x0f00) >> 8)
 173 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val)    ((reg_val) & 0x000f)
 174
 175 #define PTP_TX_EGRESS_SEC_HI                    0x0296
 176 #define PTP_TX_EGRESS_SEC_LO                    0x0297
 177 #define PTP_TX_EGRESS_NS_HI                     0x0294
 178 #define PTP_TX_EGRESS_NS_LO                     0x0295
 179 #define PTP_TX_MSG_HEADER2                      0x0299
 180
 181 #define PTP_RX_INGRESS_SEC_HI                   0x0256
 182 #define PTP_RX_INGRESS_SEC_LO                   0x0257
 183 #define PTP_RX_INGRESS_NS_HI                    0x0254
 184 #define PTP_RX_INGRESS_NS_LO                    0x0255
 185 #define PTP_RX_MSG_HEADER2                      0x0259
 186
 187 #define PTP_TSU_INT_EN                          0x0200
 188 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_      BIT(3)
 189 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_            BIT(2)
 190 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_      BIT(1)
 191 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_            BIT(0)
 192
 193 #define PTP_TSU_INT_STS                         0x0201
 194 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_    BIT(3)
 195 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_           BIT(2)
 196 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_    BIT(1)
 197 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_           BIT(0)
 198
 199 /* PHY Control 1 */
 200 #define MII_KSZPHY_CTRL_1                       0x1e
 201 #define KSZ8081_CTRL1_MDIX_STAT                 BIT(4)
 202
 203 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
 204 #define MII_KSZPHY_CTRL_2                       0x1f
 205 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
 206 /* bitmap of PHY register to set interrupt mode */
 207 #define KSZ8081_CTRL2_HP_MDIX                   BIT(15)
 208 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT          BIT(14)
 209 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX         BIT(13)
 210 #define KSZ8081_CTRL2_FORCE_LINK                BIT(11)
 211 #define KSZ8081_CTRL2_POWER_SAVING              BIT(10)
 212 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
 213 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
 214
 215 /* Write/read to/from extended registers */
 216 #define MII_KSZPHY_EXTREG                       0x0b
 217 #define KSZPHY_EXTREG_WRITE                     0x8000
 218
 219 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
 220 #define MII_KSZPHY_EXTREG_READ                  0x0d
 221
 222 /* Extended registers */
 223 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
 224 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
 225 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
 226
 227 #define PS_TO_REG                               200
 228 #define FIFO_SIZE                               8
 229
 230 struct kszphy_hw_stat {
 231         const char *string;
 232         u8 reg;
 233         u8 bits;
 234 };
 235
 236 static struct kszphy_hw_stat kszphy_hw_stats[] = {
 237         { "phy_receive_errors", 21, 16},
 238         { "phy_idle_errors", 10, 8 },
 239 };
 240
 241 struct kszphy_type {
 242         u32 led_mode_reg;
 243         u16 interrupt_level_mask;
 244         bool has_broadcast_disable;
 245         bool has_nand_tree_disable;
 246         bool has_rmii_ref_clk_sel;
 247 };
 248
 249 /* Shared structure between the PHYs of the same package. */
 250 struct lan8814_shared_priv {
 251         struct phy_device *phydev;
 252         struct ptp_clock *ptp_clock;
 253         struct ptp_clock_info ptp_clock_info;
 254
 255         /* Reference counter to how many ports in the package are enabling the
 256          * timestamping
 257          */
 258         u8 ref;
 259
 260         /* Lock for ptp_clock and ref */
 261         struct mutex shared_lock;
 262 };
 263
 264 struct lan8814_ptp_rx_ts {
 265         struct list_head list;
 266         u32 seconds;
 267         u32 nsec;
 268         u16 seq_id;
 269 };
 270
 271 struct kszphy_latencies {
 272         u16 rx_10;
 273         u16 tx_10;
 274         u16 rx_100;
 275         u16 tx_100;
 276         u16 rx_1000;
 277         u16 tx_1000;
 278 };
 279
 280 struct kszphy_ptp_priv {
 281         struct mii_timestamper mii_ts;
 282         struct phy_device *phydev;
 283
 284         struct sk_buff_head tx_queue;
 285         struct sk_buff_head rx_queue;
 286
 287         struct list_head rx_ts_list;
 288         /* Lock for Rx ts fifo */
 289         spinlock_t rx_ts_lock;
 290
 291         int hwts_tx_type;
 292         enum hwtstamp_rx_filters rx_filter;
 293         int layer;
 294         int version;
 295 };
 296
 297 struct kszphy_priv {
 298         struct kszphy_ptp_priv ptp_priv;
 299         struct kszphy_latencies latencies;
 300         const struct kszphy_type *type;
 301         int led_mode;
 302         bool rmii_ref_clk_sel;
 303         bool rmii_ref_clk_sel_val;
 304         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 305 };
 306
 307 static struct kszphy_latencies lan8814_latencies = {
 308         .rx_10          = 0x22AA,
 309         .tx_10          = 0x2E4A,
 310         .rx_100         = 0x092A,
 311         .tx_100         = 0x02C1,
 312         .rx_1000        = 0x01AD,
 313         .tx_1000        = 0x00C9,
 314 };
 315 static const struct kszphy_type ksz8021_type = {
 316         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 317         .has_broadcast_disable  = true,
 318         .has_nand_tree_disable  = true,
 319         .has_rmii_ref_clk_sel   = true,
 320 };
 321
 322 static const struct kszphy_type ksz8041_type = {
 323         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 324 };
 325
 326 static const struct kszphy_type ksz8051_type = {
 327         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 328         .has_nand_tree_disable  = true,
 329 };
 330
 331 static const struct kszphy_type ksz8081_type = {
 332         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 333         .has_broadcast_disable  = true,
 334         .has_nand_tree_disable  = true,
 335         .has_rmii_ref_clk_sel   = true,
 336 };
 337
 338 static const struct kszphy_type ks8737_type = {
 339         .interrupt_level_mask   = BIT(14),
 340 };
 341
 342 static const struct kszphy_type ksz9021_type = {
 343         .interrupt_level_mask   = BIT(14),
 344 };
 345
 346 static int kszphy_extended_write(struct phy_device *phydev,
 347                                 u32 regnum, u16 val)
 348 {
 349         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 350         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 351 }
 352
 353 static int kszphy_extended_read(struct phy_device *phydev,
 354                                 u32 regnum)
 355 {
 356         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 357         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 358 }
 359
 360 static int kszphy_ack_interrupt(struct phy_device *phydev)
 361 {
 362         /* bit[7..0] int status, which is a read and clear register. */
 363         int rc;
 364
 365         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 366
 367         return (rc < 0) ? rc : 0;
 368 }
 369
 370 static int kszphy_config_intr(struct phy_device *phydev)
 371 {
 372         const struct kszphy_type *type = phydev->drv->driver_data;
 373         int temp, err;
 374         u16 mask;
 375
 376         if (type && type->interrupt_level_mask)
 377                 mask = type->interrupt_level_mask;
 378         else
 379                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 380
 381         /* set the interrupt pin active low */
 382         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 383         if (temp < 0)
 384                 return temp;
 385         temp &= ~mask;
 386         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 387
 388         /* enable / disable interrupts */
 389         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 390                 err = kszphy_ack_interrupt(phydev);
 391                 if (err)
 392                         return err;
 393
 394                 temp = KSZPHY_INTCS_ALL;
 395                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 396         } else {
 397                 temp = 0;
 398                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 399                 if (err)
 400                         return err;
 401
 402                 err = kszphy_ack_interrupt(phydev);
 403         }
 404
 405         return err;
 406 }
 407
 408 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
 409 {
 410         int irq_status;
 411
 412         irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
 413         if (irq_status < 0) {
 414                 phy_error(phydev);
 415                 return IRQ_NONE;
 416         }
 417
 418         if (!(irq_status & KSZPHY_INTCS_STATUS))
 419                 return IRQ_NONE;
 420
 421         phy_trigger_machine(phydev);
 422
 423         return IRQ_HANDLED;
 424 }
 425
 426 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 427 {
 428         int ctrl;
 429
 430         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 431         if (ctrl < 0)
 432                 return ctrl;
 433
 434         if (val)
 435                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 436         else
 437                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 438
 439         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 440 }
 441
 442 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 443 {
 444         int rc, temp, shift;
 445
 446         switch (reg) {
 447         case MII_KSZPHY_CTRL_1:
 448                 shift = 14;
 449                 break;
 450         case MII_KSZPHY_CTRL_2:
 451                 shift = 4;
 452                 break;
 453         default:
 454                 return -EINVAL;
 455         }
 456
 457         temp = phy_read(phydev, reg);
 458         if (temp < 0) {
 459                 rc = temp;
 460                 goto out;
 461         }
 462
 463         temp &= ~(3 << shift);
 464         temp |= val << shift;
 465         rc = phy_write(phydev, reg, temp);
 466 out:
 467         if (rc < 0)
 468                 phydev_err(phydev, "failed to set led mode\n");
 469
 470         return rc;
 471 }
 472
 473 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 474  * unique (non-broadcast) address on a shared bus.
 475  */
 476 static int kszphy_broadcast_disable(struct phy_device *phydev)
 477 {
 478         int ret;
 479
 480         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 481         if (ret < 0)
 482                 goto out;
 483
 484         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 485 out:
 486         if (ret)
 487                 phydev_err(phydev, "failed to disable broadcast address\n");
 488
 489         return ret;
 490 }
 491
 492 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 493 {
 494         int ret;
 495
 496         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 497         if (ret < 0)
 498                 goto out;
 499
 500         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 501                 return 0;
 502
 503         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 504                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 505 out:
 506         if (ret)
 507                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 508
 509         return ret;
 510 }
 511
 512 /* Some config bits need to be set again on resume, handle them here. */
 513 static int kszphy_config_reset(struct phy_device *phydev)
 514 {
 515         struct kszphy_priv *priv = phydev->priv;
 516         int ret;
 517
 518         if (priv->rmii_ref_clk_sel) {
 519                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 520                 if (ret) {
 521                         phydev_err(phydev,
 522                                    "failed to set rmii reference clock\n");
 523                         return ret;
 524                 }
 525         }
 526
 527         if (priv->led_mode >= 0)
 528                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 529
 530         return 0;
 531 }
 532
 533 static int kszphy_config_init(struct phy_device *phydev)
 534 {
 535         struct kszphy_priv *priv = phydev->priv;
 536         const struct kszphy_type *type;
 537
 538         if (!priv)
 539                 return 0;
 540
 541         type = priv->type;
 542
 543         if (type->has_broadcast_disable)
 544                 kszphy_broadcast_disable(phydev);
 545
 546         if (type->has_nand_tree_disable)
 547                 kszphy_nand_tree_disable(phydev);
 548
 549         return kszphy_config_reset(phydev);
 550 }
 551
 552 static int ksz8041_fiber_mode(struct phy_device *phydev)
 553 {
 554         struct device_node *of_node = phydev->mdio.dev.of_node;
 555
 556         return of_property_read_bool(of_node, "micrel,fiber-mode");
 557 }
 558
 559 static int ksz8041_config_init(struct phy_device *phydev)
 560 {
 561         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 562
 563         /* Limit supported and advertised modes in fiber mode */
 564         if (ksz8041_fiber_mode(phydev)) {
 565                 phydev->dev_flags |= MICREL_PHY_FXEN;
 566                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 567                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 568
 569                 linkmode_and(phydev->supported, phydev->supported, mask);
 570                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 571                                  phydev->supported);
 572                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 573                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 574                                  phydev->advertising);
 575                 phydev->autoneg = AUTONEG_DISABLE;
 576         }
 577
 578         return kszphy_config_init(phydev);
 579 }
 580
 581 static int ksz8041_config_aneg(struct phy_device *phydev)
 582 {
 583         /* Skip auto-negotiation in fiber mode */
 584         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 585                 phydev->speed = SPEED_100;
 586                 return 0;
 587         }
 588
 589         return genphy_config_aneg(phydev);
 590 }
 591
 592 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
 593                                             const bool ksz_8051)
 594 {
 595         int ret;
 596
 597         if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
 598                 return 0;
 599
 600         ret = phy_read(phydev, MII_BMSR);
 601         if (ret < 0)
 602                 return ret;
 603
 604         /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
 605          * exact PHY ID. However, they can be told apart by the extended
 606          * capability registers presence. The KSZ8051 PHY has them while
 607          * the switch does not.
 608          */
 609         ret &= BMSR_ERCAP;
 610         if (ksz_8051)
 611                 return ret;
 612         else
 613                 return !ret;
 614 }
 615
 616 static int ksz8051_match_phy_device(struct phy_device *phydev)
 617 {
 618         return ksz8051_ksz8795_match_phy_device(phydev, true);
 619 }
 620
 621 static int ksz8081_config_init(struct phy_device *phydev)
 622 {
 623         /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
 624          * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
 625          * pull-down is missing, the factory test mode should be cleared by
 626          * manually writing a 0.
 627          */
 628         phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
 629
 630         return kszphy_config_init(phydev);
 631 }
 632
 633 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
 634 {
 635         u16 val;
 636
 637         switch (ctrl) {
 638         case ETH_TP_MDI:
 639                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
 640                 break;
 641         case ETH_TP_MDI_X:
 642                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
 643                         KSZ8081_CTRL2_MDI_MDI_X_SELECT;
 644                 break;
 645         case ETH_TP_MDI_AUTO:
 646                 val = 0;
 647                 break;
 648         default:
 649                 return 0;
 650         }
 651
 652         return phy_modify(phydev, MII_KSZPHY_CTRL_2,
 653                           KSZ8081_CTRL2_HP_MDIX |
 654                           KSZ8081_CTRL2_MDI_MDI_X_SELECT |
 655                           KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
 656                           KSZ8081_CTRL2_HP_MDIX | val);
 657 }
 658
 659 static int ksz8081_config_aneg(struct phy_device *phydev)
 660 {
 661         int ret;
 662
 663         ret = genphy_config_aneg(phydev);
 664         if (ret)
 665                 return ret;
 666
 667         /* The MDI-X configuration is automatically changed by the PHY after
 668          * switching from autoneg off to on. So, take MDI-X configuration under
 669          * own control and set it after autoneg configuration was done.
 670          */
 671         return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
 672 }
 673
 674 static int ksz8081_mdix_update(struct phy_device *phydev)
 675 {
 676         int ret;
 677
 678         ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
 679         if (ret < 0)
 680                 return ret;
 681
 682         if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
 683                 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
 684                         phydev->mdix_ctrl = ETH_TP_MDI_X;
 685                 else
 686                         phydev->mdix_ctrl = ETH_TP_MDI;
 687         } else {
 688                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 689         }
 690
 691         ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
 692         if (ret < 0)
 693                 return ret;
 694
 695         if (ret & KSZ8081_CTRL1_MDIX_STAT)
 696                 phydev->mdix = ETH_TP_MDI;
 697         else
 698                 phydev->mdix = ETH_TP_MDI_X;
 699
 700         return 0;
 701 }
 702
 703 static int ksz8081_read_status(struct phy_device *phydev)
 704 {
 705         int ret;
 706
 707         ret = ksz8081_mdix_update(phydev);
 708         if (ret < 0)
 709                 return ret;
 710
 711         return genphy_read_status(phydev);
 712 }
 713
 714 static int ksz8061_config_init(struct phy_device *phydev)
 715 {
 716         int ret;
 717
 718         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 719         if (ret)
 720                 return ret;
 721
 722         return kszphy_config_init(phydev);
 723 }
 724
 725 static int ksz8795_match_phy_device(struct phy_device *phydev)
 726 {
 727         return ksz8051_ksz8795_match_phy_device(phydev, false);
 728 }
 729
 730 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 731                                        const struct device_node *of_node,
 732                                        u16 reg,
 733                                        const char *field1, const char *field2,
 734                                        const char *field3, const char *field4)
 735 {
 736         int val1 = -1;
 737         int val2 = -2;
 738         int val3 = -3;
 739         int val4 = -4;
 740         int newval;
 741         int matches = 0;
 742
 743         if (!of_property_read_u32(of_node, field1, &val1))
 744                 matches++;
 745
 746         if (!of_property_read_u32(of_node, field2, &val2))
 747                 matches++;
 748
 749         if (!of_property_read_u32(of_node, field3, &val3))
 750                 matches++;
 751
 752         if (!of_property_read_u32(of_node, field4, &val4))
 753                 matches++;
 754
 755         if (!matches)
 756                 return 0;
 757
 758         if (matches < 4)
 759                 newval = kszphy_extended_read(phydev, reg);
 760         else
 761                 newval = 0;
 762
 763         if (val1 != -1)
 764                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 765
 766         if (val2 != -2)
 767                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 768
 769         if (val3 != -3)
 770                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 771
 772         if (val4 != -4)
 773                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 774
 775         return kszphy_extended_write(phydev, reg, newval);
 776 }
 777
 778 static int ksz9021_config_init(struct phy_device *phydev)
 779 {
 780         const struct device_node *of_node;
 781         const struct device *dev_walker;
 782
 783         /* The Micrel driver has a deprecated option to place phy OF
 784          * properties in the MAC node. Walk up the tree of devices to
 785          * find a device with an OF node.
 786          */
 787         dev_walker = &phydev->mdio.dev;
 788         do {
 789                 of_node = dev_walker->of_node;
 790                 dev_walker = dev_walker->parent;
 791
 792         } while (!of_node && dev_walker);
 793
 794         if (of_node) {
 795                 ksz9021_load_values_from_of(phydev, of_node,
 796                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 797                                     "txen-skew-ps", "txc-skew-ps",
 798                                     "rxdv-skew-ps", "rxc-skew-ps");
 799                 ksz9021_load_values_from_of(phydev, of_node,
 800                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 801                                     "rxd0-skew-ps", "rxd1-skew-ps",
 802                                     "rxd2-skew-ps", "rxd3-skew-ps");
 803                 ksz9021_load_values_from_of(phydev, of_node,
 804                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 805                                     "txd0-skew-ps", "txd1-skew-ps",
 806                                     "txd2-skew-ps", "txd3-skew-ps");
 807         }
 808         return 0;
 809 }
 810
 811 #define KSZ9031_PS_TO_REG               60
 812
 813 /* Extended registers */
 814 /* MMD Address 0x0 */
 815 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 816 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 817
 818 /* MMD Address 0x2 */
 819 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 820 #define MII_KSZ9031RN_RX_CTL_M          GENMASK(7, 4)
 821 #define MII_KSZ9031RN_TX_CTL_M          GENMASK(3, 0)
 822
 823 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 824 #define MII_KSZ9031RN_RXD3              GENMASK(15, 12)
 825 #define MII_KSZ9031RN_RXD2              GENMASK(11, 8)
 826 #define MII_KSZ9031RN_RXD1              GENMASK(7, 4)
 827 #define MII_KSZ9031RN_RXD0              GENMASK(3, 0)
 828
 829 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 830 #define MII_KSZ9031RN_TXD3              GENMASK(15, 12)
 831 #define MII_KSZ9031RN_TXD2              GENMASK(11, 8)
 832 #define MII_KSZ9031RN_TXD1              GENMASK(7, 4)
 833 #define MII_KSZ9031RN_TXD0              GENMASK(3, 0)
 834
 835 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 836 #define MII_KSZ9031RN_GTX_CLK           GENMASK(9, 5)
 837 #define MII_KSZ9031RN_RX_CLK            GENMASK(4, 0)
 838
 839 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
 840  * provide different RGMII options we need to configure delay offset
 841  * for each pad relative to build in delay.
 842  */
 843 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
 844  * 1.80ns
 845  */
 846 #define RX_ID                           0x7
 847 #define RX_CLK_ID                       0x19
 848
 849 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
 850  * internal 1.2ns delay.
 851  */
 852 #define RX_ND                           0xc
 853 #define RX_CLK_ND                       0x0
 854
 855 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
 856 #define TX_ID                           0x0
 857 #define TX_CLK_ID                       0x1f
 858
 859 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
 860  * dealy
 861  */
 862 #define TX_ND                           0x7
 863 #define TX_CLK_ND                       0xf
 864
 865 /* MMD Address 0x1C */
 866 #define MII_KSZ9031RN_EDPD              0x23
 867 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 868
 869 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 870                                        const struct device_node *of_node,
 871                                        u16 reg, size_t field_sz,
 872                                        const char *field[], u8 numfields,
 873                                        bool *update)
 874 {
 875         int val[4] = {-1, -2, -3, -4};
 876         int matches = 0;
 877         u16 mask;
 878         u16 maxval;
 879         u16 newval;
 880         int i;
 881
 882         for (i = 0; i < numfields; i++)
 883                 if (!of_property_read_u32(of_node, field[i], val + i))
 884                         matches++;
 885
 886         if (!matches)
 887                 return 0;
 888
 889         *update |= true;
 890
 891         if (matches < numfields)
 892                 newval = phy_read_mmd(phydev, 2, reg);
 893         else
 894                 newval = 0;
 895
 896         maxval = (field_sz == 4) ? 0xf : 0x1f;
 897         for (i = 0; i < numfields; i++)
 898                 if (val[i] != -(i + 1)) {
 899                         mask = 0xffff;
 900                         mask ^= maxval << (field_sz * i);
 901                         newval = (newval & mask) |
 902                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 903                                         << (field_sz * i));
 904                 }
 905
 906         return phy_write_mmd(phydev, 2, reg, newval);
 907 }
 908
 909 /* Center KSZ9031RNX FLP timing at 16ms. */
 910 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 911 {
 912         int result;
 913
 914         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
 915                                0x0006);
 916         if (result)
 917                 return result;
 918
 919         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
 920                                0x1A80);
 921         if (result)
 922                 return result;
 923
 924         return genphy_restart_aneg(phydev);
 925 }
 926
 927 /* Enable energy-detect power-down mode */
 928 static int ksz9031_enable_edpd(struct phy_device *phydev)
 929 {
 930         int reg;
 931
 932         reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
 933         if (reg < 0)
 934                 return reg;
 935         return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
 936                              reg | MII_KSZ9031RN_EDPD_ENABLE);
 937 }
 938
 939 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
 940 {
 941         u16 rx, tx, rx_clk, tx_clk;
 942         int ret;
 943
 944         switch (phydev->interface) {
 945         case PHY_INTERFACE_MODE_RGMII:
 946                 tx = TX_ND;
 947                 tx_clk = TX_CLK_ND;
 948                 rx = RX_ND;
 949                 rx_clk = RX_CLK_ND;
 950                 break;
 951         case PHY_INTERFACE_MODE_RGMII_ID:
 952                 tx = TX_ID;
 953                 tx_clk = TX_CLK_ID;
 954                 rx = RX_ID;
 955                 rx_clk = RX_CLK_ID;
 956                 break;
 957         case PHY_INTERFACE_MODE_RGMII_RXID:
 958                 tx = TX_ND;
 959                 tx_clk = TX_CLK_ND;
 960                 rx = RX_ID;
 961                 rx_clk = RX_CLK_ID;
 962                 break;
 963         case PHY_INTERFACE_MODE_RGMII_TXID:
 964                 tx = TX_ID;
 965                 tx_clk = TX_CLK_ID;
 966                 rx = RX_ND;
 967                 rx_clk = RX_CLK_ND;
 968                 break;
 969         default:
 970                 return 0;
 971         }
 972
 973         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
 974                             FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
 975                             FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
 976         if (ret < 0)
 977                 return ret;
 978
 979         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
 980                             FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
 981                             FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
 982                             FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
 983                             FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
 984         if (ret < 0)
 985                 return ret;
 986
 987         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
 988                             FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
 989                             FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
 990                             FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
 991                             FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
 992         if (ret < 0)
 993                 return ret;
 994
 995         return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
 996                              FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
 997                              FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
 998 }
 999
1000 static int ksz9031_config_init(struct phy_device *phydev)
1001 {
1002         const struct device_node *of_node;
1003         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1004         static const char *rx_data_skews[4] = {
1005                 "rxd0-skew-ps", "rxd1-skew-ps",
1006                 "rxd2-skew-ps", "rxd3-skew-ps"
1007         };
1008         static const char *tx_data_skews[4] = {
1009                 "txd0-skew-ps", "txd1-skew-ps",
1010                 "txd2-skew-ps", "txd3-skew-ps"
1011         };
1012         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1013         const struct device *dev_walker;
1014         int result;
1015
1016         result = ksz9031_enable_edpd(phydev);
1017         if (result < 0)
1018                 return result;
1019
1020         /* The Micrel driver has a deprecated option to place phy OF
1021          * properties in the MAC node. Walk up the tree of devices to
1022          * find a device with an OF node.
1023          */
1024         dev_walker = &phydev->mdio.dev;
1025         do {
1026                 of_node = dev_walker->of_node;
1027                 dev_walker = dev_walker->parent;
1028         } while (!of_node && dev_walker);
1029
1030         if (of_node) {
1031                 bool update = false;
1032
1033                 if (phy_interface_is_rgmii(phydev)) {
1034                         result = ksz9031_config_rgmii_delay(phydev);
1035                         if (result < 0)
1036                                 return result;
1037                 }
1038
1039                 ksz9031_of_load_skew_values(phydev, of_node,
1040                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1041                                 clk_skews, 2, &update);
1042
1043                 ksz9031_of_load_skew_values(phydev, of_node,
1044                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1045                                 control_skews, 2, &update);
1046
1047                 ksz9031_of_load_skew_values(phydev, of_node,
1048                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1049                                 rx_data_skews, 4, &update);
1050
1051                 ksz9031_of_load_skew_values(phydev, of_node,
1052                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1053                                 tx_data_skews, 4, &update);
1054
1055                 if (update && !phy_interface_is_rgmii(phydev))
1056                         phydev_warn(phydev,
1057                                     "*-skew-ps values should be used only with RGMII PHY modes\n");
1058
1059                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1060                  * When the device links in the 1000BASE-T slave mode only,
1061                  * the optional 125MHz reference output clock (CLK125_NDO)
1062                  * has wide duty cycle variation.
1063                  *
1064                  * The optional CLK125_NDO clock does not meet the RGMII
1065                  * 45/55 percent (min/max) duty cycle requirement and therefore
1066                  * cannot be used directly by the MAC side for clocking
1067                  * applications that have setup/hold time requirements on
1068                  * rising and falling clock edges.
1069                  *
1070                  * Workaround:
1071                  * Force the phy to be the master to receive a stable clock
1072                  * which meets the duty cycle requirement.
1073                  */
1074                 if (of_property_read_bool(of_node, "micrel,force-master")) {
1075                         result = phy_read(phydev, MII_CTRL1000);
1076                         if (result < 0)
1077                                 goto err_force_master;
1078
1079                         /* enable master mode, config & prefer master */
1080                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1081                         result = phy_write(phydev, MII_CTRL1000, result);
1082                         if (result < 0)
1083                                 goto err_force_master;
1084                 }
1085         }
1086
1087         return ksz9031_center_flp_timing(phydev);
1088
1089 err_force_master:
1090         phydev_err(phydev, "failed to force the phy to master mode\n");
1091         return result;
1092 }
1093
1094 #define KSZ9131_SKEW_5BIT_MAX   2400
1095 #define KSZ9131_SKEW_4BIT_MAX   800
1096 #define KSZ9131_OFFSET          700
1097 #define KSZ9131_STEP            100
1098
1099 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1100                                        struct device_node *of_node,
1101                                        u16 reg, size_t field_sz,
1102                                        char *field[], u8 numfields)
1103 {
1104         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1105                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1106         int skewval, skewmax = 0;
1107         int matches = 0;
1108         u16 maxval;
1109         u16 newval;
1110         u16 mask;
1111         int i;
1112
1113         /* psec properties in dts should mean x pico seconds */
1114         if (field_sz == 5)
1115                 skewmax = KSZ9131_SKEW_5BIT_MAX;
1116         else
1117                 skewmax = KSZ9131_SKEW_4BIT_MAX;
1118
1119         for (i = 0; i < numfields; i++)
1120                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1121                         if (skewval < -KSZ9131_OFFSET)
1122                                 skewval = -KSZ9131_OFFSET;
1123                         else if (skewval > skewmax)
1124                                 skewval = skewmax;
1125
1126                         val[i] = skewval + KSZ9131_OFFSET;
1127                         matches++;
1128                 }
1129
1130         if (!matches)
1131                 return 0;
1132
1133         if (matches < numfields)
1134                 newval = phy_read_mmd(phydev, 2, reg);
1135         else
1136                 newval = 0;
1137
1138         maxval = (field_sz == 4) ? 0xf : 0x1f;
1139         for (i = 0; i < numfields; i++)
1140                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1141                         mask = 0xffff;
1142                         mask ^= maxval << (field_sz * i);
1143                         newval = (newval & mask) |
1144                                 (((val[i] / KSZ9131_STEP) & maxval)
1145                                         << (field_sz * i));
1146                 }
1147
1148         return phy_write_mmd(phydev, 2, reg, newval);
1149 }
1150
1151 #define KSZ9131RN_MMD_COMMON_CTRL_REG   2
1152 #define KSZ9131RN_RXC_DLL_CTRL          76
1153 #define KSZ9131RN_TXC_DLL_CTRL          77
1154 #define KSZ9131RN_DLL_CTRL_BYPASS       BIT_MASK(12)
1155 #define KSZ9131RN_DLL_ENABLE_DELAY      0
1156 #define KSZ9131RN_DLL_DISABLE_DELAY     BIT(12)
1157
1158 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1159 {
1160         u16 rxcdll_val, txcdll_val;
1161         int ret;
1162
1163         switch (phydev->interface) {
1164         case PHY_INTERFACE_MODE_RGMII:
1165                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1166                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1167                 break;
1168         case PHY_INTERFACE_MODE_RGMII_ID:
1169                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1170                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1171                 break;
1172         case PHY_INTERFACE_MODE_RGMII_RXID:
1173                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1174                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1175                 break;
1176         case PHY_INTERFACE_MODE_RGMII_TXID:
1177                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1178                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1179                 break;
1180         default:
1181                 return 0;
1182         }
1183
1184         ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1185                              KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1186                              rxcdll_val);
1187         if (ret < 0)
1188                 return ret;
1189
1190         return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1191                               KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1192                               txcdll_val);
1193 }
1194
1195 /* Silicon Errata DS80000693B
1196  *
1197  * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1198  * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1199  * according to the datasheet (off if there is no link).
1200  */
1201 static int ksz9131_led_errata(struct phy_device *phydev)
1202 {
1203         int reg;
1204
1205         reg = phy_read_mmd(phydev, 2, 0);
1206         if (reg < 0)
1207                 return reg;
1208
1209         if (!(reg & BIT(4)))
1210                 return 0;
1211
1212         return phy_set_bits(phydev, 0x1e, BIT(9));
1213 }
1214
1215 static int ksz9131_config_init(struct phy_device *phydev)
1216 {
1217         struct device_node *of_node;
1218         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1219         char *rx_data_skews[4] = {
1220                 "rxd0-skew-psec", "rxd1-skew-psec",
1221                 "rxd2-skew-psec", "rxd3-skew-psec"
1222         };
1223         char *tx_data_skews[4] = {
1224                 "txd0-skew-psec", "txd1-skew-psec",
1225                 "txd2-skew-psec", "txd3-skew-psec"
1226         };
1227         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1228         const struct device *dev_walker;
1229         int ret;
1230
1231         dev_walker = &phydev->mdio.dev;
1232         do {
1233                 of_node = dev_walker->of_node;
1234                 dev_walker = dev_walker->parent;
1235         } while (!of_node && dev_walker);
1236
1237         if (!of_node)
1238                 return 0;
1239
1240         if (phy_interface_is_rgmii(phydev)) {
1241                 ret = ksz9131_config_rgmii_delay(phydev);
1242                 if (ret < 0)
1243                         return ret;
1244         }
1245
1246         ret = ksz9131_of_load_skew_values(phydev, of_node,
1247                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1248                                           clk_skews, 2);
1249         if (ret < 0)
1250                 return ret;
1251
1252         ret = ksz9131_of_load_skew_values(phydev, of_node,
1253                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1254                                           control_skews, 2);
1255         if (ret < 0)
1256                 return ret;
1257
1258         ret = ksz9131_of_load_skew_values(phydev, of_node,
1259                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1260                                           rx_data_skews, 4);
1261         if (ret < 0)
1262                 return ret;
1263
1264         ret = ksz9131_of_load_skew_values(phydev, of_node,
1265                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1266                                           tx_data_skews, 4);
1267         if (ret < 0)
1268                 return ret;
1269
1270         ret = ksz9131_led_errata(phydev);
1271         if (ret < 0)
1272                 return ret;
1273
1274         return 0;
1275 }
1276
1277 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
1278 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
1279 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
1280 static int ksz8873mll_read_status(struct phy_device *phydev)
1281 {
1282         int regval;
1283
1284         /* dummy read */
1285         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1286
1287         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1288
1289         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1290                 phydev->duplex = DUPLEX_HALF;
1291         else
1292                 phydev->duplex = DUPLEX_FULL;
1293
1294         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1295                 phydev->speed = SPEED_10;
1296         else
1297                 phydev->speed = SPEED_100;
1298
1299         phydev->link = 1;
1300         phydev->pause = phydev->asym_pause = 0;
1301
1302         return 0;
1303 }
1304
1305 static int ksz9031_get_features(struct phy_device *phydev)
1306 {
1307         int ret;
1308
1309         ret = genphy_read_abilities(phydev);
1310         if (ret < 0)
1311                 return ret;
1312
1313         /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1314          * Whenever the device's Asymmetric Pause capability is set to 1,
1315          * link-up may fail after a link-up to link-down transition.
1316          *
1317          * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1318          *
1319          * Workaround:
1320          * Do not enable the Asymmetric Pause capability bit.
1321          */
1322         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1323
1324         /* We force setting the Pause capability as the core will force the
1325          * Asymmetric Pause capability to 1 otherwise.
1326          */
1327         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1328
1329         return 0;
1330 }
1331
1332 static int ksz9031_read_status(struct phy_device *phydev)
1333 {
1334         int err;
1335         int regval;
1336
1337         err = genphy_read_status(phydev);
1338         if (err)
1339                 return err;
1340
1341         /* Make sure the PHY is not broken. Read idle error count,
1342          * and reset the PHY if it is maxed out.
1343          */
1344         regval = phy_read(phydev, MII_STAT1000);
1345         if ((regval & 0xFF) == 0xFF) {
1346                 phy_init_hw(phydev);
1347                 phydev->link = 0;
1348                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1349                         phydev->drv->config_intr(phydev);
1350                 return genphy_config_aneg(phydev);
1351         }
1352
1353         return 0;
1354 }
1355
1356 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1357 {
1358         return 0;
1359 }
1360
1361 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1362 {
1363         u16 val;
1364
1365         switch (ctrl) {
1366         case ETH_TP_MDI:
1367                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1368                 break;
1369         case ETH_TP_MDI_X:
1370                 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1371                  * counter intuitive, the "-X" in "1 = Force MDI" in the data
1372                  * sheet seems to be missing:
1373                  * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1374                  * 0 = Normal operation (transmit on TX+/TX- pins)
1375                  */
1376                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1377                 break;
1378         case ETH_TP_MDI_AUTO:
1379                 val = 0;
1380                 break;
1381         default:
1382                 return 0;
1383         }
1384
1385         return phy_modify(phydev, MII_BMCR,
1386                           KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1387                           KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1388                           KSZ886X_BMCR_HP_MDIX | val);
1389 }
1390
1391 static int ksz886x_config_aneg(struct phy_device *phydev)
1392 {
1393         int ret;
1394
1395         ret = genphy_config_aneg(phydev);
1396         if (ret)
1397                 return ret;
1398
1399         /* The MDI-X configuration is automatically changed by the PHY after
1400          * switching from autoneg off to on. So, take MDI-X configuration under
1401          * own control and set it after autoneg configuration was done.
1402          */
1403         return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1404 }
1405
1406 static int ksz886x_mdix_update(struct phy_device *phydev)
1407 {
1408         int ret;
1409
1410         ret = phy_read(phydev, MII_BMCR);
1411         if (ret < 0)
1412                 return ret;
1413
1414         if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1415                 if (ret & KSZ886X_BMCR_FORCE_MDI)
1416                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1417                 else
1418                         phydev->mdix_ctrl = ETH_TP_MDI;
1419         } else {
1420                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1421         }
1422
1423         ret = phy_read(phydev, MII_KSZPHY_CTRL);
1424         if (ret < 0)
1425                 return ret;
1426
1427         /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1428         if (ret & KSZ886X_CTRL_MDIX_STAT)
1429                 phydev->mdix = ETH_TP_MDI_X;
1430         else
1431                 phydev->mdix = ETH_TP_MDI;
1432
1433         return 0;
1434 }
1435
1436 static int ksz886x_read_status(struct phy_device *phydev)
1437 {
1438         int ret;
1439
1440         ret = ksz886x_mdix_update(phydev);
1441         if (ret < 0)
1442                 return ret;
1443
1444         return genphy_read_status(phydev);
1445 }
1446
1447 static int kszphy_get_sset_count(struct phy_device *phydev)
1448 {
1449         return ARRAY_SIZE(kszphy_hw_stats);
1450 }
1451
1452 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1453 {
1454         int i;
1455
1456         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1457                 strlcpy(data + i * ETH_GSTRING_LEN,
1458                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1459         }
1460 }
1461
1462 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1463 {
1464         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1465         struct kszphy_priv *priv = phydev->priv;
1466         int val;
1467         u64 ret;
1468
1469         val = phy_read(phydev, stat.reg);
1470         if (val < 0) {
1471                 ret = U64_MAX;
1472         } else {
1473                 val = val & ((1 << stat.bits) - 1);
1474                 priv->stats[i] += val;
1475                 ret = priv->stats[i];
1476         }
1477
1478         return ret;
1479 }
1480
1481 static void kszphy_get_stats(struct phy_device *phydev,
1482                              struct ethtool_stats *stats, u64 *data)
1483 {
1484         int i;
1485
1486         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1487                 data[i] = kszphy_get_stat(phydev, i);
1488 }
1489
1490 static int kszphy_suspend(struct phy_device *phydev)
1491 {
1492         /* Disable PHY Interrupts */
1493         if (phy_interrupt_is_valid(phydev)) {
1494                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1495                 if (phydev->drv->config_intr)
1496                         phydev->drv->config_intr(phydev);
1497         }
1498
1499         return genphy_suspend(phydev);
1500 }
1501
1502 static int kszphy_resume(struct phy_device *phydev)
1503 {
1504         int ret;
1505
1506         genphy_resume(phydev);
1507
1508         /* After switching from power-down to normal mode, an internal global
1509          * reset is automatically generated. Wait a minimum of 1 ms before
1510          * read/write access to the PHY registers.
1511          */
1512         usleep_range(1000, 2000);
1513
1514         ret = kszphy_config_reset(phydev);
1515         if (ret)
1516                 return ret;
1517
1518         /* Enable PHY Interrupts */
1519         if (phy_interrupt_is_valid(phydev)) {
1520                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1521                 if (phydev->drv->config_intr)
1522                         phydev->drv->config_intr(phydev);
1523         }
1524
1525         return 0;
1526 }
1527
1528 static int kszphy_probe(struct phy_device *phydev)
1529 {
1530         const struct kszphy_type *type = phydev->drv->driver_data;
1531         const struct device_node *np = phydev->mdio.dev.of_node;
1532         struct kszphy_priv *priv;
1533         struct clk *clk;
1534         int ret;
1535
1536         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1537         if (!priv)
1538                 return -ENOMEM;
1539
1540         phydev->priv = priv;
1541
1542         priv->type = type;
1543
1544         if (type->led_mode_reg) {
1545                 ret = of_property_read_u32(np, "micrel,led-mode",
1546                                 &priv->led_mode);
1547                 if (ret)
1548                         priv->led_mode = -1;
1549
1550                 if (priv->led_mode > 3) {
1551                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
1552                                    priv->led_mode);
1553                         priv->led_mode = -1;
1554                 }
1555         } else {
1556                 priv->led_mode = -1;
1557         }
1558
1559         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1560         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1561         if (!IS_ERR_OR_NULL(clk)) {
1562                 unsigned long rate = clk_get_rate(clk);
1563                 bool rmii_ref_clk_sel_25_mhz;
1564
1565                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1566                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1567                                 "micrel,rmii-reference-clock-select-25-mhz");
1568
1569                 if (rate > 24500000 && rate < 25500000) {
1570                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1571                 } else if (rate > 49500000 && rate < 50500000) {
1572                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1573                 } else {
1574                         phydev_err(phydev, "Clock rate out of range: %ld\n",
1575                                    rate);
1576                         return -EINVAL;
1577                 }
1578         }
1579
1580         if (ksz8041_fiber_mode(phydev))
1581                 phydev->port = PORT_FIBRE;
1582
1583         /* Support legacy board-file configuration */
1584         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1585                 priv->rmii_ref_clk_sel = true;
1586                 priv->rmii_ref_clk_sel_val = true;
1587         }
1588
1589         return 0;
1590 }
1591
1592 static int ksz886x_cable_test_start(struct phy_device *phydev)
1593 {
1594         if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1595                 return -EOPNOTSUPP;
1596
1597         /* If autoneg is enabled, we won't be able to test cross pair
1598          * short. In this case, the PHY will "detect" a link and
1599          * confuse the internal state machine - disable auto neg here.
1600          * If autoneg is disabled, we should set the speed to 10mbit.
1601          */
1602         return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1603 }
1604
1605 static int ksz886x_cable_test_result_trans(u16 status)
1606 {
1607         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1608         case KSZ8081_LMD_STAT_NORMAL:
1609                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1610         case KSZ8081_LMD_STAT_SHORT:
1611                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1612         case KSZ8081_LMD_STAT_OPEN:
1613                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1614         case KSZ8081_LMD_STAT_FAIL:
1615                 fallthrough;
1616         default:
1617                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1618         }
1619 }
1620
1621 static bool ksz886x_cable_test_failed(u16 status)
1622 {
1623         return FIELD_GET(KSZ8081_LMD_STAT_MASK, status) ==
1624                 KSZ8081_LMD_STAT_FAIL;
1625 }
1626
1627 static bool ksz886x_cable_test_fault_length_valid(u16 status)
1628 {
1629         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1630         case KSZ8081_LMD_STAT_OPEN:
1631                 fallthrough;
1632         case KSZ8081_LMD_STAT_SHORT:
1633                 return true;
1634         }
1635         return false;
1636 }
1637
1638 static int ksz886x_cable_test_fault_length(u16 status)
1639 {
1640         int dt;
1641
1642         /* According to the data sheet the distance to the fault is
1643          * DELTA_TIME * 0.4 meters.
1644          */
1645         dt = FIELD_GET(KSZ8081_LMD_DELTA_TIME_MASK, status);
1646
1647         return (dt * 400) / 10;
1648 }
1649
1650 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1651 {
1652         int val, ret;
1653
1654         ret = phy_read_poll_timeout(phydev, KSZ8081_LMD, val,
1655                                     !(val & KSZ8081_LMD_ENABLE_TEST),
1656                                     30000, 100000, true);
1657
1658         return ret < 0 ? ret : 0;
1659 }
1660
1661 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
1662 {
1663         static const int ethtool_pair[] = {
1664                 ETHTOOL_A_CABLE_PAIR_A,
1665                 ETHTOOL_A_CABLE_PAIR_B,
1666         };
1667         int ret, val, mdix;
1668
1669         /* There is no way to choice the pair, like we do one ksz9031.
1670          * We can workaround this limitation by using the MDI-X functionality.
1671          */
1672         if (pair == 0)
1673                 mdix = ETH_TP_MDI;
1674         else
1675                 mdix = ETH_TP_MDI_X;
1676
1677         switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
1678         case PHY_ID_KSZ8081:
1679                 ret = ksz8081_config_mdix(phydev, mdix);
1680                 break;
1681         case PHY_ID_KSZ886X:
1682                 ret = ksz886x_config_mdix(phydev, mdix);
1683                 break;
1684         default:
1685                 ret = -ENODEV;
1686         }
1687
1688         if (ret)
1689                 return ret;
1690
1691         /* Now we are ready to fire. This command will send a 100ns pulse
1692          * to the pair.
1693          */
1694         ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
1695         if (ret)
1696                 return ret;
1697
1698         ret = ksz886x_cable_test_wait_for_completion(phydev);
1699         if (ret)
1700                 return ret;
1701
1702         val = phy_read(phydev, KSZ8081_LMD);
1703         if (val < 0)
1704                 return val;
1705
1706         if (ksz886x_cable_test_failed(val))
1707                 return -EAGAIN;
1708
1709         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
1710                                       ksz886x_cable_test_result_trans(val));
1711         if (ret)
1712                 return ret;
1713
1714         if (!ksz886x_cable_test_fault_length_valid(val))
1715                 return 0;
1716
1717         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1718                                              ksz886x_cable_test_fault_length(val));
1719 }
1720
1721 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
1722                                          bool *finished)
1723 {
1724         unsigned long pair_mask = 0x3;
1725         int retries = 20;
1726         int pair, ret;
1727
1728         *finished = false;
1729
1730         /* Try harder if link partner is active */
1731         while (pair_mask && retries--) {
1732                 for_each_set_bit(pair, &pair_mask, 4) {
1733                         ret = ksz886x_cable_test_one_pair(phydev, pair);
1734                         if (ret == -EAGAIN)
1735                                 continue;
1736                         if (ret < 0)
1737                                 return ret;
1738                         clear_bit(pair, &pair_mask);
1739                 }
1740                 /* If link partner is in autonegotiation mode it will send 2ms
1741                  * of FLPs with at least 6ms of silence.
1742                  * Add 2ms sleep to have better chances to hit this silence.
1743                  */
1744                 if (pair_mask)
1745                         msleep(2);
1746         }
1747
1748         *finished = true;
1749
1750         return ret;
1751 }
1752
1753 #define LAN_EXT_PAGE_ACCESS_CONTROL                     0x16
1754 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA                0x17
1755 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC                0x4000
1756
1757 #define LAN8814_QSGMII_SOFT_RESET                       0x43
1758 #define LAN8814_QSGMII_SOFT_RESET_BIT                   BIT(0)
1759 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG                0x13
1760 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA       BIT(3)
1761 #define LAN8814_ALIGN_SWAP                              0x4a
1762 #define LAN8814_ALIGN_TX_A_B_SWAP                       0x1
1763 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1764
1765 #define LAN8804_ALIGN_SWAP                              0x4a
1766 #define LAN8804_ALIGN_TX_A_B_SWAP                       0x1
1767 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1768 #define LAN8814_CLOCK_MANAGEMENT                        0xd
1769 #define LAN8814_LINK_QUALITY                            0x8e
1770
1771 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
1772 {
1773         u32 data;
1774
1775         phy_lock_mdio_bus(phydev);
1776         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1777         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1778         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1779                     (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
1780         data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
1781         phy_unlock_mdio_bus(phydev);
1782
1783         return data;
1784 }
1785
1786 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
1787                                  u16 val)
1788 {
1789         phy_lock_mdio_bus(phydev);
1790         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1791         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1792         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1793                     page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
1794
1795         val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
1796         if (val != 0)
1797                 phydev_err(phydev, "Error: phy_write has returned error %d\n",
1798                            val);
1799         phy_unlock_mdio_bus(phydev);
1800         return val;
1801 }
1802
1803 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
1804 {
1805         u16 val = 0;
1806
1807         if (enable)
1808                 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
1809                       PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
1810                       PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
1811                       PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
1812
1813         return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
1814 }
1815
1816 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
1817                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
1818 {
1819         *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
1820         *seconds = (*seconds << 16) |
1821                    lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
1822
1823         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
1824         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
1825                         lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
1826
1827         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
1828 }
1829
1830 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
1831                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
1832 {
1833         *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
1834         *seconds = *seconds << 16 |
1835                    lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
1836
1837         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
1838         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
1839                         lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
1840
1841         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
1842 }
1843
1844 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
1845 {
1846         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
1847         struct phy_device *phydev = ptp_priv->phydev;
1848         struct lan8814_shared_priv *shared = phydev->shared->priv;
1849
1850         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1851                                 SOF_TIMESTAMPING_RX_HARDWARE |
1852                                 SOF_TIMESTAMPING_RAW_HARDWARE;
1853
1854         info->phc_index = ptp_clock_index(shared->ptp_clock);
1855
1856         info->tx_types =
1857                 (1 << HWTSTAMP_TX_OFF) |
1858                 (1 << HWTSTAMP_TX_ON) |
1859                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1860
1861         info->rx_filters =
1862                 (1 << HWTSTAMP_FILTER_NONE) |
1863                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1864                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1865                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1866                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1867
1868         return 0;
1869 }
1870
1871 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
1872 {
1873         int i;
1874
1875         for (i = 0; i < FIFO_SIZE; ++i)
1876                 lanphy_read_page_reg(phydev, 5,
1877                                      egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
1878
1879         /* Read to clear overflow status bit */
1880         lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
1881 }
1882
1883 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
1884 {
1885         struct kszphy_ptp_priv *ptp_priv =
1886                           container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
1887         struct phy_device *phydev = ptp_priv->phydev;
1888         struct lan8814_shared_priv *shared = phydev->shared->priv;
1889         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
1890         struct hwtstamp_config config;
1891         int txcfg = 0, rxcfg = 0;
1892         int pkt_ts_enable;
1893
1894         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1895                 return -EFAULT;
1896
1897         ptp_priv->hwts_tx_type = config.tx_type;
1898         ptp_priv->rx_filter = config.rx_filter;
1899
1900         switch (config.rx_filter) {
1901         case HWTSTAMP_FILTER_NONE:
1902                 ptp_priv->layer = 0;
1903                 ptp_priv->version = 0;
1904                 break;
1905         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1906         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1907         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1908                 ptp_priv->layer = PTP_CLASS_L4;
1909                 ptp_priv->version = PTP_CLASS_V2;
1910                 break;
1911         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1912         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1913         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1914                 ptp_priv->layer = PTP_CLASS_L2;
1915                 ptp_priv->version = PTP_CLASS_V2;
1916                 break;
1917         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1918         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1919         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1920                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1921                 ptp_priv->version = PTP_CLASS_V2;
1922                 break;
1923         default:
1924                 return -ERANGE;
1925         }
1926
1927         if (ptp_priv->layer & PTP_CLASS_L2) {
1928                 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
1929                 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
1930         } else if (ptp_priv->layer & PTP_CLASS_L4) {
1931                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
1932                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
1933         }
1934         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
1935         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
1936
1937         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
1938                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
1939         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
1940         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
1941
1942         if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
1943                 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
1944                                       PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
1945
1946         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
1947                 lan8814_config_ts_intr(ptp_priv->phydev, true);
1948         else
1949                 lan8814_config_ts_intr(ptp_priv->phydev, false);
1950
1951         mutex_lock(&shared->shared_lock);
1952         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
1953                 shared->ref++;
1954         else
1955                 shared->ref--;
1956
1957         if (shared->ref)
1958                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
1959                                       PTP_CMD_CTL_PTP_ENABLE_);
1960         else
1961                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
1962                                       PTP_CMD_CTL_PTP_DISABLE_);
1963         mutex_unlock(&shared->shared_lock);
1964
1965         /* In case of multiple starts and stops, these needs to be cleared */
1966         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
1967                 list_del(&rx_ts->list);
1968                 kfree(rx_ts);
1969         }
1970         skb_queue_purge(&ptp_priv->rx_queue);
1971         skb_queue_purge(&ptp_priv->tx_queue);
1972
1973         lan8814_flush_fifo(ptp_priv->phydev, false);
1974         lan8814_flush_fifo(ptp_priv->phydev, true);
1975
1976         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
1977 }
1978
1979 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
1980                              struct sk_buff *skb, int type)
1981 {
1982         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
1983
1984         switch (ptp_priv->hwts_tx_type) {
1985         case HWTSTAMP_TX_ONESTEP_SYNC:
1986                 if (ptp_msg_is_sync(skb, type)) {
1987                         kfree_skb(skb);
1988                         return;
1989                 }
1990                 fallthrough;
1991         case HWTSTAMP_TX_ON:
1992                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1993                 skb_queue_tail(&ptp_priv->tx_queue, skb);
1994                 break;
1995         case HWTSTAMP_TX_OFF:
1996         default:
1997                 kfree_skb(skb);
1998                 break;
1999         }
2000 }
2001
2002 static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2003 {
2004         struct ptp_header *ptp_header;
2005         u32 type;
2006
2007         skb_push(skb, ETH_HLEN);
2008         type = ptp_classify_raw(skb);
2009         ptp_header = ptp_parse_header(skb, type);
2010         skb_pull_inline(skb, ETH_HLEN);
2011
2012         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2013 }
2014
2015 static bool lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2016                                 struct sk_buff *skb)
2017 {
2018         struct skb_shared_hwtstamps *shhwtstamps;
2019         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2020         unsigned long flags;
2021         bool ret = false;
2022         u16 skb_sig;
2023
2024         lan8814_get_sig_rx(skb, &skb_sig);
2025
2026         /* Iterate over all RX timestamps and match it with the received skbs */
2027         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2028         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2029                 /* Check if we found the signature we were looking for. */
2030                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2031                         continue;
2032
2033                 shhwtstamps = skb_hwtstamps(skb);
2034                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2035                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2036                                                   rx_ts->nsec);
2037                 list_del(&rx_ts->list);
2038                 kfree(rx_ts);
2039
2040                 ret = true;
2041                 break;
2042         }
2043         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2044
2045         if (ret)
2046                 netif_rx(skb);
2047         return ret;
2048 }
2049
2050 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2051 {
2052         struct kszphy_ptp_priv *ptp_priv =
2053                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2054
2055         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2056             type == PTP_CLASS_NONE)
2057                 return false;
2058
2059         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2060                 return false;
2061
2062         /* If we failed to match then add it to the queue for when the timestamp
2063          * will come
2064          */
2065         if (!lan8814_match_rx_ts(ptp_priv, skb))
2066                 skb_queue_tail(&ptp_priv->rx_queue, skb);
2067
2068         return true;
2069 }
2070
2071 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2072                                   u32 seconds, u32 nano_seconds)
2073 {
2074         u32 sec_low, sec_high, nsec_low, nsec_high;
2075
2076         sec_low = seconds & 0xffff;
2077         sec_high = (seconds >> 16) & 0xffff;
2078         nsec_low = nano_seconds & 0xffff;
2079         nsec_high = (nano_seconds >> 16) & 0x3fff;
2080
2081         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2082         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2083         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2084         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2085
2086         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2087 }
2088
2089 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2090                                   u32 *seconds, u32 *nano_seconds)
2091 {
2092         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2093
2094         *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2095         *seconds = (*seconds << 16) |
2096                    lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2097
2098         *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2099         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2100                         lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2101 }
2102
2103 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2104                                    struct timespec64 *ts)
2105 {
2106         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2107                                                           ptp_clock_info);
2108         struct phy_device *phydev = shared->phydev;
2109         u32 nano_seconds;
2110         u32 seconds;
2111
2112         mutex_lock(&shared->shared_lock);
2113         lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2114         mutex_unlock(&shared->shared_lock);
2115         ts->tv_sec = seconds;
2116         ts->tv_nsec = nano_seconds;
2117
2118         return 0;
2119 }
2120
2121 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2122                                    const struct timespec64 *ts)
2123 {
2124         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2125                                                           ptp_clock_info);
2126         struct phy_device *phydev = shared->phydev;
2127
2128         mutex_lock(&shared->shared_lock);
2129         lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2130         mutex_unlock(&shared->shared_lock);
2131
2132         return 0;
2133 }
2134
2135 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2136                                    s64 time_step_ns)
2137 {
2138         u32 nano_seconds_step;
2139         u64 abs_time_step_ns;
2140         u32 unsigned_seconds;
2141         u32 nano_seconds;
2142         u32 remainder;
2143         s32 seconds;
2144
2145         if (time_step_ns >  15000000000LL) {
2146                 /* convert to clock set */
2147                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2148                 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2149                                                 &remainder);
2150                 nano_seconds += remainder;
2151                 if (nano_seconds >= 1000000000) {
2152                         unsigned_seconds++;
2153                         nano_seconds -= 1000000000;
2154                 }
2155                 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2156                 return;
2157         } else if (time_step_ns < -15000000000LL) {
2158                 /* convert to clock set */
2159                 time_step_ns = -time_step_ns;
2160
2161                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2162                 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2163                                                 &remainder);
2164                 nano_seconds_step = remainder;
2165                 if (nano_seconds < nano_seconds_step) {
2166                         unsigned_seconds--;
2167                         nano_seconds += 1000000000;
2168                 }
2169                 nano_seconds -= nano_seconds_step;
2170                 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2171                                       nano_seconds);
2172                 return;
2173         }
2174
2175         /* do clock step */
2176         if (time_step_ns >= 0) {
2177                 abs_time_step_ns = (u64)time_step_ns;
2178                 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2179                                            &remainder);
2180                 nano_seconds = remainder;
2181         } else {
2182                 abs_time_step_ns = (u64)(-time_step_ns);
2183                 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2184                             &remainder));
2185                 nano_seconds = remainder;
2186                 if (nano_seconds > 0) {
2187                         /* subtracting nano seconds is not allowed
2188                          * convert to subtracting from seconds,
2189                          * and adding to nanoseconds
2190                          */
2191                         seconds--;
2192                         nano_seconds = (1000000000 - nano_seconds);
2193                 }
2194         }
2195
2196         if (nano_seconds > 0) {
2197                 /* add 8 ns to cover the likely normal increment */
2198                 nano_seconds += 8;
2199         }
2200
2201         if (nano_seconds >= 1000000000) {
2202                 /* carry into seconds */
2203                 seconds++;
2204                 nano_seconds -= 1000000000;
2205         }
2206
2207         while (seconds) {
2208                 if (seconds > 0) {
2209                         u32 adjustment_value = (u32)seconds;
2210                         u16 adjustment_value_lo, adjustment_value_hi;
2211
2212                         if (adjustment_value > 0xF)
2213                                 adjustment_value = 0xF;
2214
2215                         adjustment_value_lo = adjustment_value & 0xffff;
2216                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2217
2218                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2219                                               adjustment_value_lo);
2220                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2221                                               PTP_LTC_STEP_ADJ_DIR_ |
2222                                               adjustment_value_hi);
2223                         seconds -= ((s32)adjustment_value);
2224                 } else {
2225                         u32 adjustment_value = (u32)(-seconds);
2226                         u16 adjustment_value_lo, adjustment_value_hi;
2227
2228                         if (adjustment_value > 0xF)
2229                                 adjustment_value = 0xF;
2230
2231                         adjustment_value_lo = adjustment_value & 0xffff;
2232                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2233
2234                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2235                                               adjustment_value_lo);
2236                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2237                                               adjustment_value_hi);
2238                         seconds += ((s32)adjustment_value);
2239                 }
2240                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2241                                       PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2242         }
2243         if (nano_seconds) {
2244                 u16 nano_seconds_lo;
2245                 u16 nano_seconds_hi;
2246
2247                 nano_seconds_lo = nano_seconds & 0xffff;
2248                 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2249
2250                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2251                                       nano_seconds_lo);
2252                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2253                                       PTP_LTC_STEP_ADJ_DIR_ |
2254                                       nano_seconds_hi);
2255                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2256                                       PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2257         }
2258 }
2259
2260 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2261 {
2262         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2263                                                           ptp_clock_info);
2264         struct phy_device *phydev = shared->phydev;
2265
2266         mutex_lock(&shared->shared_lock);
2267         lan8814_ptp_clock_step(phydev, delta);
2268         mutex_unlock(&shared->shared_lock);
2269
2270         return 0;
2271 }
2272
2273 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2274 {
2275         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2276                                                           ptp_clock_info);
2277         struct phy_device *phydev = shared->phydev;
2278         u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2279         bool positive = true;
2280         u32 kszphy_rate_adj;
2281
2282         if (scaled_ppm < 0) {
2283                 scaled_ppm = -scaled_ppm;
2284                 positive = false;
2285         }
2286
2287         kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2288         kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2289
2290         kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2291         kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2292
2293         if (positive)
2294                 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2295
2296         mutex_lock(&shared->shared_lock);
2297         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2298         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2299         mutex_unlock(&shared->shared_lock);
2300
2301         return 0;
2302 }
2303
2304 static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2305 {
2306         struct ptp_header *ptp_header;
2307         u32 type;
2308
2309         type = ptp_classify_raw(skb);
2310         ptp_header = ptp_parse_header(skb, type);
2311
2312         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2313 }
2314
2315 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2316 {
2317         struct phy_device *phydev = ptp_priv->phydev;
2318         struct skb_shared_hwtstamps shhwtstamps;
2319         struct sk_buff *skb, *skb_tmp;
2320         unsigned long flags;
2321         u32 seconds, nsec;
2322         bool ret = false;
2323         u16 skb_sig;
2324         u16 seq_id;
2325
2326         lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2327
2328         spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2329         skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2330                 lan8814_get_sig_tx(skb, &skb_sig);
2331
2332                 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2333                         continue;
2334
2335                 __skb_unlink(skb, &ptp_priv->tx_queue);
2336                 ret = true;
2337                 break;
2338         }
2339         spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2340
2341         if (ret) {
2342                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2343                 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2344                 skb_complete_tx_timestamp(skb, &shhwtstamps);
2345         }
2346 }
2347
2348 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2349 {
2350         struct phy_device *phydev = ptp_priv->phydev;
2351         u32 reg;
2352
2353         do {
2354                 lan8814_dequeue_tx_skb(ptp_priv);
2355
2356                 /* If other timestamps are available in the FIFO,
2357                  * process them.
2358                  */
2359                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2360         } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2361 }
2362
2363 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2364                               struct lan8814_ptp_rx_ts *rx_ts)
2365 {
2366         struct skb_shared_hwtstamps *shhwtstamps;
2367         struct sk_buff *skb, *skb_tmp;
2368         unsigned long flags;
2369         bool ret = false;
2370         u16 skb_sig;
2371
2372         spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2373         skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2374                 lan8814_get_sig_rx(skb, &skb_sig);
2375
2376                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2377                         continue;
2378
2379                 __skb_unlink(skb, &ptp_priv->rx_queue);
2380
2381                 ret = true;
2382                 break;
2383         }
2384         spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2385
2386         if (ret) {
2387                 shhwtstamps = skb_hwtstamps(skb);
2388                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2389                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2390                 netif_rx(skb);
2391         }
2392
2393         return ret;
2394 }
2395
2396 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2397 {
2398         struct phy_device *phydev = ptp_priv->phydev;
2399         struct lan8814_ptp_rx_ts *rx_ts;
2400         unsigned long flags;
2401         u32 reg;
2402
2403         do {
2404                 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2405                 if (!rx_ts)
2406                         return;
2407
2408                 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2409                                       &rx_ts->seq_id);
2410
2411                 /* If we failed to match the skb add it to the queue for when
2412                  * the frame will come
2413                  */
2414                 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2415                         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2416                         list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2417                         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2418                 } else {
2419                         kfree(rx_ts);
2420                 }
2421
2422                 /* If other timestamps are available in the FIFO,
2423                  * process them.
2424                  */
2425                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2426         } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2427 }
2428
2429 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev)
2430 {
2431         struct kszphy_priv *priv = phydev->priv;
2432         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2433         u16 status;
2434
2435         status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2436         if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2437                 lan8814_get_tx_ts(ptp_priv);
2438
2439         if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2440                 lan8814_get_rx_ts(ptp_priv);
2441
2442         if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2443                 lan8814_flush_fifo(phydev, true);
2444                 skb_queue_purge(&ptp_priv->tx_queue);
2445         }
2446
2447         if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2448                 lan8814_flush_fifo(phydev, false);
2449                 skb_queue_purge(&ptp_priv->rx_queue);
2450         }
2451 }
2452
2453 static int lan8804_config_init(struct phy_device *phydev)
2454 {
2455         int val;
2456
2457         /* MDI-X setting for swap A,B transmit */
2458         val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2459         val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2460         val |= LAN8804_ALIGN_TX_A_B_SWAP;
2461         lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2462
2463         /* Make sure that the PHY will not stop generating the clock when the
2464          * link partner goes down
2465          */
2466         lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2467         lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2468
2469         return 0;
2470 }
2471
2472 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2473 {
2474         u16 tsu_irq_status;
2475         int irq_status;
2476
2477         irq_status = phy_read(phydev, LAN8814_INTS);
2478         if (irq_status > 0 && (irq_status & LAN8814_INT_LINK))
2479                 phy_trigger_machine(phydev);
2480
2481         if (irq_status < 0) {
2482                 phy_error(phydev);
2483                 return IRQ_NONE;
2484         }
2485
2486         while (1) {
2487                 tsu_irq_status = lanphy_read_page_reg(phydev, 4,
2488                                                       LAN8814_INTR_STS_REG);
2489
2490                 if (tsu_irq_status > 0 &&
2491                     (tsu_irq_status & (LAN8814_INTR_STS_REG_1588_TSU0_ |
2492                                        LAN8814_INTR_STS_REG_1588_TSU1_ |
2493                                        LAN8814_INTR_STS_REG_1588_TSU2_ |
2494                                        LAN8814_INTR_STS_REG_1588_TSU3_)))
2495                         lan8814_handle_ptp_interrupt(phydev);
2496                 else
2497                         break;
2498         }
2499         return IRQ_HANDLED;
2500 }
2501
2502 static int lan8814_ack_interrupt(struct phy_device *phydev)
2503 {
2504         /* bit[12..0] int status, which is a read and clear register. */
2505         int rc;
2506
2507         rc = phy_read(phydev, LAN8814_INTS);
2508
2509         return (rc < 0) ? rc : 0;
2510 }
2511
2512 static int lan8814_config_intr(struct phy_device *phydev)
2513 {
2514         int err;
2515
2516         lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
2517                               LAN8814_INTR_CTRL_REG_POLARITY |
2518                               LAN8814_INTR_CTRL_REG_INTR_ENABLE);
2519
2520         /* enable / disable interrupts */
2521         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2522                 err = lan8814_ack_interrupt(phydev);
2523                 if (err)
2524                         return err;
2525
2526                 err =  phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
2527         } else {
2528                 err =  phy_write(phydev, LAN8814_INTC, 0);
2529                 if (err)
2530                         return err;
2531
2532                 err = lan8814_ack_interrupt(phydev);
2533         }
2534
2535         return err;
2536 }
2537
2538 static void lan8814_ptp_init(struct phy_device *phydev)
2539 {
2540         struct kszphy_priv *priv = phydev->priv;
2541         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2542         u32 temp;
2543
2544         lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
2545
2546         temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
2547         temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2548         lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
2549
2550         temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
2551         temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2552         lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
2553
2554         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
2555         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
2556
2557         /* Removing default registers configs related to L2 and IP */
2558         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
2559         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
2560         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
2561         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
2562
2563         skb_queue_head_init(&ptp_priv->tx_queue);
2564         skb_queue_head_init(&ptp_priv->rx_queue);
2565         INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
2566         spin_lock_init(&ptp_priv->rx_ts_lock);
2567
2568         ptp_priv->phydev = phydev;
2569
2570         ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
2571         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
2572         ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
2573         ptp_priv->mii_ts.ts_info  = lan8814_ts_info;
2574
2575         phydev->mii_ts = &ptp_priv->mii_ts;
2576 }
2577
2578 static int lan8814_ptp_probe_once(struct phy_device *phydev)
2579 {
2580         struct lan8814_shared_priv *shared = phydev->shared->priv;
2581
2582         /* Initialise shared lock for clock*/
2583         mutex_init(&shared->shared_lock);
2584
2585         shared->ptp_clock_info.owner = THIS_MODULE;
2586         snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
2587         shared->ptp_clock_info.max_adj = 31249999;
2588         shared->ptp_clock_info.n_alarm = 0;
2589         shared->ptp_clock_info.n_ext_ts = 0;
2590         shared->ptp_clock_info.n_pins = 0;
2591         shared->ptp_clock_info.pps = 0;
2592         shared->ptp_clock_info.pin_config = NULL;
2593         shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
2594         shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
2595         shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
2596         shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
2597         shared->ptp_clock_info.getcrosststamp = NULL;
2598
2599         shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
2600                                                &phydev->mdio.dev);
2601         if (IS_ERR_OR_NULL(shared->ptp_clock)) {
2602                 phydev_err(phydev, "ptp_clock_register failed %lu\n",
2603                            PTR_ERR(shared->ptp_clock));
2604                 return -EINVAL;
2605         }
2606
2607         phydev_dbg(phydev, "successfully registered ptp clock\n");
2608
2609         shared->phydev = phydev;
2610
2611         /* The EP.4 is shared between all the PHYs in the package and also it
2612          * can be accessed by any of the PHYs
2613          */
2614         lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
2615         lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
2616                               PTP_OPERATING_MODE_STANDALONE_);
2617
2618         return 0;
2619 }
2620
2621 static int lan8814_read_status(struct phy_device *phydev)
2622 {
2623         struct kszphy_priv *priv = phydev->priv;
2624         struct kszphy_latencies *latencies = &priv->latencies;
2625         int err;
2626         int regval;
2627
2628         err = genphy_read_status(phydev);
2629         if (err)
2630                 return err;
2631
2632         switch (phydev->speed) {
2633         case SPEED_1000:
2634                 lanphy_write_page_reg(phydev, 5, PTP_RX_LATENCY_1000,
2635                                       latencies->rx_1000);
2636                 lanphy_write_page_reg(phydev, 5, PTP_TX_LATENCY_1000,
2637                                       latencies->tx_1000);
2638                 break;
2639         case SPEED_100:
2640                 lanphy_write_page_reg(phydev, 5, PTP_RX_LATENCY_100,
2641                                       latencies->rx_100);
2642                 lanphy_write_page_reg(phydev, 5, PTP_TX_LATENCY_100,
2643                                       latencies->tx_100);
2644                 break;
2645         case SPEED_10:
2646                 lanphy_write_page_reg(phydev, 5, PTP_RX_LATENCY_10,
2647                                       latencies->rx_10);
2648                 lanphy_write_page_reg(phydev, 5, PTP_TX_LATENCY_10,
2649                                       latencies->tx_10);
2650                 break;
2651         default:
2652                 break;
2653         }
2654
2655         /* Make sure the PHY is not broken. Read idle error count,
2656          * and reset the PHY if it is maxed out.
2657          */
2658         regval = phy_read(phydev, MII_STAT1000);
2659         if ((regval & 0xFF) == 0xFF) {
2660                 phy_init_hw(phydev);
2661                 phydev->link = 0;
2662                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
2663                         phydev->drv->config_intr(phydev);
2664                 return genphy_config_aneg(phydev);
2665         }
2666
2667         return 0;
2668 }
2669
2670 static int lan8814_config_init(struct phy_device *phydev)
2671 {
2672         int val;
2673
2674         /* Reset the PHY */
2675         val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
2676         val |= LAN8814_QSGMII_SOFT_RESET_BIT;
2677         lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
2678
2679         /* Disable ANEG with QSGMII PCS Host side */
2680         val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
2681         val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
2682         lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
2683
2684         /* MDI-X setting for swap A,B transmit */
2685         val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
2686         val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
2687         val |= LAN8814_ALIGN_TX_A_B_SWAP;
2688         lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
2689
2690         return 0;
2691 }
2692
2693 static void lan8814_parse_latency(struct phy_device *phydev)
2694 {
2695         const struct device_node *np = phydev->mdio.dev.of_node;
2696         struct kszphy_priv *priv = phydev->priv;
2697         struct kszphy_latencies *latency = &priv->latencies;
2698         u32 val;
2699
2700         if (!of_property_read_u32(np, "lan8814,latency_rx_10", &val))
2701                 latency->rx_10 = val;
2702         if (!of_property_read_u32(np, "lan8814,latency_tx_10", &val))
2703                 latency->tx_10 = val;
2704         if (!of_property_read_u32(np, "lan8814,latency_rx_100", &val))
2705                 latency->rx_100 = val;
2706         if (!of_property_read_u32(np, "lan8814,latency_tx_100", &val))
2707                 latency->tx_100 = val;
2708         if (!of_property_read_u32(np, "lan8814,latency_rx_1000", &val))
2709                 latency->rx_1000 = val;
2710         if (!of_property_read_u32(np, "lan8814,latency_tx_1000", &val))
2711                 latency->tx_1000 = val;
2712 }
2713
2714 static int lan8814_probe(struct phy_device *phydev)
2715 {
2716         const struct device_node *np = phydev->mdio.dev.of_node;
2717         struct kszphy_priv *priv;
2718         u16 addr;
2719         int err;
2720
2721         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2722         if (!priv)
2723                 return -ENOMEM;
2724
2725         priv->led_mode = -1;
2726
2727         priv->latencies = lan8814_latencies;
2728
2729         phydev->priv = priv;
2730
2731         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2732             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) ||
2733             of_property_read_bool(np, "lan8814,ignore-ts"))
2734                 return 0;
2735
2736         /* Strap-in value for PHY address, below register read gives starting
2737          * phy address value
2738          */
2739         addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
2740         devm_phy_package_join(&phydev->mdio.dev, phydev,
2741                               addr, sizeof(struct lan8814_shared_priv));
2742
2743         if (phy_package_init_once(phydev)) {
2744                 err = lan8814_ptp_probe_once(phydev);
2745                 if (err)
2746                         return err;
2747         }
2748
2749         lan8814_parse_latency(phydev);
2750         lan8814_ptp_init(phydev);
2751
2752         return 0;
2753 }
2754
2755 static struct phy_driver ksphy_driver[] = {
2756 {
2757         .phy_id         = PHY_ID_KS8737,
2758         .phy_id_mask    = MICREL_PHY_ID_MASK,
2759         .name           = "Micrel KS8737",
2760         /* PHY_BASIC_FEATURES */
2761         .driver_data    = &ks8737_type,
2762         .config_init    = kszphy_config_init,
2763         .config_intr    = kszphy_config_intr,
2764         .handle_interrupt = kszphy_handle_interrupt,
2765         .suspend        = kszphy_suspend,
2766         .resume         = kszphy_resume,
2767 }, {
2768         .phy_id         = PHY_ID_KSZ8021,
2769         .phy_id_mask    = 0x00ffffff,
2770         .name           = "Micrel KSZ8021 or KSZ8031",
2771         /* PHY_BASIC_FEATURES */
2772         .driver_data    = &ksz8021_type,
2773         .probe          = kszphy_probe,
2774         .config_init    = kszphy_config_init,
2775         .config_intr    = kszphy_config_intr,
2776         .handle_interrupt = kszphy_handle_interrupt,
2777         .get_sset_count = kszphy_get_sset_count,
2778         .get_strings    = kszphy_get_strings,
2779         .get_stats      = kszphy_get_stats,
2780         .suspend        = kszphy_suspend,
2781         .resume         = kszphy_resume,
2782 }, {
2783         .phy_id         = PHY_ID_KSZ8031,
2784         .phy_id_mask    = 0x00ffffff,
2785         .name           = "Micrel KSZ8031",
2786         /* PHY_BASIC_FEATURES */
2787         .driver_data    = &ksz8021_type,
2788         .probe          = kszphy_probe,
2789         .config_init    = kszphy_config_init,
2790         .config_intr    = kszphy_config_intr,
2791         .handle_interrupt = kszphy_handle_interrupt,
2792         .get_sset_count = kszphy_get_sset_count,
2793         .get_strings    = kszphy_get_strings,
2794         .get_stats      = kszphy_get_stats,
2795         .suspend        = kszphy_suspend,
2796         .resume         = kszphy_resume,
2797 }, {
2798         .phy_id         = PHY_ID_KSZ8041,
2799         .phy_id_mask    = MICREL_PHY_ID_MASK,
2800         .name           = "Micrel KSZ8041",
2801         /* PHY_BASIC_FEATURES */
2802         .driver_data    = &ksz8041_type,
2803         .probe          = kszphy_probe,
2804         .config_init    = ksz8041_config_init,
2805         .config_aneg    = ksz8041_config_aneg,
2806         .config_intr    = kszphy_config_intr,
2807         .handle_interrupt = kszphy_handle_interrupt,
2808         .get_sset_count = kszphy_get_sset_count,
2809         .get_strings    = kszphy_get_strings,
2810         .get_stats      = kszphy_get_stats,
2811         /* No suspend/resume callbacks because of errata DS80000700A,
2812          * receiver error following software power down.
2813          */
2814 }, {
2815         .phy_id         = PHY_ID_KSZ8041RNLI,
2816         .phy_id_mask    = MICREL_PHY_ID_MASK,
2817         .name           = "Micrel KSZ8041RNLI",
2818         /* PHY_BASIC_FEATURES */
2819         .driver_data    = &ksz8041_type,
2820         .probe          = kszphy_probe,
2821         .config_init    = kszphy_config_init,
2822         .config_intr    = kszphy_config_intr,
2823         .handle_interrupt = kszphy_handle_interrupt,
2824         .get_sset_count = kszphy_get_sset_count,
2825         .get_strings    = kszphy_get_strings,
2826         .get_stats      = kszphy_get_stats,
2827         .suspend        = kszphy_suspend,
2828         .resume         = kszphy_resume,
2829 }, {
2830         .name           = "Micrel KSZ8051",
2831         /* PHY_BASIC_FEATURES */
2832         .driver_data    = &ksz8051_type,
2833         .probe          = kszphy_probe,
2834         .config_init    = kszphy_config_init,
2835         .config_intr    = kszphy_config_intr,
2836         .handle_interrupt = kszphy_handle_interrupt,
2837         .get_sset_count = kszphy_get_sset_count,
2838         .get_strings    = kszphy_get_strings,
2839         .get_stats      = kszphy_get_stats,
2840         .match_phy_device = ksz8051_match_phy_device,
2841         .suspend        = kszphy_suspend,
2842         .resume         = kszphy_resume,
2843 }, {
2844         .phy_id         = PHY_ID_KSZ8001,
2845         .name           = "Micrel KSZ8001 or KS8721",
2846         .phy_id_mask    = 0x00fffffc,
2847         /* PHY_BASIC_FEATURES */
2848         .driver_data    = &ksz8041_type,
2849         .probe          = kszphy_probe,
2850         .config_init    = kszphy_config_init,
2851         .config_intr    = kszphy_config_intr,
2852         .handle_interrupt = kszphy_handle_interrupt,
2853         .get_sset_count = kszphy_get_sset_count,
2854         .get_strings    = kszphy_get_strings,
2855         .get_stats      = kszphy_get_stats,
2856         .suspend        = kszphy_suspend,
2857         .resume         = kszphy_resume,
2858 }, {
2859         .phy_id         = PHY_ID_KSZ8081,
2860         .name           = "Micrel KSZ8081 or KSZ8091",
2861         .phy_id_mask    = MICREL_PHY_ID_MASK,
2862         .flags          = PHY_POLL_CABLE_TEST,
2863         /* PHY_BASIC_FEATURES */
2864         .driver_data    = &ksz8081_type,
2865         .probe          = kszphy_probe,
2866         .config_init    = ksz8081_config_init,
2867         .soft_reset     = genphy_soft_reset,
2868         .config_aneg    = ksz8081_config_aneg,
2869         .read_status    = ksz8081_read_status,
2870         .config_intr    = kszphy_config_intr,
2871         .handle_interrupt = kszphy_handle_interrupt,
2872         .get_sset_count = kszphy_get_sset_count,
2873         .get_strings    = kszphy_get_strings,
2874         .get_stats      = kszphy_get_stats,
2875         .suspend        = kszphy_suspend,
2876         .resume         = kszphy_resume,
2877         .cable_test_start       = ksz886x_cable_test_start,
2878         .cable_test_get_status  = ksz886x_cable_test_get_status,
2879 }, {
2880         .phy_id         = PHY_ID_KSZ8061,
2881         .name           = "Micrel KSZ8061",
2882         .phy_id_mask    = MICREL_PHY_ID_MASK,
2883         /* PHY_BASIC_FEATURES */
2884         .config_init    = ksz8061_config_init,
2885         .config_intr    = kszphy_config_intr,
2886         .handle_interrupt = kszphy_handle_interrupt,
2887         .suspend        = kszphy_suspend,
2888         .resume         = kszphy_resume,
2889 }, {
2890         .phy_id         = PHY_ID_KSZ9021,
2891         .phy_id_mask    = 0x000ffffe,
2892         .name           = "Micrel KSZ9021 Gigabit PHY",
2893         /* PHY_GBIT_FEATURES */
2894         .driver_data    = &ksz9021_type,
2895         .probe          = kszphy_probe,
2896         .get_features   = ksz9031_get_features,
2897         .config_init    = ksz9021_config_init,
2898         .config_intr    = kszphy_config_intr,
2899         .handle_interrupt = kszphy_handle_interrupt,
2900         .get_sset_count = kszphy_get_sset_count,
2901         .get_strings    = kszphy_get_strings,
2902         .get_stats      = kszphy_get_stats,
2903         .suspend        = kszphy_suspend,
2904         .resume         = kszphy_resume,
2905         .read_mmd       = genphy_read_mmd_unsupported,
2906         .write_mmd      = genphy_write_mmd_unsupported,
2907 }, {
2908         .phy_id         = PHY_ID_KSZ9031,
2909         .phy_id_mask    = MICREL_PHY_ID_MASK,
2910         .name           = "Micrel KSZ9031 Gigabit PHY",
2911         .driver_data    = &ksz9021_type,
2912         .probe          = kszphy_probe,
2913         .get_features   = ksz9031_get_features,
2914         .config_init    = ksz9031_config_init,
2915         .soft_reset     = genphy_soft_reset,
2916         .read_status    = ksz9031_read_status,
2917         .config_intr    = kszphy_config_intr,
2918         .handle_interrupt = kszphy_handle_interrupt,
2919         .get_sset_count = kszphy_get_sset_count,
2920         .get_strings    = kszphy_get_strings,
2921         .get_stats      = kszphy_get_stats,
2922         .suspend        = kszphy_suspend,
2923         .resume         = kszphy_resume,
2924 }, {
2925         .phy_id         = PHY_ID_LAN8814,
2926         .phy_id_mask    = MICREL_PHY_ID_MASK,
2927         .name           = "Microchip INDY Gigabit Quad PHY",
2928         .config_init    = lan8814_config_init,
2929         .probe          = lan8814_probe,
2930         .soft_reset     = genphy_soft_reset,
2931         .read_status    = lan8814_read_status,
2932         .get_sset_count = kszphy_get_sset_count,
2933         .get_strings    = kszphy_get_strings,
2934         .get_stats      = kszphy_get_stats,
2935         .suspend        = genphy_suspend,
2936         .resume         = kszphy_resume,
2937         .config_intr    = lan8814_config_intr,
2938         .handle_interrupt = lan8814_handle_interrupt,
2939 }, {
2940         .phy_id         = PHY_ID_LAN8804,
2941         .phy_id_mask    = MICREL_PHY_ID_MASK,
2942         .name           = "Microchip LAN966X Gigabit PHY",
2943         .config_init    = lan8804_config_init,
2944         .driver_data    = &ksz9021_type,
2945         .probe          = kszphy_probe,
2946         .soft_reset     = genphy_soft_reset,
2947         .read_status    = ksz9031_read_status,
2948         .get_sset_count = kszphy_get_sset_count,
2949         .get_strings    = kszphy_get_strings,
2950         .get_stats      = kszphy_get_stats,
2951         .suspend        = genphy_suspend,
2952         .resume         = kszphy_resume,
2953 }, {
2954         .phy_id         = PHY_ID_KSZ9131,
2955         .phy_id_mask    = MICREL_PHY_ID_MASK,
2956         .name           = "Microchip KSZ9131 Gigabit PHY",
2957         /* PHY_GBIT_FEATURES */
2958         .driver_data    = &ksz9021_type,
2959         .probe          = kszphy_probe,
2960         .config_init    = ksz9131_config_init,
2961         .config_intr    = kszphy_config_intr,
2962         .handle_interrupt = kszphy_handle_interrupt,
2963         .get_sset_count = kszphy_get_sset_count,
2964         .get_strings    = kszphy_get_strings,
2965         .get_stats      = kszphy_get_stats,
2966         .suspend        = kszphy_suspend,
2967         .resume         = kszphy_resume,
2968 }, {
2969         .phy_id         = PHY_ID_KSZ8873MLL,
2970         .phy_id_mask    = MICREL_PHY_ID_MASK,
2971         .name           = "Micrel KSZ8873MLL Switch",
2972         /* PHY_BASIC_FEATURES */
2973         .config_init    = kszphy_config_init,
2974         .config_aneg    = ksz8873mll_config_aneg,
2975         .read_status    = ksz8873mll_read_status,
2976         .suspend        = genphy_suspend,
2977         .resume         = genphy_resume,
2978 }, {
2979         .phy_id         = PHY_ID_KSZ886X,
2980         .phy_id_mask    = MICREL_PHY_ID_MASK,
2981         .name           = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
2982         /* PHY_BASIC_FEATURES */
2983         .flags          = PHY_POLL_CABLE_TEST,
2984         .config_init    = kszphy_config_init,
2985         .config_aneg    = ksz886x_config_aneg,
2986         .read_status    = ksz886x_read_status,
2987         .suspend        = genphy_suspend,
2988         .resume         = genphy_resume,
2989         .cable_test_start       = ksz886x_cable_test_start,
2990         .cable_test_get_status  = ksz886x_cable_test_get_status,
2991 }, {
2992         .name           = "Micrel KSZ87XX Switch",
2993         /* PHY_BASIC_FEATURES */
2994         .config_init    = kszphy_config_init,
2995         .match_phy_device = ksz8795_match_phy_device,
2996         .suspend        = genphy_suspend,
2997         .resume         = genphy_resume,
2998 }, {
2999         .phy_id         = PHY_ID_KSZ9477,
3000         .phy_id_mask    = MICREL_PHY_ID_MASK,
3001         .name           = "Microchip KSZ9477",
3002         /* PHY_GBIT_FEATURES */
3003         .config_init    = kszphy_config_init,
3004         .suspend        = genphy_suspend,
3005         .resume         = genphy_resume,
3006 } };
3007
3008 module_phy_driver(ksphy_driver);
3009
3010 MODULE_DESCRIPTION("Micrel PHY driver");
3011 MODULE_AUTHOR("David J. Choi");
3012 MODULE_LICENSE("GPL");
3013
3014 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
3015         { PHY_ID_KSZ9021, 0x000ffffe },
3016         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
3017         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
3018         { PHY_ID_KSZ8001, 0x00fffffc },
3019         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
3020         { PHY_ID_KSZ8021, 0x00ffffff },
3021         { PHY_ID_KSZ8031, 0x00ffffff },
3022         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
3023         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
3024         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
3025         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
3026         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
3027         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
3028         { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
3029         { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
3030         { }
3031 };
3032
3033 MODULE_DEVICE_TABLE(mdio, micrel_tbl);