drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drm_cache.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v9_0.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "amdgpu_gem.h"
  29
  30 #include "hdp/hdp_4_0_offset.h"
  31 #include "hdp/hdp_4_0_sh_mask.h"
  32 #include "gc/gc_9_0_sh_mask.h"
  33 #include "dce/dce_12_0_offset.h"
  34 #include "dce/dce_12_0_sh_mask.h"
  35 #include "vega10_enum.h"
  36 #include "mmhub/mmhub_1_0_offset.h"
  37 #include "athub/athub_1_0_offset.h"
  38 #include "oss/osssys_4_0_offset.h"
  39
  40 #include "soc15.h"
  41 #include "soc15_common.h"
  42 #include "umc/umc_6_0_sh_mask.h"
  43
  44 #include "gfxhub_v1_0.h"
  45 #include "mmhub_v1_0.h"
  46 #include "gfxhub_v1_1.h"
  47
  48 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  49
  50 #include "amdgpu_ras.h"
  51
  52 /* add these here since we already include dce12 headers and these are for DCN */
  53 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  54 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  55 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  56 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  57 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  58 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  59
  60 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  61 #define AMDGPU_NUM_OF_VMIDS                     8
  62
  63 static const u32 golden_settings_vega10_hdp[] =
  64 {
  65         0xf64, 0x0fffffff, 0x00000000,
  66         0xf65, 0x0fffffff, 0x00000000,
  67         0xf66, 0x0fffffff, 0x00000000,
  68         0xf67, 0x0fffffff, 0x00000000,
  69         0xf68, 0x0fffffff, 0x00000000,
  70         0xf6a, 0x0fffffff, 0x00000000,
  71         0xf6b, 0x0fffffff, 0x00000000,
  72         0xf6c, 0x0fffffff, 0x00000000,
  73         0xf6d, 0x0fffffff, 0x00000000,
  74         0xf6e, 0x0fffffff, 0x00000000,
  75 };
  76
  77 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  78 {
  79         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  80         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  81 };
  82
  83 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  84 {
  85         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  86         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  87 };
  88
  89 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
  90         (0x000143c0 + 0x00000000),
  91         (0x000143c0 + 0x00000800),
  92         (0x000143c0 + 0x00001000),
  93         (0x000143c0 + 0x00001800),
  94         (0x000543c0 + 0x00000000),
  95         (0x000543c0 + 0x00000800),
  96         (0x000543c0 + 0x00001000),
  97         (0x000543c0 + 0x00001800),
  98         (0x000943c0 + 0x00000000),
  99         (0x000943c0 + 0x00000800),
 100         (0x000943c0 + 0x00001000),
 101         (0x000943c0 + 0x00001800),
 102         (0x000d43c0 + 0x00000000),
 103         (0x000d43c0 + 0x00000800),
 104         (0x000d43c0 + 0x00001000),
 105         (0x000d43c0 + 0x00001800),
 106         (0x001143c0 + 0x00000000),
 107         (0x001143c0 + 0x00000800),
 108         (0x001143c0 + 0x00001000),
 109         (0x001143c0 + 0x00001800),
 110         (0x001543c0 + 0x00000000),
 111         (0x001543c0 + 0x00000800),
 112         (0x001543c0 + 0x00001000),
 113         (0x001543c0 + 0x00001800),
 114         (0x001943c0 + 0x00000000),
 115         (0x001943c0 + 0x00000800),
 116         (0x001943c0 + 0x00001000),
 117         (0x001943c0 + 0x00001800),
 118         (0x001d43c0 + 0x00000000),
 119         (0x001d43c0 + 0x00000800),
 120         (0x001d43c0 + 0x00001000),
 121         (0x001d43c0 + 0x00001800),
 122 };
 123
 124 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 125         (0x000143e0 + 0x00000000),
 126         (0x000143e0 + 0x00000800),
 127         (0x000143e0 + 0x00001000),
 128         (0x000143e0 + 0x00001800),
 129         (0x000543e0 + 0x00000000),
 130         (0x000543e0 + 0x00000800),
 131         (0x000543e0 + 0x00001000),
 132         (0x000543e0 + 0x00001800),
 133         (0x000943e0 + 0x00000000),
 134         (0x000943e0 + 0x00000800),
 135         (0x000943e0 + 0x00001000),
 136         (0x000943e0 + 0x00001800),
 137         (0x000d43e0 + 0x00000000),
 138         (0x000d43e0 + 0x00000800),
 139         (0x000d43e0 + 0x00001000),
 140         (0x000d43e0 + 0x00001800),
 141         (0x001143e0 + 0x00000000),
 142         (0x001143e0 + 0x00000800),
 143         (0x001143e0 + 0x00001000),
 144         (0x001143e0 + 0x00001800),
 145         (0x001543e0 + 0x00000000),
 146         (0x001543e0 + 0x00000800),
 147         (0x001543e0 + 0x00001000),
 148         (0x001543e0 + 0x00001800),
 149         (0x001943e0 + 0x00000000),
 150         (0x001943e0 + 0x00000800),
 151         (0x001943e0 + 0x00001000),
 152         (0x001943e0 + 0x00001800),
 153         (0x001d43e0 + 0x00000000),
 154         (0x001d43e0 + 0x00000800),
 155         (0x001d43e0 + 0x00001000),
 156         (0x001d43e0 + 0x00001800),
 157 };
 158
 159 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
 160         (0x000143c2 + 0x00000000),
 161         (0x000143c2 + 0x00000800),
 162         (0x000143c2 + 0x00001000),
 163         (0x000143c2 + 0x00001800),
 164         (0x000543c2 + 0x00000000),
 165         (0x000543c2 + 0x00000800),
 166         (0x000543c2 + 0x00001000),
 167         (0x000543c2 + 0x00001800),
 168         (0x000943c2 + 0x00000000),
 169         (0x000943c2 + 0x00000800),
 170         (0x000943c2 + 0x00001000),
 171         (0x000943c2 + 0x00001800),
 172         (0x000d43c2 + 0x00000000),
 173         (0x000d43c2 + 0x00000800),
 174         (0x000d43c2 + 0x00001000),
 175         (0x000d43c2 + 0x00001800),
 176         (0x001143c2 + 0x00000000),
 177         (0x001143c2 + 0x00000800),
 178         (0x001143c2 + 0x00001000),
 179         (0x001143c2 + 0x00001800),
 180         (0x001543c2 + 0x00000000),
 181         (0x001543c2 + 0x00000800),
 182         (0x001543c2 + 0x00001000),
 183         (0x001543c2 + 0x00001800),
 184         (0x001943c2 + 0x00000000),
 185         (0x001943c2 + 0x00000800),
 186         (0x001943c2 + 0x00001000),
 187         (0x001943c2 + 0x00001800),
 188         (0x001d43c2 + 0x00000000),
 189         (0x001d43c2 + 0x00000800),
 190         (0x001d43c2 + 0x00001000),
 191         (0x001d43c2 + 0x00001800),
 192 };
 193
 194 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 195                 struct amdgpu_irq_src *src,
 196                 unsigned type,
 197                 enum amdgpu_interrupt_state state)
 198 {
 199         u32 bits, i, tmp, reg;
 200
 201         bits = 0x7f;
 202
 203         switch (state) {
 204         case AMDGPU_IRQ_STATE_DISABLE:
 205                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 206                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 207                         tmp = RREG32(reg);
 208                         tmp &= ~bits;
 209                         WREG32(reg, tmp);
 210                 }
 211                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 212                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 213                         tmp = RREG32(reg);
 214                         tmp &= ~bits;
 215                         WREG32(reg, tmp);
 216                 }
 217                 break;
 218         case AMDGPU_IRQ_STATE_ENABLE:
 219                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 220                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 221                         tmp = RREG32(reg);
 222                         tmp |= bits;
 223                         WREG32(reg, tmp);
 224                 }
 225                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 226                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 227                         tmp = RREG32(reg);
 228                         tmp |= bits;
 229                         WREG32(reg, tmp);
 230                 }
 231                 break;
 232         default:
 233                 break;
 234         }
 235
 236         return 0;
 237 }
 238
 239 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 240                 struct amdgpu_iv_entry *entry)
 241 {
 242         kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 243         amdgpu_ras_reset_gpu(adev, 0);
 244         return AMDGPU_RAS_UE;
 245 }
 246
 247 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
 248                 struct amdgpu_irq_src *source,
 249                 struct amdgpu_iv_entry *entry)
 250 {
 251         struct ras_common_if *ras_if = adev->gmc.ras_if;
 252         struct ras_dispatch_if ih_data = {
 253                 .entry = entry,
 254         };
 255
 256         if (!ras_if)
 257                 return 0;
 258
 259         ih_data.head = *ras_if;
 260
 261         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 262         return 0;
 263 }
 264
 265 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 266                                         struct amdgpu_irq_src *src,
 267                                         unsigned type,
 268                                         enum amdgpu_interrupt_state state)
 269 {
 270         struct amdgpu_vmhub *hub;
 271         u32 tmp, reg, bits, i, j;
 272
 273         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 274                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 275                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 276                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 277                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 278                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 279                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 280
 281         switch (state) {
 282         case AMDGPU_IRQ_STATE_DISABLE:
 283                 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
 284                         hub = &adev->vmhub[j];
 285                         for (i = 0; i < 16; i++) {
 286                                 reg = hub->vm_context0_cntl + i;
 287                                 tmp = RREG32(reg);
 288                                 tmp &= ~bits;
 289                                 WREG32(reg, tmp);
 290                         }
 291                 }
 292                 break;
 293         case AMDGPU_IRQ_STATE_ENABLE:
 294                 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
 295                         hub = &adev->vmhub[j];
 296                         for (i = 0; i < 16; i++) {
 297                                 reg = hub->vm_context0_cntl + i;
 298                                 tmp = RREG32(reg);
 299                                 tmp |= bits;
 300                                 WREG32(reg, tmp);
 301                         }
 302                 }
 303         default:
 304                 break;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 311                                 struct amdgpu_irq_src *source,
 312                                 struct amdgpu_iv_entry *entry)
 313 {
 314         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 315         bool retry_fault = !!(entry->src_data[1] & 0x80);
 316         uint32_t status = 0;
 317         u64 addr;
 318
 319         addr = (u64)entry->src_data[0] << 12;
 320         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 321
 322         if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 323                                                     entry->timestamp))
 324                 return 1; /* This also prevents sending it to KFD */
 325
 326         /* If it's the first fault for this address, process it normally */
 327         if (!amdgpu_sriov_vf(adev)) {
 328                 status = RREG32(hub->vm_l2_pro_fault_status);
 329                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 330         }
 331
 332         if (printk_ratelimit()) {
 333                 struct amdgpu_task_info task_info;
 334
 335                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 336                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 337
 338                 dev_err(adev->dev,
 339                         "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 340                         "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 341                         entry->vmid_src ? "mmhub" : "gfxhub",
 342                         retry_fault ? "retry" : "no-retry",
 343                         entry->src_id, entry->ring_id, entry->vmid,
 344                         entry->pasid, task_info.process_name, task_info.tgid,
 345                         task_info.task_name, task_info.pid);
 346                 dev_err(adev->dev, "  in page starting at address 0x%016llx from %d\n",
 347                         addr, entry->client_id);
 348                 if (!amdgpu_sriov_vf(adev))
 349                         dev_err(adev->dev,
 350                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 351                                 status);
 352         }
 353
 354         return 0;
 355 }
 356
 357 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 358         .set = gmc_v9_0_vm_fault_interrupt_state,
 359         .process = gmc_v9_0_process_interrupt,
 360 };
 361
 362
 363 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 364         .set = gmc_v9_0_ecc_interrupt_state,
 365         .process = gmc_v9_0_process_ecc_irq,
 366 };
 367
 368 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 369 {
 370         adev->gmc.vm_fault.num_types = 1;
 371         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 372
 373         adev->gmc.ecc_irq.num_types = 1;
 374         adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 375 }
 376
 377 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 378                                         uint32_t flush_type)
 379 {
 380         u32 req = 0;
 381
 382         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 383                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 384         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 385         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 386         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 387         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 388         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 389         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 390         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 391                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 392
 393         return req;
 394 }
 395
 396 /*
 397  * GART
 398  * VMID 0 is the physical GPU addresses as used by the kernel.
 399  * VMIDs 1-15 are used for userspace clients and are handled
 400  * by the amdgpu vm/hsa code.
 401  */
 402
 403 /**
 404  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 405  *
 406  * @adev: amdgpu_device pointer
 407  * @vmid: vm instance to flush
 408  * @flush_type: the flush type
 409  *
 410  * Flush the TLB for the requested page table using certain type.
 411  */
 412 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 413                                 uint32_t vmid, uint32_t flush_type)
 414 {
 415         const unsigned eng = 17;
 416         unsigned i, j;
 417
 418         for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
 419                 struct amdgpu_vmhub *hub = &adev->vmhub[i];
 420                 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 421
 422                 /* This is necessary for a HW workaround under SRIOV as well
 423                  * as GFXOFF under bare metal
 424                  */
 425                 if (adev->gfx.kiq.ring.sched.ready &&
 426                     (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 427                     !adev->in_gpu_reset) {
 428                         uint32_t req = hub->vm_inv_eng0_req + eng;
 429                         uint32_t ack = hub->vm_inv_eng0_ack + eng;
 430
 431                         amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
 432                                                            1 << vmid);
 433                         continue;
 434                 }
 435
 436                 spin_lock(&adev->gmc.invalidate_lock);
 437                 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 438                 for (j = 0; j < adev->usec_timeout; j++) {
 439                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 440                         if (tmp & (1 << vmid))
 441                                 break;
 442                         udelay(1);
 443                 }
 444                 spin_unlock(&adev->gmc.invalidate_lock);
 445                 if (j < adev->usec_timeout)
 446                         continue;
 447
 448                 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 449         }
 450 }
 451
 452 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 453                                             unsigned vmid, uint64_t pd_addr)
 454 {
 455         struct amdgpu_device *adev = ring->adev;
 456         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 457         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 458         unsigned eng = ring->vm_inv_eng;
 459
 460         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 461                               lower_32_bits(pd_addr));
 462
 463         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 464                               upper_32_bits(pd_addr));
 465
 466         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 467                                             hub->vm_inv_eng0_ack + eng,
 468                                             req, 1 << vmid);
 469
 470         return pd_addr;
 471 }
 472
 473 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 474                                         unsigned pasid)
 475 {
 476         struct amdgpu_device *adev = ring->adev;
 477         uint32_t reg;
 478
 479         if (ring->funcs->vmhub == AMDGPU_GFXHUB)
 480                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 481         else
 482                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 483
 484         amdgpu_ring_emit_wreg(ring, reg, pasid);
 485 }
 486
 487 /*
 488  * PTE format on VEGA 10:
 489  * 63:59 reserved
 490  * 58:57 mtype
 491  * 56 F
 492  * 55 L
 493  * 54 P
 494  * 53 SW
 495  * 52 T
 496  * 50:48 reserved
 497  * 47:12 4k physical page base address
 498  * 11:7 fragment
 499  * 6 write
 500  * 5 read
 501  * 4 exe
 502  * 3 Z
 503  * 2 snooped
 504  * 1 system
 505  * 0 valid
 506  *
 507  * PDE format on VEGA 10:
 508  * 63:59 block fragment size
 509  * 58:55 reserved
 510  * 54 P
 511  * 53:48 reserved
 512  * 47:6 physical base address of PD or PTE
 513  * 5:3 reserved
 514  * 2 C
 515  * 1 system
 516  * 0 valid
 517  */
 518
 519 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 520                                                 uint32_t flags)
 521
 522 {
 523         uint64_t pte_flag = 0;
 524
 525         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 526                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 527         if (flags & AMDGPU_VM_PAGE_READABLE)
 528                 pte_flag |= AMDGPU_PTE_READABLE;
 529         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 530                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 531
 532         switch (flags & AMDGPU_VM_MTYPE_MASK) {
 533         case AMDGPU_VM_MTYPE_DEFAULT:
 534                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 535                 break;
 536         case AMDGPU_VM_MTYPE_NC:
 537                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 538                 break;
 539         case AMDGPU_VM_MTYPE_WC:
 540                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
 541                 break;
 542         case AMDGPU_VM_MTYPE_CC:
 543                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
 544                 break;
 545         case AMDGPU_VM_MTYPE_UC:
 546                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
 547                 break;
 548         default:
 549                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 550                 break;
 551         }
 552
 553         if (flags & AMDGPU_VM_PAGE_PRT)
 554                 pte_flag |= AMDGPU_PTE_PRT;
 555
 556         return pte_flag;
 557 }
 558
 559 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 560                                 uint64_t *addr, uint64_t *flags)
 561 {
 562         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 563                 *addr = adev->vm_manager.vram_base_offset + *addr -
 564                         adev->gmc.vram_start;
 565         BUG_ON(*addr & 0xFFFF00000000003FULL);
 566
 567         if (!adev->gmc.translate_further)
 568                 return;
 569
 570         if (level == AMDGPU_VM_PDB1) {
 571                 /* Set the block fragment size */
 572                 if (!(*flags & AMDGPU_PDE_PTE))
 573                         *flags |= AMDGPU_PDE_BFS(0x9);
 574
 575         } else if (level == AMDGPU_VM_PDB0) {
 576                 if (*flags & AMDGPU_PDE_PTE)
 577                         *flags &= ~AMDGPU_PDE_PTE;
 578                 else
 579                         *flags |= AMDGPU_PTE_TF;
 580         }
 581 }
 582
 583 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 584         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 585         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 586         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 587         .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
 588         .get_vm_pde = gmc_v9_0_get_vm_pde
 589 };
 590
 591 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 592 {
 593         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 594 }
 595
 596 static int gmc_v9_0_early_init(void *handle)
 597 {
 598         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 599
 600         gmc_v9_0_set_gmc_funcs(adev);
 601         gmc_v9_0_set_irq_funcs(adev);
 602
 603         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 604         adev->gmc.shared_aperture_end =
 605                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 606         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 607         adev->gmc.private_aperture_end =
 608                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 609
 610         return 0;
 611 }
 612
 613 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 614 {
 615
 616         /*
 617          * TODO:
 618          * Currently there is a bug where some memory client outside
 619          * of the driver writes to first 8M of VRAM on S3 resume,
 620          * this overrides GART which by default gets placed in first 8M and
 621          * causes VM_FAULTS once GTT is accessed.
 622          * Keep the stolen memory reservation until the while this is not solved.
 623          * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 624          */
 625         switch (adev->asic_type) {
 626         case CHIP_VEGA10:
 627                 return true;
 628         case CHIP_RAVEN:
 629         case CHIP_VEGA12:
 630         case CHIP_VEGA20:
 631         default:
 632                 return false;
 633         }
 634 }
 635
 636 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 637 {
 638         struct amdgpu_ring *ring;
 639         unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
 640                 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
 641         unsigned i;
 642         unsigned vmhub, inv_eng;
 643
 644         for (i = 0; i < adev->num_rings; ++i) {
 645                 ring = adev->rings[i];
 646                 vmhub = ring->funcs->vmhub;
 647
 648                 inv_eng = ffs(vm_inv_engs[vmhub]);
 649                 if (!inv_eng) {
 650                         dev_err(adev->dev, "no VM inv eng for ring %s\n",
 651                                 ring->name);
 652                         return -EINVAL;
 653                 }
 654
 655                 ring->vm_inv_eng = inv_eng - 1;
 656                 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
 657
 658                 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
 659                          ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
 660         }
 661
 662         return 0;
 663 }
 664
 665 static int gmc_v9_0_ecc_late_init(void *handle)
 666 {
 667         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 668         struct ras_common_if **ras_if = &adev->gmc.ras_if;
 669         struct ras_ih_if ih_info = {
 670                 .cb = gmc_v9_0_process_ras_data_cb,
 671         };
 672         struct ras_fs_if fs_info = {
 673                 .sysfs_name = "umc_err_count",
 674                 .debugfs_name = "umc_err_inject",
 675         };
 676         struct ras_common_if ras_block = {
 677                 .block = AMDGPU_RAS_BLOCK__UMC,
 678                 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
 679                 .sub_block_index = 0,
 680                 .name = "umc",
 681         };
 682         int r;
 683
 684         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {
 685                 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
 686                 return 0;
 687         }
 688         /* handle resume path. */
 689         if (*ras_if)
 690                 goto resume;
 691
 692         *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
 693         if (!*ras_if)
 694                 return -ENOMEM;
 695
 696         **ras_if = ras_block;
 697
 698         r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
 699         if (r)
 700                 goto feature;
 701
 702         ih_info.head = **ras_if;
 703         fs_info.head = **ras_if;
 704
 705         r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
 706         if (r)
 707                 goto interrupt;
 708
 709         r = amdgpu_ras_debugfs_create(adev, &fs_info);
 710         if (r)
 711                 goto debugfs;
 712
 713         r = amdgpu_ras_sysfs_create(adev, &fs_info);
 714         if (r)
 715                 goto sysfs;
 716 resume:
 717         r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
 718         if (r)
 719                 goto irq;
 720
 721         return 0;
 722 irq:
 723         amdgpu_ras_sysfs_remove(adev, *ras_if);
 724 sysfs:
 725         amdgpu_ras_debugfs_remove(adev, *ras_if);
 726 debugfs:
 727         amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
 728 interrupt:
 729         amdgpu_ras_feature_enable(adev, *ras_if, 0);
 730 feature:
 731         kfree(*ras_if);
 732         *ras_if = NULL;
 733         return -EINVAL;
 734 }
 735
 736
 737 static int gmc_v9_0_late_init(void *handle)
 738 {
 739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 740         bool r;
 741
 742         if (!gmc_v9_0_keep_stolen_memory(adev))
 743                 amdgpu_bo_late_init(adev);
 744
 745         r = gmc_v9_0_allocate_vm_inv_eng(adev);
 746         if (r)
 747                 return r;
 748         /* Check if ecc is available */
 749         if (!amdgpu_sriov_vf(adev)) {
 750                 switch (adev->asic_type) {
 751                 case CHIP_VEGA10:
 752                 case CHIP_VEGA20:
 753                         r = amdgpu_atomfirmware_mem_ecc_supported(adev);
 754                         if (!r) {
 755                                 DRM_INFO("ECC is not present.\n");
 756                                 if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
 757                                         adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
 758                         } else {
 759                                 DRM_INFO("ECC is active.\n");
 760                         }
 761
 762                         r = amdgpu_atomfirmware_sram_ecc_supported(adev);
 763                         if (!r) {
 764                                 DRM_INFO("SRAM ECC is not present.\n");
 765                         } else {
 766                                 DRM_INFO("SRAM ECC is active.\n");
 767                         }
 768                         break;
 769                 default:
 770                         break;
 771                 }
 772         }
 773
 774         r = gmc_v9_0_ecc_late_init(handle);
 775         if (r)
 776                 return r;
 777
 778         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 779 }
 780
 781 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 782                                         struct amdgpu_gmc *mc)
 783 {
 784         u64 base = 0;
 785         if (!amdgpu_sriov_vf(adev))
 786                 base = mmhub_v1_0_get_fb_location(adev);
 787         /* add the xgmi offset of the physical node */
 788         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 789         amdgpu_gmc_vram_location(adev, mc, base);
 790         amdgpu_gmc_gart_location(adev, mc);
 791         if (!amdgpu_sriov_vf(adev))
 792                 amdgpu_gmc_agp_location(adev, mc);
 793         /* base offset of vram pages */
 794         adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 795
 796         /* XXX: add the xgmi offset of the physical node? */
 797         adev->vm_manager.vram_base_offset +=
 798                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 799 }
 800
 801 /**
 802  * gmc_v9_0_mc_init - initialize the memory controller driver params
 803  *
 804  * @adev: amdgpu_device pointer
 805  *
 806  * Look up the amount of vram, vram width, and decide how to place
 807  * vram and gart within the GPU's physical address space.
 808  * Returns 0 for success.
 809  */
 810 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 811 {
 812         int chansize, numchan;
 813         int r;
 814
 815         if (amdgpu_emu_mode != 1)
 816                 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
 817         if (!adev->gmc.vram_width) {
 818                 /* hbm memory channel size */
 819                 if (adev->flags & AMD_IS_APU)
 820                         chansize = 64;
 821                 else
 822                         chansize = 128;
 823
 824                 numchan = adev->df_funcs->get_hbm_channel_number(adev);
 825                 adev->gmc.vram_width = numchan * chansize;
 826         }
 827
 828         /* size in MB on si */
 829         adev->gmc.mc_vram_size =
 830                 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 831         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 832
 833         if (!(adev->flags & AMD_IS_APU)) {
 834                 r = amdgpu_device_resize_fb_bar(adev);
 835                 if (r)
 836                         return r;
 837         }
 838         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 839         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 840
 841 #ifdef CONFIG_X86_64
 842         if (adev->flags & AMD_IS_APU) {
 843                 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 844                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 845         }
 846 #endif
 847         /* In case the PCI BAR is larger than the actual amount of vram */
 848         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 849         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 850                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 851
 852         /* set the gart size */
 853         if (amdgpu_gart_size == -1) {
 854                 switch (adev->asic_type) {
 855                 case CHIP_VEGA10:  /* all engines support GPUVM */
 856                 case CHIP_VEGA12:  /* all engines support GPUVM */
 857                 case CHIP_VEGA20:
 858                 default:
 859                         adev->gmc.gart_size = 512ULL << 20;
 860                         break;
 861                 case CHIP_RAVEN:   /* DCE SG support */
 862                         adev->gmc.gart_size = 1024ULL << 20;
 863                         break;
 864                 }
 865         } else {
 866                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 867         }
 868
 869         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 870
 871         return 0;
 872 }
 873
 874 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 875 {
 876         int r;
 877
 878         if (adev->gart.bo) {
 879                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 880                 return 0;
 881         }
 882         /* Initialize common gart structure */
 883         r = amdgpu_gart_init(adev);
 884         if (r)
 885                 return r;
 886         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 887         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
 888                                  AMDGPU_PTE_EXECUTABLE;
 889         return amdgpu_gart_table_vram_alloc(adev);
 890 }
 891
 892 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 893 {
 894         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 895         unsigned size;
 896
 897         /*
 898          * TODO Remove once GART corruption is resolved
 899          * Check related code in gmc_v9_0_sw_fini
 900          * */
 901         if (gmc_v9_0_keep_stolen_memory(adev))
 902                 return 9 * 1024 * 1024;
 903
 904         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 905                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 906         } else {
 907                 u32 viewport;
 908
 909                 switch (adev->asic_type) {
 910                 case CHIP_RAVEN:
 911                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 912                         size = (REG_GET_FIELD(viewport,
 913                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 914                                 REG_GET_FIELD(viewport,
 915                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
 916                                 4);
 917                         break;
 918                 case CHIP_VEGA10:
 919                 case CHIP_VEGA12:
 920                 case CHIP_VEGA20:
 921                 default:
 922                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
 923                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 924                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 925                                 4);
 926                         break;
 927                 }
 928         }
 929         /* return 0 if the pre-OS buffer uses up most of vram */
 930         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 931                 return 0;
 932
 933         return size;
 934 }
 935
 936 static int gmc_v9_0_sw_init(void *handle)
 937 {
 938         int r;
 939         int dma_bits;
 940         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 941
 942         gfxhub_v1_0_init(adev);
 943         mmhub_v1_0_init(adev);
 944
 945         spin_lock_init(&adev->gmc.invalidate_lock);
 946
 947         adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
 948         switch (adev->asic_type) {
 949         case CHIP_RAVEN:
 950                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
 951                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 952                 } else {
 953                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
 954                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
 955                         adev->gmc.translate_further =
 956                                 adev->vm_manager.num_level > 1;
 957                 }
 958                 break;
 959         case CHIP_VEGA10:
 960         case CHIP_VEGA12:
 961         case CHIP_VEGA20:
 962                 /*
 963                  * To fulfill 4-level page support,
 964                  * vm size is 256TB (48bit), maximum size of Vega10,
 965                  * block size 512 (9bit)
 966                  */
 967                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
 968                 if (amdgpu_sriov_vf(adev))
 969                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
 970                 else
 971                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 972                 break;
 973         default:
 974                 break;
 975         }
 976
 977         /* This interrupt is VMC page fault.*/
 978         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
 979                                 &adev->gmc.vm_fault);
 980         if (r)
 981                 return r;
 982
 983         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
 984                                 &adev->gmc.vm_fault);
 985
 986         if (r)
 987                 return r;
 988
 989         /* interrupt sent to DF. */
 990         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
 991                         &adev->gmc.ecc_irq);
 992         if (r)
 993                 return r;
 994
 995         /* Set the internal MC address mask
 996          * This is the max address of the GPU's
 997          * internal address space.
 998          */
 999         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1000
1001         /* set DMA mask + need_dma32 flags.
1002          * PCIE - can handle 44-bits.
1003          * IGP - can handle 44-bits
1004          * PCI - dma32 for legacy pci gart, 44 bits on vega10
1005          */
1006         adev->need_dma32 = false;
1007         dma_bits = adev->need_dma32 ? 32 : 44;
1008         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1009         if (r) {
1010                 adev->need_dma32 = true;
1011                 dma_bits = 32;
1012                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1013         }
1014         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1015         if (r) {
1016                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1017                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
1018         }
1019         adev->need_swiotlb = drm_need_swiotlb(dma_bits);
1020
1021         if (adev->gmc.xgmi.supported) {
1022                 r = gfxhub_v1_1_get_xgmi_info(adev);
1023                 if (r)
1024                         return r;
1025         }
1026
1027         r = gmc_v9_0_mc_init(adev);
1028         if (r)
1029                 return r;
1030
1031         adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1032
1033         /* Memory manager */
1034         r = amdgpu_bo_init(adev);
1035         if (r)
1036                 return r;
1037
1038         r = gmc_v9_0_gart_init(adev);
1039         if (r)
1040                 return r;
1041
1042         /*
1043          * number of VMs
1044          * VMID 0 is reserved for System
1045          * amdgpu graphics/compute will use VMIDs 1-7
1046          * amdkfd will use VMIDs 8-15
1047          */
1048         adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1049         adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1050
1051         amdgpu_vm_manager_init(adev);
1052
1053         return 0;
1054 }
1055
1056 static int gmc_v9_0_sw_fini(void *handle)
1057 {
1058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059
1060         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
1061                         adev->gmc.ras_if) {
1062                 struct ras_common_if *ras_if = adev->gmc.ras_if;
1063                 struct ras_ih_if ih_info = {
1064                         .head = *ras_if,
1065                 };
1066
1067                 /*remove fs first*/
1068                 amdgpu_ras_debugfs_remove(adev, ras_if);
1069                 amdgpu_ras_sysfs_remove(adev, ras_if);
1070                 /*remove the IH*/
1071                 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1072                 amdgpu_ras_feature_enable(adev, ras_if, 0);
1073                 kfree(ras_if);
1074         }
1075
1076         amdgpu_gem_force_release(adev);
1077         amdgpu_vm_manager_fini(adev);
1078
1079         if (gmc_v9_0_keep_stolen_memory(adev))
1080                 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1081
1082         amdgpu_gart_table_vram_free(adev);
1083         amdgpu_bo_fini(adev);
1084         amdgpu_gart_fini(adev);
1085
1086         return 0;
1087 }
1088
1089 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1090 {
1091
1092         switch (adev->asic_type) {
1093         case CHIP_VEGA10:
1094         case CHIP_VEGA20:
1095                 soc15_program_register_sequence(adev,
1096                                                 golden_settings_mmhub_1_0_0,
1097                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1098                 soc15_program_register_sequence(adev,
1099                                                 golden_settings_athub_1_0_0,
1100                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1101                 break;
1102         case CHIP_VEGA12:
1103                 break;
1104         case CHIP_RAVEN:
1105                 soc15_program_register_sequence(adev,
1106                                                 golden_settings_athub_1_0_0,
1107                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1108                 break;
1109         default:
1110                 break;
1111         }
1112 }
1113
1114 /**
1115  * gmc_v9_0_gart_enable - gart enable
1116  *
1117  * @adev: amdgpu_device pointer
1118  */
1119 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1120 {
1121         int r;
1122         bool value;
1123         u32 tmp;
1124
1125         amdgpu_device_program_register_sequence(adev,
1126                                                 golden_settings_vega10_hdp,
1127                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
1128
1129         if (adev->gart.bo == NULL) {
1130                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1131                 return -EINVAL;
1132         }
1133         r = amdgpu_gart_table_vram_pin(adev);
1134         if (r)
1135                 return r;
1136
1137         switch (adev->asic_type) {
1138         case CHIP_RAVEN:
1139                 mmhub_v1_0_update_power_gating(adev, true);
1140                 break;
1141         default:
1142                 break;
1143         }
1144
1145         r = gfxhub_v1_0_gart_enable(adev);
1146         if (r)
1147                 return r;
1148
1149         r = mmhub_v1_0_gart_enable(adev);
1150         if (r)
1151                 return r;
1152
1153         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1154
1155         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1156         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1157
1158         /* After HDP is initialized, flush HDP.*/
1159         adev->nbio_funcs->hdp_flush(adev, NULL);
1160
1161         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1162                 value = false;
1163         else
1164                 value = true;
1165
1166         gfxhub_v1_0_set_fault_enable_default(adev, value);
1167         mmhub_v1_0_set_fault_enable_default(adev, value);
1168         gmc_v9_0_flush_gpu_tlb(adev, 0, 0);
1169
1170         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1171                  (unsigned)(adev->gmc.gart_size >> 20),
1172                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1173         adev->gart.ready = true;
1174         return 0;
1175 }
1176
1177 static int gmc_v9_0_hw_init(void *handle)
1178 {
1179         int r;
1180         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1181
1182         /* The sequence of these two function calls matters.*/
1183         gmc_v9_0_init_golden_registers(adev);
1184
1185         if (adev->mode_info.num_crtc) {
1186                 /* Lockout access through VGA aperture*/
1187                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1188
1189                 /* disable VGA render */
1190                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1191         }
1192
1193         r = gmc_v9_0_gart_enable(adev);
1194
1195         return r;
1196 }
1197
1198 /**
1199  * gmc_v9_0_gart_disable - gart disable
1200  *
1201  * @adev: amdgpu_device pointer
1202  *
1203  * This disables all VM page table.
1204  */
1205 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1206 {
1207         gfxhub_v1_0_gart_disable(adev);
1208         mmhub_v1_0_gart_disable(adev);
1209         amdgpu_gart_table_vram_unpin(adev);
1210 }
1211
1212 static int gmc_v9_0_hw_fini(void *handle)
1213 {
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215
1216         if (amdgpu_sriov_vf(adev)) {
1217                 /* full access mode, so don't touch any GMC register */
1218                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1219                 return 0;
1220         }
1221
1222         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1223         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1224         gmc_v9_0_gart_disable(adev);
1225
1226         return 0;
1227 }
1228
1229 static int gmc_v9_0_suspend(void *handle)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         return gmc_v9_0_hw_fini(adev);
1234 }
1235
1236 static int gmc_v9_0_resume(void *handle)
1237 {
1238         int r;
1239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241         r = gmc_v9_0_hw_init(adev);
1242         if (r)
1243                 return r;
1244
1245         amdgpu_vmid_reset_all(adev);
1246
1247         return 0;
1248 }
1249
1250 static bool gmc_v9_0_is_idle(void *handle)
1251 {
1252         /* MC is always ready in GMC v9.*/
1253         return true;
1254 }
1255
1256 static int gmc_v9_0_wait_for_idle(void *handle)
1257 {
1258         /* There is no need to wait for MC idle in GMC v9.*/
1259         return 0;
1260 }
1261
1262 static int gmc_v9_0_soft_reset(void *handle)
1263 {
1264         /* XXX for emulation.*/
1265         return 0;
1266 }
1267
1268 static int gmc_v9_0_set_clockgating_state(void *handle,
1269                                         enum amd_clockgating_state state)
1270 {
1271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272
1273         return mmhub_v1_0_set_clockgating(adev, state);
1274 }
1275
1276 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1277 {
1278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280         mmhub_v1_0_get_clockgating(adev, flags);
1281 }
1282
1283 static int gmc_v9_0_set_powergating_state(void *handle,
1284                                         enum amd_powergating_state state)
1285 {
1286         return 0;
1287 }
1288
1289 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1290         .name = "gmc_v9_0",
1291         .early_init = gmc_v9_0_early_init,
1292         .late_init = gmc_v9_0_late_init,
1293         .sw_init = gmc_v9_0_sw_init,
1294         .sw_fini = gmc_v9_0_sw_fini,
1295         .hw_init = gmc_v9_0_hw_init,
1296         .hw_fini = gmc_v9_0_hw_fini,
1297         .suspend = gmc_v9_0_suspend,
1298         .resume = gmc_v9_0_resume,
1299         .is_idle = gmc_v9_0_is_idle,
1300         .wait_for_idle = gmc_v9_0_wait_for_idle,
1301         .soft_reset = gmc_v9_0_soft_reset,
1302         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1303         .set_powergating_state = gmc_v9_0_set_powergating_state,
1304         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1305 };
1306
1307 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1308 {
1309         .type = AMD_IP_BLOCK_TYPE_GMC,
1310         .major = 9,
1311         .minor = 0,
1312         .rev = 0,
1313         .funcs = &gmc_v9_0_ip_funcs,
1314 };