drivers/clk/sunxi-ng/ccu_div.c

   1 /*
   2  * Copyright (C) 2016 Maxime Ripard
   3  * Maxime Ripard <[email protected]>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/io.h>
  13
  14 #include "ccu_gate.h"
  15 #include "ccu_div.h"
  16
  17 static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
  18                                         struct clk_hw *parent,
  19                                         unsigned long *parent_rate,
  20                                         unsigned long rate,
  21                                         void *data)
  22 {
  23         struct ccu_div *cd = data;
  24
  25         if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
  26                 rate *= cd->fixed_post_div;
  27
  28         rate = divider_round_rate_parent(&cd->common.hw, parent,
  29                                          rate, parent_rate,
  30                                          cd->div.table, cd->div.width,
  31                                          cd->div.flags);
  32
  33         if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
  34                 rate /= cd->fixed_post_div;
  35
  36         return rate;
  37 }
  38
  39 static void ccu_div_disable(struct clk_hw *hw)
  40 {
  41         struct ccu_div *cd = hw_to_ccu_div(hw);
  42
  43         return ccu_gate_helper_disable(&cd->common, cd->enable);
  44 }
  45
  46 static int ccu_div_enable(struct clk_hw *hw)
  47 {
  48         struct ccu_div *cd = hw_to_ccu_div(hw);
  49
  50         return ccu_gate_helper_enable(&cd->common, cd->enable);
  51 }
  52
  53 static int ccu_div_is_enabled(struct clk_hw *hw)
  54 {
  55         struct ccu_div *cd = hw_to_ccu_div(hw);
  56
  57         return ccu_gate_helper_is_enabled(&cd->common, cd->enable);
  58 }
  59
  60 static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
  61                                         unsigned long parent_rate)
  62 {
  63         struct ccu_div *cd = hw_to_ccu_div(hw);
  64         unsigned long val;
  65         u32 reg;
  66
  67         reg = readl(cd->common.base + cd->common.reg);
  68         val = reg >> cd->div.shift;
  69         val &= (1 << cd->div.width) - 1;
  70
  71         parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
  72                                                   parent_rate);
  73
  74         val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
  75                                   cd->div.flags, cd->div.width);
  76
  77         if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
  78                 val /= cd->fixed_post_div;
  79
  80         return val;
  81 }
  82
  83 static int ccu_div_determine_rate(struct clk_hw *hw,
  84                                 struct clk_rate_request *req)
  85 {
  86         struct ccu_div *cd = hw_to_ccu_div(hw);
  87
  88         return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
  89                                              req, ccu_div_round_rate, cd);
  90 }
  91
  92 static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
  93                            unsigned long parent_rate)
  94 {
  95         struct ccu_div *cd = hw_to_ccu_div(hw);
  96         unsigned long flags;
  97         unsigned long val;
  98         u32 reg;
  99
 100         parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
 101                                                   parent_rate);
 102
 103         if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
 104                 rate *= cd->fixed_post_div;
 105
 106         val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
 107                               cd->div.flags);
 108
 109         spin_lock_irqsave(cd->common.lock, flags);
 110
 111         reg = readl(cd->common.base + cd->common.reg);
 112         reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
 113
 114         writel(reg | (val << cd->div.shift),
 115                cd->common.base + cd->common.reg);
 116
 117         spin_unlock_irqrestore(cd->common.lock, flags);
 118
 119         return 0;
 120 }
 121
 122 static u8 ccu_div_get_parent(struct clk_hw *hw)
 123 {
 124         struct ccu_div *cd = hw_to_ccu_div(hw);
 125
 126         return ccu_mux_helper_get_parent(&cd->common, &cd->mux);
 127 }
 128
 129 static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
 130 {
 131         struct ccu_div *cd = hw_to_ccu_div(hw);
 132
 133         return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index);
 134 }
 135
 136 const struct clk_ops ccu_div_ops = {
 137         .disable        = ccu_div_disable,
 138         .enable         = ccu_div_enable,
 139         .is_enabled     = ccu_div_is_enabled,
 140
 141         .get_parent     = ccu_div_get_parent,
 142         .set_parent     = ccu_div_set_parent,
 143
 144         .determine_rate = ccu_div_determine_rate,
 145         .recalc_rate    = ccu_div_recalc_rate,
 146         .set_rate       = ccu_div_set_rate,
 147 };