drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_GFX_H__
  25 #define __AMDGPU_GFX_H__
  26
  27 /*
  28  * GFX stuff
  29  */
  30 #include "clearstate_defs.h"
  31 #include "amdgpu_ring.h"
  32 #include "amdgpu_rlc.h"
  33
  34 /* GFX current status */
  35 #define AMDGPU_GFX_NORMAL_MODE                  0x00000000L
  36 #define AMDGPU_GFX_SAFE_MODE                    0x00000001L
  37 #define AMDGPU_GFX_PG_DISABLED_MODE             0x00000002L
  38 #define AMDGPU_GFX_CG_DISABLED_MODE             0x00000004L
  39 #define AMDGPU_GFX_LBPW_DISABLED_MODE           0x00000008L
  40
  41 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
  42
  43 struct amdgpu_mec {
  44         struct amdgpu_bo        *hpd_eop_obj;
  45         u64                     hpd_eop_gpu_addr;
  46         struct amdgpu_bo        *mec_fw_obj;
  47         u64                     mec_fw_gpu_addr;
  48         u32 num_mec;
  49         u32 num_pipe_per_mec;
  50         u32 num_queue_per_pipe;
  51         void                    *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
  52
  53         /* These are the resources for which amdgpu takes ownership */
  54         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
  55 };
  56
  57 struct amdgpu_kiq {
  58         u64                     eop_gpu_addr;
  59         struct amdgpu_bo        *eop_obj;
  60         spinlock_t              ring_lock;
  61         struct amdgpu_ring      ring;
  62         struct amdgpu_irq_src   irq;
  63 };
  64
  65 /*
  66  * GPU scratch registers structures, functions & helpers
  67  */
  68 struct amdgpu_scratch {
  69         unsigned                num_reg;
  70         uint32_t                reg_base;
  71         uint32_t                free_mask;
  72 };
  73
  74 /*
  75  * GFX configurations
  76  */
  77 #define AMDGPU_GFX_MAX_SE 4
  78 #define AMDGPU_GFX_MAX_SH_PER_SE 2
  79
  80 struct amdgpu_rb_config {
  81         uint32_t rb_backend_disable;
  82         uint32_t user_rb_backend_disable;
  83         uint32_t raster_config;
  84         uint32_t raster_config_1;
  85 };
  86
  87 struct gb_addr_config {
  88         uint16_t pipe_interleave_size;
  89         uint8_t num_pipes;
  90         uint8_t max_compress_frags;
  91         uint8_t num_banks;
  92         uint8_t num_se;
  93         uint8_t num_rb_per_se;
  94 };
  95
  96 struct amdgpu_gfx_config {
  97         unsigned max_shader_engines;
  98         unsigned max_tile_pipes;
  99         unsigned max_cu_per_sh;
 100         unsigned max_sh_per_se;
 101         unsigned max_backends_per_se;
 102         unsigned max_texture_channel_caches;
 103         unsigned max_gprs;
 104         unsigned max_gs_threads;
 105         unsigned max_hw_contexts;
 106         unsigned sc_prim_fifo_size_frontend;
 107         unsigned sc_prim_fifo_size_backend;
 108         unsigned sc_hiz_tile_fifo_size;
 109         unsigned sc_earlyz_tile_fifo_size;
 110
 111         unsigned num_tile_pipes;
 112         unsigned backend_enable_mask;
 113         unsigned mem_max_burst_length_bytes;
 114         unsigned mem_row_size_in_kb;
 115         unsigned shader_engine_tile_size;
 116         unsigned num_gpus;
 117         unsigned multi_gpu_tile_size;
 118         unsigned mc_arb_ramcfg;
 119         unsigned gb_addr_config;
 120         unsigned num_rbs;
 121         unsigned gs_vgt_table_depth;
 122         unsigned gs_prim_buffer_depth;
 123
 124         uint32_t tile_mode_array[32];
 125         uint32_t macrotile_mode_array[16];
 126
 127         struct gb_addr_config gb_addr_config_fields;
 128         struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 129
 130         /* gfx configure feature */
 131         uint32_t double_offchip_lds_buf;
 132         /* cached value of DB_DEBUG2 */
 133         uint32_t db_debug2;
 134         /* gfx10 specific config */
 135         uint32_t num_sc_per_sh;
 136         uint32_t num_packer_per_sc;
 137 };
 138
 139 struct amdgpu_cu_info {
 140         uint32_t simd_per_cu;
 141         uint32_t max_waves_per_simd;
 142         uint32_t wave_front_size;
 143         uint32_t max_scratch_slots_per_cu;
 144         uint32_t lds_size;
 145
 146         /* total active CU number */
 147         uint32_t number;
 148         uint32_t ao_cu_mask;
 149         uint32_t ao_cu_bitmap[4][4];
 150         uint32_t bitmap[4][4];
 151 };
 152
 153 struct amdgpu_gfx_funcs {
 154         /* get the gpu clock counter */
 155         uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
 156         void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
 157                              u32 sh_num, u32 instance);
 158         void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
 159                                uint32_t wave, uint32_t *dst, int *no_fields);
 160         void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
 161                                 uint32_t wave, uint32_t thread, uint32_t start,
 162                                 uint32_t size, uint32_t *dst);
 163         void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
 164                                 uint32_t wave, uint32_t start, uint32_t size,
 165                                 uint32_t *dst);
 166         void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
 167                                  u32 queue);
 168 };
 169
 170 struct amdgpu_ngg_buf {
 171         struct amdgpu_bo        *bo;
 172         uint64_t                gpu_addr;
 173         uint32_t                size;
 174         uint32_t                bo_size;
 175 };
 176
 177 enum {
 178         NGG_PRIM = 0,
 179         NGG_POS,
 180         NGG_CNTL,
 181         NGG_PARAM,
 182         NGG_BUF_MAX
 183 };
 184
 185 struct amdgpu_ngg {
 186         struct amdgpu_ngg_buf   buf[NGG_BUF_MAX];
 187         uint32_t                gds_reserve_addr;
 188         uint32_t                gds_reserve_size;
 189         bool                    init;
 190 };
 191
 192 struct sq_work {
 193         struct work_struct      work;
 194         unsigned ih_data;
 195 };
 196
 197 struct amdgpu_gfx {
 198         struct mutex                    gpu_clock_mutex;
 199         struct amdgpu_gfx_config        config;
 200         struct amdgpu_rlc               rlc;
 201         struct amdgpu_mec               mec;
 202         struct amdgpu_kiq               kiq;
 203         struct amdgpu_scratch           scratch;
 204         const struct firmware           *me_fw; /* ME firmware */
 205         uint32_t                        me_fw_version;
 206         const struct firmware           *pfp_fw; /* PFP firmware */
 207         uint32_t                        pfp_fw_version;
 208         const struct firmware           *ce_fw; /* CE firmware */
 209         uint32_t                        ce_fw_version;
 210         const struct firmware           *rlc_fw; /* RLC firmware */
 211         uint32_t                        rlc_fw_version;
 212         const struct firmware           *mec_fw; /* MEC firmware */
 213         uint32_t                        mec_fw_version;
 214         const struct firmware           *mec2_fw; /* MEC2 firmware */
 215         uint32_t                        mec2_fw_version;
 216         uint32_t                        me_feature_version;
 217         uint32_t                        ce_feature_version;
 218         uint32_t                        pfp_feature_version;
 219         uint32_t                        rlc_feature_version;
 220         uint32_t                        rlc_srlc_fw_version;
 221         uint32_t                        rlc_srlc_feature_version;
 222         uint32_t                        rlc_srlg_fw_version;
 223         uint32_t                        rlc_srlg_feature_version;
 224         uint32_t                        rlc_srls_fw_version;
 225         uint32_t                        rlc_srls_feature_version;
 226         uint32_t                        mec_feature_version;
 227         uint32_t                        mec2_feature_version;
 228         bool                            mec_fw_write_wait;
 229         bool                            me_fw_write_wait;
 230         struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
 231         unsigned                        num_gfx_rings;
 232         struct amdgpu_ring              compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
 233         unsigned                        num_compute_rings;
 234         struct amdgpu_irq_src           eop_irq;
 235         struct amdgpu_irq_src           priv_reg_irq;
 236         struct amdgpu_irq_src           priv_inst_irq;
 237         struct amdgpu_irq_src           cp_ecc_error_irq;
 238         struct amdgpu_irq_src           sq_irq;
 239         struct sq_work                  sq_work;
 240
 241         /* gfx status */
 242         uint32_t                        gfx_current_status;
 243         /* ce ram size*/
 244         unsigned                        ce_ram_size;
 245         struct amdgpu_cu_info           cu_info;
 246         const struct amdgpu_gfx_funcs   *funcs;
 247
 248         /* reset mask */
 249         uint32_t                        grbm_soft_reset;
 250         uint32_t                        srbm_soft_reset;
 251
 252         /* NGG */
 253         struct amdgpu_ngg               ngg;
 254
 255         /* gfx off */
 256         bool                            gfx_off_state; /* true: enabled, false: disabled */
 257         struct mutex                    gfx_off_mutex;
 258         uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
 259         struct delayed_work             gfx_off_delay_work;
 260
 261         /* pipe reservation */
 262         struct mutex                    pipe_reserve_mutex;
 263         DECLARE_BITMAP                  (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 264
 265         /*ras */
 266         struct ras_common_if            *ras_if;
 267 };
 268
 269 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 270 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
 271 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
 272
 273 /**
 274  * amdgpu_gfx_create_bitmask - create a bitmask
 275  *
 276  * @bit_width: length of the mask
 277  *
 278  * create a variable length bit mask.
 279  * Returns the bitmask.
 280  */
 281 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
 282 {
 283         return (u32)((1ULL << bit_width) - 1);
 284 }
 285
 286 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
 287 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
 288
 289 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
 290                                  unsigned max_sh);
 291
 292 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 293                              struct amdgpu_ring *ring,
 294                              struct amdgpu_irq_src *irq);
 295
 296 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
 297                               struct amdgpu_irq_src *irq);
 298
 299 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
 300 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 301                         unsigned hpd_size);
 302
 303 int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
 304                                    unsigned mqd_size);
 305 void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
 306
 307 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
 308 int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
 309                             int pipe, int queue);
 310 void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
 311                              int *mec, int *pipe, int *queue);
 312 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
 313                                      int pipe, int queue);
 314 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 315
 316 #endif