drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31
  32 /* delay 0.1 second to enable gfx off feature */
  33 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  34
  35 #define GFX_OFF_NO_DELAY 0
  36
  37 /*
  38  * GPU GFX IP block helpers function.
  39  */
  40
  41 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  42                                 int pipe, int queue)
  43 {
  44         int bit = 0;
  45
  46         bit += mec * adev->gfx.mec.num_pipe_per_mec
  47                 * adev->gfx.mec.num_queue_per_pipe;
  48         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  49         bit += queue;
  50
  51         return bit;
  52 }
  53
  54 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  55                                  int *mec, int *pipe, int *queue)
  56 {
  57         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  58         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  59                 % adev->gfx.mec.num_pipe_per_mec;
  60         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  61                / adev->gfx.mec.num_pipe_per_mec;
  62
  63 }
  64
  65 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  66                                      int mec, int pipe, int queue)
  67 {
  68         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  69                         adev->gfx.mec.queue_bitmap);
  70 }
  71
  72 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  73                                int me, int pipe, int queue)
  74 {
  75         int bit = 0;
  76
  77         bit += me * adev->gfx.me.num_pipe_per_me
  78                 * adev->gfx.me.num_queue_per_pipe;
  79         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  80         bit += queue;
  81
  82         return bit;
  83 }
  84
  85 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  86                                 int *me, int *pipe, int *queue)
  87 {
  88         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  89         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  90                 % adev->gfx.me.num_pipe_per_me;
  91         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  92                 / adev->gfx.me.num_pipe_per_me;
  93 }
  94
  95 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  96                                     int me, int pipe, int queue)
  97 {
  98         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
  99                         adev->gfx.me.queue_bitmap);
 100 }
 101
 102 /**
 103  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 104  *
 105  * @mask: array in which the per-shader array disable masks will be stored
 106  * @max_se: number of SEs
 107  * @max_sh: number of SHs
 108  *
 109  * The bitmask of CUs to be disabled in the shader array determined by se and
 110  * sh is stored in mask[se * max_sh + sh].
 111  */
 112 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 113 {
 114         unsigned se, sh, cu;
 115         const char *p;
 116
 117         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 118
 119         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 120                 return;
 121
 122         p = amdgpu_disable_cu;
 123         for (;;) {
 124                 char *next;
 125                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 126                 if (ret < 3) {
 127                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 128                         return;
 129                 }
 130
 131                 if (se < max_se && sh < max_sh && cu < 16) {
 132                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 133                         mask[se * max_sh + sh] |= 1u << cu;
 134                 } else {
 135                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 136                                   se, sh, cu);
 137                 }
 138
 139                 next = strchr(p, ',');
 140                 if (!next)
 141                         break;
 142                 p = next + 1;
 143         }
 144 }
 145
 146 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 147 {
 148         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 149 }
 150
 151 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 152 {
 153         if (amdgpu_compute_multipipe != -1) {
 154                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 155                          amdgpu_compute_multipipe);
 156                 return amdgpu_compute_multipipe == 1;
 157         }
 158
 159         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 160                 return true;
 161
 162         /* FIXME: spreading the queues across pipes causes perf regressions
 163          * on POLARIS11 compute workloads */
 164         if (adev->asic_type == CHIP_POLARIS11)
 165                 return false;
 166
 167         return adev->gfx.mec.num_mec > 1;
 168 }
 169
 170 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 171                                                 struct amdgpu_ring *ring)
 172 {
 173         int queue = ring->queue;
 174         int pipe = ring->pipe;
 175
 176         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 177          * have more than one gfx pipe.
 178          */
 179         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 180             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 181                 int me = ring->me;
 182                 int bit;
 183
 184                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 185                 if (ring == &adev->gfx.gfx_ring[bit])
 186                         return true;
 187         }
 188
 189         return false;
 190 }
 191
 192 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 193                                                struct amdgpu_ring *ring)
 194 {
 195         /* Policy: use 1st queue as high priority compute queue if we
 196          * have more than one compute queue.
 197          */
 198         if (adev->gfx.num_compute_rings > 1 &&
 199             ring == &adev->gfx.compute_ring[0])
 200                 return true;
 201
 202         return false;
 203 }
 204
 205 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 206 {
 207         int i, queue, pipe;
 208         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 209         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 210                                      adev->gfx.mec.num_queue_per_pipe,
 211                                      adev->gfx.num_compute_rings);
 212
 213         if (multipipe_policy) {
 214                 /* policy: make queues evenly cross all pipes on MEC1 only */
 215                 for (i = 0; i < max_queues_per_mec; i++) {
 216                         pipe = i % adev->gfx.mec.num_pipe_per_mec;
 217                         queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 218                                 adev->gfx.mec.num_queue_per_pipe;
 219
 220                         set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 221                                         adev->gfx.mec.queue_bitmap);
 222                 }
 223         } else {
 224                 /* policy: amdgpu owns all queues in the given pipe */
 225                 for (i = 0; i < max_queues_per_mec; ++i)
 226                         set_bit(i, adev->gfx.mec.queue_bitmap);
 227         }
 228
 229         dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 230 }
 231
 232 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 233 {
 234         int i, queue, pipe;
 235         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 236         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 237                                         adev->gfx.me.num_queue_per_pipe;
 238
 239         if (multipipe_policy) {
 240                 /* policy: amdgpu owns the first queue per pipe at this stage
 241                  * will extend to mulitple queues per pipe later */
 242                 for (i = 0; i < max_queues_per_me; i++) {
 243                         pipe = i % adev->gfx.me.num_pipe_per_me;
 244                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 245                                 adev->gfx.me.num_queue_per_pipe;
 246
 247                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 248                                 adev->gfx.me.queue_bitmap);
 249                 }
 250         } else {
 251                 for (i = 0; i < max_queues_per_me; ++i)
 252                         set_bit(i, adev->gfx.me.queue_bitmap);
 253         }
 254
 255         /* update the number of active graphics rings */
 256         adev->gfx.num_gfx_rings =
 257                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 258 }
 259
 260 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 261                                   struct amdgpu_ring *ring)
 262 {
 263         int queue_bit;
 264         int mec, pipe, queue;
 265
 266         queue_bit = adev->gfx.mec.num_mec
 267                     * adev->gfx.mec.num_pipe_per_mec
 268                     * adev->gfx.mec.num_queue_per_pipe;
 269
 270         while (--queue_bit >= 0) {
 271                 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
 272                         continue;
 273
 274                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 275
 276                 /*
 277                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 278                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 279                  * only can be issued on queue 0.
 280                  */
 281                 if ((mec == 1 && pipe > 1) || queue != 0)
 282                         continue;
 283
 284                 ring->me = mec + 1;
 285                 ring->pipe = pipe;
 286                 ring->queue = queue;
 287
 288                 return 0;
 289         }
 290
 291         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 292         return -EINVAL;
 293 }
 294
 295 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 296                              struct amdgpu_ring *ring,
 297                              struct amdgpu_irq_src *irq)
 298 {
 299         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 300         int r = 0;
 301
 302         spin_lock_init(&kiq->ring_lock);
 303
 304         ring->adev = NULL;
 305         ring->ring_obj = NULL;
 306         ring->use_doorbell = true;
 307         ring->doorbell_index = adev->doorbell_index.kiq;
 308
 309         r = amdgpu_gfx_kiq_acquire(adev, ring);
 310         if (r)
 311                 return r;
 312
 313         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 314         ring->no_scheduler = true;
 315         sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 316         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 317                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 318         if (r)
 319                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 320
 321         return r;
 322 }
 323
 324 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 325 {
 326         amdgpu_ring_fini(ring);
 327 }
 328
 329 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
 330 {
 331         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 332
 333         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 334 }
 335
 336 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 337                         unsigned hpd_size)
 338 {
 339         int r;
 340         u32 *hpd;
 341         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 342
 343         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 344                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 345                                     &kiq->eop_gpu_addr, (void **)&hpd);
 346         if (r) {
 347                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 348                 return r;
 349         }
 350
 351         memset(hpd, 0, hpd_size);
 352
 353         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 354         if (unlikely(r != 0))
 355                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 356         amdgpu_bo_kunmap(kiq->eop_obj);
 357         amdgpu_bo_unreserve(kiq->eop_obj);
 358
 359         return 0;
 360 }
 361
 362 /* create MQD for each compute/gfx queue */
 363 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 364                            unsigned mqd_size)
 365 {
 366         struct amdgpu_ring *ring = NULL;
 367         int r, i;
 368
 369         /* create MQD for KIQ */
 370         ring = &adev->gfx.kiq.ring;
 371         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 372                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 373                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 374                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 375                  * KIQ MQD no matter SRIOV or Bare-metal
 376                  */
 377                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 378                                             AMDGPU_GEM_DOMAIN_VRAM |
 379                                             AMDGPU_GEM_DOMAIN_GTT,
 380                                             &ring->mqd_obj,
 381                                             &ring->mqd_gpu_addr,
 382                                             &ring->mqd_ptr);
 383                 if (r) {
 384                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 385                         return r;
 386                 }
 387
 388                 /* prepare MQD backup */
 389                 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
 390                 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
 391                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 392         }
 393
 394         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 395                 /* create MQD for each KGQ */
 396                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 397                         ring = &adev->gfx.gfx_ring[i];
 398                         if (!ring->mqd_obj) {
 399                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 400                                                             AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 401                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 402                                 if (r) {
 403                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 404                                         return r;
 405                                 }
 406
 407                                 /* prepare MQD backup */
 408                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 409                                 if (!adev->gfx.me.mqd_backup[i])
 410                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 411                         }
 412                 }
 413         }
 414
 415         /* create MQD for each KCQ */
 416         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 417                 ring = &adev->gfx.compute_ring[i];
 418                 if (!ring->mqd_obj) {
 419                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 420                                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 421                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 422                         if (r) {
 423                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 424                                 return r;
 425                         }
 426
 427                         /* prepare MQD backup */
 428                         adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 429                         if (!adev->gfx.mec.mqd_backup[i])
 430                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 431                 }
 432         }
 433
 434         return 0;
 435 }
 436
 437 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
 438 {
 439         struct amdgpu_ring *ring = NULL;
 440         int i;
 441
 442         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 443                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 444                         ring = &adev->gfx.gfx_ring[i];
 445                         kfree(adev->gfx.me.mqd_backup[i]);
 446                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 447                                               &ring->mqd_gpu_addr,
 448                                               &ring->mqd_ptr);
 449                 }
 450         }
 451
 452         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 453                 ring = &adev->gfx.compute_ring[i];
 454                 kfree(adev->gfx.mec.mqd_backup[i]);
 455                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 456                                       &ring->mqd_gpu_addr,
 457                                       &ring->mqd_ptr);
 458         }
 459
 460         ring = &adev->gfx.kiq.ring;
 461         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
 462         amdgpu_bo_free_kernel(&ring->mqd_obj,
 463                               &ring->mqd_gpu_addr,
 464                               &ring->mqd_ptr);
 465 }
 466
 467 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
 468 {
 469         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 470         struct amdgpu_ring *kiq_ring = &kiq->ring;
 471         int i, r = 0;
 472
 473         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 474                 return -EINVAL;
 475
 476         spin_lock(&adev->gfx.kiq.ring_lock);
 477         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 478                                         adev->gfx.num_compute_rings)) {
 479                 spin_unlock(&adev->gfx.kiq.ring_lock);
 480                 return -ENOMEM;
 481         }
 482
 483         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 484                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
 485                                            RESET_QUEUES, 0, 0);
 486
 487         if (adev->gfx.kiq.ring.sched.ready && !adev->job_hang)
 488                 r = amdgpu_ring_test_helper(kiq_ring);
 489         spin_unlock(&adev->gfx.kiq.ring_lock);
 490
 491         return r;
 492 }
 493
 494 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 495                                         int queue_bit)
 496 {
 497         int mec, pipe, queue;
 498         int set_resource_bit = 0;
 499
 500         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 501
 502         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 503
 504         return set_resource_bit;
 505 }
 506
 507 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
 508 {
 509         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 510         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 511         uint64_t queue_mask = 0;
 512         int r, i;
 513
 514         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 515                 return -EINVAL;
 516
 517         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 518                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
 519                         continue;
 520
 521                 /* This situation may be hit in the future if a new HW
 522                  * generation exposes more than 64 queues. If so, the
 523                  * definition of queue_mask needs updating */
 524                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 525                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 526                         break;
 527                 }
 528
 529                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 530         }
 531
 532         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 533                                                         kiq_ring->queue);
 534         spin_lock(&adev->gfx.kiq.ring_lock);
 535         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 536                                         adev->gfx.num_compute_rings +
 537                                         kiq->pmf->set_resources_size);
 538         if (r) {
 539                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 540                 spin_unlock(&adev->gfx.kiq.ring_lock);
 541                 return r;
 542         }
 543
 544         if (adev->enable_mes)
 545                 queue_mask = ~0ULL;
 546
 547         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 548         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 549                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
 550
 551         r = amdgpu_ring_test_helper(kiq_ring);
 552         spin_unlock(&adev->gfx.kiq.ring_lock);
 553         if (r)
 554                 DRM_ERROR("KCQ enable failed\n");
 555
 556         return r;
 557 }
 558
 559 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 560  *
 561  * @adev: amdgpu_device pointer
 562  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 563  *
 564  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 565  * 2. other client can send request to disable gfx off feature, the request should be honored.
 566  * 3. other client can cancel their request of disable gfx off feature
 567  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 568  */
 569
 570 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 571 {
 572         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 573
 574         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 575                 return;
 576
 577         mutex_lock(&adev->gfx.gfx_off_mutex);
 578
 579         if (enable) {
 580                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 581                  * Note that the bug may be in a different caller than the one which triggers the
 582                  * WARN_ON_ONCE.
 583                  */
 584                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 585                         goto unlock;
 586
 587                 adev->gfx.gfx_off_req_count--;
 588
 589                 if (adev->gfx.gfx_off_req_count == 0 &&
 590                     !adev->gfx.gfx_off_state) {
 591                         /* If going to s2idle, no need to wait */
 592                         if (adev->in_s0ix) {
 593                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 594                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 595                                         adev->gfx.gfx_off_state = true;
 596                         } else {
 597                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 598                                               delay);
 599                         }
 600                 }
 601         } else {
 602                 if (adev->gfx.gfx_off_req_count == 0) {
 603                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 604
 605                         if (adev->gfx.gfx_off_state &&
 606                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 607                                 adev->gfx.gfx_off_state = false;
 608
 609                                 if (adev->gfx.funcs->init_spm_golden) {
 610                                         dev_dbg(adev->dev,
 611                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 612                                         amdgpu_gfx_init_spm_golden(adev);
 613                                 }
 614                         }
 615                 }
 616
 617                 adev->gfx.gfx_off_req_count++;
 618         }
 619
 620 unlock:
 621         mutex_unlock(&adev->gfx.gfx_off_mutex);
 622 }
 623
 624 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 625 {
 626         int r = 0;
 627
 628         mutex_lock(&adev->gfx.gfx_off_mutex);
 629
 630         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 631
 632         mutex_unlock(&adev->gfx.gfx_off_mutex);
 633
 634         return r;
 635 }
 636
 637 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 638 {
 639         int r = 0;
 640
 641         mutex_lock(&adev->gfx.gfx_off_mutex);
 642
 643         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 644
 645         mutex_unlock(&adev->gfx.gfx_off_mutex);
 646
 647         return r;
 648 }
 649
 650 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 651 {
 652         int r = 0;
 653
 654         mutex_lock(&adev->gfx.gfx_off_mutex);
 655
 656         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 657
 658         mutex_unlock(&adev->gfx.gfx_off_mutex);
 659
 660         return r;
 661 }
 662
 663 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 664 {
 665
 666         int r = 0;
 667
 668         mutex_lock(&adev->gfx.gfx_off_mutex);
 669
 670         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 671
 672         mutex_unlock(&adev->gfx.gfx_off_mutex);
 673
 674         return r;
 675 }
 676
 677 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 678 {
 679         int r;
 680
 681         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 682                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 683                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 684
 685                 r = amdgpu_ras_block_late_init(adev, ras_block);
 686                 if (r)
 687                         return r;
 688
 689                 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 690                 if (r)
 691                         goto late_fini;
 692         } else {
 693                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 694         }
 695
 696         return 0;
 697 late_fini:
 698         amdgpu_ras_block_late_fini(adev, ras_block);
 699         return r;
 700 }
 701
 702 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 703 {
 704         int err = 0;
 705         struct amdgpu_gfx_ras *ras = NULL;
 706
 707         /* adev->gfx.ras is NULL, which means gfx does not
 708          * support ras function, then do nothing here.
 709          */
 710         if (!adev->gfx.ras)
 711                 return 0;
 712
 713         ras = adev->gfx.ras;
 714
 715         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 716         if (err) {
 717                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 718                 return err;
 719         }
 720
 721         strcpy(ras->ras_block.ras_comm.name, "gfx");
 722         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 723         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 724         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 725
 726         /* If not define special ras_late_init function, use gfx default ras_late_init */
 727         if (!ras->ras_block.ras_late_init)
 728                 ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
 729
 730         /* If not defined special ras_cb function, use default ras_cb */
 731         if (!ras->ras_block.ras_cb)
 732                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 733
 734         return 0;
 735 }
 736
 737 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 738                                                 struct amdgpu_iv_entry *entry)
 739 {
 740         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 741                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 742
 743         return 0;
 744 }
 745
 746 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 747                 void *err_data,
 748                 struct amdgpu_iv_entry *entry)
 749 {
 750         /* TODO ue will trigger an interrupt.
 751          *
 752          * When “Full RAS” is enabled, the per-IP interrupt sources should
 753          * be disabled and the driver should only look for the aggregated
 754          * interrupt via sync flood
 755          */
 756         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 757                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 758                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 759                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 760                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 761                 amdgpu_ras_reset_gpu(adev);
 762         }
 763         return AMDGPU_RAS_SUCCESS;
 764 }
 765
 766 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 767                                   struct amdgpu_irq_src *source,
 768                                   struct amdgpu_iv_entry *entry)
 769 {
 770         struct ras_common_if *ras_if = adev->gfx.ras_if;
 771         struct ras_dispatch_if ih_data = {
 772                 .entry = entry,
 773         };
 774
 775         if (!ras_if)
 776                 return 0;
 777
 778         ih_data.head = *ras_if;
 779
 780         DRM_ERROR("CP ECC ERROR IRQ\n");
 781         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 782         return 0;
 783 }
 784
 785 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 786 {
 787         signed long r, cnt = 0;
 788         unsigned long flags;
 789         uint32_t seq, reg_val_offs = 0, value = 0;
 790         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 791         struct amdgpu_ring *ring = &kiq->ring;
 792
 793         if (amdgpu_device_skip_hw_access(adev))
 794                 return 0;
 795
 796         if (adev->mes.ring.sched.ready)
 797                 return amdgpu_mes_rreg(adev, reg);
 798
 799         BUG_ON(!ring->funcs->emit_rreg);
 800
 801         spin_lock_irqsave(&kiq->ring_lock, flags);
 802         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 803                 pr_err("critical bug! too many kiq readers\n");
 804                 goto failed_unlock;
 805         }
 806         amdgpu_ring_alloc(ring, 32);
 807         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 808         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 809         if (r)
 810                 goto failed_undo;
 811
 812         amdgpu_ring_commit(ring);
 813         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 814
 815         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 816
 817         /* don't wait anymore for gpu reset case because this way may
 818          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 819          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 820          * never return if we keep waiting in virt_kiq_rreg, which cause
 821          * gpu_recover() hang there.
 822          *
 823          * also don't wait anymore for IRQ context
 824          * */
 825         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 826                 goto failed_kiq_read;
 827
 828         might_sleep();
 829         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 830                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 831                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 832         }
 833
 834         if (cnt > MAX_KIQ_REG_TRY)
 835                 goto failed_kiq_read;
 836
 837         mb();
 838         value = adev->wb.wb[reg_val_offs];
 839         amdgpu_device_wb_free(adev, reg_val_offs);
 840         return value;
 841
 842 failed_undo:
 843         amdgpu_ring_undo(ring);
 844 failed_unlock:
 845         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 846 failed_kiq_read:
 847         if (reg_val_offs)
 848                 amdgpu_device_wb_free(adev, reg_val_offs);
 849         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 850         return ~0;
 851 }
 852
 853 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 854 {
 855         signed long r, cnt = 0;
 856         unsigned long flags;
 857         uint32_t seq;
 858         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 859         struct amdgpu_ring *ring = &kiq->ring;
 860
 861         BUG_ON(!ring->funcs->emit_wreg);
 862
 863         if (amdgpu_device_skip_hw_access(adev))
 864                 return;
 865
 866         if (adev->mes.ring.sched.ready) {
 867                 amdgpu_mes_wreg(adev, reg, v);
 868                 return;
 869         }
 870
 871         spin_lock_irqsave(&kiq->ring_lock, flags);
 872         amdgpu_ring_alloc(ring, 32);
 873         amdgpu_ring_emit_wreg(ring, reg, v);
 874         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 875         if (r)
 876                 goto failed_undo;
 877
 878         amdgpu_ring_commit(ring);
 879         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 880
 881         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 882
 883         /* don't wait anymore for gpu reset case because this way may
 884          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 885          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 886          * never return if we keep waiting in virt_kiq_rreg, which cause
 887          * gpu_recover() hang there.
 888          *
 889          * also don't wait anymore for IRQ context
 890          * */
 891         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 892                 goto failed_kiq_write;
 893
 894         might_sleep();
 895         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 896
 897                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 898                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 899         }
 900
 901         if (cnt > MAX_KIQ_REG_TRY)
 902                 goto failed_kiq_write;
 903
 904         return;
 905
 906 failed_undo:
 907         amdgpu_ring_undo(ring);
 908         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 909 failed_kiq_write:
 910         dev_err(adev->dev, "failed to write reg:%x\n", reg);
 911 }
 912
 913 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
 914 {
 915         if (amdgpu_num_kcq == -1) {
 916                 return 8;
 917         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
 918                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
 919                 return 8;
 920         }
 921         return amdgpu_num_kcq;
 922 }
 923
 924 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
 925                                   uint32_t ucode_id)
 926 {
 927         const struct gfx_firmware_header_v1_0 *cp_hdr;
 928         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
 929         struct amdgpu_firmware_info *info = NULL;
 930         const struct firmware *ucode_fw;
 931         unsigned int fw_size;
 932
 933         switch (ucode_id) {
 934         case AMDGPU_UCODE_ID_CP_PFP:
 935                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 936                         adev->gfx.pfp_fw->data;
 937                 adev->gfx.pfp_fw_version =
 938                         le32_to_cpu(cp_hdr->header.ucode_version);
 939                 adev->gfx.pfp_feature_version =
 940                         le32_to_cpu(cp_hdr->ucode_feature_version);
 941                 ucode_fw = adev->gfx.pfp_fw;
 942                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 943                 break;
 944         case AMDGPU_UCODE_ID_CP_RS64_PFP:
 945                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 946                         adev->gfx.pfp_fw->data;
 947                 adev->gfx.pfp_fw_version =
 948                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
 949                 adev->gfx.pfp_feature_version =
 950                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
 951                 ucode_fw = adev->gfx.pfp_fw;
 952                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
 953                 break;
 954         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
 955         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
 956                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 957                         adev->gfx.pfp_fw->data;
 958                 ucode_fw = adev->gfx.pfp_fw;
 959                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
 960                 break;
 961         case AMDGPU_UCODE_ID_CP_ME:
 962                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 963                         adev->gfx.me_fw->data;
 964                 adev->gfx.me_fw_version =
 965                         le32_to_cpu(cp_hdr->header.ucode_version);
 966                 adev->gfx.me_feature_version =
 967                         le32_to_cpu(cp_hdr->ucode_feature_version);
 968                 ucode_fw = adev->gfx.me_fw;
 969                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 970                 break;
 971         case AMDGPU_UCODE_ID_CP_RS64_ME:
 972                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 973                         adev->gfx.me_fw->data;
 974                 adev->gfx.me_fw_version =
 975                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
 976                 adev->gfx.me_feature_version =
 977                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
 978                 ucode_fw = adev->gfx.me_fw;
 979                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
 980                 break;
 981         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
 982         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
 983                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 984                         adev->gfx.me_fw->data;
 985                 ucode_fw = adev->gfx.me_fw;
 986                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
 987                 break;
 988         case AMDGPU_UCODE_ID_CP_CE:
 989                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 990                         adev->gfx.ce_fw->data;
 991                 adev->gfx.ce_fw_version =
 992                         le32_to_cpu(cp_hdr->header.ucode_version);
 993                 adev->gfx.ce_feature_version =
 994                         le32_to_cpu(cp_hdr->ucode_feature_version);
 995                 ucode_fw = adev->gfx.ce_fw;
 996                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 997                 break;
 998         case AMDGPU_UCODE_ID_CP_MEC1:
 999                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1000                         adev->gfx.mec_fw->data;
1001                 adev->gfx.mec_fw_version =
1002                         le32_to_cpu(cp_hdr->header.ucode_version);
1003                 adev->gfx.mec_feature_version =
1004                         le32_to_cpu(cp_hdr->ucode_feature_version);
1005                 ucode_fw = adev->gfx.mec_fw;
1006                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1007                           le32_to_cpu(cp_hdr->jt_size) * 4;
1008                 break;
1009         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1010                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1011                         adev->gfx.mec_fw->data;
1012                 ucode_fw = adev->gfx.mec_fw;
1013                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1014                 break;
1015         case AMDGPU_UCODE_ID_CP_MEC2:
1016                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1017                         adev->gfx.mec2_fw->data;
1018                 adev->gfx.mec2_fw_version =
1019                         le32_to_cpu(cp_hdr->header.ucode_version);
1020                 adev->gfx.mec2_feature_version =
1021                         le32_to_cpu(cp_hdr->ucode_feature_version);
1022                 ucode_fw = adev->gfx.mec2_fw;
1023                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1024                           le32_to_cpu(cp_hdr->jt_size) * 4;
1025                 break;
1026         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1027                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1028                         adev->gfx.mec2_fw->data;
1029                 ucode_fw = adev->gfx.mec2_fw;
1030                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1031                 break;
1032         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1033                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1034                         adev->gfx.mec_fw->data;
1035                 adev->gfx.mec_fw_version =
1036                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1037                 adev->gfx.mec_feature_version =
1038                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1039                 ucode_fw = adev->gfx.mec_fw;
1040                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1041                 break;
1042         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1043         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1044         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1045         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1046                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1047                         adev->gfx.mec_fw->data;
1048                 ucode_fw = adev->gfx.mec_fw;
1049                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1050                 break;
1051         default:
1052                 break;
1053         }
1054
1055         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1056                 info = &adev->firmware.ucode[ucode_id];
1057                 info->ucode_id = ucode_id;
1058                 info->fw = ucode_fw;
1059                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1060         }
1061 }