drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48
  49
  50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  51 {
  52         u32 reg_val;
  53         unsigned long start;
  54         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  55         /* confirm the setting is written */
  56         start = jiffies + HZ; /* 1 sec */
  57         do {
  58                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  59         } while ((reg_val != shift_value) && time_before(jiffies, start));
  60         if (reg_val != shift_value) {
  61                 PM8001_FAIL_DBG(pm8001_ha,
  62                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
  63                         " = 0x%x\n", reg_val));
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 const void *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74         u32 *destination1;
  75         destination1 = (u32 *)destination;
  76
  77         for (index = 0; index < dw_count; index += 4, destination1++) {
  78                 offset = (soffset + index / 4);
  79                 if (offset < (64 * 1024)) {
  80                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  81                         *destination1 =  cpu_to_le32(value);
  82                 }
  83         }
  84         return;
  85 }
  86
  87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  88         struct device_attribute *attr, char *buf)
  89 {
  90         struct Scsi_Host *shost = class_to_shost(cdev);
  91         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  92         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  93         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  94         u32 accum_len , reg_val, index, *temp;
  95         unsigned long start;
  96         u8 *direct_data;
  97         char *fatal_error_data = buf;
  98
  99         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 100         if (pm8001_ha->chip_id == chip_8001) {
 101                 pm8001_ha->forensic_info.data_buf.direct_data +=
 102                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 103                         "Not supported for SPC controller");
 104                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 105                         (char *)buf;
 106         }
 107         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 108                 PM8001_IO_DBG(pm8001_ha,
 109                 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
 110                 direct_data = (u8 *)fatal_error_data;
 111                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 112                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 113                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 114
 115                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 116
 117                 /* start to get data */
 118                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 119                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 120                                 pm8001_ha->fatal_forensic_shift_offset);
 121                 pm8001_ha->forensic_last_offset = 0;
 122                 pm8001_ha->forensic_fatal_step = 0;
 123                 pm8001_ha->fatal_bar_loc = 0;
 124         }
 125
 126         /* Read until accum_len is retrived */
 127         accum_len = pm8001_mr32(fatal_table_address,
 128                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 129         PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
 130                                                 accum_len));
 131         if (accum_len == 0xFFFFFFFF) {
 132                 PM8001_IO_DBG(pm8001_ha,
 133                         pm8001_printk("Possible PCI issue 0x%x not expected\n",
 134                                 accum_len));
 135                 return -EIO;
 136         }
 137         if (accum_len == 0 || accum_len >= 0x100000) {
 138                 pm8001_ha->forensic_info.data_buf.direct_data +=
 139                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 140                                 "%08x ", 0xFFFFFFFF);
 141                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 142                         (char *)buf;
 143         }
 144         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 145         if (pm8001_ha->forensic_fatal_step == 0) {
 146 moreData:
 147                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 148                         /* Data is in bar, copy to host memory */
 149                         pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
 150                          pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 151                                 pm8001_ha->forensic_info.data_buf.direct_len ,
 152                                         1);
 153                 }
 154                 pm8001_ha->fatal_bar_loc +=
 155                         pm8001_ha->forensic_info.data_buf.direct_len;
 156                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 157                         pm8001_ha->forensic_info.data_buf.direct_len;
 158                 pm8001_ha->forensic_last_offset +=
 159                         pm8001_ha->forensic_info.data_buf.direct_len;
 160                 pm8001_ha->forensic_info.data_buf.read_len =
 161                         pm8001_ha->forensic_info.data_buf.direct_len;
 162
 163                 if (pm8001_ha->forensic_last_offset  >= accum_len) {
 164                         pm8001_ha->forensic_info.data_buf.direct_data +=
 165                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 166                                 "%08x ", 3);
 167                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 168                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 169                                         sprintf(pm8001_ha->
 170                                          forensic_info.data_buf.direct_data,
 171                                                 "%08x ", *(temp + index));
 172                         }
 173
 174                         pm8001_ha->fatal_bar_loc = 0;
 175                         pm8001_ha->forensic_fatal_step = 1;
 176                         pm8001_ha->fatal_forensic_shift_offset = 0;
 177                         pm8001_ha->forensic_last_offset = 0;
 178                         return (char *)pm8001_ha->
 179                                 forensic_info.data_buf.direct_data -
 180                                 (char *)buf;
 181                 }
 182                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 183                         pm8001_ha->forensic_info.data_buf.direct_data +=
 184                                 sprintf(pm8001_ha->
 185                                         forensic_info.data_buf.direct_data,
 186                                         "%08x ", 2);
 187                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 188                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 189                                         sprintf(pm8001_ha->
 190                                         forensic_info.data_buf.direct_data,
 191                                         "%08x ", *(temp + index));
 192                         }
 193                         return (char *)pm8001_ha->
 194                                 forensic_info.data_buf.direct_data -
 195                                 (char *)buf;
 196                 }
 197
 198                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 199                 pm8001_ha->forensic_info.data_buf.direct_data +=
 200                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 201                                 "%08x ", 2);
 202                 for (index = 0; index < 256; index++) {
 203                         pm8001_ha->forensic_info.data_buf.direct_data +=
 204                                 sprintf(pm8001_ha->
 205                                         forensic_info.data_buf.direct_data,
 206                                                 "%08x ", *(temp + index));
 207                 }
 208                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 209                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 210                         pm8001_ha->fatal_forensic_shift_offset);
 211                 pm8001_ha->fatal_bar_loc = 0;
 212                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 213                         (char *)buf;
 214         }
 215         if (pm8001_ha->forensic_fatal_step == 1) {
 216                 pm8001_ha->fatal_forensic_shift_offset = 0;
 217                 /* Read 64K of the debug data. */
 218                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 219                         pm8001_ha->fatal_forensic_shift_offset);
 220                 pm8001_mw32(fatal_table_address,
 221                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 222                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 223
 224                 /* Poll FDDHSHK  until clear  */
 225                 start = jiffies + (2 * HZ); /* 2 sec */
 226
 227                 do {
 228                         reg_val = pm8001_mr32(fatal_table_address,
 229                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 230                 } while ((reg_val) && time_before(jiffies, start));
 231
 232                 if (reg_val != 0) {
 233                         PM8001_FAIL_DBG(pm8001_ha,
 234                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
 235                         " = 0x%x\n", reg_val));
 236                         return -EIO;
 237                 }
 238
 239                 /* Read the next 64K of the debug data. */
 240                 pm8001_ha->forensic_fatal_step = 0;
 241                 if (pm8001_mr32(fatal_table_address,
 242                         MPI_FATAL_EDUMP_TABLE_STATUS) !=
 243                                 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 244                         pm8001_mw32(fatal_table_address,
 245                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
 246                         goto moreData;
 247                 } else {
 248                         pm8001_ha->forensic_info.data_buf.direct_data +=
 249                                 sprintf(pm8001_ha->
 250                                         forensic_info.data_buf.direct_data,
 251                                                 "%08x ", 4);
 252                         pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
 253                         pm8001_ha->forensic_info.data_buf.direct_len =  0;
 254                         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 255                         pm8001_ha->forensic_info.data_buf.read_len = 0;
 256                 }
 257         }
 258
 259         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 260                 (char *)buf;
 261 }
 262
 263 /**
 264  * read_main_config_table - read the configure table and save it.
 265  * @pm8001_ha: our hba card information
 266  */
 267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 268 {
 269         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 270
 271         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 272                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 273         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 274                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 275         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 276                 pm8001_mr32(address, MAIN_FW_REVISION);
 277         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 278                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 279         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 280                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 281         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 282                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 283         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 284                 pm8001_mr32(address, MAIN_GST_OFFSET);
 285         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 286                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 287         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 288                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 289
 290         /* read Error Dump Offset and Length */
 291         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 292                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 293         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 294                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 295         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 296                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 297         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 298                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 299
 300         /* read GPIO LED settings from the configuration table */
 301         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 302                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 303
 304         /* read analog Setting offset from the configuration table */
 305         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 306                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 307
 308         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 309                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 310         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 311                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 312         /* read port recover and reset timeout */
 313         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
 314                 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
 315         /* read ILA and inactive firmware version */
 316         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
 317                 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
 318         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
 319                 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
 320 }
 321
 322 /**
 323  * read_general_status_table - read the general status table and save it.
 324  * @pm8001_ha: our hba card information
 325  */
 326 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 327 {
 328         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 329         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 330                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 331         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 332                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 333         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 334                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 335         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 336                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 337         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 338                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 339         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 340                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 341         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 342                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 343         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 344                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 345         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 346                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 347         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 348                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 349         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 350                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 351         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 352                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 353         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 354                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 355         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 356                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 357 }
 358 /**
 359  * read_phy_attr_table - read the phy attribute table and save it.
 360  * @pm8001_ha: our hba card information
 361  */
 362 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 363 {
 364         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 365         pm8001_ha->phy_attr_table.phystart1_16[0] =
 366                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 367         pm8001_ha->phy_attr_table.phystart1_16[1] =
 368                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 369         pm8001_ha->phy_attr_table.phystart1_16[2] =
 370                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 371         pm8001_ha->phy_attr_table.phystart1_16[3] =
 372                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 373         pm8001_ha->phy_attr_table.phystart1_16[4] =
 374                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 375         pm8001_ha->phy_attr_table.phystart1_16[5] =
 376                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 377         pm8001_ha->phy_attr_table.phystart1_16[6] =
 378                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 379         pm8001_ha->phy_attr_table.phystart1_16[7] =
 380                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 381         pm8001_ha->phy_attr_table.phystart1_16[8] =
 382                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 383         pm8001_ha->phy_attr_table.phystart1_16[9] =
 384                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 385         pm8001_ha->phy_attr_table.phystart1_16[10] =
 386                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 387         pm8001_ha->phy_attr_table.phystart1_16[11] =
 388                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 389         pm8001_ha->phy_attr_table.phystart1_16[12] =
 390                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 391         pm8001_ha->phy_attr_table.phystart1_16[13] =
 392                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 393         pm8001_ha->phy_attr_table.phystart1_16[14] =
 394                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 395         pm8001_ha->phy_attr_table.phystart1_16[15] =
 396                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 397
 398         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 399                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 400         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 401                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 402         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 403                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 404         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 405                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 406         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 407                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 408         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 409                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 410         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 411                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 412         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 413                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 414         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 415                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 416         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 417                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 418         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 419                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 420         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 421                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 422         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 423                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 424         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 425                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 426         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 427                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 428         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 429                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 430
 431 }
 432
 433 /**
 434  * read_inbnd_queue_table - read the inbound queue table and save it.
 435  * @pm8001_ha: our hba card information
 436  */
 437 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 438 {
 439         int i;
 440         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 441         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 442                 u32 offset = i * 0x20;
 443                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 444                         get_pci_bar_index(pm8001_mr32(address,
 445                                 (offset + IB_PIPCI_BAR)));
 446                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 447                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 448         }
 449 }
 450
 451 /**
 452  * read_outbnd_queue_table - read the outbound queue table and save it.
 453  * @pm8001_ha: our hba card information
 454  */
 455 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 456 {
 457         int i;
 458         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 459         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 460                 u32 offset = i * 0x24;
 461                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 462                         get_pci_bar_index(pm8001_mr32(address,
 463                                 (offset + OB_CIPCI_BAR)));
 464                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 465                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 466         }
 467 }
 468
 469 /**
 470  * init_default_table_values - init the default table.
 471  * @pm8001_ha: our hba card information
 472  */
 473 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 474 {
 475         int i;
 476         u32 offsetib, offsetob;
 477         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 478         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 479
 480         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 481                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 482         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 483                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 484         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 485                                                         PM8001_EVENT_LOG_SIZE;
 486         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 487         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 488                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 489         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 490                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 491         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 492                                                         PM8001_EVENT_LOG_SIZE;
 493         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 494         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 495
 496         /* Disable end to end CRC checking */
 497         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 498
 499         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 500                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 501                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 502                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 503                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 504                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 505                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 506                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 507                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 508                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 509                         pm8001_ha->memoryMap.region[IB + i].total_len;
 510                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 511                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 512                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 513                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 514                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 515                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 516                 offsetib = i * 0x20;
 517                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 518                         get_pci_bar_index(pm8001_mr32(addressib,
 519                                 (offsetib + 0x14)));
 520                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 521                         pm8001_mr32(addressib, (offsetib + 0x18));
 522                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 523                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 524         }
 525         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 526                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 527                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 528                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 529                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 530                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 531                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 532                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 533                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 534                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 535                         pm8001_ha->memoryMap.region[OB + i].total_len;
 536                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 537                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 538                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 539                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 540                 /* interrupt vector based on oq */
 541                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 542                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 543                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 544                 offsetob = i * 0x24;
 545                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 546                         get_pci_bar_index(pm8001_mr32(addressob,
 547                         offsetob + 0x14));
 548                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 549                         pm8001_mr32(addressob, (offsetob + 0x18));
 550                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 551                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 552         }
 553 }
 554
 555 /**
 556  * update_main_config_table - update the main default table to the HBA.
 557  * @pm8001_ha: our hba card information
 558  */
 559 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 560 {
 561         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 562         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 563                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 564         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 565                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 566         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 567                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 568         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 569                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 570         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 571                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 572         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 573                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 574         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 575                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 576         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 577                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 578         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 579                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 580         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 581                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 582         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 583                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 584
 585         /* SPCv specific */
 586         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 587         /* Set GPIOLED to 0x2 for LED indicator */
 588         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 589         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 590                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 591
 592         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 593                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 594         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 595                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 596
 597         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
 598         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 599                                                         PORT_RECOVERY_TIMEOUT;
 600         if (pm8001_ha->chip_id == chip_8006) {
 601                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
 602                                         0x0000ffff;
 603                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 604                                         0x140000;
 605         }
 606         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 607                         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 608 }
 609
 610 /**
 611  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 612  * @pm8001_ha: our hba card information
 613  */
 614 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 615                                          int number)
 616 {
 617         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 618         u16 offset = number * 0x20;
 619         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 620                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 621         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 622                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 623         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 624                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 625         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 626                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 627         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 628                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 629 }
 630
 631 /**
 632  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 633  * @pm8001_ha: our hba card information
 634  */
 635 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 636                                                  int number)
 637 {
 638         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 639         u16 offset = number * 0x24;
 640         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 641                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 642         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 643                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 644         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 645                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 646         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 647                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 648         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 649                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 650         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 651                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 652 }
 653
 654 /**
 655  * mpi_init_check - check firmware initialization status.
 656  * @pm8001_ha: our hba card information
 657  */
 658 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 659 {
 660         u32 max_wait_count;
 661         u32 value;
 662         u32 gst_len_mpistate;
 663
 664         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 665         table is updated */
 666         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 667         /* wait until Inbound DoorBell Clear Register toggled */
 668         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 669                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
 670         } else {
 671                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 672         }
 673         do {
 674                 udelay(1);
 675                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 676                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
 677         } while ((value != 0) && (--max_wait_count));
 678
 679         if (!max_wait_count)
 680                 return -1;
 681         /* check the MPI-State for initialization upto 100ms*/
 682         max_wait_count = 100 * 1000;/* 100 msec */
 683         do {
 684                 udelay(1);
 685                 gst_len_mpistate =
 686                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 687                                         GST_GSTLEN_MPIS_OFFSET);
 688         } while ((GST_MPI_STATE_INIT !=
 689                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
 690         if (!max_wait_count)
 691                 return -1;
 692
 693         /* check MPI Initialization error */
 694         gst_len_mpistate = gst_len_mpistate >> 16;
 695         if (0x0000 != gst_len_mpistate)
 696                 return -1;
 697
 698         return 0;
 699 }
 700
 701 /**
 702  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 703  * @pm8001_ha: our hba card information
 704  */
 705 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 706 {
 707         u32 value;
 708         u32 max_wait_count;
 709         u32 max_wait_time;
 710         int ret = 0;
 711
 712         /* reset / PCIe ready */
 713         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
 714         do {
 715                 udelay(1);
 716                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 717         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
 718
 719         /* check ila status */
 720         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
 721         do {
 722                 udelay(1);
 723                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 724         } while (((value & SCRATCH_PAD_ILA_READY) !=
 725                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
 726         if (!max_wait_count)
 727                 ret = -1;
 728         else {
 729                 PM8001_MSG_DBG(pm8001_ha,
 730                         pm8001_printk(" ila ready status in %d millisec\n",
 731                                 (max_wait_time - max_wait_count)));
 732         }
 733
 734         /* check RAAE status */
 735         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
 736         do {
 737                 udelay(1);
 738                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 739         } while (((value & SCRATCH_PAD_RAAE_READY) !=
 740                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
 741         if (!max_wait_count)
 742                 ret = -1;
 743         else {
 744                 PM8001_MSG_DBG(pm8001_ha,
 745                         pm8001_printk(" raae ready status in %d millisec\n",
 746                                         (max_wait_time - max_wait_count)));
 747         }
 748
 749         /* check iop0 status */
 750         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
 751         do {
 752                 udelay(1);
 753                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 754         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
 755                         (--max_wait_count));
 756         if (!max_wait_count)
 757                 ret = -1;
 758         else {
 759                 PM8001_MSG_DBG(pm8001_ha,
 760                         pm8001_printk(" iop0 ready status in %d millisec\n",
 761                                 (max_wait_time - max_wait_count)));
 762         }
 763
 764         /* check iop1 status only for 16 port controllers */
 765         if ((pm8001_ha->chip_id != chip_8008) &&
 766                         (pm8001_ha->chip_id != chip_8009)) {
 767                 /* 200 milli sec */
 768                 max_wait_time = max_wait_count = 200 * 1000;
 769                 do {
 770                         udelay(1);
 771                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 772                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
 773                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
 774                 if (!max_wait_count)
 775                         ret = -1;
 776                 else {
 777                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
 778                                 "iop1 ready status in %d millisec\n",
 779                                 (max_wait_time - max_wait_count)));
 780                 }
 781         }
 782
 783         return ret;
 784 }
 785
 786 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 787 {
 788         void __iomem *base_addr;
 789         u32     value;
 790         u32     offset;
 791         u32     pcibar;
 792         u32     pcilogic;
 793
 794         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 795         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
 796
 797         PM8001_INIT_DBG(pm8001_ha,
 798                 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
 799                                 offset, value));
 800         pcilogic = (value & 0xFC000000) >> 26;
 801         pcibar = get_pci_bar_index(pcilogic);
 802         PM8001_INIT_DBG(pm8001_ha,
 803                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 804         pm8001_ha->main_cfg_tbl_addr = base_addr =
 805                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 806         pm8001_ha->general_stat_tbl_addr =
 807                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
 808                                         0xFFFFFF);
 809         pm8001_ha->inbnd_q_tbl_addr =
 810                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
 811                                         0xFFFFFF);
 812         pm8001_ha->outbnd_q_tbl_addr =
 813                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
 814                                         0xFFFFFF);
 815         pm8001_ha->ivt_tbl_addr =
 816                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
 817                                         0xFFFFFF);
 818         pm8001_ha->pspa_q_tbl_addr =
 819                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
 820                                         0xFFFFFF);
 821         pm8001_ha->fatal_tbl_addr =
 822                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
 823                                         0xFFFFFF);
 824
 825         PM8001_INIT_DBG(pm8001_ha,
 826                         pm8001_printk("GST OFFSET 0x%x\n",
 827                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
 828         PM8001_INIT_DBG(pm8001_ha,
 829                         pm8001_printk("INBND OFFSET 0x%x\n",
 830                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
 831         PM8001_INIT_DBG(pm8001_ha,
 832                         pm8001_printk("OBND OFFSET 0x%x\n",
 833                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
 834         PM8001_INIT_DBG(pm8001_ha,
 835                         pm8001_printk("IVT OFFSET 0x%x\n",
 836                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
 837         PM8001_INIT_DBG(pm8001_ha,
 838                         pm8001_printk("PSPA OFFSET 0x%x\n",
 839                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
 840         PM8001_INIT_DBG(pm8001_ha,
 841                         pm8001_printk("addr - main cfg %p general status %p\n",
 842                         pm8001_ha->main_cfg_tbl_addr,
 843                         pm8001_ha->general_stat_tbl_addr));
 844         PM8001_INIT_DBG(pm8001_ha,
 845                         pm8001_printk("addr - inbnd %p obnd %p\n",
 846                         pm8001_ha->inbnd_q_tbl_addr,
 847                         pm8001_ha->outbnd_q_tbl_addr));
 848         PM8001_INIT_DBG(pm8001_ha,
 849                         pm8001_printk("addr - pspa %p ivt %p\n",
 850                         pm8001_ha->pspa_q_tbl_addr,
 851                         pm8001_ha->ivt_tbl_addr));
 852 }
 853
 854 /**
 855  * pm80xx_set_thermal_config - support the thermal configuration
 856  * @pm8001_ha: our hba card information.
 857  */
 858 int
 859 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
 860 {
 861         struct set_ctrl_cfg_req payload;
 862         struct inbound_queue_table *circularQ;
 863         int rc;
 864         u32 tag;
 865         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 866         u32 page_code;
 867
 868         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 869         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 870         if (rc)
 871                 return -1;
 872
 873         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 874         payload.tag = cpu_to_le32(tag);
 875
 876         if (IS_SPCV_12G(pm8001_ha->pdev))
 877                 page_code = THERMAL_PAGE_CODE_7H;
 878         else
 879                 page_code = THERMAL_PAGE_CODE_8H;
 880
 881         payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
 882                                 (THERMAL_ENABLE << 8) | page_code;
 883         payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
 884
 885         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 886         if (rc)
 887                 pm8001_tag_free(pm8001_ha, tag);
 888         return rc;
 889
 890 }
 891
 892 /**
 893 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
 894 * Timer configuration page
 895 * @pm8001_ha: our hba card information.
 896 */
 897 static int
 898 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
 899 {
 900         struct set_ctrl_cfg_req payload;
 901         struct inbound_queue_table *circularQ;
 902         SASProtocolTimerConfig_t SASConfigPage;
 903         int rc;
 904         u32 tag;
 905         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 906
 907         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 908         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
 909
 910         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 911
 912         if (rc)
 913                 return -1;
 914
 915         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 916         payload.tag = cpu_to_le32(tag);
 917
 918         SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
 919         SASConfigPage.MST_MSI         =  3 << 15;
 920         SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
 921         SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
 922                                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
 923         SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;
 924
 925         if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
 926                 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
 927
 928
 929         SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
 930                                                 SAS_OPNRJT_RTRY_INTVL;
 931         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
 932                                                 | SAS_COPNRJT_RTRY_TMO;
 933         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
 934                                                 | SAS_COPNRJT_RTRY_THR;
 935         SASConfigPage.MAX_AIP =  SAS_MAX_AIP;
 936
 937         PM8001_INIT_DBG(pm8001_ha,
 938                         pm8001_printk("SASConfigPage.pageCode "
 939                         "0x%08x\n", SASConfigPage.pageCode));
 940         PM8001_INIT_DBG(pm8001_ha,
 941                         pm8001_printk("SASConfigPage.MST_MSI "
 942                         " 0x%08x\n", SASConfigPage.MST_MSI));
 943         PM8001_INIT_DBG(pm8001_ha,
 944                         pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
 945                         " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
 946         PM8001_INIT_DBG(pm8001_ha,
 947                         pm8001_printk("SASConfigPage.STP_FRM_TMO "
 948                         " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
 949         PM8001_INIT_DBG(pm8001_ha,
 950                         pm8001_printk("SASConfigPage.STP_IDLE_TMO "
 951                         " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
 952         PM8001_INIT_DBG(pm8001_ha,
 953                         pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
 954                         " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
 955         PM8001_INIT_DBG(pm8001_ha,
 956                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
 957                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
 958         PM8001_INIT_DBG(pm8001_ha,
 959                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
 960                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
 961         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
 962                         " 0x%08x\n", SASConfigPage.MAX_AIP));
 963
 964         memcpy(&payload.cfg_pg, &SASConfigPage,
 965                          sizeof(SASProtocolTimerConfig_t));
 966
 967         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 968         if (rc)
 969                 pm8001_tag_free(pm8001_ha, tag);
 970
 971         return rc;
 972 }
 973
 974 /**
 975  * pm80xx_get_encrypt_info - Check for encryption
 976  * @pm8001_ha: our hba card information.
 977  */
 978 static int
 979 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
 980 {
 981         u32 scratch3_value;
 982         int ret = -1;
 983
 984         /* Read encryption status from SCRATCH PAD 3 */
 985         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 986
 987         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 988                                         SCRATCH_PAD3_ENC_READY) {
 989                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 990                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 991                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 992                                                 SCRATCH_PAD3_SMF_ENABLED)
 993                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 994                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 995                                                 SCRATCH_PAD3_SMA_ENABLED)
 996                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 997                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 998                                                 SCRATCH_PAD3_SMB_ENABLED)
 999                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1000                 pm8001_ha->encrypt_info.status = 0;
1001                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1002                         "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1003                         "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1004                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1005                         pm8001_ha->encrypt_info.sec_mode,
1006                         pm8001_ha->encrypt_info.status));
1007                 ret = 0;
1008         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1009                                         SCRATCH_PAD3_ENC_DISABLED) {
1010                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1011                         "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1012                         scratch3_value));
1013                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1014                 pm8001_ha->encrypt_info.cipher_mode = 0;
1015                 pm8001_ha->encrypt_info.sec_mode = 0;
1016                 ret = 0;
1017         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1018                                 SCRATCH_PAD3_ENC_DIS_ERR) {
1019                 pm8001_ha->encrypt_info.status =
1020                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1021                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1022                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1023                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1024                                         SCRATCH_PAD3_SMF_ENABLED)
1025                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1026                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1027                                         SCRATCH_PAD3_SMA_ENABLED)
1028                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1029                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1030                                         SCRATCH_PAD3_SMB_ENABLED)
1031                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1032                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1033                         "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1034                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1035                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1036                         pm8001_ha->encrypt_info.sec_mode,
1037                         pm8001_ha->encrypt_info.status));
1038         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1039                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1040
1041                 pm8001_ha->encrypt_info.status =
1042                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1043                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1044                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1045                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1046                                         SCRATCH_PAD3_SMF_ENABLED)
1047                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1048                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1049                                         SCRATCH_PAD3_SMA_ENABLED)
1050                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1051                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1052                                         SCRATCH_PAD3_SMB_ENABLED)
1053                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1054
1055                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1056                         "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1057                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1058                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1059                         pm8001_ha->encrypt_info.sec_mode,
1060                         pm8001_ha->encrypt_info.status));
1061         }
1062         return ret;
1063 }
1064
1065 /**
1066  * pm80xx_encrypt_update - update flash with encryption informtion
1067  * @pm8001_ha: our hba card information.
1068  */
1069 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1070 {
1071         struct kek_mgmt_req payload;
1072         struct inbound_queue_table *circularQ;
1073         int rc;
1074         u32 tag;
1075         u32 opc = OPC_INB_KEK_MANAGEMENT;
1076
1077         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1078         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1079         if (rc)
1080                 return -1;
1081
1082         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1083         payload.tag = cpu_to_le32(tag);
1084         /* Currently only one key is used. New KEK index is 1.
1085          * Current KEK index is 1. Store KEK to NVRAM is 1.
1086          */
1087         payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1088                                         KEK_MGMT_SUBOP_KEYCARDUPDATE);
1089
1090         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1091         if (rc)
1092                 pm8001_tag_free(pm8001_ha, tag);
1093
1094         return rc;
1095 }
1096
1097 /**
1098  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1099  * @pm8001_ha: our hba card information
1100  */
1101 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1102 {
1103         int ret;
1104         u8 i = 0;
1105
1106         /* check the firmware status */
1107         if (-1 == check_fw_ready(pm8001_ha)) {
1108                 PM8001_FAIL_DBG(pm8001_ha,
1109                         pm8001_printk("Firmware is not ready!\n"));
1110                 return -EBUSY;
1111         }
1112
1113         /* Initialize pci space address eg: mpi offset */
1114         init_pci_device_addresses(pm8001_ha);
1115         init_default_table_values(pm8001_ha);
1116         read_main_config_table(pm8001_ha);
1117         read_general_status_table(pm8001_ha);
1118         read_inbnd_queue_table(pm8001_ha);
1119         read_outbnd_queue_table(pm8001_ha);
1120         read_phy_attr_table(pm8001_ha);
1121
1122         /* update main config table ,inbound table and outbound table */
1123         update_main_config_table(pm8001_ha);
1124         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1125                 update_inbnd_queue_table(pm8001_ha, i);
1126         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1127                 update_outbnd_queue_table(pm8001_ha, i);
1128
1129         /* notify firmware update finished and check initialization status */
1130         if (0 == mpi_init_check(pm8001_ha)) {
1131                 PM8001_INIT_DBG(pm8001_ha,
1132                         pm8001_printk("MPI initialize successful!\n"));
1133         } else
1134                 return -EBUSY;
1135
1136         /* send SAS protocol timer configuration page to FW */
1137         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1138
1139         /* Check for encryption */
1140         if (pm8001_ha->chip->encrypt) {
1141                 PM8001_INIT_DBG(pm8001_ha,
1142                         pm8001_printk("Checking for encryption\n"));
1143                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1144                 if (ret == -1) {
1145                         PM8001_INIT_DBG(pm8001_ha,
1146                                 pm8001_printk("Encryption error !!\n"));
1147                         if (pm8001_ha->encrypt_info.status == 0x81) {
1148                                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1149                                         "Encryption enabled with error."
1150                                         "Saving encryption key to flash\n"));
1151                                 pm80xx_encrypt_update(pm8001_ha);
1152                         }
1153                 }
1154         }
1155         return 0;
1156 }
1157
1158 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1159 {
1160         u32 max_wait_count;
1161         u32 value;
1162         u32 gst_len_mpistate;
1163         init_pci_device_addresses(pm8001_ha);
1164         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1165         table is stop */
1166         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1167
1168         /* wait until Inbound DoorBell Clear Register toggled */
1169         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1170                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1171         } else {
1172                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1173         }
1174         do {
1175                 udelay(1);
1176                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1177                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1178         } while ((value != 0) && (--max_wait_count));
1179
1180         if (!max_wait_count) {
1181                 PM8001_FAIL_DBG(pm8001_ha,
1182                         pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1183                 return -1;
1184         }
1185
1186         /* check the MPI-State for termination in progress */
1187         /* wait until Inbound DoorBell Clear Register toggled */
1188         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
1189         do {
1190                 udelay(1);
1191                 gst_len_mpistate =
1192                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1193                         GST_GSTLEN_MPIS_OFFSET);
1194                 if (GST_MPI_STATE_UNINIT ==
1195                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1196                         break;
1197         } while (--max_wait_count);
1198         if (!max_wait_count) {
1199                 PM8001_FAIL_DBG(pm8001_ha,
1200                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1201                                 gst_len_mpistate & GST_MPI_STATE_MASK));
1202                 return -1;
1203         }
1204
1205         return 0;
1206 }
1207
1208 /**
1209  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1210  * the FW register status to the originated status.
1211  * @pm8001_ha: our hba card information
1212  */
1213
1214 static int
1215 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1216 {
1217         u32 regval;
1218         u32 bootloader_state;
1219         u32 ibutton0, ibutton1;
1220
1221         /* Check if MPI is in ready state to reset */
1222         if (mpi_uninit_check(pm8001_ha) != 0) {
1223                 PM8001_FAIL_DBG(pm8001_ha,
1224                         pm8001_printk("MPI state is not ready\n"));
1225                 return -1;
1226         }
1227
1228         /* checked for reset register normal state; 0x0 */
1229         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1230         PM8001_INIT_DBG(pm8001_ha,
1231                 pm8001_printk("reset register before write : 0x%x\n", regval));
1232
1233         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1234         mdelay(500);
1235
1236         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1237         PM8001_INIT_DBG(pm8001_ha,
1238         pm8001_printk("reset register after write 0x%x\n", regval));
1239
1240         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1241                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1242                 PM8001_MSG_DBG(pm8001_ha,
1243                         pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1244                                         regval));
1245         } else {
1246                 PM8001_MSG_DBG(pm8001_ha,
1247                         pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1248                                         regval));
1249
1250                 /* check bootloader is successfully executed or in HDA mode */
1251                 bootloader_state =
1252                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1253                         SCRATCH_PAD1_BOOTSTATE_MASK;
1254
1255                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1256                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1257                                 "Bootloader state - HDA mode SEEPROM\n"));
1258                 } else if (bootloader_state ==
1259                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1260                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1261                                 "Bootloader state - HDA mode Bootstrap Pin\n"));
1262                 } else if (bootloader_state ==
1263                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1264                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1265                                 "Bootloader state - HDA mode soft reset\n"));
1266                 } else if (bootloader_state ==
1267                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1268                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1269                                 "Bootloader state-HDA mode critical error\n"));
1270                 }
1271                 return -EBUSY;
1272         }
1273
1274         /* check the firmware status after reset */
1275         if (-1 == check_fw_ready(pm8001_ha)) {
1276                 PM8001_FAIL_DBG(pm8001_ha,
1277                         pm8001_printk("Firmware is not ready!\n"));
1278                 /* check iButton feature support for motherboard controller */
1279                 if (pm8001_ha->pdev->subsystem_vendor !=
1280                         PCI_VENDOR_ID_ADAPTEC2 &&
1281                         pm8001_ha->pdev->subsystem_vendor !=
1282                         PCI_VENDOR_ID_ATTO &&
1283                         pm8001_ha->pdev->subsystem_vendor != 0) {
1284                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1285                                         MSGU_HOST_SCRATCH_PAD_6);
1286                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1287                                         MSGU_HOST_SCRATCH_PAD_7);
1288                         if (!ibutton0 && !ibutton1) {
1289                                 PM8001_FAIL_DBG(pm8001_ha,
1290                                         pm8001_printk("iButton Feature is"
1291                                         " not Available!!!\n"));
1292                                 return -EBUSY;
1293                         }
1294                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1295                                 PM8001_FAIL_DBG(pm8001_ha,
1296                                         pm8001_printk("CRC Check for iButton"
1297                                         " Feature Failed!!!\n"));
1298                                 return -EBUSY;
1299                         }
1300                 }
1301         }
1302         PM8001_INIT_DBG(pm8001_ha,
1303                 pm8001_printk("SPCv soft reset Complete\n"));
1304         return 0;
1305 }
1306
1307 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1308 {
1309          u32 i;
1310
1311         PM8001_INIT_DBG(pm8001_ha,
1312                 pm8001_printk("chip reset start\n"));
1313
1314         /* do SPCv chip reset. */
1315         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1316         PM8001_INIT_DBG(pm8001_ha,
1317                 pm8001_printk("SPC soft reset Complete\n"));
1318
1319         /* Check this ..whether delay is required or no */
1320         /* delay 10 usec */
1321         udelay(10);
1322
1323         /* wait for 20 msec until the firmware gets reloaded */
1324         i = 20;
1325         do {
1326                 mdelay(1);
1327         } while ((--i) != 0);
1328
1329         PM8001_INIT_DBG(pm8001_ha,
1330                 pm8001_printk("chip reset finished\n"));
1331 }
1332
1333 /**
1334  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1335  * @pm8001_ha: our hba card information
1336  */
1337 static void
1338 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1339 {
1340         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1341         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1342 }
1343
1344 /**
1345  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1346  * @pm8001_ha: our hba card information
1347  */
1348 static void
1349 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1350 {
1351         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1352 }
1353
1354 /**
1355  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1356  * @pm8001_ha: our hba card information
1357  */
1358 static void
1359 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1360 {
1361 #ifdef PM8001_USE_MSIX
1362         u32 mask;
1363         mask = (u32)(1 << vec);
1364
1365         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1366         return;
1367 #endif
1368         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1369
1370 }
1371
1372 /**
1373  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1374  * @pm8001_ha: our hba card information
1375  */
1376 static void
1377 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1378 {
1379 #ifdef PM8001_USE_MSIX
1380         u32 mask;
1381         if (vec == 0xFF)
1382                 mask = 0xFFFFFFFF;
1383         else
1384                 mask = (u32)(1 << vec);
1385         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1386         return;
1387 #endif
1388         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1389 }
1390
1391 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1392                 struct pm8001_device *pm8001_ha_dev)
1393 {
1394         int res;
1395         u32 ccb_tag;
1396         struct pm8001_ccb_info *ccb;
1397         struct sas_task *task = NULL;
1398         struct task_abort_req task_abort;
1399         struct inbound_queue_table *circularQ;
1400         u32 opc = OPC_INB_SATA_ABORT;
1401         int ret;
1402
1403         if (!pm8001_ha_dev) {
1404                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1405                 return;
1406         }
1407
1408         task = sas_alloc_slow_task(GFP_ATOMIC);
1409
1410         if (!task) {
1411                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1412                                                 "allocate task\n"));
1413                 return;
1414         }
1415
1416         task->task_done = pm8001_task_done;
1417
1418         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1419         if (res) {
1420                 sas_free_task(task);
1421                 return;
1422         }
1423
1424         ccb = &pm8001_ha->ccb_info[ccb_tag];
1425         ccb->device = pm8001_ha_dev;
1426         ccb->ccb_tag = ccb_tag;
1427         ccb->task = task;
1428
1429         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1430
1431         memset(&task_abort, 0, sizeof(task_abort));
1432         task_abort.abort_all = cpu_to_le32(1);
1433         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1434         task_abort.tag = cpu_to_le32(ccb_tag);
1435
1436         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1437         if (ret) {
1438                 sas_free_task(task);
1439                 pm8001_tag_free(pm8001_ha, ccb_tag);
1440         }
1441 }
1442
1443 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1444                 struct pm8001_device *pm8001_ha_dev)
1445 {
1446         struct sata_start_req sata_cmd;
1447         int res;
1448         u32 ccb_tag;
1449         struct pm8001_ccb_info *ccb;
1450         struct sas_task *task = NULL;
1451         struct host_to_dev_fis fis;
1452         struct domain_device *dev;
1453         struct inbound_queue_table *circularQ;
1454         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1455
1456         task = sas_alloc_slow_task(GFP_ATOMIC);
1457
1458         if (!task) {
1459                 PM8001_FAIL_DBG(pm8001_ha,
1460                         pm8001_printk("cannot allocate task !!!\n"));
1461                 return;
1462         }
1463         task->task_done = pm8001_task_done;
1464
1465         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1466         if (res) {
1467                 sas_free_task(task);
1468                 PM8001_FAIL_DBG(pm8001_ha,
1469                         pm8001_printk("cannot allocate tag !!!\n"));
1470                 return;
1471         }
1472
1473         /* allocate domain device by ourselves as libsas
1474          * is not going to provide any
1475         */
1476         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1477         if (!dev) {
1478                 sas_free_task(task);
1479                 pm8001_tag_free(pm8001_ha, ccb_tag);
1480                 PM8001_FAIL_DBG(pm8001_ha,
1481                         pm8001_printk("Domain device cannot be allocated\n"));
1482                 return;
1483         }
1484
1485         task->dev = dev;
1486         task->dev->lldd_dev = pm8001_ha_dev;
1487
1488         ccb = &pm8001_ha->ccb_info[ccb_tag];
1489         ccb->device = pm8001_ha_dev;
1490         ccb->ccb_tag = ccb_tag;
1491         ccb->task = task;
1492         ccb->n_elem = 0;
1493         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1494         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1495
1496         memset(&sata_cmd, 0, sizeof(sata_cmd));
1497         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1498
1499         /* construct read log FIS */
1500         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1501         fis.fis_type = 0x27;
1502         fis.flags = 0x80;
1503         fis.command = ATA_CMD_READ_LOG_EXT;
1504         fis.lbal = 0x10;
1505         fis.sector_count = 0x1;
1506
1507         sata_cmd.tag = cpu_to_le32(ccb_tag);
1508         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1509         sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1510         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1511
1512         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1513         if (res) {
1514                 sas_free_task(task);
1515                 pm8001_tag_free(pm8001_ha, ccb_tag);
1516                 kfree(dev);
1517         }
1518 }
1519
1520 /**
1521  * mpi_ssp_completion- process the event that FW response to the SSP request.
1522  * @pm8001_ha: our hba card information
1523  * @piomb: the message contents of this outbound message.
1524  *
1525  * When FW has completed a ssp request for example a IO request, after it has
1526  * filled the SG data with the data, it will trigger this event represent
1527  * that he has finished the job,please check the coresponding buffer.
1528  * So we will tell the caller who maybe waiting the result to tell upper layer
1529  * that the task has been finished.
1530  */
1531 static void
1532 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1533 {
1534         struct sas_task *t;
1535         struct pm8001_ccb_info *ccb;
1536         unsigned long flags;
1537         u32 status;
1538         u32 param;
1539         u32 tag;
1540         struct ssp_completion_resp *psspPayload;
1541         struct task_status_struct *ts;
1542         struct ssp_response_iu *iu;
1543         struct pm8001_device *pm8001_dev;
1544         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1545         status = le32_to_cpu(psspPayload->status);
1546         tag = le32_to_cpu(psspPayload->tag);
1547         ccb = &pm8001_ha->ccb_info[tag];
1548         if ((status == IO_ABORTED) && ccb->open_retry) {
1549                 /* Being completed by another */
1550                 ccb->open_retry = 0;
1551                 return;
1552         }
1553         pm8001_dev = ccb->device;
1554         param = le32_to_cpu(psspPayload->param);
1555         t = ccb->task;
1556
1557         if (status && status != IO_UNDERFLOW)
1558                 PM8001_FAIL_DBG(pm8001_ha,
1559                         pm8001_printk("sas IO status 0x%x\n", status));
1560         if (unlikely(!t || !t->lldd_task || !t->dev))
1561                 return;
1562         ts = &t->task_status;
1563         /* Print sas address of IO failed device */
1564         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1565                 (status != IO_UNDERFLOW))
1566                 PM8001_FAIL_DBG(pm8001_ha,
1567                         pm8001_printk("SAS Address of IO Failure Drive"
1568                         ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1569
1570         switch (status) {
1571         case IO_SUCCESS:
1572                 PM8001_IO_DBG(pm8001_ha,
1573                         pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1574                                 param));
1575                 if (param == 0) {
1576                         ts->resp = SAS_TASK_COMPLETE;
1577                         ts->stat = SAM_STAT_GOOD;
1578                 } else {
1579                         ts->resp = SAS_TASK_COMPLETE;
1580                         ts->stat = SAS_PROTO_RESPONSE;
1581                         ts->residual = param;
1582                         iu = &psspPayload->ssp_resp_iu;
1583                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1584                 }
1585                 if (pm8001_dev)
1586                         pm8001_dev->running_req--;
1587                 break;
1588         case IO_ABORTED:
1589                 PM8001_IO_DBG(pm8001_ha,
1590                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1591                 ts->resp = SAS_TASK_COMPLETE;
1592                 ts->stat = SAS_ABORTED_TASK;
1593                 break;
1594         case IO_UNDERFLOW:
1595                 /* SSP Completion with error */
1596                 PM8001_IO_DBG(pm8001_ha,
1597                         pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1598                                 param));
1599                 ts->resp = SAS_TASK_COMPLETE;
1600                 ts->stat = SAS_DATA_UNDERRUN;
1601                 ts->residual = param;
1602                 if (pm8001_dev)
1603                         pm8001_dev->running_req--;
1604                 break;
1605         case IO_NO_DEVICE:
1606                 PM8001_IO_DBG(pm8001_ha,
1607                         pm8001_printk("IO_NO_DEVICE\n"));
1608                 ts->resp = SAS_TASK_UNDELIVERED;
1609                 ts->stat = SAS_PHY_DOWN;
1610                 break;
1611         case IO_XFER_ERROR_BREAK:
1612                 PM8001_IO_DBG(pm8001_ha,
1613                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1614                 ts->resp = SAS_TASK_COMPLETE;
1615                 ts->stat = SAS_OPEN_REJECT;
1616                 /* Force the midlayer to retry */
1617                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1618                 break;
1619         case IO_XFER_ERROR_PHY_NOT_READY:
1620                 PM8001_IO_DBG(pm8001_ha,
1621                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1622                 ts->resp = SAS_TASK_COMPLETE;
1623                 ts->stat = SAS_OPEN_REJECT;
1624                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1625                 break;
1626         case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1627                 PM8001_IO_DBG(pm8001_ha,
1628                         pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1629                 ts->resp = SAS_TASK_COMPLETE;
1630                 ts->stat = SAS_OPEN_REJECT;
1631                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1632                 break;
1633         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1634                 PM8001_IO_DBG(pm8001_ha,
1635                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1636                 ts->resp = SAS_TASK_COMPLETE;
1637                 ts->stat = SAS_OPEN_REJECT;
1638                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1639                 break;
1640         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1641                 PM8001_IO_DBG(pm8001_ha,
1642                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1643                 ts->resp = SAS_TASK_COMPLETE;
1644                 ts->stat = SAS_OPEN_REJECT;
1645                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1646                 break;
1647         case IO_OPEN_CNX_ERROR_BREAK:
1648                 PM8001_IO_DBG(pm8001_ha,
1649                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1650                 ts->resp = SAS_TASK_COMPLETE;
1651                 ts->stat = SAS_OPEN_REJECT;
1652                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1653                 break;
1654         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1655         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1656         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1657         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1658         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1659         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1660                 PM8001_IO_DBG(pm8001_ha,
1661                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1662                 ts->resp = SAS_TASK_COMPLETE;
1663                 ts->stat = SAS_OPEN_REJECT;
1664                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1665                 if (!t->uldd_task)
1666                         pm8001_handle_event(pm8001_ha,
1667                                 pm8001_dev,
1668                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1669                 break;
1670         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1671                 PM8001_IO_DBG(pm8001_ha,
1672                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1673                 ts->resp = SAS_TASK_COMPLETE;
1674                 ts->stat = SAS_OPEN_REJECT;
1675                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1676                 break;
1677         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1678                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1679                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1680                 ts->resp = SAS_TASK_COMPLETE;
1681                 ts->stat = SAS_OPEN_REJECT;
1682                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1683                 break;
1684         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1685                 PM8001_IO_DBG(pm8001_ha,
1686                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1687                 ts->resp = SAS_TASK_UNDELIVERED;
1688                 ts->stat = SAS_OPEN_REJECT;
1689                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1690                 break;
1691         case IO_XFER_ERROR_NAK_RECEIVED:
1692                 PM8001_IO_DBG(pm8001_ha,
1693                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1694                 ts->resp = SAS_TASK_COMPLETE;
1695                 ts->stat = SAS_OPEN_REJECT;
1696                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1697                 break;
1698         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1699                 PM8001_IO_DBG(pm8001_ha,
1700                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1701                 ts->resp = SAS_TASK_COMPLETE;
1702                 ts->stat = SAS_NAK_R_ERR;
1703                 break;
1704         case IO_XFER_ERROR_DMA:
1705                 PM8001_IO_DBG(pm8001_ha,
1706                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1707                 ts->resp = SAS_TASK_COMPLETE;
1708                 ts->stat = SAS_OPEN_REJECT;
1709                 break;
1710         case IO_XFER_OPEN_RETRY_TIMEOUT:
1711                 PM8001_IO_DBG(pm8001_ha,
1712                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1713                 ts->resp = SAS_TASK_COMPLETE;
1714                 ts->stat = SAS_OPEN_REJECT;
1715                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1716                 break;
1717         case IO_XFER_ERROR_OFFSET_MISMATCH:
1718                 PM8001_IO_DBG(pm8001_ha,
1719                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1720                 ts->resp = SAS_TASK_COMPLETE;
1721                 ts->stat = SAS_OPEN_REJECT;
1722                 break;
1723         case IO_PORT_IN_RESET:
1724                 PM8001_IO_DBG(pm8001_ha,
1725                         pm8001_printk("IO_PORT_IN_RESET\n"));
1726                 ts->resp = SAS_TASK_COMPLETE;
1727                 ts->stat = SAS_OPEN_REJECT;
1728                 break;
1729         case IO_DS_NON_OPERATIONAL:
1730                 PM8001_IO_DBG(pm8001_ha,
1731                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1732                 ts->resp = SAS_TASK_COMPLETE;
1733                 ts->stat = SAS_OPEN_REJECT;
1734                 if (!t->uldd_task)
1735                         pm8001_handle_event(pm8001_ha,
1736                                 pm8001_dev,
1737                                 IO_DS_NON_OPERATIONAL);
1738                 break;
1739         case IO_DS_IN_RECOVERY:
1740                 PM8001_IO_DBG(pm8001_ha,
1741                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1742                 ts->resp = SAS_TASK_COMPLETE;
1743                 ts->stat = SAS_OPEN_REJECT;
1744                 break;
1745         case IO_TM_TAG_NOT_FOUND:
1746                 PM8001_IO_DBG(pm8001_ha,
1747                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1748                 ts->resp = SAS_TASK_COMPLETE;
1749                 ts->stat = SAS_OPEN_REJECT;
1750                 break;
1751         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1752                 PM8001_IO_DBG(pm8001_ha,
1753                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1754                 ts->resp = SAS_TASK_COMPLETE;
1755                 ts->stat = SAS_OPEN_REJECT;
1756                 break;
1757         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1758                 PM8001_IO_DBG(pm8001_ha,
1759                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1760                 ts->resp = SAS_TASK_COMPLETE;
1761                 ts->stat = SAS_OPEN_REJECT;
1762                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1763                 break;
1764         default:
1765                 PM8001_IO_DBG(pm8001_ha,
1766                         pm8001_printk("Unknown status 0x%x\n", status));
1767                 /* not allowed case. Therefore, return failed status */
1768                 ts->resp = SAS_TASK_COMPLETE;
1769                 ts->stat = SAS_OPEN_REJECT;
1770                 break;
1771         }
1772         PM8001_IO_DBG(pm8001_ha,
1773                 pm8001_printk("scsi_status = 0x%x\n ",
1774                 psspPayload->ssp_resp_iu.status));
1775         spin_lock_irqsave(&t->task_state_lock, flags);
1776         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1777         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1778         t->task_state_flags |= SAS_TASK_STATE_DONE;
1779         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1780                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1781                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1782                         "task 0x%p done with io_status 0x%x resp 0x%x "
1783                         "stat 0x%x but aborted by upper layer!\n",
1784                         t, status, ts->resp, ts->stat));
1785                 if (t->slow_task)
1786                         complete(&t->slow_task->completion);
1787                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1788         } else {
1789                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1790                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1791                 mb();/* in order to force CPU ordering */
1792                 t->task_done(t);
1793         }
1794 }
1795
1796 /*See the comments for mpi_ssp_completion */
1797 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1798 {
1799         struct sas_task *t;
1800         unsigned long flags;
1801         struct task_status_struct *ts;
1802         struct pm8001_ccb_info *ccb;
1803         struct pm8001_device *pm8001_dev;
1804         struct ssp_event_resp *psspPayload =
1805                 (struct ssp_event_resp *)(piomb + 4);
1806         u32 event = le32_to_cpu(psspPayload->event);
1807         u32 tag = le32_to_cpu(psspPayload->tag);
1808         u32 port_id = le32_to_cpu(psspPayload->port_id);
1809
1810         ccb = &pm8001_ha->ccb_info[tag];
1811         t = ccb->task;
1812         pm8001_dev = ccb->device;
1813         if (event)
1814                 PM8001_FAIL_DBG(pm8001_ha,
1815                         pm8001_printk("sas IO status 0x%x\n", event));
1816         if (unlikely(!t || !t->lldd_task || !t->dev))
1817                 return;
1818         ts = &t->task_status;
1819         PM8001_IO_DBG(pm8001_ha,
1820                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1821                                 port_id, tag, event));
1822         switch (event) {
1823         case IO_OVERFLOW:
1824                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1825                 ts->resp = SAS_TASK_COMPLETE;
1826                 ts->stat = SAS_DATA_OVERRUN;
1827                 ts->residual = 0;
1828                 if (pm8001_dev)
1829                         pm8001_dev->running_req--;
1830                 break;
1831         case IO_XFER_ERROR_BREAK:
1832                 PM8001_IO_DBG(pm8001_ha,
1833                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1834                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1835                 return;
1836         case IO_XFER_ERROR_PHY_NOT_READY:
1837                 PM8001_IO_DBG(pm8001_ha,
1838                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1839                 ts->resp = SAS_TASK_COMPLETE;
1840                 ts->stat = SAS_OPEN_REJECT;
1841                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1842                 break;
1843         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1844                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1845                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1846                 ts->resp = SAS_TASK_COMPLETE;
1847                 ts->stat = SAS_OPEN_REJECT;
1848                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1849                 break;
1850         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1851                 PM8001_IO_DBG(pm8001_ha,
1852                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1853                 ts->resp = SAS_TASK_COMPLETE;
1854                 ts->stat = SAS_OPEN_REJECT;
1855                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1856                 break;
1857         case IO_OPEN_CNX_ERROR_BREAK:
1858                 PM8001_IO_DBG(pm8001_ha,
1859                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1860                 ts->resp = SAS_TASK_COMPLETE;
1861                 ts->stat = SAS_OPEN_REJECT;
1862                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1863                 break;
1864         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1865         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1866         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1867         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1868         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1869         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1870                 PM8001_IO_DBG(pm8001_ha,
1871                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1872                 ts->resp = SAS_TASK_COMPLETE;
1873                 ts->stat = SAS_OPEN_REJECT;
1874                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1875                 if (!t->uldd_task)
1876                         pm8001_handle_event(pm8001_ha,
1877                                 pm8001_dev,
1878                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1879                 break;
1880         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1881                 PM8001_IO_DBG(pm8001_ha,
1882                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1883                 ts->resp = SAS_TASK_COMPLETE;
1884                 ts->stat = SAS_OPEN_REJECT;
1885                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1886                 break;
1887         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1888                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1889                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1890                 ts->resp = SAS_TASK_COMPLETE;
1891                 ts->stat = SAS_OPEN_REJECT;
1892                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1893                 break;
1894         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1895                 PM8001_IO_DBG(pm8001_ha,
1896                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1897                 ts->resp = SAS_TASK_COMPLETE;
1898                 ts->stat = SAS_OPEN_REJECT;
1899                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1900                 break;
1901         case IO_XFER_ERROR_NAK_RECEIVED:
1902                 PM8001_IO_DBG(pm8001_ha,
1903                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1904                 ts->resp = SAS_TASK_COMPLETE;
1905                 ts->stat = SAS_OPEN_REJECT;
1906                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1907                 break;
1908         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1909                 PM8001_IO_DBG(pm8001_ha,
1910                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1911                 ts->resp = SAS_TASK_COMPLETE;
1912                 ts->stat = SAS_NAK_R_ERR;
1913                 break;
1914         case IO_XFER_OPEN_RETRY_TIMEOUT:
1915                 PM8001_IO_DBG(pm8001_ha,
1916                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1917                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1918                 return;
1919         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1920                 PM8001_IO_DBG(pm8001_ha,
1921                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1922                 ts->resp = SAS_TASK_COMPLETE;
1923                 ts->stat = SAS_DATA_OVERRUN;
1924                 break;
1925         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1926                 PM8001_IO_DBG(pm8001_ha,
1927                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1928                 ts->resp = SAS_TASK_COMPLETE;
1929                 ts->stat = SAS_DATA_OVERRUN;
1930                 break;
1931         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1932                 PM8001_IO_DBG(pm8001_ha,
1933                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1934                 ts->resp = SAS_TASK_COMPLETE;
1935                 ts->stat = SAS_DATA_OVERRUN;
1936                 break;
1937         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1938                 PM8001_IO_DBG(pm8001_ha,
1939                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1940                 ts->resp = SAS_TASK_COMPLETE;
1941                 ts->stat = SAS_DATA_OVERRUN;
1942                 break;
1943         case IO_XFER_ERROR_OFFSET_MISMATCH:
1944                 PM8001_IO_DBG(pm8001_ha,
1945                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1946                 ts->resp = SAS_TASK_COMPLETE;
1947                 ts->stat = SAS_DATA_OVERRUN;
1948                 break;
1949         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1950                 PM8001_IO_DBG(pm8001_ha,
1951                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1952                 ts->resp = SAS_TASK_COMPLETE;
1953                 ts->stat = SAS_DATA_OVERRUN;
1954                 break;
1955         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1956                 PM8001_IO_DBG(pm8001_ha,
1957                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1958                 /* TBC: used default set values */
1959                 ts->resp = SAS_TASK_COMPLETE;
1960                 ts->stat = SAS_DATA_OVERRUN;
1961                 break;
1962         case IO_XFER_CMD_FRAME_ISSUED:
1963                 PM8001_IO_DBG(pm8001_ha,
1964                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1965                 return;
1966         default:
1967                 PM8001_IO_DBG(pm8001_ha,
1968                         pm8001_printk("Unknown status 0x%x\n", event));
1969                 /* not allowed case. Therefore, return failed status */
1970                 ts->resp = SAS_TASK_COMPLETE;
1971                 ts->stat = SAS_DATA_OVERRUN;
1972                 break;
1973         }
1974         spin_lock_irqsave(&t->task_state_lock, flags);
1975         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1976         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1977         t->task_state_flags |= SAS_TASK_STATE_DONE;
1978         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1979                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1980                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1981                         "task 0x%p done with event 0x%x resp 0x%x "
1982                         "stat 0x%x but aborted by upper layer!\n",
1983                         t, event, ts->resp, ts->stat));
1984                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1985         } else {
1986                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1987                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1988                 mb();/* in order to force CPU ordering */
1989                 t->task_done(t);
1990         }
1991 }
1992
1993 /*See the comments for mpi_ssp_completion */
1994 static void
1995 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1996 {
1997         struct sas_task *t;
1998         struct pm8001_ccb_info *ccb;
1999         u32 param;
2000         u32 status;
2001         u32 tag;
2002         int i, j;
2003         u8 sata_addr_low[4];
2004         u32 temp_sata_addr_low, temp_sata_addr_hi;
2005         u8 sata_addr_hi[4];
2006         struct sata_completion_resp *psataPayload;
2007         struct task_status_struct *ts;
2008         struct ata_task_resp *resp ;
2009         u32 *sata_resp;
2010         struct pm8001_device *pm8001_dev;
2011         unsigned long flags;
2012
2013         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2014         status = le32_to_cpu(psataPayload->status);
2015         tag = le32_to_cpu(psataPayload->tag);
2016
2017         if (!tag) {
2018                 PM8001_FAIL_DBG(pm8001_ha,
2019                         pm8001_printk("tag null\n"));
2020                 return;
2021         }
2022         ccb = &pm8001_ha->ccb_info[tag];
2023         param = le32_to_cpu(psataPayload->param);
2024         if (ccb) {
2025                 t = ccb->task;
2026                 pm8001_dev = ccb->device;
2027         } else {
2028                 PM8001_FAIL_DBG(pm8001_ha,
2029                         pm8001_printk("ccb null\n"));
2030                 return;
2031         }
2032
2033         if (t) {
2034                 if (t->dev && (t->dev->lldd_dev))
2035                         pm8001_dev = t->dev->lldd_dev;
2036         } else {
2037                 PM8001_FAIL_DBG(pm8001_ha,
2038                         pm8001_printk("task null\n"));
2039                 return;
2040         }
2041
2042         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2043                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2044                 PM8001_FAIL_DBG(pm8001_ha,
2045                         pm8001_printk("task or dev null\n"));
2046                 return;
2047         }
2048
2049         ts = &t->task_status;
2050         if (!ts) {
2051                 PM8001_FAIL_DBG(pm8001_ha,
2052                         pm8001_printk("ts null\n"));
2053                 return;
2054         }
2055         /* Print sas address of IO failed device */
2056         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2057                 (status != IO_UNDERFLOW)) {
2058                 if (!((t->dev->parent) &&
2059                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2060                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2061                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2062                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2063                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2064                         memcpy(&temp_sata_addr_low, sata_addr_low,
2065                                 sizeof(sata_addr_low));
2066                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2067                                 sizeof(sata_addr_hi));
2068                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2069                                                 |((temp_sata_addr_hi << 8) &
2070                                                 0xff0000) |
2071                                                 ((temp_sata_addr_hi >> 8)
2072                                                 & 0xff00) |
2073                                                 ((temp_sata_addr_hi << 24) &
2074                                                 0xff000000));
2075                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2076                                                 & 0xff) |
2077                                                 ((temp_sata_addr_low << 8)
2078                                                 & 0xff0000) |
2079                                                 ((temp_sata_addr_low >> 8)
2080                                                 & 0xff00) |
2081                                                 ((temp_sata_addr_low << 24)
2082                                                 & 0xff000000)) +
2083                                                 pm8001_dev->attached_phy +
2084                                                 0x10);
2085                         PM8001_FAIL_DBG(pm8001_ha,
2086                                 pm8001_printk("SAS Address of IO Failure Drive:"
2087                                 "%08x%08x", temp_sata_addr_hi,
2088                                         temp_sata_addr_low));
2089
2090                 } else {
2091                         PM8001_FAIL_DBG(pm8001_ha,
2092                                 pm8001_printk("SAS Address of IO Failure Drive:"
2093                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2094                 }
2095         }
2096         switch (status) {
2097         case IO_SUCCESS:
2098                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2099                 if (param == 0) {
2100                         ts->resp = SAS_TASK_COMPLETE;
2101                         ts->stat = SAM_STAT_GOOD;
2102                         /* check if response is for SEND READ LOG */
2103                         if (pm8001_dev &&
2104                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2105                                 /* set new bit for abort_all */
2106                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2107                                 /* clear bit for read log */
2108                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2109                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2110                                 /* Free the tag */
2111                                 pm8001_tag_free(pm8001_ha, tag);
2112                                 sas_free_task(t);
2113                                 return;
2114                         }
2115                 } else {
2116                         u8 len;
2117                         ts->resp = SAS_TASK_COMPLETE;
2118                         ts->stat = SAS_PROTO_RESPONSE;
2119                         ts->residual = param;
2120                         PM8001_IO_DBG(pm8001_ha,
2121                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2122                                 param));
2123                         sata_resp = &psataPayload->sata_resp[0];
2124                         resp = (struct ata_task_resp *)ts->buf;
2125                         if (t->ata_task.dma_xfer == 0 &&
2126                         t->data_dir == PCI_DMA_FROMDEVICE) {
2127                                 len = sizeof(struct pio_setup_fis);
2128                                 PM8001_IO_DBG(pm8001_ha,
2129                                 pm8001_printk("PIO read len = %d\n", len));
2130                         } else if (t->ata_task.use_ncq) {
2131                                 len = sizeof(struct set_dev_bits_fis);
2132                                 PM8001_IO_DBG(pm8001_ha,
2133                                         pm8001_printk("FPDMA len = %d\n", len));
2134                         } else {
2135                                 len = sizeof(struct dev_to_host_fis);
2136                                 PM8001_IO_DBG(pm8001_ha,
2137                                 pm8001_printk("other len = %d\n", len));
2138                         }
2139                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2140                                 resp->frame_len = len;
2141                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2142                                 ts->buf_valid_size = sizeof(*resp);
2143                         } else
2144                                 PM8001_IO_DBG(pm8001_ha,
2145                                         pm8001_printk("response to large\n"));
2146                 }
2147                 if (pm8001_dev)
2148                         pm8001_dev->running_req--;
2149                 break;
2150         case IO_ABORTED:
2151                 PM8001_IO_DBG(pm8001_ha,
2152                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2153                 ts->resp = SAS_TASK_COMPLETE;
2154                 ts->stat = SAS_ABORTED_TASK;
2155                 if (pm8001_dev)
2156                         pm8001_dev->running_req--;
2157                 break;
2158                 /* following cases are to do cases */
2159         case IO_UNDERFLOW:
2160                 /* SATA Completion with error */
2161                 PM8001_IO_DBG(pm8001_ha,
2162                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2163                 ts->resp = SAS_TASK_COMPLETE;
2164                 ts->stat = SAS_DATA_UNDERRUN;
2165                 ts->residual = param;
2166                 if (pm8001_dev)
2167                         pm8001_dev->running_req--;
2168                 break;
2169         case IO_NO_DEVICE:
2170                 PM8001_IO_DBG(pm8001_ha,
2171                         pm8001_printk("IO_NO_DEVICE\n"));
2172                 ts->resp = SAS_TASK_UNDELIVERED;
2173                 ts->stat = SAS_PHY_DOWN;
2174                 break;
2175         case IO_XFER_ERROR_BREAK:
2176                 PM8001_IO_DBG(pm8001_ha,
2177                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2178                 ts->resp = SAS_TASK_COMPLETE;
2179                 ts->stat = SAS_INTERRUPTED;
2180                 break;
2181         case IO_XFER_ERROR_PHY_NOT_READY:
2182                 PM8001_IO_DBG(pm8001_ha,
2183                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2184                 ts->resp = SAS_TASK_COMPLETE;
2185                 ts->stat = SAS_OPEN_REJECT;
2186                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2187                 break;
2188         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2189                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2190                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2191                 ts->resp = SAS_TASK_COMPLETE;
2192                 ts->stat = SAS_OPEN_REJECT;
2193                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2194                 break;
2195         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2196                 PM8001_IO_DBG(pm8001_ha,
2197                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2198                 ts->resp = SAS_TASK_COMPLETE;
2199                 ts->stat = SAS_OPEN_REJECT;
2200                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2201                 break;
2202         case IO_OPEN_CNX_ERROR_BREAK:
2203                 PM8001_IO_DBG(pm8001_ha,
2204                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2205                 ts->resp = SAS_TASK_COMPLETE;
2206                 ts->stat = SAS_OPEN_REJECT;
2207                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2208                 break;
2209         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2210         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2211         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2212         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2213         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2214         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2215                 PM8001_IO_DBG(pm8001_ha,
2216                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2217                 ts->resp = SAS_TASK_COMPLETE;
2218                 ts->stat = SAS_DEV_NO_RESPONSE;
2219                 if (!t->uldd_task) {
2220                         pm8001_handle_event(pm8001_ha,
2221                                 pm8001_dev,
2222                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2223                         ts->resp = SAS_TASK_UNDELIVERED;
2224                         ts->stat = SAS_QUEUE_FULL;
2225                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2226                         return;
2227                 }
2228                 break;
2229         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2230                 PM8001_IO_DBG(pm8001_ha,
2231                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2232                 ts->resp = SAS_TASK_UNDELIVERED;
2233                 ts->stat = SAS_OPEN_REJECT;
2234                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2235                 if (!t->uldd_task) {
2236                         pm8001_handle_event(pm8001_ha,
2237                                 pm8001_dev,
2238                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2239                         ts->resp = SAS_TASK_UNDELIVERED;
2240                         ts->stat = SAS_QUEUE_FULL;
2241                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2242                         return;
2243                 }
2244                 break;
2245         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2246                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2247                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2248                 ts->resp = SAS_TASK_COMPLETE;
2249                 ts->stat = SAS_OPEN_REJECT;
2250                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2251                 break;
2252         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2253                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2254                         "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2255                 ts->resp = SAS_TASK_COMPLETE;
2256                 ts->stat = SAS_DEV_NO_RESPONSE;
2257                 if (!t->uldd_task) {
2258                         pm8001_handle_event(pm8001_ha,
2259                                 pm8001_dev,
2260                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2261                         ts->resp = SAS_TASK_UNDELIVERED;
2262                         ts->stat = SAS_QUEUE_FULL;
2263                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2264                         return;
2265                 }
2266                 break;
2267         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2268                 PM8001_IO_DBG(pm8001_ha,
2269                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2270                 ts->resp = SAS_TASK_COMPLETE;
2271                 ts->stat = SAS_OPEN_REJECT;
2272                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2273                 break;
2274         case IO_XFER_ERROR_NAK_RECEIVED:
2275                 PM8001_IO_DBG(pm8001_ha,
2276                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2277                 ts->resp = SAS_TASK_COMPLETE;
2278                 ts->stat = SAS_NAK_R_ERR;
2279                 break;
2280         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2281                 PM8001_IO_DBG(pm8001_ha,
2282                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2283                 ts->resp = SAS_TASK_COMPLETE;
2284                 ts->stat = SAS_NAK_R_ERR;
2285                 break;
2286         case IO_XFER_ERROR_DMA:
2287                 PM8001_IO_DBG(pm8001_ha,
2288                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2289                 ts->resp = SAS_TASK_COMPLETE;
2290                 ts->stat = SAS_ABORTED_TASK;
2291                 break;
2292         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2293                 PM8001_IO_DBG(pm8001_ha,
2294                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2295                 ts->resp = SAS_TASK_UNDELIVERED;
2296                 ts->stat = SAS_DEV_NO_RESPONSE;
2297                 break;
2298         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2299                 PM8001_IO_DBG(pm8001_ha,
2300                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2301                 ts->resp = SAS_TASK_COMPLETE;
2302                 ts->stat = SAS_DATA_UNDERRUN;
2303                 break;
2304         case IO_XFER_OPEN_RETRY_TIMEOUT:
2305                 PM8001_IO_DBG(pm8001_ha,
2306                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2307                 ts->resp = SAS_TASK_COMPLETE;
2308                 ts->stat = SAS_OPEN_TO;
2309                 break;
2310         case IO_PORT_IN_RESET:
2311                 PM8001_IO_DBG(pm8001_ha,
2312                         pm8001_printk("IO_PORT_IN_RESET\n"));
2313                 ts->resp = SAS_TASK_COMPLETE;
2314                 ts->stat = SAS_DEV_NO_RESPONSE;
2315                 break;
2316         case IO_DS_NON_OPERATIONAL:
2317                 PM8001_IO_DBG(pm8001_ha,
2318                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2319                 ts->resp = SAS_TASK_COMPLETE;
2320                 ts->stat = SAS_DEV_NO_RESPONSE;
2321                 if (!t->uldd_task) {
2322                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2323                                         IO_DS_NON_OPERATIONAL);
2324                         ts->resp = SAS_TASK_UNDELIVERED;
2325                         ts->stat = SAS_QUEUE_FULL;
2326                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2327                         return;
2328                 }
2329                 break;
2330         case IO_DS_IN_RECOVERY:
2331                 PM8001_IO_DBG(pm8001_ha,
2332                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2333                 ts->resp = SAS_TASK_COMPLETE;
2334                 ts->stat = SAS_DEV_NO_RESPONSE;
2335                 break;
2336         case IO_DS_IN_ERROR:
2337                 PM8001_IO_DBG(pm8001_ha,
2338                         pm8001_printk("IO_DS_IN_ERROR\n"));
2339                 ts->resp = SAS_TASK_COMPLETE;
2340                 ts->stat = SAS_DEV_NO_RESPONSE;
2341                 if (!t->uldd_task) {
2342                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2343                                         IO_DS_IN_ERROR);
2344                         ts->resp = SAS_TASK_UNDELIVERED;
2345                         ts->stat = SAS_QUEUE_FULL;
2346                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2347                         return;
2348                 }
2349                 break;
2350         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2351                 PM8001_IO_DBG(pm8001_ha,
2352                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2353                 ts->resp = SAS_TASK_COMPLETE;
2354                 ts->stat = SAS_OPEN_REJECT;
2355                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2356                 break;
2357         default:
2358                 PM8001_IO_DBG(pm8001_ha,
2359                         pm8001_printk("Unknown status 0x%x\n", status));
2360                 /* not allowed case. Therefore, return failed status */
2361                 ts->resp = SAS_TASK_COMPLETE;
2362                 ts->stat = SAS_DEV_NO_RESPONSE;
2363                 break;
2364         }
2365         spin_lock_irqsave(&t->task_state_lock, flags);
2366         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2367         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2368         t->task_state_flags |= SAS_TASK_STATE_DONE;
2369         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2370                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2371                 PM8001_FAIL_DBG(pm8001_ha,
2372                         pm8001_printk("task 0x%p done with io_status 0x%x"
2373                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2374                         t, status, ts->resp, ts->stat));
2375                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2376         } else {
2377                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2378                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2379         }
2380 }
2381
2382 /*See the comments for mpi_ssp_completion */
2383 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2384 {
2385         struct sas_task *t;
2386         struct task_status_struct *ts;
2387         struct pm8001_ccb_info *ccb;
2388         struct pm8001_device *pm8001_dev;
2389         struct sata_event_resp *psataPayload =
2390                 (struct sata_event_resp *)(piomb + 4);
2391         u32 event = le32_to_cpu(psataPayload->event);
2392         u32 tag = le32_to_cpu(psataPayload->tag);
2393         u32 port_id = le32_to_cpu(psataPayload->port_id);
2394         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2395         unsigned long flags;
2396
2397         ccb = &pm8001_ha->ccb_info[tag];
2398
2399         if (ccb) {
2400                 t = ccb->task;
2401                 pm8001_dev = ccb->device;
2402         } else {
2403                 PM8001_FAIL_DBG(pm8001_ha,
2404                         pm8001_printk("No CCB !!!. returning\n"));
2405                 return;
2406         }
2407         if (event)
2408                 PM8001_FAIL_DBG(pm8001_ha,
2409                         pm8001_printk("SATA EVENT 0x%x\n", event));
2410
2411         /* Check if this is NCQ error */
2412         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2413                 /* find device using device id */
2414                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2415                 /* send read log extension */
2416                 if (pm8001_dev)
2417                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2418                 return;
2419         }
2420
2421         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2422                 PM8001_FAIL_DBG(pm8001_ha,
2423                         pm8001_printk("task or dev null\n"));
2424                 return;
2425         }
2426
2427         ts = &t->task_status;
2428         PM8001_IO_DBG(pm8001_ha,
2429                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2430                                 port_id, tag, event));
2431         switch (event) {
2432         case IO_OVERFLOW:
2433                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2434                 ts->resp = SAS_TASK_COMPLETE;
2435                 ts->stat = SAS_DATA_OVERRUN;
2436                 ts->residual = 0;
2437                 if (pm8001_dev)
2438                         pm8001_dev->running_req--;
2439                 break;
2440         case IO_XFER_ERROR_BREAK:
2441                 PM8001_IO_DBG(pm8001_ha,
2442                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2443                 ts->resp = SAS_TASK_COMPLETE;
2444                 ts->stat = SAS_INTERRUPTED;
2445                 break;
2446         case IO_XFER_ERROR_PHY_NOT_READY:
2447                 PM8001_IO_DBG(pm8001_ha,
2448                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2449                 ts->resp = SAS_TASK_COMPLETE;
2450                 ts->stat = SAS_OPEN_REJECT;
2451                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2452                 break;
2453         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2454                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2455                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2456                 ts->resp = SAS_TASK_COMPLETE;
2457                 ts->stat = SAS_OPEN_REJECT;
2458                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2459                 break;
2460         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2461                 PM8001_IO_DBG(pm8001_ha,
2462                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2463                 ts->resp = SAS_TASK_COMPLETE;
2464                 ts->stat = SAS_OPEN_REJECT;
2465                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2466                 break;
2467         case IO_OPEN_CNX_ERROR_BREAK:
2468                 PM8001_IO_DBG(pm8001_ha,
2469                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2470                 ts->resp = SAS_TASK_COMPLETE;
2471                 ts->stat = SAS_OPEN_REJECT;
2472                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2473                 break;
2474         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2475         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2476         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2477         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2478         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2479         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2480                 PM8001_FAIL_DBG(pm8001_ha,
2481                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2482                 ts->resp = SAS_TASK_UNDELIVERED;
2483                 ts->stat = SAS_DEV_NO_RESPONSE;
2484                 if (!t->uldd_task) {
2485                         pm8001_handle_event(pm8001_ha,
2486                                 pm8001_dev,
2487                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2488                         ts->resp = SAS_TASK_COMPLETE;
2489                         ts->stat = SAS_QUEUE_FULL;
2490                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2491                         return;
2492                 }
2493                 break;
2494         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2495                 PM8001_IO_DBG(pm8001_ha,
2496                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2497                 ts->resp = SAS_TASK_UNDELIVERED;
2498                 ts->stat = SAS_OPEN_REJECT;
2499                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2500                 break;
2501         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2502                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2503                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2504                 ts->resp = SAS_TASK_COMPLETE;
2505                 ts->stat = SAS_OPEN_REJECT;
2506                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2507                 break;
2508         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2509                 PM8001_IO_DBG(pm8001_ha,
2510                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2511                 ts->resp = SAS_TASK_COMPLETE;
2512                 ts->stat = SAS_OPEN_REJECT;
2513                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2514                 break;
2515         case IO_XFER_ERROR_NAK_RECEIVED:
2516                 PM8001_IO_DBG(pm8001_ha,
2517                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2518                 ts->resp = SAS_TASK_COMPLETE;
2519                 ts->stat = SAS_NAK_R_ERR;
2520                 break;
2521         case IO_XFER_ERROR_PEER_ABORTED:
2522                 PM8001_IO_DBG(pm8001_ha,
2523                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2524                 ts->resp = SAS_TASK_COMPLETE;
2525                 ts->stat = SAS_NAK_R_ERR;
2526                 break;
2527         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2528                 PM8001_IO_DBG(pm8001_ha,
2529                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2530                 ts->resp = SAS_TASK_COMPLETE;
2531                 ts->stat = SAS_DATA_UNDERRUN;
2532                 break;
2533         case IO_XFER_OPEN_RETRY_TIMEOUT:
2534                 PM8001_IO_DBG(pm8001_ha,
2535                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2536                 ts->resp = SAS_TASK_COMPLETE;
2537                 ts->stat = SAS_OPEN_TO;
2538                 break;
2539         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2540                 PM8001_IO_DBG(pm8001_ha,
2541                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2542                 ts->resp = SAS_TASK_COMPLETE;
2543                 ts->stat = SAS_OPEN_TO;
2544                 break;
2545         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2546                 PM8001_IO_DBG(pm8001_ha,
2547                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2548                 ts->resp = SAS_TASK_COMPLETE;
2549                 ts->stat = SAS_OPEN_TO;
2550                 break;
2551         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2552                 PM8001_IO_DBG(pm8001_ha,
2553                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2554                 ts->resp = SAS_TASK_COMPLETE;
2555                 ts->stat = SAS_OPEN_TO;
2556                 break;
2557         case IO_XFER_ERROR_OFFSET_MISMATCH:
2558                 PM8001_IO_DBG(pm8001_ha,
2559                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2560                 ts->resp = SAS_TASK_COMPLETE;
2561                 ts->stat = SAS_OPEN_TO;
2562                 break;
2563         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2564                 PM8001_IO_DBG(pm8001_ha,
2565                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2566                 ts->resp = SAS_TASK_COMPLETE;
2567                 ts->stat = SAS_OPEN_TO;
2568                 break;
2569         case IO_XFER_CMD_FRAME_ISSUED:
2570                 PM8001_IO_DBG(pm8001_ha,
2571                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2572                 break;
2573         case IO_XFER_PIO_SETUP_ERROR:
2574                 PM8001_IO_DBG(pm8001_ha,
2575                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2576                 ts->resp = SAS_TASK_COMPLETE;
2577                 ts->stat = SAS_OPEN_TO;
2578                 break;
2579         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2580                 PM8001_FAIL_DBG(pm8001_ha,
2581                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2582                 /* TBC: used default set values */
2583                 ts->resp = SAS_TASK_COMPLETE;
2584                 ts->stat = SAS_OPEN_TO;
2585                 break;
2586         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2587                 PM8001_FAIL_DBG(pm8001_ha,
2588                         pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2589                 /* TBC: used default set values */
2590                 ts->resp = SAS_TASK_COMPLETE;
2591                 ts->stat = SAS_OPEN_TO;
2592                 break;
2593         default:
2594                 PM8001_IO_DBG(pm8001_ha,
2595                         pm8001_printk("Unknown status 0x%x\n", event));
2596                 /* not allowed case. Therefore, return failed status */
2597                 ts->resp = SAS_TASK_COMPLETE;
2598                 ts->stat = SAS_OPEN_TO;
2599                 break;
2600         }
2601         spin_lock_irqsave(&t->task_state_lock, flags);
2602         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2603         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2604         t->task_state_flags |= SAS_TASK_STATE_DONE;
2605         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2606                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2607                 PM8001_FAIL_DBG(pm8001_ha,
2608                         pm8001_printk("task 0x%p done with io_status 0x%x"
2609                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2610                         t, event, ts->resp, ts->stat));
2611                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2612         } else {
2613                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2614                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2615         }
2616 }
2617
2618 /*See the comments for mpi_ssp_completion */
2619 static void
2620 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2621 {
2622         u32 param, i;
2623         struct sas_task *t;
2624         struct pm8001_ccb_info *ccb;
2625         unsigned long flags;
2626         u32 status;
2627         u32 tag;
2628         struct smp_completion_resp *psmpPayload;
2629         struct task_status_struct *ts;
2630         struct pm8001_device *pm8001_dev;
2631         char *pdma_respaddr = NULL;
2632
2633         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2634         status = le32_to_cpu(psmpPayload->status);
2635         tag = le32_to_cpu(psmpPayload->tag);
2636
2637         ccb = &pm8001_ha->ccb_info[tag];
2638         param = le32_to_cpu(psmpPayload->param);
2639         t = ccb->task;
2640         ts = &t->task_status;
2641         pm8001_dev = ccb->device;
2642         if (status)
2643                 PM8001_FAIL_DBG(pm8001_ha,
2644                         pm8001_printk("smp IO status 0x%x\n", status));
2645         if (unlikely(!t || !t->lldd_task || !t->dev))
2646                 return;
2647
2648         switch (status) {
2649
2650         case IO_SUCCESS:
2651                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2652                 ts->resp = SAS_TASK_COMPLETE;
2653                 ts->stat = SAM_STAT_GOOD;
2654                 if (pm8001_dev)
2655                         pm8001_dev->running_req--;
2656                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2657                         PM8001_IO_DBG(pm8001_ha,
2658                                 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2659                                                 param));
2660                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2661                                                 ((u64)sg_dma_address
2662                                                 (&t->smp_task.smp_resp))));
2663                         for (i = 0; i < param; i++) {
2664                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2665                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2666                                         "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2667                                         i, *(pdma_respaddr+i),
2668                                         psmpPayload->_r_a[i]));
2669                         }
2670                 }
2671                 break;
2672         case IO_ABORTED:
2673                 PM8001_IO_DBG(pm8001_ha,
2674                         pm8001_printk("IO_ABORTED IOMB\n"));
2675                 ts->resp = SAS_TASK_COMPLETE;
2676                 ts->stat = SAS_ABORTED_TASK;
2677                 if (pm8001_dev)
2678                         pm8001_dev->running_req--;
2679                 break;
2680         case IO_OVERFLOW:
2681                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2682                 ts->resp = SAS_TASK_COMPLETE;
2683                 ts->stat = SAS_DATA_OVERRUN;
2684                 ts->residual = 0;
2685                 if (pm8001_dev)
2686                         pm8001_dev->running_req--;
2687                 break;
2688         case IO_NO_DEVICE:
2689                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2690                 ts->resp = SAS_TASK_COMPLETE;
2691                 ts->stat = SAS_PHY_DOWN;
2692                 break;
2693         case IO_ERROR_HW_TIMEOUT:
2694                 PM8001_IO_DBG(pm8001_ha,
2695                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2696                 ts->resp = SAS_TASK_COMPLETE;
2697                 ts->stat = SAM_STAT_BUSY;
2698                 break;
2699         case IO_XFER_ERROR_BREAK:
2700                 PM8001_IO_DBG(pm8001_ha,
2701                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2702                 ts->resp = SAS_TASK_COMPLETE;
2703                 ts->stat = SAM_STAT_BUSY;
2704                 break;
2705         case IO_XFER_ERROR_PHY_NOT_READY:
2706                 PM8001_IO_DBG(pm8001_ha,
2707                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2708                 ts->resp = SAS_TASK_COMPLETE;
2709                 ts->stat = SAM_STAT_BUSY;
2710                 break;
2711         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2712                 PM8001_IO_DBG(pm8001_ha,
2713                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2714                 ts->resp = SAS_TASK_COMPLETE;
2715                 ts->stat = SAS_OPEN_REJECT;
2716                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2717                 break;
2718         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2719                 PM8001_IO_DBG(pm8001_ha,
2720                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2721                 ts->resp = SAS_TASK_COMPLETE;
2722                 ts->stat = SAS_OPEN_REJECT;
2723                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2724                 break;
2725         case IO_OPEN_CNX_ERROR_BREAK:
2726                 PM8001_IO_DBG(pm8001_ha,
2727                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2728                 ts->resp = SAS_TASK_COMPLETE;
2729                 ts->stat = SAS_OPEN_REJECT;
2730                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2731                 break;
2732         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2733         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2734         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2735         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2736         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2737         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2738                 PM8001_IO_DBG(pm8001_ha,
2739                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2740                 ts->resp = SAS_TASK_COMPLETE;
2741                 ts->stat = SAS_OPEN_REJECT;
2742                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2743                 pm8001_handle_event(pm8001_ha,
2744                                 pm8001_dev,
2745                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2746                 break;
2747         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2748                 PM8001_IO_DBG(pm8001_ha,
2749                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2750                 ts->resp = SAS_TASK_COMPLETE;
2751                 ts->stat = SAS_OPEN_REJECT;
2752                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2753                 break;
2754         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2755                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2756                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2757                 ts->resp = SAS_TASK_COMPLETE;
2758                 ts->stat = SAS_OPEN_REJECT;
2759                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2760                 break;
2761         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2762                 PM8001_IO_DBG(pm8001_ha,
2763                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2764                 ts->resp = SAS_TASK_COMPLETE;
2765                 ts->stat = SAS_OPEN_REJECT;
2766                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2767                 break;
2768         case IO_XFER_ERROR_RX_FRAME:
2769                 PM8001_IO_DBG(pm8001_ha,
2770                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2771                 ts->resp = SAS_TASK_COMPLETE;
2772                 ts->stat = SAS_DEV_NO_RESPONSE;
2773                 break;
2774         case IO_XFER_OPEN_RETRY_TIMEOUT:
2775                 PM8001_IO_DBG(pm8001_ha,
2776                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2777                 ts->resp = SAS_TASK_COMPLETE;
2778                 ts->stat = SAS_OPEN_REJECT;
2779                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2780                 break;
2781         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2782                 PM8001_IO_DBG(pm8001_ha,
2783                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2784                 ts->resp = SAS_TASK_COMPLETE;
2785                 ts->stat = SAS_QUEUE_FULL;
2786                 break;
2787         case IO_PORT_IN_RESET:
2788                 PM8001_IO_DBG(pm8001_ha,
2789                         pm8001_printk("IO_PORT_IN_RESET\n"));
2790                 ts->resp = SAS_TASK_COMPLETE;
2791                 ts->stat = SAS_OPEN_REJECT;
2792                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2793                 break;
2794         case IO_DS_NON_OPERATIONAL:
2795                 PM8001_IO_DBG(pm8001_ha,
2796                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2797                 ts->resp = SAS_TASK_COMPLETE;
2798                 ts->stat = SAS_DEV_NO_RESPONSE;
2799                 break;
2800         case IO_DS_IN_RECOVERY:
2801                 PM8001_IO_DBG(pm8001_ha,
2802                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2803                 ts->resp = SAS_TASK_COMPLETE;
2804                 ts->stat = SAS_OPEN_REJECT;
2805                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2806                 break;
2807         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2808                 PM8001_IO_DBG(pm8001_ha,
2809                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2810                 ts->resp = SAS_TASK_COMPLETE;
2811                 ts->stat = SAS_OPEN_REJECT;
2812                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2813                 break;
2814         default:
2815                 PM8001_IO_DBG(pm8001_ha,
2816                         pm8001_printk("Unknown status 0x%x\n", status));
2817                 ts->resp = SAS_TASK_COMPLETE;
2818                 ts->stat = SAS_DEV_NO_RESPONSE;
2819                 /* not allowed case. Therefore, return failed status */
2820                 break;
2821         }
2822         spin_lock_irqsave(&t->task_state_lock, flags);
2823         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2824         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2825         t->task_state_flags |= SAS_TASK_STATE_DONE;
2826         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2827                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2828                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2829                         "task 0x%p done with io_status 0x%x resp 0x%x"
2830                         "stat 0x%x but aborted by upper layer!\n",
2831                         t, status, ts->resp, ts->stat));
2832                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2833         } else {
2834                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2835                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2836                 mb();/* in order to force CPU ordering */
2837                 t->task_done(t);
2838         }
2839 }
2840
2841 /**
2842  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2843  * @pm8001_ha: our hba card information
2844  * @Qnum: the outbound queue message number.
2845  * @SEA: source of event to ack
2846  * @port_id: port id.
2847  * @phyId: phy id.
2848  * @param0: parameter 0.
2849  * @param1: parameter 1.
2850  */
2851 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2852         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2853 {
2854         struct hw_event_ack_req  payload;
2855         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2856
2857         struct inbound_queue_table *circularQ;
2858
2859         memset((u8 *)&payload, 0, sizeof(payload));
2860         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2861         payload.tag = cpu_to_le32(1);
2862         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2863                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2864         payload.param0 = cpu_to_le32(param0);
2865         payload.param1 = cpu_to_le32(param1);
2866         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2867 }
2868
2869 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2870         u32 phyId, u32 phy_op);
2871
2872 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
2873                                         void *piomb)
2874 {
2875         struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
2876         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2877         u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2878         u32 lr_status_evt_portid =
2879                 le32_to_cpu(pPayload->lr_status_evt_portid);
2880         u8 deviceType = pPayload->sas_identify.dev_type;
2881         u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2882         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2883         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2884         struct pm8001_port *port = &pm8001_ha->port[port_id];
2885
2886         if (deviceType == SAS_END_DEVICE) {
2887                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2888                                         PHY_NOTIFY_ENABLE_SPINUP);
2889         }
2890
2891         port->wide_port_phymap |= (1U << phy_id);
2892         pm8001_get_lrate_mode(phy, link_rate);
2893         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2894         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2895         phy->phy_attached = 1;
2896 }
2897
2898 /**
2899  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2900  * @pm8001_ha: our hba card information
2901  * @piomb: IO message buffer
2902  */
2903 static void
2904 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2905 {
2906         struct hw_event_resp *pPayload =
2907                 (struct hw_event_resp *)(piomb + 4);
2908         u32 lr_status_evt_portid =
2909                 le32_to_cpu(pPayload->lr_status_evt_portid);
2910         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2911
2912         u8 link_rate =
2913                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2914         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2915         u8 phy_id =
2916                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2917         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2918
2919         struct pm8001_port *port = &pm8001_ha->port[port_id];
2920         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2921         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2922         unsigned long flags;
2923         u8 deviceType = pPayload->sas_identify.dev_type;
2924         port->port_state = portstate;
2925         port->wide_port_phymap |= (1U << phy_id);
2926         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2927         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2928                 "portid:%d; phyid:%d; linkrate:%d; "
2929                 "portstate:%x; devicetype:%x\n",
2930                 port_id, phy_id, link_rate, portstate, deviceType));
2931
2932         switch (deviceType) {
2933         case SAS_PHY_UNUSED:
2934                 PM8001_MSG_DBG(pm8001_ha,
2935                         pm8001_printk("device type no device.\n"));
2936                 break;
2937         case SAS_END_DEVICE:
2938                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2939                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2940                         PHY_NOTIFY_ENABLE_SPINUP);
2941                 port->port_attached = 1;
2942                 pm8001_get_lrate_mode(phy, link_rate);
2943                 break;
2944         case SAS_EDGE_EXPANDER_DEVICE:
2945                 PM8001_MSG_DBG(pm8001_ha,
2946                         pm8001_printk("expander device.\n"));
2947                 port->port_attached = 1;
2948                 pm8001_get_lrate_mode(phy, link_rate);
2949                 break;
2950         case SAS_FANOUT_EXPANDER_DEVICE:
2951                 PM8001_MSG_DBG(pm8001_ha,
2952                         pm8001_printk("fanout expander device.\n"));
2953                 port->port_attached = 1;
2954                 pm8001_get_lrate_mode(phy, link_rate);
2955                 break;
2956         default:
2957                 PM8001_MSG_DBG(pm8001_ha,
2958                         pm8001_printk("unknown device type(%x)\n", deviceType));
2959                 break;
2960         }
2961         phy->phy_type |= PORT_TYPE_SAS;
2962         phy->identify.device_type = deviceType;
2963         phy->phy_attached = 1;
2964         if (phy->identify.device_type == SAS_END_DEVICE)
2965                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2966         else if (phy->identify.device_type != SAS_PHY_UNUSED)
2967                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2968         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2969         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2970         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2971         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2972                 sizeof(struct sas_identify_frame)-4);
2973         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2974         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2975         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2976         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2977                 mdelay(200);/*delay a moment to wait disk to spinup*/
2978         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2979 }
2980
2981 /**
2982  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2983  * @pm8001_ha: our hba card information
2984  * @piomb: IO message buffer
2985  */
2986 static void
2987 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2988 {
2989         struct hw_event_resp *pPayload =
2990                 (struct hw_event_resp *)(piomb + 4);
2991         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2992         u32 lr_status_evt_portid =
2993                 le32_to_cpu(pPayload->lr_status_evt_portid);
2994         u8 link_rate =
2995                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2996         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2997         u8 phy_id =
2998                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2999
3000         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3001
3002         struct pm8001_port *port = &pm8001_ha->port[port_id];
3003         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3004         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3005         unsigned long flags;
3006         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3007                 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3008                                 port_id, phy_id, link_rate, portstate));
3009
3010         port->port_state = portstate;
3011         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3012         port->port_attached = 1;
3013         pm8001_get_lrate_mode(phy, link_rate);
3014         phy->phy_type |= PORT_TYPE_SATA;
3015         phy->phy_attached = 1;
3016         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3017         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3018         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3019         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3020                 sizeof(struct dev_to_host_fis));
3021         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3022         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3023         phy->identify.device_type = SAS_SATA_DEV;
3024         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3025         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3026         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3027 }
3028
3029 /**
3030  * hw_event_phy_down -we should notify the libsas the phy is down.
3031  * @pm8001_ha: our hba card information
3032  * @piomb: IO message buffer
3033  */
3034 static void
3035 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3036 {
3037         struct hw_event_resp *pPayload =
3038                 (struct hw_event_resp *)(piomb + 4);
3039
3040         u32 lr_status_evt_portid =
3041                 le32_to_cpu(pPayload->lr_status_evt_portid);
3042         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3043         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3044         u8 phy_id =
3045                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3046         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3047
3048         struct pm8001_port *port = &pm8001_ha->port[port_id];
3049         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3050         u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3051         port->port_state = portstate;
3052         phy->identify.device_type = 0;
3053         phy->phy_attached = 0;
3054         switch (portstate) {
3055         case PORT_VALID:
3056                 break;
3057         case PORT_INVALID:
3058                 PM8001_MSG_DBG(pm8001_ha,
3059                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3060                 PM8001_MSG_DBG(pm8001_ha,
3061                         pm8001_printk(" Last phy Down and port invalid\n"));
3062                 if (port_sata) {
3063                         phy->phy_type = 0;
3064                         port->port_attached = 0;
3065                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3066                                         port_id, phy_id, 0, 0);
3067                 }
3068                 sas_phy_disconnected(&phy->sas_phy);
3069                 break;
3070         case PORT_IN_RESET:
3071                 PM8001_MSG_DBG(pm8001_ha,
3072                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3073                 break;
3074         case PORT_NOT_ESTABLISHED:
3075                 PM8001_MSG_DBG(pm8001_ha,
3076                         pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3077                 port->port_attached = 0;
3078                 break;
3079         case PORT_LOSTCOMM:
3080                 PM8001_MSG_DBG(pm8001_ha,
3081                         pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3082                 PM8001_MSG_DBG(pm8001_ha,
3083                         pm8001_printk(" Last phy Down and port invalid\n"));
3084                 if (port_sata) {
3085                         port->port_attached = 0;
3086                         phy->phy_type = 0;
3087                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3088                                         port_id, phy_id, 0, 0);
3089                 }
3090                 sas_phy_disconnected(&phy->sas_phy);
3091                 break;
3092         default:
3093                 port->port_attached = 0;
3094                 PM8001_MSG_DBG(pm8001_ha,
3095                         pm8001_printk(" Phy Down and(default) = 0x%x\n",
3096                         portstate));
3097                 break;
3098
3099         }
3100         if (port_sata && (portstate != PORT_IN_RESET)) {
3101                 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3102
3103                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3104         }
3105 }
3106
3107 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3108 {
3109         struct phy_start_resp *pPayload =
3110                 (struct phy_start_resp *)(piomb + 4);
3111         u32 status =
3112                 le32_to_cpu(pPayload->status);
3113         u32 phy_id =
3114                 le32_to_cpu(pPayload->phyid);
3115         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3116
3117         PM8001_INIT_DBG(pm8001_ha,
3118                 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3119                                 status, phy_id));
3120         if (status == 0) {
3121                 phy->phy_state = 1;
3122                 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3123                         complete(phy->enable_completion);
3124         }
3125         return 0;
3126
3127 }
3128
3129 /**
3130  * mpi_thermal_hw_event -The hw event has come.
3131  * @pm8001_ha: our hba card information
3132  * @piomb: IO message buffer
3133  */
3134 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3135 {
3136         struct thermal_hw_event *pPayload =
3137                 (struct thermal_hw_event *)(piomb + 4);
3138
3139         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3140         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3141
3142         if (thermal_event & 0x40) {
3143                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3144                         "Thermal Event: Local high temperature violated!\n"));
3145                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3146                         "Thermal Event: Measured local high temperature %d\n",
3147                                 ((rht_lht & 0xFF00) >> 8)));
3148         }
3149         if (thermal_event & 0x10) {
3150                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3151                         "Thermal Event: Remote high temperature violated!\n"));
3152                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3153                         "Thermal Event: Measured remote high temperature %d\n",
3154                                 ((rht_lht & 0xFF000000) >> 24)));
3155         }
3156         return 0;
3157 }
3158
3159 /**
3160  * mpi_hw_event -The hw event has come.
3161  * @pm8001_ha: our hba card information
3162  * @piomb: IO message buffer
3163  */
3164 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3165 {
3166         unsigned long flags, i;
3167         struct hw_event_resp *pPayload =
3168                 (struct hw_event_resp *)(piomb + 4);
3169         u32 lr_status_evt_portid =
3170                 le32_to_cpu(pPayload->lr_status_evt_portid);
3171         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3172         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3173         u8 phy_id =
3174                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3175         u16 eventType =
3176                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3177         u8 status =
3178                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3179         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3180         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3181         struct pm8001_port *port = &pm8001_ha->port[port_id];
3182         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3183         PM8001_MSG_DBG(pm8001_ha,
3184                 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3185                                 port_id, phy_id, eventType, status));
3186
3187         switch (eventType) {
3188
3189         case HW_EVENT_SAS_PHY_UP:
3190                 PM8001_MSG_DBG(pm8001_ha,
3191                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3192                 hw_event_sas_phy_up(pm8001_ha, piomb);
3193                 break;
3194         case HW_EVENT_SATA_PHY_UP:
3195                 PM8001_MSG_DBG(pm8001_ha,
3196                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3197                 hw_event_sata_phy_up(pm8001_ha, piomb);
3198                 break;
3199         case HW_EVENT_SATA_SPINUP_HOLD:
3200                 PM8001_MSG_DBG(pm8001_ha,
3201                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3202                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3203                 break;
3204         case HW_EVENT_PHY_DOWN:
3205                 PM8001_MSG_DBG(pm8001_ha,
3206                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3207                 hw_event_phy_down(pm8001_ha, piomb);
3208                 if (pm8001_ha->reset_in_progress) {
3209                         PM8001_MSG_DBG(pm8001_ha,
3210                                 pm8001_printk("Reset in progress\n"));
3211                         return 0;
3212                 }
3213                 phy->phy_attached = 0;
3214                 phy->phy_state = 0;
3215                 break;
3216         case HW_EVENT_PORT_INVALID:
3217                 PM8001_MSG_DBG(pm8001_ha,
3218                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3219                 sas_phy_disconnected(sas_phy);
3220                 phy->phy_attached = 0;
3221                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3222                 break;
3223         /* the broadcast change primitive received, tell the LIBSAS this event
3224         to revalidate the sas domain*/
3225         case HW_EVENT_BROADCAST_CHANGE:
3226                 PM8001_MSG_DBG(pm8001_ha,
3227                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3228                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3229                         port_id, phy_id, 1, 0);
3230                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3231                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3232                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3233                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3234                 break;
3235         case HW_EVENT_PHY_ERROR:
3236                 PM8001_MSG_DBG(pm8001_ha,
3237                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3238                 sas_phy_disconnected(&phy->sas_phy);
3239                 phy->phy_attached = 0;
3240                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3241                 break;
3242         case HW_EVENT_BROADCAST_EXP:
3243                 PM8001_MSG_DBG(pm8001_ha,
3244                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3245                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3246                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3247                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3248                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3249                 break;
3250         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3251                 PM8001_MSG_DBG(pm8001_ha,
3252                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3253                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3254                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3255                 break;
3256         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3257                 PM8001_MSG_DBG(pm8001_ha,
3258                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3259                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3260                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3261                         port_id, phy_id, 0, 0);
3262                 break;
3263         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3264                 PM8001_MSG_DBG(pm8001_ha,
3265                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3266                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3267                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3268                         port_id, phy_id, 0, 0);
3269                 break;
3270         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3271                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3272                                 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3273                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3274                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3275                         port_id, phy_id, 0, 0);
3276                 break;
3277         case HW_EVENT_MALFUNCTION:
3278                 PM8001_MSG_DBG(pm8001_ha,
3279                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3280                 break;
3281         case HW_EVENT_BROADCAST_SES:
3282                 PM8001_MSG_DBG(pm8001_ha,
3283                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3284                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3285                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3286                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3287                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3288                 break;
3289         case HW_EVENT_INBOUND_CRC_ERROR:
3290                 PM8001_MSG_DBG(pm8001_ha,
3291                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3292                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3293                         HW_EVENT_INBOUND_CRC_ERROR,
3294                         port_id, phy_id, 0, 0);
3295                 break;
3296         case HW_EVENT_HARD_RESET_RECEIVED:
3297                 PM8001_MSG_DBG(pm8001_ha,
3298                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3299                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3300                 break;
3301         case HW_EVENT_ID_FRAME_TIMEOUT:
3302                 PM8001_MSG_DBG(pm8001_ha,
3303                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3304                 sas_phy_disconnected(sas_phy);
3305                 phy->phy_attached = 0;
3306                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3307                 break;
3308         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3309                 PM8001_MSG_DBG(pm8001_ha,
3310                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3311                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3312                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3313                         port_id, phy_id, 0, 0);
3314                 sas_phy_disconnected(sas_phy);
3315                 phy->phy_attached = 0;
3316                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3317                 break;
3318         case HW_EVENT_PORT_RESET_TIMER_TMO:
3319                 PM8001_MSG_DBG(pm8001_ha,
3320                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3321                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3322                         port_id, phy_id, 0, 0);
3323                 sas_phy_disconnected(sas_phy);
3324                 phy->phy_attached = 0;
3325                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3326                 if (pm8001_ha->phy[phy_id].reset_completion) {
3327                         pm8001_ha->phy[phy_id].port_reset_status =
3328                                         PORT_RESET_TMO;
3329                         complete(pm8001_ha->phy[phy_id].reset_completion);
3330                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3331                 }
3332                 break;
3333         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3334                 PM8001_MSG_DBG(pm8001_ha,
3335                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3336                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3337                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3338                         port_id, phy_id, 0, 0);
3339                 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3340                         if (port->wide_port_phymap & (1 << i)) {
3341                                 phy = &pm8001_ha->phy[i];
3342                                 sas_ha->notify_phy_event(&phy->sas_phy,
3343                                                 PHYE_LOSS_OF_SIGNAL);
3344                                 port->wide_port_phymap &= ~(1 << i);
3345                         }
3346                 }
3347                 break;
3348         case HW_EVENT_PORT_RECOVER:
3349                 PM8001_MSG_DBG(pm8001_ha,
3350                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3351                 hw_event_port_recover(pm8001_ha, piomb);
3352                 break;
3353         case HW_EVENT_PORT_RESET_COMPLETE:
3354                 PM8001_MSG_DBG(pm8001_ha,
3355                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3356                 if (pm8001_ha->phy[phy_id].reset_completion) {
3357                         pm8001_ha->phy[phy_id].port_reset_status =
3358                                         PORT_RESET_SUCCESS;
3359                         complete(pm8001_ha->phy[phy_id].reset_completion);
3360                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3361                 }
3362                 break;
3363         case EVENT_BROADCAST_ASYNCH_EVENT:
3364                 PM8001_MSG_DBG(pm8001_ha,
3365                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3366                 break;
3367         default:
3368                 PM8001_MSG_DBG(pm8001_ha,
3369                         pm8001_printk("Unknown event type 0x%x\n", eventType));
3370                 break;
3371         }
3372         return 0;
3373 }
3374
3375 /**
3376  * mpi_phy_stop_resp - SPCv specific
3377  * @pm8001_ha: our hba card information
3378  * @piomb: IO message buffer
3379  */
3380 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3381 {
3382         struct phy_stop_resp *pPayload =
3383                 (struct phy_stop_resp *)(piomb + 4);
3384         u32 status =
3385                 le32_to_cpu(pPayload->status);
3386         u32 phyid =
3387                 le32_to_cpu(pPayload->phyid);
3388         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3389         PM8001_MSG_DBG(pm8001_ha,
3390                         pm8001_printk("phy:0x%x status:0x%x\n",
3391                                         phyid, status));
3392         if (status == 0)
3393                 phy->phy_state = 0;
3394         return 0;
3395 }
3396
3397 /**
3398  * mpi_set_controller_config_resp - SPCv specific
3399  * @pm8001_ha: our hba card information
3400  * @piomb: IO message buffer
3401  */
3402 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3403                         void *piomb)
3404 {
3405         struct set_ctrl_cfg_resp *pPayload =
3406                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3407         u32 status = le32_to_cpu(pPayload->status);
3408         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3409
3410         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3411                         "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3412                         status, err_qlfr_pgcd));
3413
3414         return 0;
3415 }
3416
3417 /**
3418  * mpi_get_controller_config_resp - SPCv specific
3419  * @pm8001_ha: our hba card information
3420  * @piomb: IO message buffer
3421  */
3422 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3423                         void *piomb)
3424 {
3425         PM8001_MSG_DBG(pm8001_ha,
3426                         pm8001_printk(" pm80xx_addition_functionality\n"));
3427
3428         return 0;
3429 }
3430
3431 /**
3432  * mpi_get_phy_profile_resp - SPCv specific
3433  * @pm8001_ha: our hba card information
3434  * @piomb: IO message buffer
3435  */
3436 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3437                         void *piomb)
3438 {
3439         PM8001_MSG_DBG(pm8001_ha,
3440                         pm8001_printk(" pm80xx_addition_functionality\n"));
3441
3442         return 0;
3443 }
3444
3445 /**
3446  * mpi_flash_op_ext_resp - SPCv specific
3447  * @pm8001_ha: our hba card information
3448  * @piomb: IO message buffer
3449  */
3450 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3451 {
3452         PM8001_MSG_DBG(pm8001_ha,
3453                         pm8001_printk(" pm80xx_addition_functionality\n"));
3454
3455         return 0;
3456 }
3457
3458 /**
3459  * mpi_set_phy_profile_resp - SPCv specific
3460  * @pm8001_ha: our hba card information
3461  * @piomb: IO message buffer
3462  */
3463 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3464                         void *piomb)
3465 {
3466         u8 page_code;
3467         struct set_phy_profile_resp *pPayload =
3468                 (struct set_phy_profile_resp *)(piomb + 4);
3469         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3470         u32 status = le32_to_cpu(pPayload->status);
3471
3472         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3473         if (status) {
3474                 /* status is FAILED */
3475                 PM8001_FAIL_DBG(pm8001_ha,
3476                         pm8001_printk("PhyProfile command failed  with status "
3477                         "0x%08X \n", status));
3478                 return -1;
3479         } else {
3480                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3481                         PM8001_FAIL_DBG(pm8001_ha,
3482                                 pm8001_printk("Invalid page code 0x%X\n",
3483                                         page_code));
3484                         return -1;
3485                 }
3486         }
3487         return 0;
3488 }
3489
3490 /**
3491  * mpi_kek_management_resp - SPCv specific
3492  * @pm8001_ha: our hba card information
3493  * @piomb: IO message buffer
3494  */
3495 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3496                         void *piomb)
3497 {
3498         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3499
3500         u32 status = le32_to_cpu(pPayload->status);
3501         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3502         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3503
3504         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3505                 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3506                 status, kidx_new_curr_ksop, err_qlfr));
3507
3508         return 0;
3509 }
3510
3511 /**
3512  * mpi_dek_management_resp - SPCv specific
3513  * @pm8001_ha: our hba card information
3514  * @piomb: IO message buffer
3515  */
3516 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3517                         void *piomb)
3518 {
3519         PM8001_MSG_DBG(pm8001_ha,
3520                         pm8001_printk(" pm80xx_addition_functionality\n"));
3521
3522         return 0;
3523 }
3524
3525 /**
3526  * ssp_coalesced_comp_resp - SPCv specific
3527  * @pm8001_ha: our hba card information
3528  * @piomb: IO message buffer
3529  */
3530 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3531                         void *piomb)
3532 {
3533         PM8001_MSG_DBG(pm8001_ha,
3534                         pm8001_printk(" pm80xx_addition_functionality\n"));
3535
3536         return 0;
3537 }
3538
3539 /**
3540  * process_one_iomb - process one outbound Queue memory block
3541  * @pm8001_ha: our hba card information
3542  * @piomb: IO message buffer
3543  */
3544 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3545 {
3546         __le32 pHeader = *(__le32 *)piomb;
3547         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3548
3549         switch (opc) {
3550         case OPC_OUB_ECHO:
3551                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3552                 break;
3553         case OPC_OUB_HW_EVENT:
3554                 PM8001_MSG_DBG(pm8001_ha,
3555                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3556                 mpi_hw_event(pm8001_ha, piomb);
3557                 break;
3558         case OPC_OUB_THERM_HW_EVENT:
3559                 PM8001_MSG_DBG(pm8001_ha,
3560                         pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3561                 mpi_thermal_hw_event(pm8001_ha, piomb);
3562                 break;
3563         case OPC_OUB_SSP_COMP:
3564                 PM8001_MSG_DBG(pm8001_ha,
3565                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3566                 mpi_ssp_completion(pm8001_ha, piomb);
3567                 break;
3568         case OPC_OUB_SMP_COMP:
3569                 PM8001_MSG_DBG(pm8001_ha,
3570                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3571                 mpi_smp_completion(pm8001_ha, piomb);
3572                 break;
3573         case OPC_OUB_LOCAL_PHY_CNTRL:
3574                 PM8001_MSG_DBG(pm8001_ha,
3575                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3576                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3577                 break;
3578         case OPC_OUB_DEV_REGIST:
3579                 PM8001_MSG_DBG(pm8001_ha,
3580                 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3581                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3582                 break;
3583         case OPC_OUB_DEREG_DEV:
3584                 PM8001_MSG_DBG(pm8001_ha,
3585                         pm8001_printk("unregister the device\n"));
3586                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3587                 break;
3588         case OPC_OUB_GET_DEV_HANDLE:
3589                 PM8001_MSG_DBG(pm8001_ha,
3590                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3591                 break;
3592         case OPC_OUB_SATA_COMP:
3593                 PM8001_MSG_DBG(pm8001_ha,
3594                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3595                 mpi_sata_completion(pm8001_ha, piomb);
3596                 break;
3597         case OPC_OUB_SATA_EVENT:
3598                 PM8001_MSG_DBG(pm8001_ha,
3599                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3600                 mpi_sata_event(pm8001_ha, piomb);
3601                 break;
3602         case OPC_OUB_SSP_EVENT:
3603                 PM8001_MSG_DBG(pm8001_ha,
3604                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3605                 mpi_ssp_event(pm8001_ha, piomb);
3606                 break;
3607         case OPC_OUB_DEV_HANDLE_ARRIV:
3608                 PM8001_MSG_DBG(pm8001_ha,
3609                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3610                 /*This is for target*/
3611                 break;
3612         case OPC_OUB_SSP_RECV_EVENT:
3613                 PM8001_MSG_DBG(pm8001_ha,
3614                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3615                 /*This is for target*/
3616                 break;
3617         case OPC_OUB_FW_FLASH_UPDATE:
3618                 PM8001_MSG_DBG(pm8001_ha,
3619                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3620                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3621                 break;
3622         case OPC_OUB_GPIO_RESPONSE:
3623                 PM8001_MSG_DBG(pm8001_ha,
3624                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3625                 break;
3626         case OPC_OUB_GPIO_EVENT:
3627                 PM8001_MSG_DBG(pm8001_ha,
3628                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3629                 break;
3630         case OPC_OUB_GENERAL_EVENT:
3631                 PM8001_MSG_DBG(pm8001_ha,
3632                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3633                 pm8001_mpi_general_event(pm8001_ha, piomb);
3634                 break;
3635         case OPC_OUB_SSP_ABORT_RSP:
3636                 PM8001_MSG_DBG(pm8001_ha,
3637                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3638                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3639                 break;
3640         case OPC_OUB_SATA_ABORT_RSP:
3641                 PM8001_MSG_DBG(pm8001_ha,
3642                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3643                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3644                 break;
3645         case OPC_OUB_SAS_DIAG_MODE_START_END:
3646                 PM8001_MSG_DBG(pm8001_ha,
3647                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3648                 break;
3649         case OPC_OUB_SAS_DIAG_EXECUTE:
3650                 PM8001_MSG_DBG(pm8001_ha,
3651                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3652                 break;
3653         case OPC_OUB_GET_TIME_STAMP:
3654                 PM8001_MSG_DBG(pm8001_ha,
3655                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3656                 break;
3657         case OPC_OUB_SAS_HW_EVENT_ACK:
3658                 PM8001_MSG_DBG(pm8001_ha,
3659                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3660                 break;
3661         case OPC_OUB_PORT_CONTROL:
3662                 PM8001_MSG_DBG(pm8001_ha,
3663                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3664                 break;
3665         case OPC_OUB_SMP_ABORT_RSP:
3666                 PM8001_MSG_DBG(pm8001_ha,
3667                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3668                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3669                 break;
3670         case OPC_OUB_GET_NVMD_DATA:
3671                 PM8001_MSG_DBG(pm8001_ha,
3672                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3673                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3674                 break;
3675         case OPC_OUB_SET_NVMD_DATA:
3676                 PM8001_MSG_DBG(pm8001_ha,
3677                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3678                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3679                 break;
3680         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3681                 PM8001_MSG_DBG(pm8001_ha,
3682                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3683                 break;
3684         case OPC_OUB_SET_DEVICE_STATE:
3685                 PM8001_MSG_DBG(pm8001_ha,
3686                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3687                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3688                 break;
3689         case OPC_OUB_GET_DEVICE_STATE:
3690                 PM8001_MSG_DBG(pm8001_ha,
3691                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3692                 break;
3693         case OPC_OUB_SET_DEV_INFO:
3694                 PM8001_MSG_DBG(pm8001_ha,
3695                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3696                 break;
3697         /* spcv specifc commands */
3698         case OPC_OUB_PHY_START_RESP:
3699                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3700                         "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3701                 mpi_phy_start_resp(pm8001_ha, piomb);
3702                 break;
3703         case OPC_OUB_PHY_STOP_RESP:
3704                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3705                         "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3706                 mpi_phy_stop_resp(pm8001_ha, piomb);
3707                 break;
3708         case OPC_OUB_SET_CONTROLLER_CONFIG:
3709                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3710                         "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3711                 mpi_set_controller_config_resp(pm8001_ha, piomb);
3712                 break;
3713         case OPC_OUB_GET_CONTROLLER_CONFIG:
3714                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3715                         "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3716                 mpi_get_controller_config_resp(pm8001_ha, piomb);
3717                 break;
3718         case OPC_OUB_GET_PHY_PROFILE:
3719                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3720                         "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3721                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3722                 break;
3723         case OPC_OUB_FLASH_OP_EXT:
3724                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3725                         "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3726                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3727                 break;
3728         case OPC_OUB_SET_PHY_PROFILE:
3729                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3730                         "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3731                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3732                 break;
3733         case OPC_OUB_KEK_MANAGEMENT_RESP:
3734                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3735                         "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3736                 mpi_kek_management_resp(pm8001_ha, piomb);
3737                 break;
3738         case OPC_OUB_DEK_MANAGEMENT_RESP:
3739                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3740                         "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3741                 mpi_dek_management_resp(pm8001_ha, piomb);
3742                 break;
3743         case OPC_OUB_SSP_COALESCED_COMP_RESP:
3744                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3745                         "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3746                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3747                 break;
3748         default:
3749                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3750                         "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3751                 break;
3752         }
3753 }
3754
3755 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3756 {
3757         struct outbound_queue_table *circularQ;
3758         void *pMsg1 = NULL;
3759         u8 uninitialized_var(bc);
3760         u32 ret = MPI_IO_STATUS_FAIL;
3761         unsigned long flags;
3762
3763         spin_lock_irqsave(&pm8001_ha->lock, flags);
3764         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3765         do {
3766                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3767                 if (MPI_IO_STATUS_SUCCESS == ret) {
3768                         /* process the outbound message */
3769                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3770                         /* free the message from the outbound circular buffer */
3771                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3772                                                         circularQ, bc);
3773                 }
3774                 if (MPI_IO_STATUS_BUSY == ret) {
3775                         /* Update the producer index from SPC */
3776                         circularQ->producer_index =
3777                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3778                         if (le32_to_cpu(circularQ->producer_index) ==
3779                                 circularQ->consumer_idx)
3780                                 /* OQ is empty */
3781                                 break;
3782                 }
3783         } while (1);
3784         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3785         return ret;
3786 }
3787
3788 /* PCI_DMA_... to our direction translation. */
3789 static const u8 data_dir_flags[] = {
3790         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3791         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3792         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3793         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3794 };
3795
3796 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3797                         struct smp_req *psmp_cmd, int mode, int length)
3798 {
3799         psmp_cmd->tag = hTag;
3800         psmp_cmd->device_id = cpu_to_le32(deviceID);
3801         if (mode == SMP_DIRECT) {
3802                 length = length - 4; /* subtract crc */
3803                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3804         } else {
3805                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3806         }
3807 }
3808
3809 /**
3810  * pm8001_chip_smp_req - send a SMP task to FW
3811  * @pm8001_ha: our hba card information.
3812  * @ccb: the ccb information this request used.
3813  */
3814 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3815         struct pm8001_ccb_info *ccb)
3816 {
3817         int elem, rc;
3818         struct sas_task *task = ccb->task;
3819         struct domain_device *dev = task->dev;
3820         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3821         struct scatterlist *sg_req, *sg_resp;
3822         u32 req_len, resp_len;
3823         struct smp_req smp_cmd;
3824         u32 opc;
3825         struct inbound_queue_table *circularQ;
3826         char *preq_dma_addr = NULL;
3827         __le64 tmp_addr;
3828         u32 i, length;
3829
3830         memset(&smp_cmd, 0, sizeof(smp_cmd));
3831         /*
3832          * DMA-map SMP request, response buffers
3833          */
3834         sg_req = &task->smp_task.smp_req;
3835         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3836         if (!elem)
3837                 return -ENOMEM;
3838         req_len = sg_dma_len(sg_req);
3839
3840         sg_resp = &task->smp_task.smp_resp;
3841         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3842         if (!elem) {
3843                 rc = -ENOMEM;
3844                 goto err_out;
3845         }
3846         resp_len = sg_dma_len(sg_resp);
3847         /* must be in dwords */
3848         if ((req_len & 0x3) || (resp_len & 0x3)) {
3849                 rc = -EINVAL;
3850                 goto err_out_2;
3851         }
3852
3853         opc = OPC_INB_SMP_REQUEST;
3854         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3855         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3856
3857         length = sg_req->length;
3858         PM8001_IO_DBG(pm8001_ha,
3859                 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3860         if (!(length - 8))
3861                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3862         else
3863                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3864
3865
3866         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3867         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3868
3869         /* INDIRECT MODE command settings. Use DMA */
3870         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3871                 PM8001_IO_DBG(pm8001_ha,
3872                         pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3873                 /* for SPCv indirect mode. Place the top 4 bytes of
3874                  * SMP Request header here. */
3875                 for (i = 0; i < 4; i++)
3876                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3877                 /* exclude top 4 bytes for SMP req header */
3878                 smp_cmd.long_smp_req.long_req_addr =
3879                         cpu_to_le64((u64)sg_dma_address
3880                                 (&task->smp_task.smp_req) + 4);
3881                 /* exclude 4 bytes for SMP req header and CRC */
3882                 smp_cmd.long_smp_req.long_req_size =
3883                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3884                 smp_cmd.long_smp_req.long_resp_addr =
3885                                 cpu_to_le64((u64)sg_dma_address
3886                                         (&task->smp_task.smp_resp));
3887                 smp_cmd.long_smp_req.long_resp_size =
3888                                 cpu_to_le32((u32)sg_dma_len
3889                                         (&task->smp_task.smp_resp)-4);
3890         } else { /* DIRECT MODE */
3891                 smp_cmd.long_smp_req.long_req_addr =
3892                         cpu_to_le64((u64)sg_dma_address
3893                                         (&task->smp_task.smp_req));
3894                 smp_cmd.long_smp_req.long_req_size =
3895                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3896                 smp_cmd.long_smp_req.long_resp_addr =
3897                         cpu_to_le64((u64)sg_dma_address
3898                                 (&task->smp_task.smp_resp));
3899                 smp_cmd.long_smp_req.long_resp_size =
3900                         cpu_to_le32
3901                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3902         }
3903         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3904                 PM8001_IO_DBG(pm8001_ha,
3905                         pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3906                 for (i = 0; i < length; i++)
3907                         if (i < 16) {
3908                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3909                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3910                                         "Byte[%d]:%x (DMA data:%x)\n",
3911                                         i, smp_cmd.smp_req16[i],
3912                                         *(preq_dma_addr)));
3913                         } else {
3914                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3915                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3916                                         "Byte[%d]:%x (DMA data:%x)\n",
3917                                         i, smp_cmd.smp_req[i],
3918                                         *(preq_dma_addr)));
3919                         }
3920         }
3921
3922         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3923                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3924         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3925                                         (u32 *)&smp_cmd, 0);
3926         if (rc)
3927                 goto err_out_2;
3928         return 0;
3929
3930 err_out_2:
3931         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3932                         PCI_DMA_FROMDEVICE);
3933 err_out:
3934         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3935                         PCI_DMA_TODEVICE);
3936         return rc;
3937 }
3938
3939 static int check_enc_sas_cmd(struct sas_task *task)
3940 {
3941         u8 cmd = task->ssp_task.cmd->cmnd[0];
3942
3943         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3944                 return 1;
3945         else
3946                 return 0;
3947 }
3948
3949 static int check_enc_sat_cmd(struct sas_task *task)
3950 {
3951         int ret = 0;
3952         switch (task->ata_task.fis.command) {
3953         case ATA_CMD_FPDMA_READ:
3954         case ATA_CMD_READ_EXT:
3955         case ATA_CMD_READ:
3956         case ATA_CMD_FPDMA_WRITE:
3957         case ATA_CMD_WRITE_EXT:
3958         case ATA_CMD_WRITE:
3959         case ATA_CMD_PIO_READ:
3960         case ATA_CMD_PIO_READ_EXT:
3961         case ATA_CMD_PIO_WRITE:
3962         case ATA_CMD_PIO_WRITE_EXT:
3963                 ret = 1;
3964                 break;
3965         default:
3966                 ret = 0;
3967                 break;
3968         }
3969         return ret;
3970 }
3971
3972 /**
3973  * pm80xx_chip_ssp_io_req - send a SSP task to FW
3974  * @pm8001_ha: our hba card information.
3975  * @ccb: the ccb information this request used.
3976  */
3977 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3978         struct pm8001_ccb_info *ccb)
3979 {
3980         struct sas_task *task = ccb->task;
3981         struct domain_device *dev = task->dev;
3982         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3983         struct ssp_ini_io_start_req ssp_cmd;
3984         u32 tag = ccb->ccb_tag;
3985         int ret;
3986         u64 phys_addr, start_addr, end_addr;
3987         u32 end_addr_high, end_addr_low;
3988         struct inbound_queue_table *circularQ;
3989         u32 q_index;
3990         u32 opc = OPC_INB_SSPINIIOSTART;
3991         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3992         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3993         /* data address domain added for spcv; set to 0 by host,
3994          * used internally by controller
3995          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3996          */
3997         ssp_cmd.dad_dir_m_tlr =
3998                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3999         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4000         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4001         ssp_cmd.tag = cpu_to_le32(tag);
4002         if (task->ssp_task.enable_first_burst)
4003                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4004         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4005         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4006         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4007                        task->ssp_task.cmd->cmd_len);
4008         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4009         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4010
4011         /* Check if encryption is set */
4012         if (pm8001_ha->chip->encrypt &&
4013                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4014                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4015                         "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4016                         task->ssp_task.cmd->cmnd[0]));
4017                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4018                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4019                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4020                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4021
4022                 /* fill in PRD (scatter/gather) table, if any */
4023                 if (task->num_scatter > 1) {
4024                         pm8001_chip_make_sg(task->scatter,
4025                                                 ccb->n_elem, ccb->buf_prd);
4026                         phys_addr = ccb->ccb_dma_handle +
4027                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4028                         ssp_cmd.enc_addr_low =
4029                                 cpu_to_le32(lower_32_bits(phys_addr));
4030                         ssp_cmd.enc_addr_high =
4031                                 cpu_to_le32(upper_32_bits(phys_addr));
4032                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4033                 } else if (task->num_scatter == 1) {
4034                         u64 dma_addr = sg_dma_address(task->scatter);
4035                         ssp_cmd.enc_addr_low =
4036                                 cpu_to_le32(lower_32_bits(dma_addr));
4037                         ssp_cmd.enc_addr_high =
4038                                 cpu_to_le32(upper_32_bits(dma_addr));
4039                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4040                         ssp_cmd.enc_esgl = 0;
4041                         /* Check 4G Boundary */
4042                         start_addr = cpu_to_le64(dma_addr);
4043                         end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4044                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4045                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4046                         if (end_addr_high != ssp_cmd.enc_addr_high) {
4047                                 PM8001_FAIL_DBG(pm8001_ha,
4048                                         pm8001_printk("The sg list address "
4049                                         "start_addr=0x%016llx data_len=0x%x "
4050                                         "end_addr_high=0x%08x end_addr_low="
4051                                         "0x%08x has crossed 4G boundary\n",
4052                                                 start_addr, ssp_cmd.enc_len,
4053                                                 end_addr_high, end_addr_low));
4054                                 pm8001_chip_make_sg(task->scatter, 1,
4055                                         ccb->buf_prd);
4056                                 phys_addr = ccb->ccb_dma_handle +
4057                                         offsetof(struct pm8001_ccb_info,
4058                                                 buf_prd[0]);
4059                                 ssp_cmd.enc_addr_low =
4060                                         cpu_to_le32(lower_32_bits(phys_addr));
4061                                 ssp_cmd.enc_addr_high =
4062                                         cpu_to_le32(upper_32_bits(phys_addr));
4063                                 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4064                         }
4065                 } else if (task->num_scatter == 0) {
4066                         ssp_cmd.enc_addr_low = 0;
4067                         ssp_cmd.enc_addr_high = 0;
4068                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4069                         ssp_cmd.enc_esgl = 0;
4070                 }
4071                 /* XTS mode. All other fields are 0 */
4072                 ssp_cmd.key_cmode = 0x6 << 4;
4073                 /* set tweak values. Should be the start lba */
4074                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4075                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4076                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4077                                                 (task->ssp_task.cmd->cmnd[5]));
4078         } else {
4079                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4080                         "Sending Normal SAS command 0x%x inb q %x\n",
4081                         task->ssp_task.cmd->cmnd[0], q_index));
4082                 /* fill in PRD (scatter/gather) table, if any */
4083                 if (task->num_scatter > 1) {
4084                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4085                                         ccb->buf_prd);
4086                         phys_addr = ccb->ccb_dma_handle +
4087                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4088                         ssp_cmd.addr_low =
4089                                 cpu_to_le32(lower_32_bits(phys_addr));
4090                         ssp_cmd.addr_high =
4091                                 cpu_to_le32(upper_32_bits(phys_addr));
4092                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4093                 } else if (task->num_scatter == 1) {
4094                         u64 dma_addr = sg_dma_address(task->scatter);
4095                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4096                         ssp_cmd.addr_high =
4097                                 cpu_to_le32(upper_32_bits(dma_addr));
4098                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4099                         ssp_cmd.esgl = 0;
4100                         /* Check 4G Boundary */
4101                         start_addr = cpu_to_le64(dma_addr);
4102                         end_addr = (start_addr + ssp_cmd.len) - 1;
4103                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4104                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4105                         if (end_addr_high != ssp_cmd.addr_high) {
4106                                 PM8001_FAIL_DBG(pm8001_ha,
4107                                         pm8001_printk("The sg list address "
4108                                         "start_addr=0x%016llx data_len=0x%x "
4109                                         "end_addr_high=0x%08x end_addr_low="
4110                                         "0x%08x has crossed 4G boundary\n",
4111                                                  start_addr, ssp_cmd.len,
4112                                                  end_addr_high, end_addr_low));
4113                                 pm8001_chip_make_sg(task->scatter, 1,
4114                                         ccb->buf_prd);
4115                                 phys_addr = ccb->ccb_dma_handle +
4116                                         offsetof(struct pm8001_ccb_info,
4117                                                  buf_prd[0]);
4118                                 ssp_cmd.addr_low =
4119                                         cpu_to_le32(lower_32_bits(phys_addr));
4120                                 ssp_cmd.addr_high =
4121                                         cpu_to_le32(upper_32_bits(phys_addr));
4122                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4123                         }
4124                 } else if (task->num_scatter == 0) {
4125                         ssp_cmd.addr_low = 0;
4126                         ssp_cmd.addr_high = 0;
4127                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4128                         ssp_cmd.esgl = 0;
4129                 }
4130         }
4131         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4132         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4133                                                 &ssp_cmd, q_index);
4134         return ret;
4135 }
4136
4137 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4138         struct pm8001_ccb_info *ccb)
4139 {
4140         struct sas_task *task = ccb->task;
4141         struct domain_device *dev = task->dev;
4142         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4143         u32 tag = ccb->ccb_tag;
4144         int ret;
4145         u32 q_index;
4146         struct sata_start_req sata_cmd;
4147         u32 hdr_tag, ncg_tag = 0;
4148         u64 phys_addr, start_addr, end_addr;
4149         u32 end_addr_high, end_addr_low;
4150         u32 ATAP = 0x0;
4151         u32 dir;
4152         struct inbound_queue_table *circularQ;
4153         unsigned long flags;
4154         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4155         memset(&sata_cmd, 0, sizeof(sata_cmd));
4156         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4157         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4158
4159         if (task->data_dir == PCI_DMA_NONE) {
4160                 ATAP = 0x04; /* no data*/
4161                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4162         } else if (likely(!task->ata_task.device_control_reg_update)) {
4163                 if (task->ata_task.dma_xfer) {
4164                         ATAP = 0x06; /* DMA */
4165                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4166                 } else {
4167                         ATAP = 0x05; /* PIO*/
4168                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4169                 }
4170                 if (task->ata_task.use_ncq &&
4171                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4172                         ATAP = 0x07; /* FPDMA */
4173                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4174                 }
4175         }
4176         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4177                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4178                 ncg_tag = hdr_tag;
4179         }
4180         dir = data_dir_flags[task->data_dir] << 8;
4181         sata_cmd.tag = cpu_to_le32(tag);
4182         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4183         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4184
4185         sata_cmd.sata_fis = task->ata_task.fis;
4186         if (likely(!task->ata_task.device_control_reg_update))
4187                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4188         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4189
4190         /* Check if encryption is set */
4191         if (pm8001_ha->chip->encrypt &&
4192                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4193                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4194                         "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4195                         sata_cmd.sata_fis.command));
4196                 opc = OPC_INB_SATA_DIF_ENC_IO;
4197
4198                 /* set encryption bit */
4199                 sata_cmd.ncqtag_atap_dir_m_dad =
4200                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4201                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4202                                                         /* dad (bit 0-1) is 0 */
4203                 /* fill in PRD (scatter/gather) table, if any */
4204                 if (task->num_scatter > 1) {
4205                         pm8001_chip_make_sg(task->scatter,
4206                                                 ccb->n_elem, ccb->buf_prd);
4207                         phys_addr = ccb->ccb_dma_handle +
4208                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4209                         sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4210                         sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4211                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4212                 } else if (task->num_scatter == 1) {
4213                         u64 dma_addr = sg_dma_address(task->scatter);
4214                         sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4215                         sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4216                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4217                         sata_cmd.enc_esgl = 0;
4218                         /* Check 4G Boundary */
4219                         start_addr = cpu_to_le64(dma_addr);
4220                         end_addr = (start_addr + sata_cmd.enc_len) - 1;
4221                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4222                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4223                         if (end_addr_high != sata_cmd.enc_addr_high) {
4224                                 PM8001_FAIL_DBG(pm8001_ha,
4225                                         pm8001_printk("The sg list address "
4226                                         "start_addr=0x%016llx data_len=0x%x "
4227                                         "end_addr_high=0x%08x end_addr_low"
4228                                         "=0x%08x has crossed 4G boundary\n",
4229                                                 start_addr, sata_cmd.enc_len,
4230                                                 end_addr_high, end_addr_low));
4231                                 pm8001_chip_make_sg(task->scatter, 1,
4232                                         ccb->buf_prd);
4233                                 phys_addr = ccb->ccb_dma_handle +
4234                                                 offsetof(struct pm8001_ccb_info,
4235                                                 buf_prd[0]);
4236                                 sata_cmd.enc_addr_low =
4237                                         lower_32_bits(phys_addr);
4238                                 sata_cmd.enc_addr_high =
4239                                         upper_32_bits(phys_addr);
4240                                 sata_cmd.enc_esgl =
4241                                         cpu_to_le32(1 << 31);
4242                         }
4243                 } else if (task->num_scatter == 0) {
4244                         sata_cmd.enc_addr_low = 0;
4245                         sata_cmd.enc_addr_high = 0;
4246                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4247                         sata_cmd.enc_esgl = 0;
4248                 }
4249                 /* XTS mode. All other fields are 0 */
4250                 sata_cmd.key_index_mode = 0x6 << 4;
4251                 /* set tweak values. Should be the start lba */
4252                 sata_cmd.twk_val0 =
4253                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4254                                         (sata_cmd.sata_fis.lbah << 16) |
4255                                         (sata_cmd.sata_fis.lbam << 8) |
4256                                         (sata_cmd.sata_fis.lbal));
4257                 sata_cmd.twk_val1 =
4258                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4259                                          (sata_cmd.sata_fis.lbam_exp));
4260         } else {
4261                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4262                         "Sending Normal SATA command 0x%x inb %x\n",
4263                         sata_cmd.sata_fis.command, q_index));
4264                 /* dad (bit 0-1) is 0 */
4265                 sata_cmd.ncqtag_atap_dir_m_dad =
4266                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4267                                         ((ATAP & 0x3f) << 10) | dir);
4268
4269                 /* fill in PRD (scatter/gather) table, if any */
4270                 if (task->num_scatter > 1) {
4271                         pm8001_chip_make_sg(task->scatter,
4272                                         ccb->n_elem, ccb->buf_prd);
4273                         phys_addr = ccb->ccb_dma_handle +
4274                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4275                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4276                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4277                         sata_cmd.esgl = cpu_to_le32(1 << 31);
4278                 } else if (task->num_scatter == 1) {
4279                         u64 dma_addr = sg_dma_address(task->scatter);
4280                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4281                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4282                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4283                         sata_cmd.esgl = 0;
4284                         /* Check 4G Boundary */
4285                         start_addr = cpu_to_le64(dma_addr);
4286                         end_addr = (start_addr + sata_cmd.len) - 1;
4287                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4288                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4289                         if (end_addr_high != sata_cmd.addr_high) {
4290                                 PM8001_FAIL_DBG(pm8001_ha,
4291                                         pm8001_printk("The sg list address "
4292                                         "start_addr=0x%016llx data_len=0x%x"
4293                                         "end_addr_high=0x%08x end_addr_low="
4294                                         "0x%08x has crossed 4G boundary\n",
4295                                                 start_addr, sata_cmd.len,
4296                                                 end_addr_high, end_addr_low));
4297                                 pm8001_chip_make_sg(task->scatter, 1,
4298                                         ccb->buf_prd);
4299                                 phys_addr = ccb->ccb_dma_handle +
4300                                         offsetof(struct pm8001_ccb_info,
4301                                         buf_prd[0]);
4302                                 sata_cmd.addr_low =
4303                                         lower_32_bits(phys_addr);
4304                                 sata_cmd.addr_high =
4305                                         upper_32_bits(phys_addr);
4306                                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4307                         }
4308                 } else if (task->num_scatter == 0) {
4309                         sata_cmd.addr_low = 0;
4310                         sata_cmd.addr_high = 0;
4311                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4312                         sata_cmd.esgl = 0;
4313                 }
4314                         /* scsi cdb */
4315                         sata_cmd.atapi_scsi_cdb[0] =
4316                                 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4317                                 (task->ata_task.atapi_packet[1] << 8) |
4318                                 (task->ata_task.atapi_packet[2] << 16) |
4319                                 (task->ata_task.atapi_packet[3] << 24)));
4320                         sata_cmd.atapi_scsi_cdb[1] =
4321                                 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4322                                 (task->ata_task.atapi_packet[5] << 8) |
4323                                 (task->ata_task.atapi_packet[6] << 16) |
4324                                 (task->ata_task.atapi_packet[7] << 24)));
4325                         sata_cmd.atapi_scsi_cdb[2] =
4326                                 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4327                                 (task->ata_task.atapi_packet[9] << 8) |
4328                                 (task->ata_task.atapi_packet[10] << 16) |
4329                                 (task->ata_task.atapi_packet[11] << 24)));
4330                         sata_cmd.atapi_scsi_cdb[3] =
4331                                 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4332                                 (task->ata_task.atapi_packet[13] << 8) |
4333                                 (task->ata_task.atapi_packet[14] << 16) |
4334                                 (task->ata_task.atapi_packet[15] << 24)));
4335         }
4336
4337         /* Check for read log for failed drive and return */
4338         if (sata_cmd.sata_fis.command == 0x2f) {
4339                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4340                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4341                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4342                         struct task_status_struct *ts;
4343
4344                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4345                         ts = &task->task_status;
4346
4347                         spin_lock_irqsave(&task->task_state_lock, flags);
4348                         ts->resp = SAS_TASK_COMPLETE;
4349                         ts->stat = SAM_STAT_GOOD;
4350                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4351                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4352                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4353                         if (unlikely((task->task_state_flags &
4354                                         SAS_TASK_STATE_ABORTED))) {
4355                                 spin_unlock_irqrestore(&task->task_state_lock,
4356                                                         flags);
4357                                 PM8001_FAIL_DBG(pm8001_ha,
4358                                         pm8001_printk("task 0x%p resp 0x%x "
4359                                         " stat 0x%x but aborted by upper layer "
4360                                         "\n", task, ts->resp, ts->stat));
4361                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4362                                 return 0;
4363                         } else {
4364                                 spin_unlock_irqrestore(&task->task_state_lock,
4365                                                         flags);
4366                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4367                                                                 ccb, tag);
4368                                 return 0;
4369                         }
4370                 }
4371         }
4372         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4373         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4374                                                 &sata_cmd, q_index);
4375         return ret;
4376 }
4377
4378 /**
4379  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4380  * @pm8001_ha: our hba card information.
4381  * @num: the inbound queue number
4382  * @phy_id: the phy id which we wanted to start up.
4383  */
4384 static int
4385 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4386 {
4387         struct phy_start_req payload;
4388         struct inbound_queue_table *circularQ;
4389         int ret;
4390         u32 tag = 0x01;
4391         u32 opcode = OPC_INB_PHYSTART;
4392         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4393         memset(&payload, 0, sizeof(payload));
4394         payload.tag = cpu_to_le32(tag);
4395
4396         PM8001_INIT_DBG(pm8001_ha,
4397                 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4398         /*
4399          ** [0:7]       PHY Identifier
4400          ** [8:11]      link rate 1.5G, 3G, 6G
4401          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4402          ** [14]        0b disable spin up hold; 1b enable spin up hold
4403          ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4404          */
4405         if (!IS_SPCV_12G(pm8001_ha->pdev))
4406                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4407                                 LINKMODE_AUTO | LINKRATE_15 |
4408                                 LINKRATE_30 | LINKRATE_60 | phy_id);
4409         else
4410                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4411                                 LINKMODE_AUTO | LINKRATE_15 |
4412                                 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4413                                 phy_id);
4414
4415         /* SSC Disable and SAS Analog ST configuration */
4416         /**
4417         payload.ase_sh_lm_slr_phyid =
4418                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4419                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4420                 phy_id);
4421         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4422         **/
4423
4424         payload.sas_identify.dev_type = SAS_END_DEVICE;
4425         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4426         memcpy(payload.sas_identify.sas_addr,
4427           &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
4428         payload.sas_identify.phy_id = phy_id;
4429         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4430         return ret;
4431 }
4432
4433 /**
4434  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4435  * @pm8001_ha: our hba card information.
4436  * @num: the inbound queue number
4437  * @phy_id: the phy id which we wanted to start up.
4438  */
4439 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4440         u8 phy_id)
4441 {
4442         struct phy_stop_req payload;
4443         struct inbound_queue_table *circularQ;
4444         int ret;
4445         u32 tag = 0x01;
4446         u32 opcode = OPC_INB_PHYSTOP;
4447         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4448         memset(&payload, 0, sizeof(payload));
4449         payload.tag = cpu_to_le32(tag);
4450         payload.phy_id = cpu_to_le32(phy_id);
4451         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4452         return ret;
4453 }
4454
4455 /**
4456  * see comments on pm8001_mpi_reg_resp.
4457  */
4458 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4459         struct pm8001_device *pm8001_dev, u32 flag)
4460 {
4461         struct reg_dev_req payload;
4462         u32     opc;
4463         u32 stp_sspsmp_sata = 0x4;
4464         struct inbound_queue_table *circularQ;
4465         u32 linkrate, phy_id;
4466         int rc, tag = 0xdeadbeef;
4467         struct pm8001_ccb_info *ccb;
4468         u8 retryFlag = 0x1;
4469         u16 firstBurstSize = 0;
4470         u16 ITNT = 2000;
4471         struct domain_device *dev = pm8001_dev->sas_device;
4472         struct domain_device *parent_dev = dev->parent;
4473         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4474
4475         memset(&payload, 0, sizeof(payload));
4476         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4477         if (rc)
4478                 return rc;
4479         ccb = &pm8001_ha->ccb_info[tag];
4480         ccb->device = pm8001_dev;
4481         ccb->ccb_tag = tag;
4482         payload.tag = cpu_to_le32(tag);
4483
4484         if (flag == 1) {
4485                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4486         } else {
4487                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4488                         stp_sspsmp_sata = 0x00; /* stp*/
4489                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4490                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4491                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4492                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4493         }
4494         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4495                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4496         else
4497                 phy_id = pm8001_dev->attached_phy;
4498
4499         opc = OPC_INB_REG_DEV;
4500
4501         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4502                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4503
4504         payload.phyid_portid =
4505                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4506                 ((phy_id & 0xFF) << 8));
4507
4508         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4509                 ((linkrate & 0x0F) << 24) |
4510                 ((stp_sspsmp_sata & 0x03) << 28));
4511         payload.firstburstsize_ITNexustimeout =
4512                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4513
4514         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4515                 SAS_ADDR_SIZE);
4516
4517         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4518         if (rc)
4519                 pm8001_tag_free(pm8001_ha, tag);
4520
4521         return rc;
4522 }
4523
4524 /**
4525  * pm80xx_chip_phy_ctl_req - support the local phy operation
4526  * @pm8001_ha: our hba card information.
4527  * @num: the inbound queue number
4528  * @phy_id: the phy id which we wanted to operate
4529  * @phy_op:
4530  */
4531 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4532         u32 phyId, u32 phy_op)
4533 {
4534         u32 tag;
4535         int rc;
4536         struct local_phy_ctl_req payload;
4537         struct inbound_queue_table *circularQ;
4538         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4539         memset(&payload, 0, sizeof(payload));
4540         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4541         if (rc)
4542                 return rc;
4543         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4544         payload.tag = cpu_to_le32(tag);
4545         payload.phyop_phyid =
4546                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4547         return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4548 }
4549
4550 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4551 {
4552         u32 value;
4553 #ifdef PM8001_USE_MSIX
4554         return 1;
4555 #endif
4556         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4557         if (value)
4558                 return 1;
4559         return 0;
4560
4561 }
4562
4563 /**
4564  * pm8001_chip_isr - PM8001 isr handler.
4565  * @pm8001_ha: our hba card information.
4566  * @irq: irq number.
4567  * @stat: stat.
4568  */
4569 static irqreturn_t
4570 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4571 {
4572         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4573         process_oq(pm8001_ha, vec);
4574         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4575         return IRQ_HANDLED;
4576 }
4577
4578 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4579         u32 operation, u32 phyid, u32 length, u32 *buf)
4580 {
4581         u32 tag , i, j = 0;
4582         int rc;
4583         struct set_phy_profile_req payload;
4584         struct inbound_queue_table *circularQ;
4585         u32 opc = OPC_INB_SET_PHY_PROFILE;
4586
4587         memset(&payload, 0, sizeof(payload));
4588         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4589         if (rc)
4590                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4591         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4592         payload.tag = cpu_to_le32(tag);
4593         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
4594         PM8001_INIT_DBG(pm8001_ha,
4595                 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4596                         payload.ppc_phyid, length));
4597         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4598                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
4599                 j++;
4600         }
4601         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4602         if (rc)
4603                 pm8001_tag_free(pm8001_ha, tag);
4604 }
4605
4606 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4607         u32 length, u8 *buf)
4608 {
4609         u32 page_code, i;
4610
4611         page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4612         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4613                 mpi_set_phy_profile_req(pm8001_ha,
4614                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4615                 length = length + PHY_DWORD_LENGTH;
4616         }
4617         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4618 }
4619
4620 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4621                 u32 phy, u32 length, u32 *buf)
4622 {
4623         u32 tag, opc;
4624         int rc, i;
4625         struct set_phy_profile_req payload;
4626         struct inbound_queue_table *circularQ;
4627
4628         memset(&payload, 0, sizeof(payload));
4629
4630         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4631         if (rc)
4632                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4633
4634         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4635         opc = OPC_INB_SET_PHY_PROFILE;
4636
4637         payload.tag = cpu_to_le32(tag);
4638         payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4639                                 | (phy & 0xFF));
4640
4641         for (i = 0; i < length; i++)
4642                 payload.reserved[i] = cpu_to_le32(*(buf + i));
4643
4644         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4645         if (rc)
4646                 pm8001_tag_free(pm8001_ha, tag);
4647
4648         PM8001_INIT_DBG(pm8001_ha,
4649                 pm8001_printk("PHY %d settings applied", phy));
4650 }
4651 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4652         .name                   = "pmc80xx",
4653         .chip_init              = pm80xx_chip_init,
4654         .chip_soft_rst          = pm80xx_chip_soft_rst,
4655         .chip_rst               = pm80xx_hw_chip_rst,
4656         .chip_iounmap           = pm8001_chip_iounmap,
4657         .isr                    = pm80xx_chip_isr,
4658         .is_our_interupt        = pm80xx_chip_is_our_interupt,
4659         .isr_process_oq         = process_oq,
4660         .interrupt_enable       = pm80xx_chip_interrupt_enable,
4661         .interrupt_disable      = pm80xx_chip_interrupt_disable,
4662         .make_prd               = pm8001_chip_make_sg,
4663         .smp_req                = pm80xx_chip_smp_req,
4664         .ssp_io_req             = pm80xx_chip_ssp_io_req,
4665         .sata_req               = pm80xx_chip_sata_req,
4666         .phy_start_req          = pm80xx_chip_phy_start_req,
4667         .phy_stop_req           = pm80xx_chip_phy_stop_req,
4668         .reg_dev_req            = pm80xx_chip_reg_dev_req,
4669         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4670         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
4671         .task_abort             = pm8001_chip_abort_task,
4672         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4673         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4674         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4675         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4676         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4677 };