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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2000-2015 Avago Technologies.  All rights reserved.
4  *
5  *
6  *          Name:  mpi2_cnfg.h
7  *         Title:  MPI Configuration messages and pages
8  * Creation Date:  November 10, 2006
9  *
10  *   mpi2_cnfg.h Version:  02.00.40
11  *
12  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13  *       prefix are for use only on MPI v2.5 products, and must not be used
14  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
15  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16  *
17  * Version History
18  * ---------------
19  *
20  * Date      Version   Description
21  * --------  --------  ------------------------------------------------------
22  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
23  * 06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
24  *                     Added Manufacturing Page 11.
25  *                     Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26  *                     define.
27  * 06-26-07  02.00.02  Adding generic structure for product-specific
28  *                     Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
29  *                     Rework of BIOS Page 2 configuration page.
30  *                     Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31  *                     forms.
32  *                     Added configuration pages IOC Page 8 and Driver
33  *                     Persistent Mapping Page 0.
34  * 08-31-07  02.00.03  Modified configuration pages dealing with Integrated
35  *                     RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
36  *                     RAID Physical Disk Pages 0 and 1, RAID Configuration
37  *                     Page 0).
38  *                     Added new value for AccessStatus field of SAS Device
39  *                     Page 0 (_SATA_NEEDS_INITIALIZATION).
40  * 10-31-07  02.00.04  Added missing SEPDevHandle field to
41  *                     MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
42  * 12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
43  *                     NVDATA.
44  *                     Modified IOC Page 7 to use masks and added field for
45  *                     SASBroadcastPrimitiveMasks.
46  *                     Added MPI2_CONFIG_PAGE_BIOS_4.
47  *                     Added MPI2_CONFIG_PAGE_LOG_0.
48  * 02-29-08  02.00.06  Modified various names to make them 32-character unique.
49  *                     Added SAS Device IDs.
50  *                     Updated Integrated RAID configuration pages including
51  *                     Manufacturing Page 4, IOC Page 6, and RAID Configuration
52  *                     Page 0.
53  * 05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
54  *                     Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
55  *                     Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
56  *                     Added missing MaxNumRoutedSasAddresses field to
57  *                     MPI2_CONFIG_PAGE_EXPANDER_0.
58  *                     Added SAS Port Page 0.
59  *                     Modified structure layout for
60  *                     MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
61  * 06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
62  *                     MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
63  * 10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64  *                     to 0x000000FF.
65  *                     Added two new values for the Physical Disk Coercion Size
66  *                     bits in the Flags field of Manufacturing Page 4.
67  *                     Added product-specific Manufacturing pages 16 to 31.
68  *                     Modified Flags bits for controlling write cache on SATA
69  *                     drives in IO Unit Page 1.
70  *                     Added new bit to AdditionalControlFlags of SAS IO Unit
71  *                     Page 1 to control Invalid Topology Correction.
72  *                     Added additional defines for RAID Volume Page 0
73  *                     VolumeStatusFlags field.
74  *                     Modified meaning of RAID Volume Page 0 VolumeSettings
75  *                     define for auto-configure of hot-swap drives.
76  *                     Added SupportedPhysDisks field to RAID Volume Page 1 and
77  *                     added related defines.
78  *                     Added PhysDiskAttributes field (and related defines) to
79  *                     RAID Physical Disk Page 0.
80  *                     Added MPI2_SAS_PHYINFO_PHY_VACANT define.
81  *                     Added three new DiscoveryStatus bits for SAS IO Unit
82  *                     Page 0 and SAS Expander Page 0.
83  *                     Removed multiplexing information from SAS IO Unit pages.
84  *                     Added BootDeviceWaitTime field to SAS IO Unit Page 4.
85  *                     Removed Zone Address Resolved bit from PhyInfo and from
86  *                     Expander Page 0 Flags field.
87  *                     Added two new AccessStatus values to SAS Device Page 0
88  *                     for indicating routing problems. Added 3 reserved words
89  *                     to this page.
90  * 01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
91  *                     Inserted missing reserved field into structure for IOC
92  *                     Page 6.
93  *                     Added more pending task bits to RAID Volume Page 0
94  *                     VolumeStatusFlags defines.
95  *                     Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
96  *                     Added a new DiscoveryStatus bit for SAS IO Unit Page 0
97  *                     and SAS Expander Page 0 to flag a downstream initiator
98  *                     when in simplified routing mode.
99  *                     Removed SATA Init Failure defines for DiscoveryStatus
100  *                     fields of SAS IO Unit Page 0 and SAS Expander Page 0.
101  *                     Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
102  *                     Added PortGroups, DmaGroup, and ControlGroup fields to
103  *                     SAS Device Page 0.
104  * 05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
105  *                     Unit Page 6.
106  *                     Added expander reduced functionality data to SAS
107  *                     Expander Page 0.
108  *                     Added SAS PHY Page 2 and SAS PHY Page 3.
109  * 07-30-09  02.00.12  Added IO Unit Page 7.
110  *                     Added new device ids.
111  *                     Added SAS IO Unit Page 5.
112  *                     Added partial and slumber power management capable flags
113  *                     to SAS Device Page 0 Flags field.
114  *                     Added PhyInfo defines for power condition.
115  *                     Added Ethernet configuration pages.
116  * 10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
117  *                     Added SAS PHY Page 4 structure and defines.
118  * 02-10-10  02.00.14  Modified the comments for the configuration page
119  *                     structures that contain an array of data. The host
120  *                     should use the "count" field in the page data (e.g. the
121  *                     NumPhys field) to determine the number of valid elements
122  *                     in the array.
123  *                     Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
124  *                     Added PowerManagementCapabilities to IO Unit Page 7.
125  *                     Added PortWidthModGroup field to
126  *                     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
127  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
128  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
129  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
130  * 05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131  *                     define.
132  *                     Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
133  *                     Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
134  * 08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
135  *                     defines.
136  * 11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
137  *                     MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138  *                     the Pinout field.
139  *                     Added BoardTemperature and BoardTemperatureUnits fields
140  *                     to MPI2_CONFIG_PAGE_IO_UNIT_7.
141  *                     Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
142  *                     and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
143  * 02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
144  *                     Added IO Unit Page 8, IO Unit Page 9,
145  *                     and IO Unit Page 10.
146  *                     Added SASNotifyPrimitiveMasks field to
147  *                     MPI2_CONFIG_PAGE_IOC_7.
148  * 03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
149  * 05-25-11  02.00.20  Cleaned up a few comments.
150  * 08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
151  *                     for PCIe link as obsolete.
152  *                     Added SpinupFlags field containing a Disable Spin-up bit
153  *                     to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154  *                     Unit Page 4.
155  * 11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
156  *                     Added UEFIVersion field to BIOS Page 1 and defined new
157  *                     BiosOptions bits.
158  *                     Incorporating additions for MPI v2.5.
159  * 11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
160  *                     Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
161  * 12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
162  *                     obsolete for MPI v2.5 and later.
163  *                     Added some defines for 12G SAS speeds.
164  * 04-09-13  02.00.25  Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
165  *                     Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
166  *                     match the specification.
167  * 08-19-13  02.00.26  Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168  *                      future use.
169  * 12-05-13  02.00.27  Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
170  *                     MPI2_CONFIG_PAGE_MAN_7.
171  *                     Added EnclosureLevel and ConnectorName fields to
172  *                     MPI2_CONFIG_PAGE_SAS_DEV_0.
173  *                     Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
174  *                     MPI2_CONFIG_PAGE_SAS_DEV_0.
175  *                     Added EnclosureLevel field to
176  *                     MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
177  *                     Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
178  *                     MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
179  * 01-08-14  02.00.28  Added more defines for the BiosOptions field of
180  *                     MPI2_CONFIG_PAGE_BIOS_1.
181  * 06-13-14  02.00.29  Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
182  *                     more defines for the BiosOptions field.
183  * 11-18-14  02.00.30  Updated copyright information.
184  *                     Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
185  *                     Added AdapterOrderAux fields to BIOS Page 3.
186  * 03-16-15  02.00.31  Updated for MPI v2.6.
187  *                     Added Flags field to IO Unit Page 7.
188  *                     Added new SAS Phy Event codes
189  * 05-25-15  02.00.33  Added more defines for the BiosOptions field of
190  *                     MPI2_CONFIG_PAGE_BIOS_1.
191  * 08-25-15  02.00.34  Bumped Header Version.
192  * 12-18-15  02.00.35  Added SATADeviceWaitTime to SAS IO Unit Page 4.
193  * 01-21-16  02.00.36  Added/modified MPI2_MFGPAGE_DEVID_SAS defines.
194  *                     Added Link field to PCIe Link Pages
195  *                     Added EnclosureLevel and ConnectorName to PCIe
196  *                     Device Page 0.
197  *                     Added define for PCIE IoUnit page 1 max rate shift.
198  *                     Added comment for reserved ExtPageTypes.
199  *                     Added SAS 4 22.5 gbs speed support.
200  *                     Added PCIe 4 16.0 GT/sec speec support.
201  *                     Removed AHCI support.
202  *                     Removed SOP support.
203  *                     Added NegotiatedLinkRate and NegotiatedPortWidth to
204  *                     PCIe device page 0.
205  * 04-10-16  02.00.37  Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines
206  * 07-01-16  02.00.38  Added Manufacturing page 7 Connector types.
207  *                     Changed declaration of ConnectorName in PCIe DevicePage0
208  *                     to match SAS DevicePage 0.
209  *                     Added SATADeviceWaitTime to IO Unit Page 11.
210  *                     Added MPI26_MFGPAGE_DEVID_SAS4008
211  *                     Added x16 PCIe width to IO Unit Page 7
212  *                     Added LINKFLAGS to control SRIS in PCIe IO Unit page 1
213  *                     phy data.
214  *                     Added InitStatus to PCIe IO Unit Page 1 header.
215  * 09-01-16  02.00.39  Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines.
216  *                     Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and
217  *                     MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats.
218  * 02-02-17  02.00.40  Added MPI2_MANPAGE7_SLOT_UNKNOWN.
219  *                     Added ChassisSlot field to SAS Enclosure Page 0.
220  *                     Added ChassisSlot Valid bit (bit 5) to the Flags field
221  *                     in SAS Enclosure Page 0.
222  * --------------------------------------------------------------------------
223  */
224
225 #ifndef MPI2_CNFG_H
226 #define MPI2_CNFG_H
227
228 /*****************************************************************************
229 *  Configuration Page Header and defines
230 *****************************************************************************/
231
232 /*Config Page Header */
233 typedef struct _MPI2_CONFIG_PAGE_HEADER {
234         U8                 PageVersion;                /*0x00 */
235         U8                 PageLength;                 /*0x01 */
236         U8                 PageNumber;                 /*0x02 */
237         U8                 PageType;                   /*0x03 */
238 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
239         Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
240
241 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
242         MPI2_CONFIG_PAGE_HEADER  Struct;
243         U8                       Bytes[4];
244         U16                      Word16[2];
245         U32                      Word32;
246 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
247         Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
248
249 /*Extended Config Page Header */
250 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
251         U8                  PageVersion;                /*0x00 */
252         U8                  Reserved1;                  /*0x01 */
253         U8                  PageNumber;                 /*0x02 */
254         U8                  PageType;                   /*0x03 */
255         U16                 ExtPageLength;              /*0x04 */
256         U8                  ExtPageType;                /*0x06 */
257         U8                  Reserved2;                  /*0x07 */
258 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
259         *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
260         Mpi2ConfigExtendedPageHeader_t,
261         *pMpi2ConfigExtendedPageHeader_t;
262
263 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
264         MPI2_CONFIG_PAGE_HEADER          Struct;
265         MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
266         U8                               Bytes[8];
267         U16                              Word16[4];
268         U32                              Word32[2];
269 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
270         *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
271         Mpi2ConfigPageExtendedHeaderUnion,
272         *pMpi2ConfigPageExtendedHeaderUnion;
273
274
275 /*PageType field values */
276 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
277 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
278 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
279 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
280
281 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
282 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
283 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
284 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
285 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
286 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
287 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
288 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
289
290 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
291
292
293 /*ExtPageType field values */
294 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
295 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
296 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
297 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
298 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
299 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
300 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
301 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
302 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
303 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
304 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
305 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT        (0x1B)
306 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH         (0x1C)
307 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE         (0x1D)
308 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK           (0x1E)
309
310
311 /*****************************************************************************
312 *  PageAddress defines
313 *****************************************************************************/
314
315 /*RAID Volume PageAddress format */
316 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
317 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
318 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
319
320 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
321
322
323 /*RAID Physical Disk PageAddress format */
324 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
325 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
326 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
327 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
328
329 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
330 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
331
332
333 /*SAS Expander PageAddress format */
334 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
335 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
336 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
337 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
338
339 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
340 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
341 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
342
343
344 /*SAS Device PageAddress format */
345 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
346 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
347 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
348
349 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
350
351
352 /*SAS PHY PageAddress format */
353 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
354 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
355 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
356
357 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
358 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
359
360
361 /*SAS Port PageAddress format */
362 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
363 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
364 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
365
366 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
367
368
369 /*SAS Enclosure PageAddress format */
370 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
371 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
372 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
373
374 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
375
376 /*Enclosure PageAddress format */
377 #define MPI26_ENCLOS_PGAD_FORM_MASK                 (0xF0000000)
378 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE      (0x00000000)
379 #define MPI26_ENCLOS_PGAD_FORM_HANDLE               (0x10000000)
380
381 #define MPI26_ENCLOS_PGAD_HANDLE_MASK               (0x0000FFFF)
382
383 /*RAID Configuration PageAddress format */
384 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
385 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
386 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
387 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
388
389 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
390
391
392 /*Driver Persistent Mapping PageAddress format */
393 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
394 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
395
396 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
397 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
398 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
399
400
401 /*Ethernet PageAddress format */
402 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
403 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
404
405 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
406
407
408 /*PCIe Switch PageAddress format */
409 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK            (0xF0000000)
410 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL   (0x00000000)
411 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM    (0x10000000)
412 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL     (0x20000000)
413
414 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK          (0x0000FFFF)
415 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK         (0x00FF0000)
416 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT        (16)
417
418
419 /*PCIe Device PageAddress format */
420 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK            (0xF0000000)
421 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
422 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE          (0x20000000)
423
424 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK          (0x0000FFFF)
425
426 /*PCIe Link PageAddress format */
427 #define MPI26_PCIE_LINK_PGAD_FORM_MASK            (0xF0000000)
428 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK   (0x00000000)
429 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM        (0x10000000)
430
431 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK       (0x000000FF)
432
433
434
435 /****************************************************************************
436 *  Configuration messages
437 ****************************************************************************/
438
439 /*Configuration Request Message */
440 typedef struct _MPI2_CONFIG_REQUEST {
441         U8                      Action;                     /*0x00 */
442         U8                      SGLFlags;                   /*0x01 */
443         U8                      ChainOffset;                /*0x02 */
444         U8                      Function;                   /*0x03 */
445         U16                     ExtPageLength;              /*0x04 */
446         U8                      ExtPageType;                /*0x06 */
447         U8                      MsgFlags;                   /*0x07 */
448         U8                      VP_ID;                      /*0x08 */
449         U8                      VF_ID;                      /*0x09 */
450         U16                     Reserved1;                  /*0x0A */
451         U8                      Reserved2;                  /*0x0C */
452         U8                      ProxyVF_ID;                 /*0x0D */
453         U16                     Reserved4;                  /*0x0E */
454         U32                     Reserved3;                  /*0x10 */
455         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
456         U32                     PageAddress;                /*0x18 */
457         MPI2_SGE_IO_UNION       PageBufferSGE;              /*0x1C */
458 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
459         Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
460
461 /*values for the Action field */
462 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
463 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
464 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
465 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
466 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
467 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
468 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
469 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
470
471 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
472
473
474 /*Config Reply Message */
475 typedef struct _MPI2_CONFIG_REPLY {
476         U8                      Action;                     /*0x00 */
477         U8                      SGLFlags;                   /*0x01 */
478         U8                      MsgLength;                  /*0x02 */
479         U8                      Function;                   /*0x03 */
480         U16                     ExtPageLength;              /*0x04 */
481         U8                      ExtPageType;                /*0x06 */
482         U8                      MsgFlags;                   /*0x07 */
483         U8                      VP_ID;                      /*0x08 */
484         U8                      VF_ID;                      /*0x09 */
485         U16                     Reserved1;                  /*0x0A */
486         U16                     Reserved2;                  /*0x0C */
487         U16                     IOCStatus;                  /*0x0E */
488         U32                     IOCLogInfo;                 /*0x10 */
489         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
490 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
491         Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
492
493
494
495 /*****************************************************************************
496 *
497 *              C o n f i g u r a t i o n    P a g e s
498 *
499 *****************************************************************************/
500
501 /****************************************************************************
502 *  Manufacturing Config pages
503 ****************************************************************************/
504
505 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
506
507 /*MPI v2.0 SAS products */
508 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
509 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
510 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
511 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
512 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
513 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
514 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
515
516 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
517
518 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
519 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
520 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
521 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
522 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
523 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
524 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
525 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
526 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
527 #define MPI2_MFGPAGE_DEVID_SAS2308_MPI_EP           (0x02B0)
528
529 /*MPI v2.5 SAS products */
530 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
531 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
532 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
533 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
534 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
535 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
536
537 /* MPI v2.6 SAS Products */
538 #define MPI26_MFGPAGE_DEVID_SAS3216                 (0x00C9)
539 #define MPI26_MFGPAGE_DEVID_SAS3224                 (0x00C4)
540 #define MPI26_MFGPAGE_DEVID_SAS3316_1               (0x00C5)
541 #define MPI26_MFGPAGE_DEVID_SAS3316_2               (0x00C6)
542 #define MPI26_MFGPAGE_DEVID_SAS3316_3               (0x00C7)
543 #define MPI26_MFGPAGE_DEVID_SAS3316_4               (0x00C8)
544 #define MPI26_MFGPAGE_DEVID_SAS3324_1               (0x00C0)
545 #define MPI26_MFGPAGE_DEVID_SAS3324_2               (0x00C1)
546 #define MPI26_MFGPAGE_DEVID_SAS3324_3               (0x00C2)
547 #define MPI26_MFGPAGE_DEVID_SAS3324_4               (0x00C3)
548
549 #define MPI26_MFGPAGE_DEVID_SAS3516                 (0x00AA)
550 #define MPI26_MFGPAGE_DEVID_SAS3516_1               (0x00AB)
551 #define MPI26_MFGPAGE_DEVID_SAS3416                 (0x00AC)
552 #define MPI26_MFGPAGE_DEVID_SAS3508                 (0x00AD)
553 #define MPI26_MFGPAGE_DEVID_SAS3508_1               (0x00AE)
554 #define MPI26_MFGPAGE_DEVID_SAS3408                 (0x00AF)
555 #define MPI26_MFGPAGE_DEVID_SAS3716                 (0x00D0)
556 #define MPI26_MFGPAGE_DEVID_SAS3616                 (0x00D1)
557 #define MPI26_MFGPAGE_DEVID_SAS3708                 (0x00D2)
558
559 #define MPI26_MFGPAGE_DEVID_SAS4008                 (0x00A1)
560
561
562 /*Manufacturing Page 0 */
563
564 typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
565         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
566         U8                      ChipName[16];               /*0x04 */
567         U8                      ChipRevision[8];            /*0x14 */
568         U8                      BoardName[16];              /*0x1C */
569         U8                      BoardAssembly[16];          /*0x2C */
570         U8                      BoardTracerNumber[16];      /*0x3C */
571 } MPI2_CONFIG_PAGE_MAN_0,
572         *PTR_MPI2_CONFIG_PAGE_MAN_0,
573         Mpi2ManufacturingPage0_t,
574         *pMpi2ManufacturingPage0_t;
575
576 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
577
578
579 /*Manufacturing Page 1 */
580
581 typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
582         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
583         U8                      VPD[256];                   /*0x04 */
584 } MPI2_CONFIG_PAGE_MAN_1,
585         *PTR_MPI2_CONFIG_PAGE_MAN_1,
586         Mpi2ManufacturingPage1_t,
587         *pMpi2ManufacturingPage1_t;
588
589 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
590
591
592 typedef struct _MPI2_CHIP_REVISION_ID {
593         U16 DeviceID;                                       /*0x00 */
594         U8  PCIRevisionID;                                  /*0x02 */
595         U8  Reserved;                                       /*0x03 */
596 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
597         Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
598
599
600 /*Manufacturing Page 2 */
601
602 /*
603  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
604  *one and check Header.PageLength at runtime.
605  */
606 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
607 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
608 #endif
609
610 typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
611         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
612         MPI2_CHIP_REVISION_ID   ChipId;                     /*0x04 */
613         U32
614                 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
615 } MPI2_CONFIG_PAGE_MAN_2,
616         *PTR_MPI2_CONFIG_PAGE_MAN_2,
617         Mpi2ManufacturingPage2_t,
618         *pMpi2ManufacturingPage2_t;
619
620 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
621
622
623 /*Manufacturing Page 3 */
624
625 /*
626  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
627  *one and check Header.PageLength at runtime.
628  */
629 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
630 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
631 #endif
632
633 typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
634         MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
635         MPI2_CHIP_REVISION_ID               ChipId;         /*0x04 */
636         U32
637                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
638 } MPI2_CONFIG_PAGE_MAN_3,
639         *PTR_MPI2_CONFIG_PAGE_MAN_3,
640         Mpi2ManufacturingPage3_t,
641         *pMpi2ManufacturingPage3_t;
642
643 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
644
645
646 /*Manufacturing Page 4 */
647
648 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
649         U8                          PowerSaveFlags;                 /*0x00 */
650         U8                          InternalOperationsSleepTime;    /*0x01 */
651         U8                          InternalOperationsRunTime;      /*0x02 */
652         U8                          HostIdleTime;                   /*0x03 */
653 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
654         *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
655         Mpi2ManPage4PwrSaveSettings_t,
656         *pMpi2ManPage4PwrSaveSettings_t;
657
658 /*defines for the PowerSaveFlags field */
659 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
660 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
661 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
662 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
663
664 typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
665         MPI2_CONFIG_PAGE_HEADER             Header;                 /*0x00 */
666         U32                                 Reserved1;              /*0x04 */
667         U32                                 Flags;                  /*0x08 */
668         U8                                  InquirySize;            /*0x0C */
669         U8                                  Reserved2;              /*0x0D */
670         U16                                 Reserved3;              /*0x0E */
671         U8                                  InquiryData[56];        /*0x10 */
672         U32                                 RAID0VolumeSettings;    /*0x48 */
673         U32                                 RAID1EVolumeSettings;   /*0x4C */
674         U32                                 RAID1VolumeSettings;    /*0x50 */
675         U32                                 RAID10VolumeSettings;   /*0x54 */
676         U32                                 Reserved4;              /*0x58 */
677         U32                                 Reserved5;              /*0x5C */
678         MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /*0x60 */
679         U8                                  MaxOCEDisks;            /*0x64 */
680         U8                                  ResyncRate;             /*0x65 */
681         U16                                 DataScrubDuration;      /*0x66 */
682         U8                                  MaxHotSpares;           /*0x68 */
683         U8                                  MaxPhysDisksPerVol;     /*0x69 */
684         U8                                  MaxPhysDisks;           /*0x6A */
685         U8                                  MaxVolumes;             /*0x6B */
686 } MPI2_CONFIG_PAGE_MAN_4,
687         *PTR_MPI2_CONFIG_PAGE_MAN_4,
688         Mpi2ManufacturingPage4_t,
689         *pMpi2ManufacturingPage4_t;
690
691 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
692
693 /*Manufacturing Page 4 Flags field */
694 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
695 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
696
697 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
698 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
699 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
700
701 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
702 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
703 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
704 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
705 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
706
707 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
708 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
709 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
710 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
711
712 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
713 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
714 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
715 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
716 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
717 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
718 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
719 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
720
721
722 /*Manufacturing Page 5 */
723
724 /*
725  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
726  *one and check the value returned for NumPhys at runtime.
727  */
728 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
729 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
730 #endif
731
732 typedef struct _MPI2_MANUFACTURING5_ENTRY {
733         U64                                 WWID;           /*0x00 */
734         U64                                 DeviceName;     /*0x08 */
735 } MPI2_MANUFACTURING5_ENTRY,
736         *PTR_MPI2_MANUFACTURING5_ENTRY,
737         Mpi2Manufacturing5Entry_t,
738         *pMpi2Manufacturing5Entry_t;
739
740 typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
741         MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
742         U8                                  NumPhys;        /*0x04 */
743         U8                                  Reserved1;      /*0x05 */
744         U16                                 Reserved2;      /*0x06 */
745         U32                                 Reserved3;      /*0x08 */
746         U32                                 Reserved4;      /*0x0C */
747         MPI2_MANUFACTURING5_ENTRY
748                 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
749 } MPI2_CONFIG_PAGE_MAN_5,
750         *PTR_MPI2_CONFIG_PAGE_MAN_5,
751         Mpi2ManufacturingPage5_t,
752         *pMpi2ManufacturingPage5_t;
753
754 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
755
756
757 /*Manufacturing Page 6 */
758
759 typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
760         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
761         U32                             ProductSpecificInfo;/*0x04 */
762 } MPI2_CONFIG_PAGE_MAN_6,
763         *PTR_MPI2_CONFIG_PAGE_MAN_6,
764         Mpi2ManufacturingPage6_t,
765         *pMpi2ManufacturingPage6_t;
766
767 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
768
769
770 /*Manufacturing Page 7 */
771
772 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
773         U32                         Pinout;                 /*0x00 */
774         U8                          Connector[16];          /*0x04 */
775         U8                          Location;               /*0x14 */
776         U8                          ReceptacleID;           /*0x15 */
777         U16                         Slot;                   /*0x16 */
778         U32                         Reserved2;              /*0x18 */
779 } MPI2_MANPAGE7_CONNECTOR_INFO,
780         *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
781         Mpi2ManPage7ConnectorInfo_t,
782         *pMpi2ManPage7ConnectorInfo_t;
783
784 /*defines for the Pinout field */
785 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
786 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
787
788 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
789 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
790 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
791 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
792 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
793 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
794 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
795 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
796 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
797 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
798 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
799 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
800 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
801 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
802 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
803 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A                 (0x0E)
804 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i               (0x0F)
805 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i                (0x10)
806 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i                (0x11)
807 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i                (0x12)
808 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i                (0x13)
809
810 /*defines for the Location field */
811 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
812 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
813 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
814 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
815 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
816 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
817 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
818
819 /*defines for the Slot field */
820 #define MPI2_MANPAGE7_SLOT_UNKNOWN                      (0xFFFF)
821
822 /*
823  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
824  *one and check the value returned for NumPhys at runtime.
825  */
826 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
827 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
828 #endif
829
830 typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
831         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
832         U32                             Reserved1;          /*0x04 */
833         U32                             Reserved2;          /*0x08 */
834         U32                             Flags;              /*0x0C */
835         U8                              EnclosureName[16];  /*0x10 */
836         U8                              NumPhys;            /*0x20 */
837         U8                              Reserved3;          /*0x21 */
838         U16                             Reserved4;          /*0x22 */
839         MPI2_MANPAGE7_CONNECTOR_INFO
840         ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
841 } MPI2_CONFIG_PAGE_MAN_7,
842         *PTR_MPI2_CONFIG_PAGE_MAN_7,
843         Mpi2ManufacturingPage7_t,
844         *pMpi2ManufacturingPage7_t;
845
846 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
847
848 /*defines for the Flags field */
849 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL         (0x00000008)
850 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
851 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
852
853
854 /*
855  *Generic structure to use for product-specific manufacturing pages
856  *(currently Manufacturing Page 8 through Manufacturing Page 31).
857  */
858
859 typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
860         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
861         U32                             ProductSpecificInfo;/*0x04 */
862 } MPI2_CONFIG_PAGE_MAN_PS,
863         *PTR_MPI2_CONFIG_PAGE_MAN_PS,
864         Mpi2ManufacturingPagePS_t,
865         *pMpi2ManufacturingPagePS_t;
866
867 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
868 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
869 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
870 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
871 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
872 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
873 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
874 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
875 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
876 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
877 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
878 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
879 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
880 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
881 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
882 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
883 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
884 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
885 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
886 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
887 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
888 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
889 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
890 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
891
892
893 /****************************************************************************
894 *  IO Unit Config Pages
895 ****************************************************************************/
896
897 /*IO Unit Page 0 */
898
899 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
900         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
901         U64                     UniqueValue;                /*0x04 */
902         MPI2_VERSION_UNION      NvdataVersionDefault;       /*0x08 */
903         MPI2_VERSION_UNION      NvdataVersionPersistent;    /*0x0A */
904 } MPI2_CONFIG_PAGE_IO_UNIT_0,
905         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
906         Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
907
908 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
909
910
911 /*IO Unit Page 1 */
912
913 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
914         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
915         U32                     Flags;                      /*0x04 */
916 } MPI2_CONFIG_PAGE_IO_UNIT_1,
917         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
918         Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
919
920 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
921
922 /*IO Unit Page 1 Flags defines */
923 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
924 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
925 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
926 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
927 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
928 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
929 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
930 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
931 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
932 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
933 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
934 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
935 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
936
937
938 /*IO Unit Page 3 */
939
940 /*
941  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
942  *one and check the value returned for GPIOCount at runtime.
943  */
944 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
945 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
946 #endif
947
948 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
949         MPI2_CONFIG_PAGE_HEADER Header;                  /*0x00 */
950         U8                      GPIOCount;               /*0x04 */
951         U8                      Reserved1;               /*0x05 */
952         U16                     Reserved2;               /*0x06 */
953         U16
954                 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
955 } MPI2_CONFIG_PAGE_IO_UNIT_3,
956         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
957         Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
958
959 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
960
961 /*defines for IO Unit Page 3 GPIOVal field */
962 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
963 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
964 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
965 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
966
967
968 /*IO Unit Page 5 */
969
970 /*
971  *Upper layer code (drivers, utilities, etc.) should leave this define set to
972  *one and check the value returned for NumDmaEngines at runtime.
973  */
974 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
975 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
976 #endif
977
978 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
979         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
980         U64
981                 RaidAcceleratorBufferBaseAddress;           /*0x04 */
982         U64
983                 RaidAcceleratorBufferSize;                  /*0x0C */
984         U64
985                 RaidAcceleratorControlBaseAddress;          /*0x14 */
986         U8                      RAControlSize;              /*0x1C */
987         U8                      NumDmaEngines;              /*0x1D */
988         U8                      RAMinControlSize;           /*0x1E */
989         U8                      RAMaxControlSize;           /*0x1F */
990         U32                     Reserved1;                  /*0x20 */
991         U32                     Reserved2;                  /*0x24 */
992         U32                     Reserved3;                  /*0x28 */
993         U32
994         DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
995 } MPI2_CONFIG_PAGE_IO_UNIT_5,
996         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
997         Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
998
999 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
1000
1001 /*defines for IO Unit Page 5 DmaEngineCapabilities field */
1002 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFFFF0000)
1003 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
1004
1005 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
1006 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
1007 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
1008 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
1009
1010
1011 /*IO Unit Page 6 */
1012
1013 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
1014         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1015         U16                     Flags;                  /*0x04 */
1016         U8                      RAHostControlSize;      /*0x06 */
1017         U8                      Reserved0;              /*0x07 */
1018         U64
1019                 RaidAcceleratorHostControlBaseAddress;  /*0x08 */
1020         U32                     Reserved1;              /*0x10 */
1021         U32                     Reserved2;              /*0x14 */
1022         U32                     Reserved3;              /*0x18 */
1023 } MPI2_CONFIG_PAGE_IO_UNIT_6,
1024         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
1025         Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
1026
1027 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
1028
1029 /*defines for IO Unit Page 6 Flags field */
1030 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
1031
1032
1033 /*IO Unit Page 7 */
1034
1035 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
1036         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1037         U8                      CurrentPowerMode;       /*0x04 */
1038         U8                      PreviousPowerMode;      /*0x05 */
1039         U8                      PCIeWidth;              /*0x06 */
1040         U8                      PCIeSpeed;              /*0x07 */
1041         U32                     ProcessorState;         /*0x08 */
1042         U32
1043                 PowerManagementCapabilities;            /*0x0C */
1044         U16                     IOCTemperature;         /*0x10 */
1045         U8
1046                 IOCTemperatureUnits;                    /*0x12 */
1047         U8                      IOCSpeed;               /*0x13 */
1048         U16                     BoardTemperature;       /*0x14 */
1049         U8
1050                 BoardTemperatureUnits;                  /*0x16 */
1051         U8                      Reserved3;              /*0x17 */
1052         U32                     BoardPowerRequirement;  /*0x18 */
1053         U32                     PCISlotPowerAllocation; /*0x1C */
1054 /* reserved prior to MPI v2.6 */
1055         U8              Flags;                  /* 0x20 */
1056         U8              Reserved6;                      /* 0x21 */
1057         U16             Reserved7;                      /* 0x22 */
1058         U32             Reserved8;                      /* 0x24 */
1059 } MPI2_CONFIG_PAGE_IO_UNIT_7,
1060         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
1061         Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
1062
1063 #define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x05)
1064
1065 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
1066 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
1067 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
1068 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
1069 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
1070 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
1071
1072 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
1073 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
1074 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
1075 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
1076 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
1077 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
1078
1079
1080 /*defines for IO Unit Page 7 PCIeWidth field */
1081 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
1082 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
1083 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
1084 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
1085 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16             (0x10)
1086
1087 /*defines for IO Unit Page 7 PCIeSpeed field */
1088 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
1089 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
1090 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
1091 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS       (0x03)
1092
1093 /*defines for IO Unit Page 7 ProcessorState field */
1094 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
1095 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
1096
1097 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
1098 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
1099 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
1100
1101 /*defines for IO Unit Page 7 PowerManagementCapabilities field */
1102 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
1103 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
1104 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
1105 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
1106 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
1107 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
1108 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
1109 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
1110 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
1111 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
1112 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
1113 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
1114 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
1115 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
1116 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
1117 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008)
1118 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004)
1119 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002)
1120 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001)
1121
1122 /*obsolete names for the PowerManagementCapabilities bits (above) */
1123 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
1124 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
1125 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
1126 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /*obsolete */
1127 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /*obsolete */
1128
1129
1130 /*defines for IO Unit Page 7 IOCTemperatureUnits field */
1131 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
1132 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
1133 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
1134
1135 /*defines for IO Unit Page 7 IOCSpeed field */
1136 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
1137 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
1138 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
1139 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
1140
1141 /*defines for IO Unit Page 7 BoardTemperatureUnits field */
1142 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
1143 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
1144 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
1145
1146 /* defines for IO Unit Page 7 Flags field */
1147 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC       (0x01)
1148
1149 /*IO Unit Page 8 */
1150
1151 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
1152
1153 typedef struct _MPI2_IOUNIT8_SENSOR {
1154         U16                     Flags;                  /*0x00 */
1155         U16                     Reserved1;              /*0x02 */
1156         U16
1157                 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1158         U32                     Reserved2;              /*0x0C */
1159         U32                     Reserved3;              /*0x10 */
1160         U32                     Reserved4;              /*0x14 */
1161 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1162         Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1163
1164 /*defines for IO Unit Page 8 Sensor Flags field */
1165 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
1166 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
1167 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
1168 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
1169
1170 /*
1171  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1172  *one and check the value returned for NumSensors at runtime.
1173  */
1174 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1175 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
1176 #endif
1177
1178 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1179         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1180         U32                     Reserved1;              /*0x04 */
1181         U32                     Reserved2;              /*0x08 */
1182         U8                      NumSensors;             /*0x0C */
1183         U8                      PollingInterval;        /*0x0D */
1184         U16                     Reserved3;              /*0x0E */
1185         MPI2_IOUNIT8_SENSOR
1186                 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1187 } MPI2_CONFIG_PAGE_IO_UNIT_8,
1188         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1189         Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1190
1191 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
1192
1193
1194 /*IO Unit Page 9 */
1195
1196 typedef struct _MPI2_IOUNIT9_SENSOR {
1197         U16                     CurrentTemperature;     /*0x00 */
1198         U16                     Reserved1;              /*0x02 */
1199         U8                      Flags;                  /*0x04 */
1200         U8                      Reserved2;              /*0x05 */
1201         U16                     Reserved3;              /*0x06 */
1202         U32                     Reserved4;              /*0x08 */
1203         U32                     Reserved5;              /*0x0C */
1204 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1205         Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1206
1207 /*defines for IO Unit Page 9 Sensor Flags field */
1208 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
1209
1210 /*
1211  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1212  *one and check the value returned for NumSensors at runtime.
1213  */
1214 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1215 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
1216 #endif
1217
1218 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1219         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1220         U32                     Reserved1;              /*0x04 */
1221         U32                     Reserved2;              /*0x08 */
1222         U8                      NumSensors;             /*0x0C */
1223         U8                      Reserved4;              /*0x0D */
1224         U16                     Reserved3;              /*0x0E */
1225         MPI2_IOUNIT9_SENSOR
1226                 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1227 } MPI2_CONFIG_PAGE_IO_UNIT_9,
1228         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1229         Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1230
1231 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1232
1233
1234 /*IO Unit Page 10 */
1235
1236 typedef struct _MPI2_IOUNIT10_FUNCTION {
1237         U8                      CreditPercent;      /*0x00 */
1238         U8                      Reserved1;          /*0x01 */
1239         U16                     Reserved2;          /*0x02 */
1240 } MPI2_IOUNIT10_FUNCTION,
1241         *PTR_MPI2_IOUNIT10_FUNCTION,
1242         Mpi2IOUnit10Function_t,
1243         *pMpi2IOUnit10Function_t;
1244
1245 /*
1246  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1247  *one and check the value returned for NumFunctions at runtime.
1248  */
1249 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1250 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1251 #endif
1252
1253 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1254         MPI2_CONFIG_PAGE_HEADER Header;                      /*0x00 */
1255         U8                      NumFunctions;                /*0x04 */
1256         U8                      Reserved1;                   /*0x05 */
1257         U16                     Reserved2;                   /*0x06 */
1258         U32                     Reserved3;                   /*0x08 */
1259         U32                     Reserved4;                   /*0x0C */
1260         MPI2_IOUNIT10_FUNCTION
1261                 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1262 } MPI2_CONFIG_PAGE_IO_UNIT_10,
1263         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1264         Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1265
1266 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1267
1268
1269 /* IO Unit Page 11 (for MPI v2.6 and later) */
1270
1271 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP {
1272         U8          MaxTargetSpinup;            /* 0x00 */
1273         U8          SpinupDelay;                /* 0x01 */
1274         U8          SpinupFlags;                /* 0x02 */
1275         U8          Reserved1;                  /* 0x03 */
1276 } MPI26_IOUNIT11_SPINUP_GROUP,
1277         *PTR_MPI26_IOUNIT11_SPINUP_GROUP,
1278         Mpi26IOUnit11SpinupGroup_t,
1279         *pMpi26IOUnit11SpinupGroup_t;
1280
1281 /* defines for IO Unit Page 11 SpinupFlags */
1282 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG          (0x01)
1283
1284
1285 /*
1286  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1287  * four and check the value returned for NumPhys at runtime.
1288  */
1289 #ifndef MPI26_IOUNITPAGE11_PHY_MAX
1290 #define MPI26_IOUNITPAGE11_PHY_MAX        (4)
1291 #endif
1292
1293 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 {
1294         MPI2_CONFIG_PAGE_HEADER       Header;                          /*0x00 */
1295         U32                           Reserved1;                      /*0x04 */
1296         MPI26_IOUNIT11_SPINUP_GROUP   SpinupGroupParameters[4];       /*0x08 */
1297         U32                           Reserved2;                      /*0x18 */
1298         U32                           Reserved3;                      /*0x1C */
1299         U32                           Reserved4;                      /*0x20 */
1300         U8                            BootDeviceWaitTime;             /*0x24 */
1301         U8                            Reserved5;                      /*0x25 */
1302         U16                           Reserved6;                      /*0x26 */
1303         U8                            NumPhys;                        /*0x28 */
1304         U8                            PEInitialSpinupDelay;           /*0x29 */
1305         U8                            PEReplyDelay;                   /*0x2A */
1306         U8                            Flags;                          /*0x2B */
1307         U8                            PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */
1308 } MPI26_CONFIG_PAGE_IO_UNIT_11,
1309         *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
1310         Mpi26IOUnitPage11_t,
1311         *pMpi26IOUnitPage11_t;
1312
1313 #define MPI26_IOUNITPAGE11_PAGEVERSION                  (0x00)
1314
1315 /* defines for Flags field */
1316 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE        (0x01)
1317
1318 /* defines for PHY field */
1319 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK        (0x03)
1320
1321
1322
1323
1324
1325
1326 /****************************************************************************
1327 *  IOC Config Pages
1328 ****************************************************************************/
1329
1330 /*IOC Page 0 */
1331
1332 typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1333         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1334         U32                     Reserved1;                  /*0x04 */
1335         U32                     Reserved2;                  /*0x08 */
1336         U16                     VendorID;                   /*0x0C */
1337         U16                     DeviceID;                   /*0x0E */
1338         U8                      RevisionID;                 /*0x10 */
1339         U8                      Reserved3;                  /*0x11 */
1340         U16                     Reserved4;                  /*0x12 */
1341         U32                     ClassCode;                  /*0x14 */
1342         U16                     SubsystemVendorID;          /*0x18 */
1343         U16                     SubsystemID;                /*0x1A */
1344 } MPI2_CONFIG_PAGE_IOC_0,
1345         *PTR_MPI2_CONFIG_PAGE_IOC_0,
1346         Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1347
1348 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1349
1350
1351 /*IOC Page 1 */
1352
1353 typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1354         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1355         U32                     Flags;                      /*0x04 */
1356         U32                     CoalescingTimeout;          /*0x08 */
1357         U8                      CoalescingDepth;            /*0x0C */
1358         U8                      PCISlotNum;                 /*0x0D */
1359         U8                      PCIBusNum;                  /*0x0E */
1360         U8                      PCIDomainSegment;           /*0x0F */
1361         U32                     Reserved1;                  /*0x10 */
1362         U32                     Reserved2;                  /*0x14 */
1363 } MPI2_CONFIG_PAGE_IOC_1,
1364         *PTR_MPI2_CONFIG_PAGE_IOC_1,
1365         Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1366
1367 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1368
1369 /*defines for IOC Page 1 Flags field */
1370 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1371
1372 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1373 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1374 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1375
1376 /*IOC Page 6 */
1377
1378 typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1379         MPI2_CONFIG_PAGE_HEADER Header;         /*0x00 */
1380         U32
1381                 CapabilitiesFlags;              /*0x04 */
1382         U8                      MaxDrivesRAID0; /*0x08 */
1383         U8                      MaxDrivesRAID1; /*0x09 */
1384         U8
1385                  MaxDrivesRAID1E;                /*0x0A */
1386         U8
1387                  MaxDrivesRAID10;               /*0x0B */
1388         U8                      MinDrivesRAID0; /*0x0C */
1389         U8                      MinDrivesRAID1; /*0x0D */
1390         U8
1391                  MinDrivesRAID1E;                /*0x0E */
1392         U8
1393                  MinDrivesRAID10;                /*0x0F */
1394         U32                     Reserved1;      /*0x10 */
1395         U8
1396                  MaxGlobalHotSpares;             /*0x14 */
1397         U8                      MaxPhysDisks;   /*0x15 */
1398         U8                      MaxVolumes;     /*0x16 */
1399         U8                      MaxConfigs;     /*0x17 */
1400         U8                      MaxOCEDisks;    /*0x18 */
1401         U8                      Reserved2;      /*0x19 */
1402         U16                     Reserved3;      /*0x1A */
1403         U32
1404                 SupportedStripeSizeMapRAID0;    /*0x1C */
1405         U32
1406                 SupportedStripeSizeMapRAID1E;   /*0x20 */
1407         U32
1408                 SupportedStripeSizeMapRAID10;   /*0x24 */
1409         U32                     Reserved4;      /*0x28 */
1410         U32                     Reserved5;      /*0x2C */
1411         U16
1412                 DefaultMetadataSize;            /*0x30 */
1413         U16                     Reserved6;      /*0x32 */
1414         U16
1415                 MaxBadBlockTableEntries;        /*0x34 */
1416         U16                     Reserved7;      /*0x36 */
1417         U32
1418                 IRNvsramVersion;                /*0x38 */
1419 } MPI2_CONFIG_PAGE_IOC_6,
1420         *PTR_MPI2_CONFIG_PAGE_IOC_6,
1421         Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1422
1423 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
1424
1425 /*defines for IOC Page 6 CapabilitiesFlags */
1426 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
1427 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1428 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1429 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1430 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1431 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1432
1433
1434 /*IOC Page 7 */
1435
1436 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1437
1438 typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1439         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1440         U32                     Reserved1;                  /*0x04 */
1441         U32
1442                 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1443         U16                     SASBroadcastPrimitiveMasks; /*0x18 */
1444         U16                     SASNotifyPrimitiveMasks;    /*0x1A */
1445         U32                     Reserved3;                  /*0x1C */
1446 } MPI2_CONFIG_PAGE_IOC_7,
1447         *PTR_MPI2_CONFIG_PAGE_IOC_7,
1448         Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1449
1450 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1451
1452
1453 /*IOC Page 8 */
1454
1455 typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1456         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1457         U8                      NumDevsPerEnclosure;        /*0x04 */
1458         U8                      Reserved1;                  /*0x05 */
1459         U16                     Reserved2;                  /*0x06 */
1460         U16                     MaxPersistentEntries;       /*0x08 */
1461         U16                     MaxNumPhysicalMappedIDs;    /*0x0A */
1462         U16                     Flags;                      /*0x0C */
1463         U16                     Reserved3;                  /*0x0E */
1464         U16                     IRVolumeMappingFlags;       /*0x10 */
1465         U16                     Reserved4;                  /*0x12 */
1466         U32                     Reserved5;                  /*0x14 */
1467 } MPI2_CONFIG_PAGE_IOC_8,
1468         *PTR_MPI2_CONFIG_PAGE_IOC_8,
1469         Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1470
1471 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1472
1473 /*defines for IOC Page 8 Flags field */
1474 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1475 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1476
1477 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1478 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1479 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1480
1481 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1482 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1483
1484 /*defines for IOC Page 8 IRVolumeMappingFlags */
1485 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1486 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1487 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1488
1489
1490 /****************************************************************************
1491 *  BIOS Config Pages
1492 ****************************************************************************/
1493
1494 /*BIOS Page 1 */
1495
1496 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1497         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1498         U32                     BiosOptions;                /*0x04 */
1499         U32                     IOCSettings;                /*0x08 */
1500         U8                      SSUTimeout;                 /*0x0C */
1501         U8                      Reserved1;                  /*0x0D */
1502         U16                     Reserved2;                  /*0x0E */
1503         U32                     DeviceSettings;             /*0x10 */
1504         U16                     NumberOfDevices;            /*0x14 */
1505         U16                     UEFIVersion;                /*0x16 */
1506         U16                     IOTimeoutBlockDevicesNonRM; /*0x18 */
1507         U16                     IOTimeoutSequential;        /*0x1A */
1508         U16                     IOTimeoutOther;             /*0x1C */
1509         U16                     IOTimeoutBlockDevicesRM;    /*0x1E */
1510 } MPI2_CONFIG_PAGE_BIOS_1,
1511         *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1512         Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1513
1514 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x07)
1515
1516 /*values for BIOS Page 1 BiosOptions field */
1517 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE    (0x00008000)
1518 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG                  (0x00004000)
1519
1520 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
1521 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
1522 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL                        (0x00000000)
1523 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE                   (0x00000800)
1524 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID                        (0x00001000)
1525 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS                        (0x00001800)
1526 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY                        (0x00002000)
1527
1528 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS         (0x00000400)
1529
1530 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD       (0x00000300)
1531 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD   (0x00000000)
1532 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD       (0x00000100)
1533 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD    (0x00000200)
1534 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD    (0x00000300)
1535
1536 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                  (0x000000F0)
1537 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                   (0x00000000)
1538
1539 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION   (0x00000006)
1540 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII              (0x00000000)
1541 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII             (0x00000002)
1542 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII       (0x00000004)
1543
1544 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                 (0x00000001)
1545
1546 /*values for BIOS Page 1 IOCSettings field */
1547 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1548 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1549 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1550
1551 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1552 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1553 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1554 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1555
1556 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1557 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1558 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1559 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1560 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1561
1562 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1563
1564 /*values for BIOS Page 1 DeviceSettings field */
1565 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1566 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1567 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1568 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1569 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1570
1571 /*defines for BIOS Page 1 UEFIVersion field */
1572 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
1573 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
1574 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
1575 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
1576
1577
1578
1579 /*BIOS Page 2 */
1580
1581 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1582         U32         Reserved1;                              /*0x00 */
1583         U32         Reserved2;                              /*0x04 */
1584         U32         Reserved3;                              /*0x08 */
1585         U32         Reserved4;                              /*0x0C */
1586         U32         Reserved5;                              /*0x10 */
1587         U32         Reserved6;                              /*0x14 */
1588 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1589         *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1590         Mpi2BootDeviceAdapterOrder_t,
1591         *pMpi2BootDeviceAdapterOrder_t;
1592
1593 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1594         U64         SASAddress;                             /*0x00 */
1595         U8          LUN[8];                                 /*0x08 */
1596         U32         Reserved1;                              /*0x10 */
1597         U32         Reserved2;                              /*0x14 */
1598 } MPI2_BOOT_DEVICE_SAS_WWID,
1599         *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1600         Mpi2BootDeviceSasWwid_t,
1601         *pMpi2BootDeviceSasWwid_t;
1602
1603 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1604         U64         EnclosureLogicalID;                     /*0x00 */
1605         U32         Reserved1;                              /*0x08 */
1606         U32         Reserved2;                              /*0x0C */
1607         U16         SlotNumber;                             /*0x10 */
1608         U16         Reserved3;                              /*0x12 */
1609         U32         Reserved4;                              /*0x14 */
1610 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1611         *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1612         Mpi2BootDeviceEnclosureSlot_t,
1613         *pMpi2BootDeviceEnclosureSlot_t;
1614
1615 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1616         U64         DeviceName;                             /*0x00 */
1617         U8          LUN[8];                                 /*0x08 */
1618         U32         Reserved1;                              /*0x10 */
1619         U32         Reserved2;                              /*0x14 */
1620 } MPI2_BOOT_DEVICE_DEVICE_NAME,
1621         *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1622         Mpi2BootDeviceDeviceName_t,
1623         *pMpi2BootDeviceDeviceName_t;
1624
1625 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1626         MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1627         MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1628         MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1629         MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1630 } MPI2_BIOSPAGE2_BOOT_DEVICE,
1631         *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1632         Mpi2BiosPage2BootDevice_t,
1633         *pMpi2BiosPage2BootDevice_t;
1634
1635 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1636         MPI2_CONFIG_PAGE_HEADER     Header;                 /*0x00 */
1637         U32                         Reserved1;              /*0x04 */
1638         U32                         Reserved2;              /*0x08 */
1639         U32                         Reserved3;              /*0x0C */
1640         U32                         Reserved4;              /*0x10 */
1641         U32                         Reserved5;              /*0x14 */
1642         U32                         Reserved6;              /*0x18 */
1643         U8                          ReqBootDeviceForm;      /*0x1C */
1644         U8                          Reserved7;              /*0x1D */
1645         U16                         Reserved8;              /*0x1E */
1646         MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /*0x20 */
1647         U8                          ReqAltBootDeviceForm;   /*0x38 */
1648         U8                          Reserved9;              /*0x39 */
1649         U16                         Reserved10;             /*0x3A */
1650         MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /*0x3C */
1651         U8                          CurrentBootDeviceForm;  /*0x58 */
1652         U8                          Reserved11;             /*0x59 */
1653         U16                         Reserved12;             /*0x5A */
1654         MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /*0x58 */
1655 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1656         Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1657
1658 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1659
1660 /*values for BIOS Page 2 BootDeviceForm fields */
1661 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1662 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1663 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1664 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1665 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1666
1667
1668 /*BIOS Page 3 */
1669
1670 #define MPI2_BIOSPAGE3_NUM_ADAPTER      (4)
1671
1672 typedef struct _MPI2_ADAPTER_INFO {
1673         U8      PciBusNumber;                        /*0x00 */
1674         U8      PciDeviceAndFunctionNumber;          /*0x01 */
1675         U16     AdapterFlags;                        /*0x02 */
1676 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1677         Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1678
1679 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1680 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1681
1682 typedef struct _MPI2_ADAPTER_ORDER_AUX {
1683         U64     WWID;                                   /* 0x00 */
1684         U32     Reserved1;                              /* 0x08 */
1685         U32     Reserved2;                              /* 0x0C */
1686 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX,
1687         Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t;
1688
1689
1690 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1691         MPI2_CONFIG_PAGE_HEADER Header;              /*0x00 */
1692         U32                     GlobalFlags;         /*0x04 */
1693         U32                     BiosVersion;         /*0x08 */
1694         MPI2_ADAPTER_INFO       AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER];
1695         U32                     Reserved1;           /*0x1C */
1696         MPI2_ADAPTER_ORDER_AUX  AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER];
1697 } MPI2_CONFIG_PAGE_BIOS_3,
1698         *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1699         Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1700
1701 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x01)
1702
1703 /*values for BIOS Page 3 GlobalFlags */
1704 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1705 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1706 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1707
1708 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1709 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1710 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1711 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1712
1713
1714 /*BIOS Page 4 */
1715
1716 /*
1717  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1718  *one and check the value returned for NumPhys at runtime.
1719  */
1720 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1721 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1722 #endif
1723
1724 typedef struct _MPI2_BIOS4_ENTRY {
1725         U64                     ReassignmentWWID;       /*0x00 */
1726         U64                     ReassignmentDeviceName; /*0x08 */
1727 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1728         Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1729
1730 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1731         MPI2_CONFIG_PAGE_HEADER Header;             /*0x00 */
1732         U8                      NumPhys;            /*0x04 */
1733         U8                      Reserved1;          /*0x05 */
1734         U16                     Reserved2;          /*0x06 */
1735         MPI2_BIOS4_ENTRY
1736                 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /*0x08 */
1737 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1738         Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1739
1740 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1741
1742
1743 /****************************************************************************
1744 *  RAID Volume Config Pages
1745 ****************************************************************************/
1746
1747 /*RAID Volume Page 0 */
1748
1749 typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1750         U8                      RAIDSetNum;        /*0x00 */
1751         U8                      PhysDiskMap;       /*0x01 */
1752         U8                      PhysDiskNum;       /*0x02 */
1753         U8                      Reserved;          /*0x03 */
1754 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1755         Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1756
1757 /*defines for the PhysDiskMap field */
1758 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1759 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1760
1761 typedef struct _MPI2_RAIDVOL0_SETTINGS {
1762         U16                     Settings;          /*0x00 */
1763         U8                      HotSparePool;      /*0x01 */
1764         U8                      Reserved;          /*0x02 */
1765 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1766         Mpi2RaidVol0Settings_t,
1767         *pMpi2RaidVol0Settings_t;
1768
1769 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1770 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1771 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1772 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1773 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1774 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1775 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1776 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1777 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1778
1779 /*RAID Volume Page 0 VolumeSettings defines */
1780 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1781 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1782
1783 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1784 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1785 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1786 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1787
1788 /*
1789  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1790  *one and check the value returned for NumPhysDisks at runtime.
1791  */
1792 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1793 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1794 #endif
1795
1796 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1797         MPI2_CONFIG_PAGE_HEADER Header;            /*0x00 */
1798         U16                     DevHandle;         /*0x04 */
1799         U8                      VolumeState;       /*0x06 */
1800         U8                      VolumeType;        /*0x07 */
1801         U32                     VolumeStatusFlags; /*0x08 */
1802         MPI2_RAIDVOL0_SETTINGS  VolumeSettings;    /*0x0C */
1803         U64                     MaxLBA;            /*0x10 */
1804         U32                     StripeSize;        /*0x18 */
1805         U16                     BlockSize;         /*0x1C */
1806         U16                     Reserved1;         /*0x1E */
1807         U8                      SupportedPhysDisks;/*0x20 */
1808         U8                      ResyncRate;        /*0x21 */
1809         U16                     DataScrubDuration; /*0x22 */
1810         U8                      NumPhysDisks;      /*0x24 */
1811         U8                      Reserved2;         /*0x25 */
1812         U8                      Reserved3;         /*0x26 */
1813         U8                      InactiveStatus;    /*0x27 */
1814         MPI2_RAIDVOL0_PHYS_DISK
1815         PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1816 } MPI2_CONFIG_PAGE_RAID_VOL_0,
1817         *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1818         Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1819
1820 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1821
1822 /*values for RAID VolumeState */
1823 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1824 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1825 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1826 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1827 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1828 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1829
1830 /*values for RAID VolumeType */
1831 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1832 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1833 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1834 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1835 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1836
1837 /*values for RAID Volume Page 0 VolumeStatusFlags field */
1838 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1839 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1840 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1841 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1842 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1843 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1844 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1845 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1846 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1847 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1848 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1849 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1850 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1851 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1852 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1853 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1854 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1855 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1856 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1857
1858 /*values for RAID Volume Page 0 SupportedPhysDisks field */
1859 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1860 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1861 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1862 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1863
1864 /*values for RAID Volume Page 0 InactiveStatus field */
1865 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1866 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1867 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1868 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1869 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1870 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1871 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1872
1873
1874 /*RAID Volume Page 1 */
1875
1876 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1877         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1878         U16                     DevHandle;                  /*0x04 */
1879         U16                     Reserved0;                  /*0x06 */
1880         U8                      GUID[24];                   /*0x08 */
1881         U8                      Name[16];                   /*0x20 */
1882         U64                     WWID;                       /*0x30 */
1883         U32                     Reserved1;                  /*0x38 */
1884         U32                     Reserved2;                  /*0x3C */
1885 } MPI2_CONFIG_PAGE_RAID_VOL_1,
1886         *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1887         Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1888
1889 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1890
1891
1892 /****************************************************************************
1893 *  RAID Physical Disk Config Pages
1894 ****************************************************************************/
1895
1896 /*RAID Physical Disk Page 0 */
1897
1898 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1899         U16                     Reserved1;                  /*0x00 */
1900         U8                      HotSparePool;               /*0x02 */
1901         U8                      Reserved2;                  /*0x03 */
1902 } MPI2_RAIDPHYSDISK0_SETTINGS,
1903         *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1904         Mpi2RaidPhysDisk0Settings_t,
1905         *pMpi2RaidPhysDisk0Settings_t;
1906
1907 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1908
1909 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1910         U8                      VendorID[8];                /*0x00 */
1911         U8                      ProductID[16];              /*0x08 */
1912         U8                      ProductRevLevel[4];         /*0x18 */
1913         U8                      SerialNum[32];              /*0x1C */
1914 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1915         *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1916         Mpi2RaidPhysDisk0InquiryData_t,
1917         *pMpi2RaidPhysDisk0InquiryData_t;
1918
1919 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1920         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
1921         U16                             DevHandle;          /*0x04 */
1922         U8                              Reserved1;          /*0x06 */
1923         U8                              PhysDiskNum;        /*0x07 */
1924         MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;   /*0x08 */
1925         U32                             Reserved2;          /*0x0C */
1926         MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;        /*0x10 */
1927         U32                             Reserved3;          /*0x4C */
1928         U8                              PhysDiskState;      /*0x50 */
1929         U8                              OfflineReason;      /*0x51 */
1930         U8                              IncompatibleReason; /*0x52 */
1931         U8                              PhysDiskAttributes; /*0x53 */
1932         U32                             PhysDiskStatusFlags;/*0x54 */
1933         U64                             DeviceMaxLBA;       /*0x58 */
1934         U64                             HostMaxLBA;         /*0x60 */
1935         U64                             CoercedMaxLBA;      /*0x68 */
1936         U16                             BlockSize;          /*0x70 */
1937         U16                             Reserved5;          /*0x72 */
1938         U32                             Reserved6;          /*0x74 */
1939 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1940         *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1941         Mpi2RaidPhysDiskPage0_t,
1942         *pMpi2RaidPhysDiskPage0_t;
1943
1944 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1945
1946 /*PhysDiskState defines */
1947 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1948 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1949 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1950 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1951 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1952 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1953 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1954 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1955
1956 /*OfflineReason defines */
1957 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
1958 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1959 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1960 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1961 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1962 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1963 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1964
1965 /*IncompatibleReason defines */
1966 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1967 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1968 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1969 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1970 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1971 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1972 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
1973 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1974
1975 /*PhysDiskAttributes defines */
1976 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
1977 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1978 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1979
1980 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
1981 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1982 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1983
1984 /*PhysDiskStatusFlags defines */
1985 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1986 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1987 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1988 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1989 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1990 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1991 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1992 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1993
1994
1995 /*RAID Physical Disk Page 1 */
1996
1997 /*
1998  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1999  *one and check the value returned for NumPhysDiskPaths at runtime.
2000  */
2001 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
2002 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
2003 #endif
2004
2005 typedef struct _MPI2_RAIDPHYSDISK1_PATH {
2006         U16             DevHandle;          /*0x00 */
2007         U16             Reserved1;          /*0x02 */
2008         U64             WWID;               /*0x04 */
2009         U64             OwnerWWID;          /*0x0C */
2010         U8              OwnerIdentifier;    /*0x14 */
2011         U8              Reserved2;          /*0x15 */
2012         U16             Flags;              /*0x16 */
2013 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
2014         Mpi2RaidPhysDisk1Path_t,
2015         *pMpi2RaidPhysDisk1Path_t;
2016
2017 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
2018 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
2019 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
2020 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
2021
2022 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
2023         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
2024         U8                              NumPhysDiskPaths;   /*0x04 */
2025         U8                              PhysDiskNum;        /*0x05 */
2026         U16                             Reserved1;          /*0x06 */
2027         U32                             Reserved2;          /*0x08 */
2028         MPI2_RAIDPHYSDISK1_PATH
2029                 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
2030 } MPI2_CONFIG_PAGE_RD_PDISK_1,
2031         *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
2032         Mpi2RaidPhysDiskPage1_t,
2033         *pMpi2RaidPhysDiskPage1_t;
2034
2035 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
2036
2037
2038 /****************************************************************************
2039 *  values for fields used by several types of SAS Config Pages
2040 ****************************************************************************/
2041
2042 /*values for NegotiatedLinkRates fields */
2043 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
2044 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
2045 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
2046 /*link rates used for Negotiated Physical and Logical Link Rate */
2047 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
2048 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
2049 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
2050 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
2051 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
2052 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
2053 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
2054 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
2055 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
2056 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
2057 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
2058 #define MPI26_SAS_NEG_LINK_RATE_22_5                    (0x0C)
2059
2060
2061 /*values for AttachedPhyInfo fields */
2062 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
2063 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
2064 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
2065
2066 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
2067 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
2068 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
2069 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
2070 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
2071 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
2072 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
2073 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
2074 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
2075 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
2076
2077
2078 /*values for PhyInfo fields */
2079 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
2080
2081 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
2082 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
2083 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
2084 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
2085 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
2086
2087 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
2088 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
2089 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
2090 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
2091 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
2092 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
2093
2094 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
2095 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
2096 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
2097 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
2098 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
2099 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
2100 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
2101 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
2102 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
2103 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
2104
2105 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
2106 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
2107 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
2108 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
2109
2110 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
2111 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
2112
2113 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
2114 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
2115 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
2116 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
2117
2118
2119 /*values for SAS ProgrammedLinkRate fields */
2120 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
2121 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
2122 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
2123 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
2124 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
2125 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
2126 #define MPI26_SAS_PRATE_MAX_RATE_22_5                   (0xC0)
2127 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
2128 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
2129 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
2130 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
2131 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
2132 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
2133 #define MPI26_SAS_PRATE_MIN_RATE_22_5                   (0x0C)
2134
2135
2136 /*values for SAS HwLinkRate fields */
2137 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
2138 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
2139 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
2140 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
2141 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
2142 #define MPI26_SAS_HWRATE_MAX_RATE_22_5                  (0xC0)
2143 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
2144 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
2145 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
2146 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
2147 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
2148 #define MPI26_SAS_HWRATE_MIN_RATE_22_5                  (0x0C)
2149
2150
2151
2152 /****************************************************************************
2153 *  SAS IO Unit Config Pages
2154 ****************************************************************************/
2155
2156 /*SAS IO Unit Page 0 */
2157
2158 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
2159         U8          Port;                   /*0x00 */
2160         U8          PortFlags;              /*0x01 */
2161         U8          PhyFlags;               /*0x02 */
2162         U8          NegotiatedLinkRate;     /*0x03 */
2163         U32         ControllerPhyDeviceInfo;/*0x04 */
2164         U16         AttachedDevHandle;      /*0x08 */
2165         U16         ControllerDevHandle;    /*0x0A */
2166         U32         DiscoveryStatus;        /*0x0C */
2167         U32         Reserved;               /*0x10 */
2168 } MPI2_SAS_IO_UNIT0_PHY_DATA,
2169         *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
2170         Mpi2SasIOUnit0PhyData_t,
2171         *pMpi2SasIOUnit0PhyData_t;
2172
2173 /*
2174  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2175  *one and check the value returned for NumPhys at runtime.
2176  */
2177 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
2178 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
2179 #endif
2180
2181 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
2182         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
2183         U32                                 Reserved1;/*0x08 */
2184         U8                                  NumPhys;  /*0x0C */
2185         U8                                  Reserved2;/*0x0D */
2186         U16                                 Reserved3;/*0x0E */
2187         MPI2_SAS_IO_UNIT0_PHY_DATA
2188                 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];    /*0x10 */
2189 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
2190         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2191         Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
2192
2193 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
2194
2195 /*values for SAS IO Unit Page 0 PortFlags */
2196 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
2197 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
2198
2199 /*values for SAS IO Unit Page 0 PhyFlags */
2200 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT       (0x40)
2201 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT       (0x20)
2202 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
2203 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
2204
2205 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2206
2207 /*see mpi2_sas.h for values for
2208  *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2209
2210 /*values for SAS IO Unit Page 0 DiscoveryStatus */
2211 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
2212 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
2213 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
2214 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
2215 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
2216 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
2217 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
2218 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
2219 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
2220 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2221 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
2222 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2223 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2224 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2225 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2226 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2227 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2228 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2229 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2230 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2231
2232
2233 /*SAS IO Unit Page 1 */
2234
2235 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2236         U8          Port;                       /*0x00 */
2237         U8          PortFlags;                  /*0x01 */
2238         U8          PhyFlags;                   /*0x02 */
2239         U8          MaxMinLinkRate;             /*0x03 */
2240         U32         ControllerPhyDeviceInfo;    /*0x04 */
2241         U16         MaxTargetPortConnectTime;   /*0x08 */
2242         U16         Reserved1;                  /*0x0A */
2243 } MPI2_SAS_IO_UNIT1_PHY_DATA,
2244         *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2245         Mpi2SasIOUnit1PhyData_t,
2246         *pMpi2SasIOUnit1PhyData_t;
2247
2248 /*
2249  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2250  *one and check the value returned for NumPhys at runtime.
2251  */
2252 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2253 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
2254 #endif
2255
2256 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2257         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
2258         U16
2259                 ControlFlags;                       /*0x08 */
2260         U16
2261                 SASNarrowMaxQueueDepth;             /*0x0A */
2262         U16
2263                 AdditionalControlFlags;             /*0x0C */
2264         U16
2265                 SASWideMaxQueueDepth;               /*0x0E */
2266         U8
2267                 NumPhys;                            /*0x10 */
2268         U8
2269                 SATAMaxQDepth;                      /*0x11 */
2270         U8
2271                 ReportDeviceMissingDelay;           /*0x12 */
2272         U8
2273                 IODeviceMissingDelay;               /*0x13 */
2274         MPI2_SAS_IO_UNIT1_PHY_DATA
2275                 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /*0x14 */
2276 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2277         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2278         Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2279
2280 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
2281
2282 /*values for SAS IO Unit Page 1 ControlFlags */
2283 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
2284 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
2285 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000)
2286 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
2287
2288 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
2289 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
2290 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
2291 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
2292 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
2293
2294 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
2295 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
2296 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
2297 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
2298 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
2299 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
2300 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
2301 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001)
2302
2303 /*values for SAS IO Unit Page 1 AdditionalControlFlags */
2304 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
2305 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2306 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2307 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
2308 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2309 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2310 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2311 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2312 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2313
2314 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2315 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
2316 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
2317
2318 /*values for SAS IO Unit Page 1 PortFlags */
2319 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
2320
2321 /*values for SAS IO Unit Page 1 PhyFlags */
2322 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
2323 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
2324 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
2325 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
2326
2327 /*values for SAS IO Unit Page 1 MaxMinLinkRate */
2328 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
2329 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
2330 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
2331 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
2332 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
2333 #define MPI26_SASIOUNIT1_MAX_RATE_22_5                              (0xC0)
2334 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
2335 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
2336 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
2337 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
2338 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
2339 #define MPI26_SASIOUNIT1_MIN_RATE_22_5                              (0x0C)
2340
2341 /*see mpi2_sas.h for values for
2342  *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2343
2344
2345 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
2346
2347 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2348         U8          MaxTargetSpinup;            /*0x00 */
2349         U8          SpinupDelay;                /*0x01 */
2350         U8          SpinupFlags;                /*0x02 */
2351         U8          Reserved1;                  /*0x03 */
2352 } MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2353         *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2354         Mpi2SasIOUnit4SpinupGroup_t,
2355         *pMpi2SasIOUnit4SpinupGroup_t;
2356 /*defines for SAS IO Unit Page 4 SpinupFlags */
2357 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
2358
2359
2360 /*
2361  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2362  *one and check the value returned for NumPhys at runtime.
2363  */
2364 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2365 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
2366 #endif
2367
2368 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2369         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;/*0x00 */
2370         MPI2_SAS_IOUNIT4_SPINUP_GROUP
2371                 SpinupGroupParameters[4];       /*0x08 */
2372         U32
2373                 Reserved1;                      /*0x18 */
2374         U32
2375                 Reserved2;                      /*0x1C */
2376         U32
2377                 Reserved3;                      /*0x20 */
2378         U8
2379                 BootDeviceWaitTime;             /*0x24 */
2380         U8
2381                 SATADeviceWaitTime;             /*0x25 */
2382         U16
2383                 Reserved5;                      /*0x26 */
2384         U8
2385                 NumPhys;                        /*0x28 */
2386         U8
2387                 PEInitialSpinupDelay;           /*0x29 */
2388         U8
2389                 PEReplyDelay;                   /*0x2A */
2390         U8
2391                 Flags;                          /*0x2B */
2392         U8
2393                 PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /*0x2C */
2394 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2395         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2396         Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2397
2398 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2399
2400 /*defines for Flags field */
2401 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2402
2403 /*defines for PHY field */
2404 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2405
2406
2407 /*SAS IO Unit Page 5 */
2408
2409 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2410         U8          ControlFlags;               /*0x00 */
2411         U8          PortWidthModGroup;          /*0x01 */
2412         U16         InactivityTimerExponent;    /*0x02 */
2413         U8          SATAPartialTimeout;         /*0x04 */
2414         U8          Reserved2;                  /*0x05 */
2415         U8          SATASlumberTimeout;         /*0x06 */
2416         U8          Reserved3;                  /*0x07 */
2417         U8          SASPartialTimeout;          /*0x08 */
2418         U8          Reserved4;                  /*0x09 */
2419         U8          SASSlumberTimeout;          /*0x0A */
2420         U8          Reserved5;                  /*0x0B */
2421 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2422         *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2423         Mpi2SasIOUnit5PhyPmSettings_t,
2424         *pMpi2SasIOUnit5PhyPmSettings_t;
2425
2426 /*defines for ControlFlags field */
2427 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2428 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2429 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2430 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2431
2432 /*defines for PortWidthModeGroup field */
2433 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2434
2435 /*defines for InactivityTimerExponent field */
2436 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2437 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2438 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2439 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2440 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2441 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2442 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2443 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2444
2445 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2446 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2447 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2448 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2449 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2450 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2451 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2452 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2453
2454 /*
2455  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2456  *one and check the value returned for NumPhys at runtime.
2457  */
2458 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2459 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2460 #endif
2461
2462 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2463         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
2464         U8                                  NumPhys;  /*0x08 */
2465         U8                                  Reserved1;/*0x09 */
2466         U16                                 Reserved2;/*0x0A */
2467         U32                                 Reserved3;/*0x0C */
2468         MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2469         SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2470 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2471         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2472         Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2473
2474 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2475
2476
2477 /*SAS IO Unit Page 6 */
2478
2479 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2480         U8          CurrentStatus;              /*0x00 */
2481         U8          CurrentModulation;          /*0x01 */
2482         U8          CurrentUtilization;         /*0x02 */
2483         U8          Reserved1;                  /*0x03 */
2484         U32         Reserved2;                  /*0x04 */
2485 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2486         *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2487         Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2488         *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2489
2490 /*defines for CurrentStatus field */
2491 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2492 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2493 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2494 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2495 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2496 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2497 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2498 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2499
2500 /*defines for CurrentModulation field */
2501 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2502 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2503 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2504 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2505
2506 /*
2507  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2508  *one and check the value returned for NumGroups at runtime.
2509  */
2510 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2511 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2512 #endif
2513
2514 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2515         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /*0x00 */
2516         U32                                 Reserved1;              /*0x08 */
2517         U32                                 Reserved2;              /*0x0C */
2518         U8                                  NumGroups;              /*0x10 */
2519         U8                                  Reserved3;              /*0x11 */
2520         U16                                 Reserved4;              /*0x12 */
2521         MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2522         PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2523 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2524         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2525         Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2526
2527 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2528
2529
2530 /*SAS IO Unit Page 7 */
2531
2532 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2533         U8          Flags;                      /*0x00 */
2534         U8          Reserved1;                  /*0x01 */
2535         U16         Reserved2;                  /*0x02 */
2536         U8          Threshold75Pct;             /*0x04 */
2537         U8          Threshold50Pct;             /*0x05 */
2538         U8          Threshold25Pct;             /*0x06 */
2539         U8          Reserved3;                  /*0x07 */
2540 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2541         *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2542         Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2543         *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2544
2545 /*defines for Flags field */
2546 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2547
2548
2549 /*
2550  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2551  *one and check the value returned for NumGroups at runtime.
2552  */
2553 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2554 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2555 #endif
2556
2557 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2558         MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;             /*0x00 */
2559         U8                               SamplingInterval;   /*0x08 */
2560         U8                               WindowLength;       /*0x09 */
2561         U16                              Reserved1;          /*0x0A */
2562         U32                              Reserved2;          /*0x0C */
2563         U32                              Reserved3;          /*0x10 */
2564         U8                               NumGroups;          /*0x14 */
2565         U8                               Reserved4;          /*0x15 */
2566         U16                              Reserved5;          /*0x16 */
2567         MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2568         PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2569 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2570         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2571         Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2572
2573 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2574
2575
2576 /*SAS IO Unit Page 8 */
2577
2578 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2579         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2580                 Header;                         /*0x00 */
2581         U32
2582                 Reserved1;                      /*0x08 */
2583         U32
2584                 PowerManagementCapabilities;    /*0x0C */
2585         U8
2586                 TxRxSleepStatus;                /*0x10 */
2587         U8
2588                 Reserved2;                      /*0x11 */
2589         U16
2590                 Reserved3;                      /*0x12 */
2591 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2592         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2593         Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2594
2595 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2596
2597 /*defines for PowerManagementCapabilities field */
2598 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2599 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2600 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2601 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2602 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2603 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2604 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2605 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2606 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2607 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2608
2609 /*defines for TxRxSleepStatus field */
2610 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
2611 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
2612 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
2613 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
2614
2615
2616
2617 /*SAS IO Unit Page 16 */
2618
2619 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2620         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2621                 Header;                             /*0x00 */
2622         U64
2623                 TimeStamp;                          /*0x08 */
2624         U32
2625                 Reserved1;                          /*0x10 */
2626         U32
2627                 Reserved2;                          /*0x14 */
2628         U32
2629                 FastPathPendedRequests;             /*0x18 */
2630         U32
2631                 FastPathUnPendedRequests;           /*0x1C */
2632         U32
2633                 FastPathHostRequestStarts;          /*0x20 */
2634         U32
2635                 FastPathFirmwareRequestStarts;      /*0x24 */
2636         U32
2637                 FastPathHostCompletions;            /*0x28 */
2638         U32
2639                 FastPathFirmwareCompletions;        /*0x2C */
2640         U32
2641                 NonFastPathRequestStarts;           /*0x30 */
2642         U32
2643                 NonFastPathHostCompletions;         /*0x30 */
2644 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2645         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2646         Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2647
2648 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
2649
2650
2651 /****************************************************************************
2652 *  SAS Expander Config Pages
2653 ****************************************************************************/
2654
2655 /*SAS Expander Page 0 */
2656
2657 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2658         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2659                 Header;                     /*0x00 */
2660         U8
2661                 PhysicalPort;               /*0x08 */
2662         U8
2663                 ReportGenLength;            /*0x09 */
2664         U16
2665                 EnclosureHandle;            /*0x0A */
2666         U64
2667                 SASAddress;                 /*0x0C */
2668         U32
2669                 DiscoveryStatus;            /*0x14 */
2670         U16
2671                 DevHandle;                  /*0x18 */
2672         U16
2673                 ParentDevHandle;            /*0x1A */
2674         U16
2675                 ExpanderChangeCount;        /*0x1C */
2676         U16
2677                 ExpanderRouteIndexes;       /*0x1E */
2678         U8
2679                 NumPhys;                    /*0x20 */
2680         U8
2681                 SASLevel;                   /*0x21 */
2682         U16
2683                 Flags;                      /*0x22 */
2684         U16
2685                 STPBusInactivityTimeLimit;  /*0x24 */
2686         U16
2687                 STPMaxConnectTimeLimit;     /*0x26 */
2688         U16
2689                 STP_SMP_NexusLossTime;      /*0x28 */
2690         U16
2691                 MaxNumRoutedSasAddresses;   /*0x2A */
2692         U64
2693                 ActiveZoneManagerSASAddress;/*0x2C */
2694         U16
2695                 ZoneLockInactivityLimit;    /*0x34 */
2696         U16
2697                 Reserved1;                  /*0x36 */
2698         U8
2699                 TimeToReducedFunc;          /*0x38 */
2700         U8
2701                 InitialTimeToReducedFunc;   /*0x39 */
2702         U8
2703                 MaxReducedFuncTime;         /*0x3A */
2704         U8
2705                 Reserved2;                  /*0x3B */
2706 } MPI2_CONFIG_PAGE_EXPANDER_0,
2707         *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2708         Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2709
2710 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2711
2712 /*values for SAS Expander Page 0 DiscoveryStatus field */
2713 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2714 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2715 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2716 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2717 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2718 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2719 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2720 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2721 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2722 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2723 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2724 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2725 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2726 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2727 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2728 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2729 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2730 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2731 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2732 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2733
2734 /*values for SAS Expander Page 0 Flags field */
2735 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2736 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2737 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2738 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2739 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2740 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2741 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2742 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2743 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2744 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2745 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2746
2747
2748 /*SAS Expander Page 1 */
2749
2750 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2751         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2752                 Header;                     /*0x00 */
2753         U8
2754                 PhysicalPort;               /*0x08 */
2755         U8
2756                 Reserved1;                  /*0x09 */
2757         U16
2758                 Reserved2;                  /*0x0A */
2759         U8
2760                 NumPhys;                    /*0x0C */
2761         U8
2762                 Phy;                        /*0x0D */
2763         U16
2764                 NumTableEntriesProgrammed;  /*0x0E */
2765         U8
2766                 ProgrammedLinkRate;         /*0x10 */
2767         U8
2768                 HwLinkRate;                 /*0x11 */
2769         U16
2770                 AttachedDevHandle;          /*0x12 */
2771         U32
2772                 PhyInfo;                    /*0x14 */
2773         U32
2774                 AttachedDeviceInfo;         /*0x18 */
2775         U16
2776                 ExpanderDevHandle;          /*0x1C */
2777         U8
2778                 ChangeCount;                /*0x1E */
2779         U8
2780                 NegotiatedLinkRate;         /*0x1F */
2781         U8
2782                 PhyIdentifier;              /*0x20 */
2783         U8
2784                 AttachedPhyIdentifier;      /*0x21 */
2785         U8
2786                 Reserved3;                  /*0x22 */
2787         U8
2788                 DiscoveryInfo;              /*0x23 */
2789         U32
2790                 AttachedPhyInfo;            /*0x24 */
2791         U8
2792                 ZoneGroup;                  /*0x28 */
2793         U8
2794                 SelfConfigStatus;           /*0x29 */
2795         U16
2796                 Reserved4;                  /*0x2A */
2797 } MPI2_CONFIG_PAGE_EXPANDER_1,
2798         *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2799         Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2800
2801 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2802
2803 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2804
2805 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2806
2807 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2808
2809 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2810  *used for the AttachedDeviceInfo field */
2811
2812 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2813
2814 /*values for SAS Expander Page 1 DiscoveryInfo field */
2815 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2816 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2817 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2818
2819 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2820
2821
2822 /****************************************************************************
2823 *  SAS Device Config Pages
2824 ****************************************************************************/
2825
2826 /*SAS Device Page 0 */
2827
2828 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2829         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2830                 Header;                 /*0x00 */
2831         U16
2832                 Slot;                   /*0x08 */
2833         U16
2834                 EnclosureHandle;        /*0x0A */
2835         U64
2836                 SASAddress;             /*0x0C */
2837         U16
2838                 ParentDevHandle;        /*0x14 */
2839         U8
2840                 PhyNum;                 /*0x16 */
2841         U8
2842                 AccessStatus;           /*0x17 */
2843         U16
2844                 DevHandle;              /*0x18 */
2845         U8
2846                 AttachedPhyIdentifier;  /*0x1A */
2847         U8
2848                 ZoneGroup;              /*0x1B */
2849         U32
2850                 DeviceInfo;             /*0x1C */
2851         U16
2852                 Flags;                  /*0x20 */
2853         U8
2854                 PhysicalPort;           /*0x22 */
2855         U8
2856                 MaxPortConnections;     /*0x23 */
2857         U64
2858                 DeviceName;             /*0x24 */
2859         U8
2860                 PortGroups;             /*0x2C */
2861         U8
2862                 DmaGroup;               /*0x2D */
2863         U8
2864                 ControlGroup;           /*0x2E */
2865         U8
2866                 EnclosureLevel;         /*0x2F */
2867         U32
2868                 ConnectorName[4];       /*0x30 */
2869         U32
2870                 Reserved3;              /*0x34 */
2871 } MPI2_CONFIG_PAGE_SAS_DEV_0,
2872         *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2873         Mpi2SasDevicePage0_t,
2874         *pMpi2SasDevicePage0_t;
2875
2876 #define MPI2_SASDEVICE0_PAGEVERSION         (0x09)
2877
2878 /*values for SAS Device Page 0 AccessStatus field */
2879 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2880 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2881 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2882 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2883 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2884 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2885 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2886 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2887 /*specific values for SATA Init failures */
2888 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2889 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2890 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2891 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2892 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2893 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2894 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2895 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2896 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2897 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2898 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2899
2900 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2901
2902 /*values for SAS Device Page 0 Flags field */
2903 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2904 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
2905 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
2906 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2907 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2908 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2909 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2910 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2911 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2912 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2913 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2914 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2915 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2916 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE              (0x0004)
2917 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID             (0x0002)
2918 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2919
2920
2921 /*SAS Device Page 1 */
2922
2923 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2924         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2925                 Header;                 /*0x00 */
2926         U32
2927                 Reserved1;              /*0x08 */
2928         U64
2929                 SASAddress;             /*0x0C */
2930         U32
2931                 Reserved2;              /*0x14 */
2932         U16
2933                 DevHandle;              /*0x18 */
2934         U16
2935                 Reserved3;              /*0x1A */
2936         U8
2937                 InitialRegDeviceFIS[20];/*0x1C */
2938 } MPI2_CONFIG_PAGE_SAS_DEV_1,
2939         *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2940         Mpi2SasDevicePage1_t,
2941         *pMpi2SasDevicePage1_t;
2942
2943 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2944
2945
2946 /****************************************************************************
2947 *  SAS PHY Config Pages
2948 ****************************************************************************/
2949
2950 /*SAS PHY Page 0 */
2951
2952 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2953         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2954                 Header;                 /*0x00 */
2955         U16
2956                 OwnerDevHandle;         /*0x08 */
2957         U16
2958                 Reserved1;              /*0x0A */
2959         U16
2960                 AttachedDevHandle;      /*0x0C */
2961         U8
2962                 AttachedPhyIdentifier;  /*0x0E */
2963         U8
2964                 Reserved2;              /*0x0F */
2965         U32
2966                 AttachedPhyInfo;        /*0x10 */
2967         U8
2968                 ProgrammedLinkRate;     /*0x14 */
2969         U8
2970                 HwLinkRate;             /*0x15 */
2971         U8
2972                 ChangeCount;            /*0x16 */
2973         U8
2974                 Flags;                  /*0x17 */
2975         U32
2976                 PhyInfo;                /*0x18 */
2977         U8
2978                 NegotiatedLinkRate;     /*0x1C */
2979         U8
2980                 Reserved3;              /*0x1D */
2981         U16
2982                 Reserved4;              /*0x1E */
2983 } MPI2_CONFIG_PAGE_SAS_PHY_0,
2984         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2985         Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2986
2987 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
2988
2989 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2990
2991 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2992
2993 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2994
2995 /*values for SAS PHY Page 0 Flags field */
2996 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2997
2998 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2999
3000 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3001
3002
3003 /*SAS PHY Page 1 */
3004
3005 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
3006         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3007                 Header;                     /*0x00 */
3008         U32
3009                 Reserved1;                  /*0x08 */
3010         U32
3011                 InvalidDwordCount;          /*0x0C */
3012         U32
3013                 RunningDisparityErrorCount; /*0x10 */
3014         U32
3015                 LossDwordSynchCount;        /*0x14 */
3016         U32
3017                 PhyResetProblemCount;       /*0x18 */
3018 } MPI2_CONFIG_PAGE_SAS_PHY_1,
3019         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
3020         Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
3021
3022 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
3023
3024
3025 /*SAS PHY Page 2 */
3026
3027 typedef struct _MPI2_SASPHY2_PHY_EVENT {
3028         U8          PhyEventCode;       /*0x00 */
3029         U8          Reserved1;          /*0x01 */
3030         U16         Reserved2;          /*0x02 */
3031         U32         PhyEventInfo;       /*0x04 */
3032 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
3033         Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
3034
3035 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
3036
3037
3038 /*
3039  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3040  *one and check the value returned for NumPhyEvents at runtime.
3041  */
3042 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
3043 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
3044 #endif
3045
3046 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
3047         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3048                 Header;                     /*0x00 */
3049         U32
3050                 Reserved1;                  /*0x08 */
3051         U8
3052                 NumPhyEvents;               /*0x0C */
3053         U8
3054                 Reserved2;                  /*0x0D */
3055         U16
3056                 Reserved3;                  /*0x0E */
3057         MPI2_SASPHY2_PHY_EVENT
3058                 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
3059 } MPI2_CONFIG_PAGE_SAS_PHY_2,
3060         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
3061         Mpi2SasPhyPage2_t,
3062         *pMpi2SasPhyPage2_t;
3063
3064 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
3065
3066
3067 /*SAS PHY Page 3 */
3068
3069 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
3070         U8          PhyEventCode;       /*0x00 */
3071         U8          Reserved1;          /*0x01 */
3072         U16         Reserved2;          /*0x02 */
3073         U8          CounterType;        /*0x04 */
3074         U8          ThresholdWindow;    /*0x05 */
3075         U8          TimeUnits;          /*0x06 */
3076         U8          Reserved3;          /*0x07 */
3077         U32         EventThreshold;     /*0x08 */
3078         U16         ThresholdFlags;     /*0x0C */
3079         U16         Reserved4;          /*0x0E */
3080 } MPI2_SASPHY3_PHY_EVENT_CONFIG,
3081         *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
3082         Mpi2SasPhy3PhyEventConfig_t,
3083         *pMpi2SasPhy3PhyEventConfig_t;
3084
3085 /*values for PhyEventCode field */
3086 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
3087 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
3088 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
3089 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
3090 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
3091 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
3092 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
3093 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
3094 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
3095 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
3096 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
3097 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
3098 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
3099 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
3100 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
3101 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
3102 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
3103 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
3104 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
3105 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
3106 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
3107 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
3108 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
3109 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
3110 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
3111 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
3112 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
3113 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
3114 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
3115 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
3116 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
3117 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
3118 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
3119 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
3120 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
3121 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
3122 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
3123
3124 /*Following codes are product specific and in MPI v2.6 and later */
3125 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME             (0xD3)
3126 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xD4)
3127 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME                 (0xD5)
3128 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT       (0xD6)
3129 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START               (0xD7)
3130 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT        (0xD8)
3131 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN           (0xD9)
3132 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE        (0xDA)
3133 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE       (0xDB)
3134 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE        (0xDC)
3135
3136
3137 /*values for the CounterType field */
3138 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
3139 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
3140 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
3141
3142 /*values for the TimeUnits field */
3143 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
3144 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
3145 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
3146 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
3147
3148 /*values for the ThresholdFlags field */
3149 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
3150 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
3151
3152 /*
3153  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3154  *one and check the value returned for NumPhyEvents at runtime.
3155  */
3156 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
3157 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
3158 #endif
3159
3160 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
3161         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3162                 Header;                     /*0x00 */
3163         U32
3164                 Reserved1;                  /*0x08 */
3165         U8
3166                 NumPhyEvents;               /*0x0C */
3167         U8
3168                 Reserved2;                  /*0x0D */
3169         U16
3170                 Reserved3;                  /*0x0E */
3171         MPI2_SASPHY3_PHY_EVENT_CONFIG
3172                 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
3173 } MPI2_CONFIG_PAGE_SAS_PHY_3,
3174         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
3175         Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
3176
3177 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
3178
3179
3180 /*SAS PHY Page 4 */
3181
3182 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
3183         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3184                 Header;                     /*0x00 */
3185         U16
3186                 Reserved1;                  /*0x08 */
3187         U8
3188                 Reserved2;                  /*0x0A */
3189         U8
3190                 Flags;                      /*0x0B */
3191         U8
3192                 InitialFrame[28];           /*0x0C */
3193 } MPI2_CONFIG_PAGE_SAS_PHY_4,
3194         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
3195         Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
3196
3197 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
3198
3199 /*values for the Flags field */
3200 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
3201 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
3202
3203
3204
3205
3206 /****************************************************************************
3207 *  SAS Port Config Pages
3208 ****************************************************************************/
3209
3210 /*SAS Port Page 0 */
3211
3212 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
3213         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3214                 Header;                     /*0x00 */
3215         U8
3216                 PortNumber;                 /*0x08 */
3217         U8
3218                 PhysicalPort;               /*0x09 */
3219         U8
3220                 PortWidth;                  /*0x0A */
3221         U8
3222                 PhysicalPortWidth;          /*0x0B */
3223         U8
3224                 ZoneGroup;                  /*0x0C */
3225         U8
3226                 Reserved1;                  /*0x0D */
3227         U16
3228                 Reserved2;                  /*0x0E */
3229         U64
3230                 SASAddress;                 /*0x10 */
3231         U32
3232                 DeviceInfo;                 /*0x18 */
3233         U32
3234                 Reserved3;                  /*0x1C */
3235         U32
3236                 Reserved4;                  /*0x20 */
3237 } MPI2_CONFIG_PAGE_SAS_PORT_0,
3238         *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3239         Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3240
3241 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
3242
3243 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3244
3245
3246 /****************************************************************************
3247 *  SAS Enclosure Config Pages
3248 ****************************************************************************/
3249
3250 /*SAS Enclosure Page 0 */
3251
3252 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3253         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3254         U32     Reserved1;                      /*0x08 */
3255         U64     EnclosureLogicalID;             /*0x0C */
3256         U16     Flags;                          /*0x14 */
3257         U16     EnclosureHandle;                /*0x16 */
3258         U16     NumSlots;                       /*0x18 */
3259         U16     StartSlot;                      /*0x1A */
3260         U8      ChassisSlot;                    /*0x1C */
3261         U8      EnclosureLeve;                  /*0x1D */
3262         U16     SEPDevHandle;                   /*0x1E */
3263         U32     Reserved3;                      /*0x20 */
3264         U32     Reserved4;                      /*0x24 */
3265 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3266         *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3267         Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t,
3268         MPI26_CONFIG_PAGE_ENCLOSURE_0,
3269         *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0,
3270         Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t;
3271
3272 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
3273
3274 /*values for SAS Enclosure Page 0 Flags field */
3275 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID    (0x0020)
3276 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
3277 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
3278 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
3279 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
3280 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
3281 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
3282 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
3283 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
3284
3285 #define MPI26_ENCLOSURE0_PAGEVERSION        (0x04)
3286
3287 /*Values for Enclosure Page 0 Flags field */
3288 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID       (0x0020)
3289 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID         (0x0010)
3290 #define MPI26_ENCLS0_FLAGS_MNG_MASK                 (0x000F)
3291 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN              (0x0000)
3292 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES              (0x0001)
3293 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO            (0x0002)
3294 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO            (0x0003)
3295 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE        (0x0004)
3296 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO             (0x0005)
3297
3298 /****************************************************************************
3299 *  Log Config Page
3300 ****************************************************************************/
3301
3302 /*Log Page 0 */
3303
3304 /*
3305  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3306  *one and check the value returned for NumLogEntries at runtime.
3307  */
3308 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3309 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
3310 #endif
3311
3312 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
3313
3314 typedef struct _MPI2_LOG_0_ENTRY {
3315         U64         TimeStamp;                      /*0x00 */
3316         U32         Reserved1;                      /*0x08 */
3317         U16         LogSequence;                    /*0x0C */
3318         U16         LogEntryQualifier;              /*0x0E */
3319         U8          VP_ID;                          /*0x10 */
3320         U8          VF_ID;                          /*0x11 */
3321         U16         Reserved2;                      /*0x12 */
3322         U8
3323                 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3324 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3325         Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3326
3327 /*values for Log Page 0 LogEntry LogEntryQualifier field */
3328 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
3329 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
3330 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
3331 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
3332 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
3333
3334 typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3335         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;       /*0x00 */
3336         U32                                 Reserved1;    /*0x08 */
3337         U32                                 Reserved2;    /*0x0C */
3338         U16                                 NumLogEntries;/*0x10 */
3339         U16                                 Reserved3;    /*0x12 */
3340         MPI2_LOG_0_ENTRY
3341                 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3342 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3343         Mpi2LogPage0_t, *pMpi2LogPage0_t;
3344
3345 #define MPI2_LOG_0_PAGEVERSION              (0x02)
3346
3347
3348 /****************************************************************************
3349 *  RAID Config Page
3350 ****************************************************************************/
3351
3352 /*RAID Page 0 */
3353
3354 /*
3355  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3356  *one and check the value returned for NumElements at runtime.
3357  */
3358 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3359 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
3360 #endif
3361
3362 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3363         U16                     ElementFlags;             /*0x00 */
3364         U16                     VolDevHandle;             /*0x02 */
3365         U8                      HotSparePool;             /*0x04 */
3366         U8                      PhysDiskNum;              /*0x05 */
3367         U16                     PhysDiskDevHandle;        /*0x06 */
3368 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3369         *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3370         Mpi2RaidConfig0ConfigElement_t,
3371         *pMpi2RaidConfig0ConfigElement_t;
3372
3373 /*values for the ElementFlags field */
3374 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
3375 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
3376 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
3377 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
3378 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
3379
3380
3381 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3382         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;         /*0x00 */
3383         U8                                  NumHotSpares;   /*0x08 */
3384         U8                                  NumPhysDisks;   /*0x09 */
3385         U8                                  NumVolumes;     /*0x0A */
3386         U8                                  ConfigNum;      /*0x0B */
3387         U32                                 Flags;          /*0x0C */
3388         U8                                  ConfigGUID[24]; /*0x10 */
3389         U32                                 Reserved1;      /*0x28 */
3390         U8                                  NumElements;    /*0x2C */
3391         U8                                  Reserved2;      /*0x2D */
3392         U16                                 Reserved3;      /*0x2E */
3393         MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3394                 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3395 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3396         *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3397         Mpi2RaidConfigurationPage0_t,
3398         *pMpi2RaidConfigurationPage0_t;
3399
3400 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
3401
3402 /*values for RAID Configuration Page 0 Flags field */
3403 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
3404
3405
3406 /****************************************************************************
3407 *  Driver Persistent Mapping Config Pages
3408 ****************************************************************************/
3409
3410 /*Driver Persistent Mapping Page 0 */
3411
3412 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3413         U64     PhysicalIdentifier;         /*0x00 */
3414         U16     MappingInformation;         /*0x08 */
3415         U16     DeviceIndex;                /*0x0A */
3416         U32     PhysicalBitsMapping;        /*0x0C */
3417         U32     Reserved1;                  /*0x10 */
3418 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3419         *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3420         Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3421
3422 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3423         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
3424         MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;  /*0x08 */
3425 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3426         *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3427         Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3428
3429 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
3430
3431 /*values for Driver Persistent Mapping Page 0 MappingInformation field */
3432 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
3433 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
3434 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
3435
3436
3437 /****************************************************************************
3438 *  Ethernet Config Pages
3439 ****************************************************************************/
3440
3441 /*Ethernet Page 0 */
3442
3443 /*IP address (union of IPv4 and IPv6) */
3444 typedef union _MPI2_ETHERNET_IP_ADDR {
3445         U32     IPv4Addr;
3446         U32     IPv6Addr[4];
3447 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3448         Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3449
3450 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
3451
3452 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3453         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;          /*0x00 */
3454         U8                                  NumInterfaces;   /*0x08 */
3455         U8                                  Reserved0;       /*0x09 */
3456         U16                                 Reserved1;       /*0x0A */
3457         U32                                 Status;          /*0x0C */
3458         U8                                  MediaState;      /*0x10 */
3459         U8                                  Reserved2;       /*0x11 */
3460         U16                                 Reserved3;       /*0x12 */
3461         U8                                  MacAddress[6];   /*0x14 */
3462         U8                                  Reserved4;       /*0x1A */
3463         U8                                  Reserved5;       /*0x1B */
3464         MPI2_ETHERNET_IP_ADDR               IpAddress;       /*0x1C */
3465         MPI2_ETHERNET_IP_ADDR               SubnetMask;      /*0x2C */
3466         MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;/*0x3C */
3467         MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;   /*0x4C */
3468         MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;   /*0x5C */
3469         MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;   /*0x6C */
3470         U8
3471                 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3472 } MPI2_CONFIG_PAGE_ETHERNET_0,
3473         *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3474         Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3475
3476 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
3477
3478 /*values for Ethernet Page 0 Status field */
3479 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
3480 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
3481 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
3482 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
3483 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
3484 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
3485 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
3486 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
3487 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
3488 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
3489 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
3490 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
3491
3492 /*values for Ethernet Page 0 MediaState field */
3493 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
3494 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
3495 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
3496
3497 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
3498 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
3499 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
3500 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
3501 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
3502
3503
3504 /*Ethernet Page 1 */
3505
3506 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3507         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3508                 Header;                 /*0x00 */
3509         U32
3510                 Reserved0;              /*0x08 */
3511         U32
3512                 Flags;                  /*0x0C */
3513         U8
3514                 MediaState;             /*0x10 */
3515         U8
3516                 Reserved1;              /*0x11 */
3517         U16
3518                 Reserved2;              /*0x12 */
3519         U8
3520                 MacAddress[6];          /*0x14 */
3521         U8
3522                 Reserved3;              /*0x1A */
3523         U8
3524                 Reserved4;              /*0x1B */
3525         MPI2_ETHERNET_IP_ADDR
3526                 StaticIpAddress;        /*0x1C */
3527         MPI2_ETHERNET_IP_ADDR
3528                 StaticSubnetMask;       /*0x2C */
3529         MPI2_ETHERNET_IP_ADDR
3530                 StaticGatewayIpAddress; /*0x3C */
3531         MPI2_ETHERNET_IP_ADDR
3532                 StaticDNS1IpAddress;    /*0x4C */
3533         MPI2_ETHERNET_IP_ADDR
3534                 StaticDNS2IpAddress;    /*0x5C */
3535         U32
3536                 Reserved5;              /*0x6C */
3537         U32
3538                 Reserved6;              /*0x70 */
3539         U32
3540                 Reserved7;              /*0x74 */
3541         U32
3542                 Reserved8;              /*0x78 */
3543         U8
3544                 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3545 } MPI2_CONFIG_PAGE_ETHERNET_1,
3546         *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3547         Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3548
3549 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
3550
3551 /*values for Ethernet Page 1 Flags field */
3552 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
3553 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
3554 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
3555 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
3556 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
3557 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
3558 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
3559 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
3560 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
3561
3562 /*values for Ethernet Page 1 MediaState field */
3563 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
3564 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
3565 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
3566
3567 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
3568 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
3569 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
3570 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
3571 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
3572
3573
3574 /****************************************************************************
3575 *  Extended Manufacturing Config Pages
3576 ****************************************************************************/
3577
3578 /*
3579  *Generic structure to use for product-specific extended manufacturing pages
3580  *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3581  *Page 60).
3582  */
3583
3584 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3585         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3586                 Header;                 /*0x00 */
3587         U32
3588                 ProductSpecificInfo;    /*0x08 */
3589 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3590         *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3591         Mpi2ExtManufacturingPagePS_t,
3592         *pMpi2ExtManufacturingPagePS_t;
3593
3594 /*PageVersion should be provided by product-specific code */
3595
3596
3597
3598 /****************************************************************************
3599 *  values for fields used by several types of PCIe Config Pages
3600 ****************************************************************************/
3601
3602 /*values for NegotiatedLinkRates fields */
3603 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL          (0x0F)
3604 /*link rates used for Negotiated Physical Link Rate */
3605 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN                (0x00)
3606 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED           (0x01)
3607 #define MPI26_PCIE_NEG_LINK_RATE_2_5                    (0x02)
3608 #define MPI26_PCIE_NEG_LINK_RATE_5_0                    (0x03)
3609 #define MPI26_PCIE_NEG_LINK_RATE_8_0                    (0x04)
3610 #define MPI26_PCIE_NEG_LINK_RATE_16_0                   (0x05)
3611
3612
3613 /****************************************************************************
3614 *  PCIe IO Unit Config Pages (MPI v2.6 and later)
3615 ****************************************************************************/
3616
3617 /*PCIe IO Unit Page 0 */
3618
3619 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA {
3620         U8      Link;                   /*0x00 */
3621         U8      LinkFlags;              /*0x01 */
3622         U8      PhyFlags;               /*0x02 */
3623         U8      NegotiatedLinkRate;     /*0x03 */
3624         U32     ControllerPhyDeviceInfo;/*0x04 */
3625         U16     AttachedDevHandle;      /*0x08 */
3626         U16     ControllerDevHandle;    /*0x0A */
3627         U32     EnumerationStatus;      /*0x0C */
3628         U32     Reserved1;              /*0x10 */
3629 } MPI26_PCIE_IO_UNIT0_PHY_DATA,
3630         *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA,
3631         Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t;
3632
3633 /*
3634  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3635  *one and check the value returned for NumPhys at runtime.
3636  */
3637 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX
3638 #define MPI26_PCIE_IOUNIT0_PHY_MAX      (1)
3639 #endif
3640
3641 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 {
3642         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3643         U32     Reserved1;                              /*0x08 */
3644         U8      NumPhys;                                /*0x0C */
3645         U8      InitStatus;                             /*0x0D */
3646         U16     Reserved3;                              /*0x0E */
3647         MPI26_PCIE_IO_UNIT0_PHY_DATA
3648                 PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX];    /*0x10 */
3649 } MPI26_CONFIG_PAGE_PIOUNIT_0,
3650         *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0,
3651         Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t;
3652
3653 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION                   (0x00)
3654
3655 /*values for PCIe IO Unit Page 0 LinkFlags */
3656 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
3657
3658 /*values for PCIe IO Unit Page 0 PhyFlags */
3659 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED             (0x08)
3660
3661 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3662
3663 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3664  *values
3665  */
3666
3667 /*values for PCIe IO Unit Page 0 EnumerationStatus */
3668 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED          (0x40000000)
3669 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED           (0x20000000)
3670
3671
3672 /*PCIe IO Unit Page 1 */
3673
3674 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA {
3675         U8      Link;                       /*0x00 */
3676         U8      LinkFlags;                  /*0x01 */
3677         U8      PhyFlags;                   /*0x02 */
3678         U8      MaxMinLinkRate;             /*0x03 */
3679         U32     ControllerPhyDeviceInfo;    /*0x04 */
3680         U32     Reserved1;                  /*0x08 */
3681 } MPI26_PCIE_IO_UNIT1_PHY_DATA,
3682         *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA,
3683         Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t;
3684
3685 /*values for LinkFlags */
3686 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS    (0x00)
3687 #define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS     (0x01)
3688
3689 /*
3690  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3691  *one and check the value returned for NumPhys at runtime.
3692  */
3693 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX
3694 #define MPI26_PCIE_IOUNIT1_PHY_MAX      (1)
3695 #endif
3696
3697 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 {
3698         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3699         U16     ControlFlags;                       /*0x08 */
3700         U16     Reserved;                           /*0x0A */
3701         U16     AdditionalControlFlags;             /*0x0C */
3702         U16     NVMeMaxQueueDepth;                  /*0x0E */
3703         U8      NumPhys;                            /*0x10 */
3704         U8      Reserved1;                          /*0x11 */
3705         U16     Reserved2;                          /*0x12 */
3706         MPI26_PCIE_IO_UNIT1_PHY_DATA
3707                 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */
3708 } MPI26_CONFIG_PAGE_PIOUNIT_1,
3709         *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1,
3710         Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t;
3711
3712 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION   (0x00)
3713
3714 /*values for PCIe IO Unit Page 1 PhyFlags */
3715 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                      (0x08)
3716 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY                    (0x01)
3717
3718 /*values for PCIe IO Unit Page 1 MaxMinLinkRate */
3719 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK                             (0xF0)
3720 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT                            (4)
3721 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5                              (0x20)
3722 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0                              (0x30)
3723 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0                              (0x40)
3724 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0                             (0x50)
3725
3726 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3727  *values
3728  */
3729
3730
3731 /****************************************************************************
3732 *  PCIe Switch Config Pages (MPI v2.6 and later)
3733 ****************************************************************************/
3734
3735 /*PCIe Switch Page 0 */
3736
3737 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 {
3738         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3739         U8      PhysicalPort;               /*0x08 */
3740         U8      Reserved1;                  /*0x09 */
3741         U16     Reserved2;                  /*0x0A */
3742         U16     DevHandle;                  /*0x0C */
3743         U16     ParentDevHandle;            /*0x0E */
3744         U8      NumPorts;                   /*0x10 */
3745         U8      PCIeLevel;                  /*0x11 */
3746         U16     Reserved3;                  /*0x12 */
3747         U32     Reserved4;                  /*0x14 */
3748         U32     Reserved5;                  /*0x18 */
3749         U32     Reserved6;                  /*0x1C */
3750 } MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0,
3751         Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t;
3752
3753 #define MPI26_PCIESWITCH0_PAGEVERSION       (0x00)
3754
3755
3756 /*PCIe Switch Page 1 */
3757
3758 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 {
3759         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3760         U8      PhysicalPort;               /*0x08 */
3761         U8      Reserved1;                  /*0x09 */
3762         U16     Reserved2;                  /*0x0A */
3763         U8      NumPorts;                   /*0x0C */
3764         U8      PortNum;                    /*0x0D */
3765         U16     AttachedDevHandle;          /*0x0E */
3766         U16     SwitchDevHandle;            /*0x10 */
3767         U8      NegotiatedPortWidth;        /*0x12 */
3768         U8      NegotiatedLinkRate;         /*0x13 */
3769         U32     Reserved4;                  /*0x14 */
3770         U32     Reserved5;                  /*0x18 */
3771 } MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1,
3772         Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t;
3773
3774 #define MPI26_PCIESWITCH1_PAGEVERSION       (0x00)
3775
3776 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3777
3778
3779 /****************************************************************************
3780 *  PCIe Device Config Pages (MPI v2.6 and later)
3781 ****************************************************************************/
3782
3783 /*PCIe Device Page 0 */
3784
3785 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 {
3786         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3787         U16     Slot;                   /*0x08 */
3788         U16     EnclosureHandle;        /*0x0A */
3789         U64     WWID;                   /*0x0C */
3790         U16     ParentDevHandle;        /*0x14 */
3791         U8      PortNum;                /*0x16 */
3792         U8      AccessStatus;           /*0x17 */
3793         U16     DevHandle;              /*0x18 */
3794         U8      PhysicalPort;           /*0x1A */
3795         U8      Reserved1;              /*0x1B */
3796         U32     DeviceInfo;             /*0x1C */
3797         U32     Flags;                  /*0x20 */
3798         U8      SupportedLinkRates;     /*0x24 */
3799         U8      MaxPortWidth;           /*0x25 */
3800         U8      NegotiatedPortWidth;    /*0x26 */
3801         U8      NegotiatedLinkRate;     /*0x27 */
3802         U8      EnclosureLevel;         /*0x28 */
3803         U8      Reserved2;              /*0x29 */
3804         U16     Reserved3;              /*0x2A */
3805         U8      ConnectorName[4];       /*0x2C */
3806         U32     Reserved4;              /*0x30 */
3807         U32     Reserved5;              /*0x34 */
3808 } MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0,
3809         Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t;
3810
3811 #define MPI26_PCIEDEVICE0_PAGEVERSION       (0x01)
3812
3813 /*values for PCIe Device Page 0 AccessStatus field */
3814 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS                    (0x00)
3815 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION         (0x04)
3816 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED            (0x02)
3817 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED               (0x07)
3818 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED   (0x08)
3819 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE           (0x09)
3820 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED                (0x0A)
3821 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN                      (0x10)
3822
3823 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT           (0x30)
3824 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED      (0x31)
3825 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED         (0x32)
3826 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED          (0x33)
3827 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED        (0x34)
3828 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED         (0x35)
3829 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
3830 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT            (0x37)
3831 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS          (0x38)
3832
3833 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX                (0x3F)
3834
3835 /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo
3836  *field
3837  */
3838
3839 /*values for PCIe Device Page 0 Flags field */
3840 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE            (0x8000)
3841 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH              (0x4000)
3842 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE              (0x2000)
3843 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION      (0x0400)
3844 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION            (0x0200)
3845 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE             (0x0100)
3846 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED        (0x0080)
3847 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED            (0x0040)
3848 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED              (0x0020)
3849 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED              (0x0010)
3850 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID               (0x0002)
3851 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT                 (0x0001)
3852
3853 /* values for PCIe Device Page 0 SupportedLinkRates field */
3854 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED             (0x08)
3855 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED              (0x04)
3856 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED              (0x02)
3857 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED              (0x01)
3858
3859 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3860
3861
3862 /*PCIe Device Page 2 */
3863
3864 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 {
3865         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3866         U16     DevHandle;              /*0x08 */
3867         U16     Reserved1;              /*0x0A */
3868         U32     MaximumDataTransferSize;/*0x0C */
3869         U32     Capabilities;           /*0x10 */
3870         U32     Reserved2;              /*0x14 */
3871 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
3872         Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t;
3873
3874 #define MPI26_PCIEDEVICE2_PAGEVERSION       (0x00)
3875
3876 /*defines for PCIe Device Page 2 Capabilities field */
3877 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT                  (0x00000004)
3878 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT          (0x00000002)
3879 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT                 (0x00000001)
3880
3881
3882 /****************************************************************************
3883 *  PCIe Link Config Pages (MPI v2.6 and later)
3884 ****************************************************************************/
3885
3886 /*PCIe Link Page 1 */
3887
3888 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 {
3889         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3890         U8      Link;                           /*0x08 */
3891         U8      Reserved1;                      /*0x09 */
3892         U16     Reserved2;                      /*0x0A */
3893         U32     CorrectableErrorCount;          /*0x0C */
3894         U16     NonFatalErrorCount;             /*0x10 */
3895         U16     Reserved3;                      /*0x12 */
3896         U16     FatalErrorCount;                /*0x14 */
3897         U16     Reserved4;                      /*0x16 */
3898 } MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1,
3899         Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t;
3900
3901 #define MPI26_PCIELINK1_PAGEVERSION            (0x00)
3902
3903 /*PCIe Link Page 2 */
3904
3905 typedef struct _MPI26_PCIELINK2_LINK_EVENT {
3906         U8      LinkEventCode;          /*0x00 */
3907         U8      Reserved1;              /*0x01 */
3908         U16     Reserved2;              /*0x02 */
3909         U32     LinkEventInfo;          /*0x04 */
3910 } MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT,
3911         Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t;
3912
3913 /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */
3914
3915
3916 /*
3917  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3918  *one and check the value returned for NumLinkEvents at runtime.
3919  */
3920 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX
3921 #define MPI26_PCIELINK2_LINK_EVENT_MAX      (1)
3922 #endif
3923
3924 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 {
3925         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
3926         U8      Link;                       /*0x08 */
3927         U8      Reserved1;                  /*0x09 */
3928         U16     Reserved2;                  /*0x0A */
3929         U8      NumLinkEvents;              /*0x0C */
3930         U8      Reserved3;                  /*0x0D */
3931         U16     Reserved4;                  /*0x0E */
3932         MPI26_PCIELINK2_LINK_EVENT
3933                 LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX];      /*0x10 */
3934 } MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2,
3935         Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t;
3936
3937 #define MPI26_PCIELINK2_PAGEVERSION            (0x00)
3938
3939 /*PCIe Link Page 3 */
3940
3941 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG {
3942         U8      LinkEventCode;      /*0x00 */
3943         U8      Reserved1;          /*0x01 */
3944         U16     Reserved2;          /*0x02 */
3945         U8      CounterType;        /*0x04 */
3946         U8      ThresholdWindow;    /*0x05 */
3947         U8      TimeUnits;          /*0x06 */
3948         U8      Reserved3;          /*0x07 */
3949         U32     EventThreshold;     /*0x08 */
3950         U16     ThresholdFlags;     /*0x0C */
3951         U16     Reserved4;          /*0x0E */
3952 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG,
3953         Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t;
3954
3955 /*values for LinkEventCode field */
3956 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT                              (0x00)
3957 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED            (0x01)
3958 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED              (0x02)
3959 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED                  (0x03)
3960 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED              (0x04)
3961 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED      (0x05)
3962 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED               (0x06)
3963 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP                          (0x07)
3964 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP                     (0x08)
3965 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP                         (0x09)
3966 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE                  (0x0A)
3967 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE                     (0x0B)
3968 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE                     (0x0C)
3969 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE                        (0x0D)
3970 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE                  (0x0E)
3971 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE                 (0x0F)
3972 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR                          (0x10)
3973 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR                          (0x11)
3974 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR                       (0x12)
3975
3976 /*values for the CounterType field */
3977 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING               (0x00)
3978 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING             (0x01)
3979 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE             (0x02)
3980
3981 /*values for the TimeUnits field */
3982 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS            (0x00)
3983 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS           (0x01)
3984 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND              (0x02)
3985 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS            (0x03)
3986
3987 /*values for the ThresholdFlags field */
3988 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY                 (0x0001)
3989
3990 /*
3991  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3992  *one and check the value returned for NumLinkEvents at runtime.
3993  */
3994 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX
3995 #define MPI26_PCIELINK3_LINK_EVENT_MAX      (1)
3996 #endif
3997
3998 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 {
3999         MPI2_CONFIG_EXTENDED_PAGE_HEADER        Header; /*0x00 */
4000         U8      Link;                       /*0x08 */
4001         U8      Reserved1;                  /*0x09 */
4002         U16     Reserved2;                  /*0x0A */
4003         U8      NumLinkEvents;              /*0x0C */
4004         U8      Reserved3;                  /*0x0D */
4005         U16     Reserved4;                  /*0x0E */
4006         MPI26_PCIELINK3_LINK_EVENT_CONFIG
4007                 LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /*0x10 */
4008 } MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3,
4009         Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t;
4010
4011 #define MPI26_PCIELINK3_PAGEVERSION            (0x00)
4012
4013
4014 #endif
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