drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_psp.h"
  29 #include "amdgpu_ras.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v11_0.h"
  33
  34 #include "mp/mp_11_0_offset.h"
  35 #include "mp/mp_11_0_sh_mask.h"
  36 #include "gc/gc_9_0_offset.h"
  37 #include "sdma0/sdma0_4_0_offset.h"
  38 #include "nbio/nbio_7_4_offset.h"
  39
  40 #include "oss/osssys_4_0_offset.h"
  41 #include "oss/osssys_4_0_sh_mask.h"
  42
  43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
  55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
  58
  59 /* address block */
  60 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  61 /* navi10 reg offset define */
  62 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  63 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  64 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  65 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  66 /* memory training timeout define */
  67 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  68
  69 /* For large FW files the time to complete can be very long */
  70 #define USBC_PD_POLLING_LIMIT_S 240
  71
  72 static int psp_v11_0_init_microcode(struct psp_context *psp)
  73 {
  74         struct amdgpu_device *adev = psp->adev;
  75         const char *chip_name;
  76         char fw_name[30];
  77         int err = 0;
  78         const struct psp_firmware_header_v1_0 *sos_hdr;
  79         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
  80         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
  81         const struct psp_firmware_header_v1_0 *asd_hdr;
  82         const struct ta_firmware_header_v1_0 *ta_hdr;
  83
  84         DRM_DEBUG("\n");
  85
  86         switch (adev->asic_type) {
  87         case CHIP_VEGA20:
  88                 chip_name = "vega20";
  89                 break;
  90         case CHIP_NAVI10:
  91                 chip_name = "navi10";
  92                 break;
  93         case CHIP_NAVI14:
  94                 chip_name = "navi14";
  95                 break;
  96         case CHIP_NAVI12:
  97                 chip_name = "navi12";
  98                 break;
  99         case CHIP_ARCTURUS:
 100                 chip_name = "arcturus";
 101                 break;
 102         default:
 103                 BUG();
 104         }
 105
 106         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
 107         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
 108         if (err)
 109                 goto out;
 110
 111         err = amdgpu_ucode_validate(adev->psp.sos_fw);
 112         if (err)
 113                 goto out;
 114
 115         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
 116         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
 117
 118         switch (sos_hdr->header.header_version_major) {
 119         case 1:
 120                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
 121                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
 122                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
 123                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
 124                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
 125                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
 126                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 127                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
 128                 if (sos_hdr->header.header_version_minor == 1) {
 129                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
 130                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
 131                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 132                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
 133                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
 134                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 135                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
 136                 }
 137                 if (sos_hdr->header.header_version_minor == 2) {
 138                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
 139                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
 140                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 141                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
 142                 }
 143                 break;
 144         default:
 145                 dev_err(adev->dev,
 146                         "Unsupported psp sos firmware\n");
 147                 err = -EINVAL;
 148                 goto out;
 149         }
 150
 151         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 152         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 153         if (err)
 154                 goto out1;
 155
 156         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 157         if (err)
 158                 goto out1;
 159
 160         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 161         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
 162         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
 163         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 164         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 165                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
 166
 167         switch (adev->asic_type) {
 168         case CHIP_VEGA20:
 169         case CHIP_ARCTURUS:
 170                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 171                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 172                 if (err) {
 173                         release_firmware(adev->psp.ta_fw);
 174                         adev->psp.ta_fw = NULL;
 175                         dev_info(adev->dev,
 176                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 177                 } else {
 178                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 179                         if (err)
 180                                 goto out2;
 181
 182                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 183                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 184                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 185                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 186                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 187                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 188                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 189                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 190                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 191                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 192                 }
 193                 break;
 194         case CHIP_NAVI10:
 195         case CHIP_NAVI14:
 196         case CHIP_NAVI12:
 197                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 198                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 199                 if (err) {
 200                         release_firmware(adev->psp.ta_fw);
 201                         adev->psp.ta_fw = NULL;
 202                         dev_info(adev->dev,
 203                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 204                 } else {
 205                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 206                         if (err)
 207                                 goto out2;
 208
 209                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 210                         adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
 211                         adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
 212                         adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
 213                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 214
 215                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 216
 217                         adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
 218                         adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
 219                         adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
 220                                 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
 221                 }
 222                 break;
 223         default:
 224                 BUG();
 225         }
 226
 227         return 0;
 228
 229 out2:
 230         release_firmware(adev->psp.ta_fw);
 231         adev->psp.ta_fw = NULL;
 232 out1:
 233         release_firmware(adev->psp.asd_fw);
 234         adev->psp.asd_fw = NULL;
 235 out:
 236         dev_err(adev->dev,
 237                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 238         release_firmware(adev->psp.sos_fw);
 239         adev->psp.sos_fw = NULL;
 240
 241         return err;
 242 }
 243
 244 int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
 245 {
 246         struct amdgpu_device *adev = psp->adev;
 247
 248         int ret;
 249         int retry_loop;
 250
 251         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 252                 /* Wait for bootloader to signify that is
 253                     ready having bit 31 of C2PMSG_35 set to 1 */
 254                 ret = psp_wait_for(psp,
 255                                    SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 256                                    0x80000000,
 257                                    0x80000000,
 258                                    false);
 259
 260                 if (ret == 0)
 261                         return 0;
 262         }
 263
 264         return ret;
 265 }
 266
 267 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
 268 {
 269         struct amdgpu_device *adev = psp->adev;
 270         uint32_t sol_reg;
 271
 272         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 273
 274         return sol_reg != 0x0;
 275 }
 276
 277 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 278 {
 279         int ret;
 280         uint32_t psp_gfxdrv_command_reg = 0;
 281         struct amdgpu_device *adev = psp->adev;
 282
 283         /* Check tOS sign of life register to confirm sys driver and sOS
 284          * are already been loaded.
 285          */
 286         if (psp_v11_0_is_sos_alive(psp)) {
 287                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 288                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 289                 return 0;
 290         }
 291
 292         ret = psp_v11_0_wait_for_bootloader(psp);
 293         if (ret)
 294                 return ret;
 295
 296         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 297
 298         /* Copy PSP KDB binary to memory */
 299         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 300
 301         /* Provide the PSP KDB to bootloader */
 302         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 303                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 304         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 305         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 306                psp_gfxdrv_command_reg);
 307
 308         ret = psp_v11_0_wait_for_bootloader(psp);
 309
 310         return ret;
 311 }
 312
 313 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 314 {
 315         int ret;
 316         uint32_t psp_gfxdrv_command_reg = 0;
 317         struct amdgpu_device *adev = psp->adev;
 318
 319         /* Check sOS sign of life register to confirm sys driver and sOS
 320          * are already been loaded.
 321          */
 322         if (psp_v11_0_is_sos_alive(psp)) {
 323                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 324                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 325                 return 0;
 326         }
 327
 328         ret = psp_v11_0_wait_for_bootloader(psp);
 329         if (ret)
 330                 return ret;
 331
 332         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 333
 334         /* Copy PSP System Driver binary to memory */
 335         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 336
 337         /* Provide the sys driver to bootloader */
 338         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 339                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 340         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 341         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 342                psp_gfxdrv_command_reg);
 343
 344         /* there might be handshake issue with hardware which needs delay */
 345         mdelay(20);
 346
 347         ret = psp_v11_0_wait_for_bootloader(psp);
 348
 349         return ret;
 350 }
 351
 352 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 353 {
 354         int ret;
 355         unsigned int psp_gfxdrv_command_reg = 0;
 356         struct amdgpu_device *adev = psp->adev;
 357
 358         /* Check sOS sign of life register to confirm sys driver and sOS
 359          * are already been loaded.
 360          */
 361         if (psp_v11_0_is_sos_alive(psp))
 362                 return 0;
 363
 364         ret = psp_v11_0_wait_for_bootloader(psp);
 365         if (ret)
 366                 return ret;
 367
 368         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 369
 370         /* Copy Secure OS binary to PSP memory */
 371         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 372
 373         /* Provide the PSP secure OS to bootloader */
 374         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 375                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 376         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 377         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 378                psp_gfxdrv_command_reg);
 379
 380         /* there might be handshake issue with hardware which needs delay */
 381         mdelay(20);
 382         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 383                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 384                            0, true);
 385
 386         return ret;
 387 }
 388
 389 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 390 {
 391         struct amdgpu_device *adev = psp->adev;
 392         uint32_t tmp;
 393
 394         /* Change IH ring for VMC */
 395         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 396         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 397         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 398
 399         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 400         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 401         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 402
 403         mdelay(20);
 404         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 405                      0x80000000, 0x8000FFFF, false);
 406
 407         /* Change IH ring for UMC */
 408         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 409         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 410
 411         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 412         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 413         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 414
 415         mdelay(20);
 416         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 417                      0x80000000, 0x8000FFFF, false);
 418 }
 419
 420 static int psp_v11_0_ring_init(struct psp_context *psp,
 421                               enum psp_ring_type ring_type)
 422 {
 423         int ret = 0;
 424         struct psp_ring *ring;
 425         struct amdgpu_device *adev = psp->adev;
 426
 427         if (!amdgpu_sriov_vf(adev))
 428                 psp_v11_0_reroute_ih(psp);
 429
 430         ring = &psp->km_ring;
 431
 432         ring->ring_type = ring_type;
 433
 434         /* allocate 4k Page of Local Frame Buffer memory for ring */
 435         ring->ring_size = 0x1000;
 436         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 437                                       AMDGPU_GEM_DOMAIN_VRAM,
 438                                       &adev->firmware.rbuf,
 439                                       &ring->ring_mem_mc_addr,
 440                                       (void **)&ring->ring_mem);
 441         if (ret) {
 442                 ring->ring_size = 0;
 443                 return ret;
 444         }
 445
 446         return 0;
 447 }
 448
 449 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 450 {
 451         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 452                 return true;
 453         return false;
 454 }
 455
 456 static int psp_v11_0_ring_stop(struct psp_context *psp,
 457                               enum psp_ring_type ring_type)
 458 {
 459         int ret = 0;
 460         struct amdgpu_device *adev = psp->adev;
 461
 462         /* Write the ring destroy command*/
 463         if (psp_v11_0_support_vmr_ring(psp))
 464                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 465                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 466         else
 467                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 468                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 469
 470         /* there might be handshake issue with hardware which needs delay */
 471         mdelay(20);
 472
 473         /* Wait for response flag (bit 31) */
 474         if (psp_v11_0_support_vmr_ring(psp))
 475                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 476                                    0x80000000, 0x80000000, false);
 477         else
 478                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 479                                    0x80000000, 0x80000000, false);
 480
 481         return ret;
 482 }
 483
 484 static int psp_v11_0_ring_create(struct psp_context *psp,
 485                                 enum psp_ring_type ring_type)
 486 {
 487         int ret = 0;
 488         unsigned int psp_ring_reg = 0;
 489         struct psp_ring *ring = &psp->km_ring;
 490         struct amdgpu_device *adev = psp->adev;
 491
 492         if (psp_v11_0_support_vmr_ring(psp)) {
 493                 ret = psp_v11_0_ring_stop(psp, ring_type);
 494                 if (ret) {
 495                         DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
 496                         return ret;
 497                 }
 498
 499                 /* Write low address of the ring to C2PMSG_102 */
 500                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 501                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 502                 /* Write high address of the ring to C2PMSG_103 */
 503                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 504                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 505
 506                 /* Write the ring initialization command to C2PMSG_101 */
 507                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 508                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 509
 510                 /* there might be handshake issue with hardware which needs delay */
 511                 mdelay(20);
 512
 513                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 514                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 515                                    0x80000000, 0x8000FFFF, false);
 516
 517         } else {
 518                 /* Wait for sOS ready for ring creation */
 519                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 520                                    0x80000000, 0x80000000, false);
 521                 if (ret) {
 522                         DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
 523                         return ret;
 524                 }
 525
 526                 /* Write low address of the ring to C2PMSG_69 */
 527                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 528                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 529                 /* Write high address of the ring to C2PMSG_70 */
 530                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 531                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 532                 /* Write size of ring to C2PMSG_71 */
 533                 psp_ring_reg = ring->ring_size;
 534                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 535                 /* Write the ring initialization command to C2PMSG_64 */
 536                 psp_ring_reg = ring_type;
 537                 psp_ring_reg = psp_ring_reg << 16;
 538                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 539
 540                 /* there might be handshake issue with hardware which needs delay */
 541                 mdelay(20);
 542
 543                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 544                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 545                                    0x80000000, 0x8000FFFF, false);
 546         }
 547
 548         return ret;
 549 }
 550
 551
 552 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 553                                  enum psp_ring_type ring_type)
 554 {
 555         int ret = 0;
 556         struct psp_ring *ring = &psp->km_ring;
 557         struct amdgpu_device *adev = psp->adev;
 558
 559         ret = psp_v11_0_ring_stop(psp, ring_type);
 560         if (ret)
 561                 DRM_ERROR("Fail to stop psp ring\n");
 562
 563         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 564                               &ring->ring_mem_mc_addr,
 565                               (void **)&ring->ring_mem);
 566
 567         return ret;
 568 }
 569
 570 static int
 571 psp_v11_0_sram_map(struct amdgpu_device *adev,
 572                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 573                   unsigned int *sram_data_reg_offset,
 574                   enum AMDGPU_UCODE_ID ucode_id)
 575 {
 576         int ret = 0;
 577
 578         switch (ucode_id) {
 579 /* TODO: needs to confirm */
 580 #if 0
 581         case AMDGPU_UCODE_ID_SMC:
 582                 *sram_offset = 0;
 583                 *sram_addr_reg_offset = 0;
 584                 *sram_data_reg_offset = 0;
 585                 break;
 586 #endif
 587
 588         case AMDGPU_UCODE_ID_CP_CE:
 589                 *sram_offset = 0x0;
 590                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 591                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 592                 break;
 593
 594         case AMDGPU_UCODE_ID_CP_PFP:
 595                 *sram_offset = 0x0;
 596                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 597                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 598                 break;
 599
 600         case AMDGPU_UCODE_ID_CP_ME:
 601                 *sram_offset = 0x0;
 602                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 603                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 604                 break;
 605
 606         case AMDGPU_UCODE_ID_CP_MEC1:
 607                 *sram_offset = 0x10000;
 608                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 609                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 610                 break;
 611
 612         case AMDGPU_UCODE_ID_CP_MEC2:
 613                 *sram_offset = 0x10000;
 614                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 615                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 616                 break;
 617
 618         case AMDGPU_UCODE_ID_RLC_G:
 619                 *sram_offset = 0x2000;
 620                 if (adev->asic_type < CHIP_NAVI10) {
 621                         *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 622                         *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 623                 } else {
 624                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
 625                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
 626                 }
 627                 break;
 628
 629         case AMDGPU_UCODE_ID_SDMA0:
 630                 *sram_offset = 0x0;
 631                 if (adev->asic_type < CHIP_NAVI10) {
 632                         *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 633                         *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 634                 } else {
 635                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
 636                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
 637                 }
 638                 break;
 639
 640 /* TODO: needs to confirm */
 641 #if 0
 642         case AMDGPU_UCODE_ID_SDMA1:
 643                 *sram_offset = ;
 644                 *sram_addr_reg_offset = ;
 645                 break;
 646
 647         case AMDGPU_UCODE_ID_UVD:
 648                 *sram_offset = ;
 649                 *sram_addr_reg_offset = ;
 650                 break;
 651
 652         case AMDGPU_UCODE_ID_VCE:
 653                 *sram_offset = ;
 654                 *sram_addr_reg_offset = ;
 655                 break;
 656 #endif
 657
 658         case AMDGPU_UCODE_ID_MAXIMUM:
 659         default:
 660                 ret = -EINVAL;
 661                 break;
 662         }
 663
 664         return ret;
 665 }
 666
 667 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 668                                        struct amdgpu_firmware_info *ucode,
 669                                        enum AMDGPU_UCODE_ID ucode_type)
 670 {
 671         int err = 0;
 672         unsigned int fw_sram_reg_val = 0;
 673         unsigned int fw_sram_addr_reg_offset = 0;
 674         unsigned int fw_sram_data_reg_offset = 0;
 675         unsigned int ucode_size;
 676         uint32_t *ucode_mem = NULL;
 677         struct amdgpu_device *adev = psp->adev;
 678
 679         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 680                                 &fw_sram_data_reg_offset, ucode_type);
 681         if (err)
 682                 return false;
 683
 684         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 685
 686         ucode_size = ucode->ucode_size;
 687         ucode_mem = (uint32_t *)ucode->kaddr;
 688         while (ucode_size) {
 689                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 690
 691                 if (*ucode_mem != fw_sram_reg_val)
 692                         return false;
 693
 694                 ucode_mem++;
 695                 /* 4 bytes */
 696                 ucode_size -= 4;
 697         }
 698
 699         return true;
 700 }
 701
 702 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 703 {
 704         int ret;
 705         uint32_t offset;
 706         struct amdgpu_device *adev = psp->adev;
 707
 708         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 709
 710         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 711
 712         if (ret) {
 713                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 714                 return -EINVAL;
 715         }
 716
 717         /*send the mode 1 reset command*/
 718         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 719
 720         msleep(500);
 721
 722         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 723
 724         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 725
 726         if (ret) {
 727                 DRM_INFO("psp mode 1 reset failed!\n");
 728                 return -EINVAL;
 729         }
 730
 731         DRM_INFO("psp mode1 reset succeed \n");
 732
 733         return 0;
 734 }
 735
 736 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 737  * For now, return success and hack the hive_id so high level code can
 738  * start testing
 739  */
 740 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 741         int number_devices, struct psp_xgmi_topology_info *topology)
 742 {
 743         struct ta_xgmi_shared_memory *xgmi_cmd;
 744         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 745         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 746         int i;
 747         int ret;
 748
 749         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 750                 return -EINVAL;
 751
 752         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 753         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 754
 755         /* Fill in the shared memory with topology information as input */
 756         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 757         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 758         topology_info_input->num_nodes = number_devices;
 759
 760         for (i = 0; i < topology_info_input->num_nodes; i++) {
 761                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 762                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 763                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 764                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 765         }
 766
 767         /* Invoke xgmi ta to get the topology information */
 768         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 769         if (ret)
 770                 return ret;
 771
 772         /* Read the output topology information from the shared memory */
 773         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 774         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 775         for (i = 0; i < topology->num_nodes; i++) {
 776                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 777                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 778                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 779                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 780         }
 781
 782         return 0;
 783 }
 784
 785 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 786         int number_devices, struct psp_xgmi_topology_info *topology)
 787 {
 788         struct ta_xgmi_shared_memory *xgmi_cmd;
 789         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 790         int i;
 791
 792         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 793                 return -EINVAL;
 794
 795         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 796         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 797
 798         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 799         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 800         topology_info_input->num_nodes = number_devices;
 801
 802         for (i = 0; i < topology_info_input->num_nodes; i++) {
 803                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 804                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 805                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 806                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 807         }
 808
 809         /* Invoke xgmi ta to set topology information */
 810         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 811 }
 812
 813 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 814 {
 815         struct ta_xgmi_shared_memory *xgmi_cmd;
 816         int ret;
 817
 818         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 819         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 820
 821         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 822
 823         /* Invoke xgmi ta to get hive id */
 824         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 825         if (ret)
 826                 return ret;
 827
 828         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 829
 830         return 0;
 831 }
 832
 833 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 834 {
 835         struct ta_xgmi_shared_memory *xgmi_cmd;
 836         int ret;
 837
 838         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 839         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 840
 841         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 842
 843         /* Invoke xgmi ta to get the node id */
 844         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 845         if (ret)
 846                 return ret;
 847
 848         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 849
 850         return 0;
 851 }
 852
 853 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
 854                 struct ta_ras_trigger_error_input *info)
 855 {
 856         struct ta_ras_shared_memory *ras_cmd;
 857         int ret;
 858
 859         if (!psp->ras.ras_initialized)
 860                 return -EINVAL;
 861
 862         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 863         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 864
 865         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
 866         ras_cmd->ras_in_message.trigger_error = *info;
 867
 868         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 869         if (ret)
 870                 return -EINVAL;
 871
 872         /* If err_event_athub occurs error inject was successful, however
 873            return status from TA is no long reliable */
 874         if (amdgpu_ras_intr_triggered())
 875                 return 0;
 876
 877         return ras_cmd->ras_status;
 878 }
 879
 880 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
 881 {
 882 #if 0
 883         // not support yet.
 884         struct ta_ras_shared_memory *ras_cmd;
 885         int ret;
 886
 887         if (!psp->ras.ras_initialized)
 888                 return -EINVAL;
 889
 890         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 891         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 892
 893         ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
 894         ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
 895
 896         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 897         if (ret)
 898                 return -EINVAL;
 899
 900         return ras_cmd->ras_status;
 901 #else
 902         return -EINVAL;
 903 #endif
 904 }
 905
 906 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
 907 {
 908         return psp_rlc_autoload_start(psp);
 909 }
 910
 911 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
 912 {
 913         int ret;
 914         int i;
 915         uint32_t data_32;
 916         int max_wait;
 917         struct amdgpu_device *adev = psp->adev;
 918
 919         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 920         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
 921         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
 922
 923         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 924         for (i = 0; i < max_wait; i++) {
 925                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 926                                    0x80000000, 0x80000000, false);
 927                 if (ret == 0)
 928                         break;
 929         }
 930         if (i < max_wait)
 931                 ret = 0;
 932         else
 933                 ret = -ETIME;
 934
 935         DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
 936                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 937                   (ret == 0) ? "succeed" : "failed",
 938                   i, adev->usec_timeout/1000);
 939         return ret;
 940 }
 941
 942 static void psp_v11_0_memory_training_fini(struct psp_context *psp)
 943 {
 944         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 945
 946         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 947         kfree(ctx->sys_cache);
 948         ctx->sys_cache = NULL;
 949 }
 950
 951 static int psp_v11_0_memory_training_init(struct psp_context *psp)
 952 {
 953         int ret;
 954         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 955
 956         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 957                 DRM_DEBUG("memory training is not supported!\n");
 958                 return 0;
 959         }
 960
 961         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 962         if (ctx->sys_cache == NULL) {
 963                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 964                 ret = -ENOMEM;
 965                 goto Err_out;
 966         }
 967
 968         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 969                   ctx->train_data_size,
 970                   ctx->p2c_train_data_offset,
 971                   ctx->c2p_train_data_offset);
 972         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 973         return 0;
 974
 975 Err_out:
 976         psp_v11_0_memory_training_fini(psp);
 977         return ret;
 978 }
 979
 980 /*
 981  * save and restore proces
 982  */
 983 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 984 {
 985         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 986         uint32_t *pcache = (uint32_t*)ctx->sys_cache;
 987         struct amdgpu_device *adev = psp->adev;
 988         uint32_t p2c_header[4];
 989         uint32_t sz;
 990         void *buf;
 991         int ret;
 992
 993         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 994                 DRM_DEBUG("Memory training is not supported.\n");
 995                 return 0;
 996         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 997                 DRM_ERROR("Memory training initialization failure.\n");
 998                 return -EINVAL;
 999         }
1000
1001         if (psp_v11_0_is_sos_alive(psp)) {
1002                 DRM_DEBUG("SOS is alive, skip memory training.\n");
1003                 return 0;
1004         }
1005
1006         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
1007         DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
1008                   pcache[0], pcache[1], pcache[2], pcache[3],
1009                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
1010
1011         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
1012                 DRM_DEBUG("Short training depends on restore.\n");
1013                 ops |= PSP_MEM_TRAIN_RESTORE;
1014         }
1015
1016         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
1017             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1018                 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
1019                 ops |= PSP_MEM_TRAIN_SAVE;
1020         }
1021
1022         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1023             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1024               pcache[3] == p2c_header[3])) {
1025                 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
1026                 ops |= PSP_MEM_TRAIN_SAVE;
1027         }
1028
1029         if ((ops & PSP_MEM_TRAIN_SAVE) &&
1030             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1031                 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
1032                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
1033         }
1034
1035         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1036                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
1037                 ops |= PSP_MEM_TRAIN_SAVE;
1038         }
1039
1040         DRM_DEBUG("Memory training ops:%x.\n", ops);
1041
1042         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1043                 /*
1044                  * Long traing will encroach certain mount of bottom VRAM,
1045                  * saving the content of this bottom VRAM to system memory
1046                  * before training, and restoring it after training to avoid
1047                  * VRAM corruption.
1048                  */
1049                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
1050
1051                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
1052                         DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
1053                                   adev->gmc.visible_vram_size,
1054                                   adev->mman.aper_base_kaddr);
1055                         return -EINVAL;
1056                 }
1057
1058                 buf = vmalloc(sz);
1059                 if (!buf) {
1060                         DRM_ERROR("failed to allocate system memory.\n");
1061                         return -ENOMEM;
1062                 }
1063
1064                 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
1065                 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
1066                 if (ret) {
1067                         DRM_ERROR("Send long training msg failed.\n");
1068                         vfree(buf);
1069                         return ret;
1070                 }
1071
1072                 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
1073                 adev->nbio.funcs->hdp_flush(adev, NULL);
1074                 vfree(buf);
1075         }
1076
1077         if (ops & PSP_MEM_TRAIN_SAVE) {
1078                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
1079         }
1080
1081         if (ops & PSP_MEM_TRAIN_RESTORE) {
1082                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
1083         }
1084
1085         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
1086                 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
1087                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
1088                 if (ret) {
1089                         DRM_ERROR("send training msg failed.\n");
1090                         return ret;
1091                 }
1092         }
1093         ctx->training_cnt++;
1094         return 0;
1095 }
1096
1097 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
1098 {
1099         uint32_t data;
1100         struct amdgpu_device *adev = psp->adev;
1101
1102         if (psp_v11_0_support_vmr_ring(psp))
1103                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
1104         else
1105                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
1106
1107         return data;
1108 }
1109
1110 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
1111 {
1112         struct amdgpu_device *adev = psp->adev;
1113
1114         if (psp_v11_0_support_vmr_ring(psp)) {
1115                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
1116                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
1117         } else
1118                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
1119 }
1120
1121 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr)
1122 {
1123         struct amdgpu_device *adev = psp->adev;
1124         uint32_t reg_status;
1125         int ret, i = 0;
1126
1127         /* Write lower 32-bit address of the PD Controller FW */
1128         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr));
1129         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
1130                              0x80000000, 0x80000000, false);
1131         if (ret)
1132                 return ret;
1133
1134         /* Fireup interrupt so PSP can pick up the lower address */
1135         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000);
1136         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
1137                              0x80000000, 0x80000000, false);
1138         if (ret)
1139                 return ret;
1140
1141         reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
1142
1143         if ((reg_status & 0xFFFF) != 0) {
1144                 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n",
1145                                 reg_status & 0xFFFF);
1146                 return -EIO;
1147         }
1148
1149         /* Write upper 32-bit address of the PD Controller FW */
1150         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr));
1151
1152         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
1153                              0x80000000, 0x80000000, false);
1154         if (ret)
1155                 return ret;
1156
1157         /* Fireup interrupt so PSP can pick up the upper address */
1158         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000);
1159
1160         /* FW load takes very long time */
1161         do {
1162                 msleep(1000);
1163                 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
1164
1165                 if (reg_status & 0x80000000)
1166                         goto done;
1167
1168         } while (++i < USBC_PD_POLLING_LIMIT_S);
1169
1170         return -ETIME;
1171 done:
1172
1173         if ((reg_status & 0xFFFF) != 0) {
1174                 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n",
1175                                 reg_status & 0xFFFF);
1176                 return -EIO;
1177         }
1178
1179         return 0;
1180 }
1181
1182 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
1183 {
1184         struct amdgpu_device *adev = psp->adev;
1185         int ret;
1186
1187         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
1188
1189         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
1190                                      0x80000000, 0x80000000, false);
1191         if (!ret)
1192                 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
1193
1194         return ret;
1195 }
1196
1197 static const struct psp_funcs psp_v11_0_funcs = {
1198         .init_microcode = psp_v11_0_init_microcode,
1199         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
1200         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
1201         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
1202         .ring_init = psp_v11_0_ring_init,
1203         .ring_create = psp_v11_0_ring_create,
1204         .ring_stop = psp_v11_0_ring_stop,
1205         .ring_destroy = psp_v11_0_ring_destroy,
1206         .compare_sram_data = psp_v11_0_compare_sram_data,
1207         .mode1_reset = psp_v11_0_mode1_reset,
1208         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
1209         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
1210         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
1211         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
1212         .support_vmr_ring = psp_v11_0_support_vmr_ring,
1213         .ras_trigger_error = psp_v11_0_ras_trigger_error,
1214         .ras_cure_posion = psp_v11_0_ras_cure_posion,
1215         .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
1216         .mem_training_init = psp_v11_0_memory_training_init,
1217         .mem_training_fini = psp_v11_0_memory_training_fini,
1218         .mem_training = psp_v11_0_memory_training,
1219         .ring_get_wptr = psp_v11_0_ring_get_wptr,
1220         .ring_set_wptr = psp_v11_0_ring_set_wptr,
1221         .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
1222         .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
1223 };
1224
1225 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
1226 {
1227         psp->funcs = &psp_v11_0_funcs;
1228 }