drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <[email protected]>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 bool intel_format_is_yuv(u32 format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51         case DRM_FORMAT_NV12:
  52                 return true;
  53         default:
  54                 return false;
  55         }
  56 }
  57
  58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  59                              int usecs)
  60 {
  61         /* paranoia */
  62         if (!adjusted_mode->crtc_htotal)
  63                 return 1;
  64
  65         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  66                             1000 * adjusted_mode->crtc_htotal);
  67 }
  68
  69 /* FIXME: We should instead only take spinlocks once for the entire update
  70  * instead of once per mmio. */
  71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  72 #define VBLANK_EVASION_TIME_US 250
  73 #else
  74 #define VBLANK_EVASION_TIME_US 100
  75 #endif
  76
  77 /**
  78  * intel_pipe_update_start() - start update of a set of display registers
  79  * @new_crtc_state: the new crtc state
  80  *
  81  * Mark the start of an update to pipe registers that should be updated
  82  * atomically regarding vblank. If the next vblank will happens within
  83  * the next 100 us, this function waits until the vblank passes.
  84  *
  85  * After a successful call to this function, interrupts will be disabled
  86  * until a subsequent call to intel_pipe_update_end(). That is done to
  87  * avoid random delays.
  88  */
  89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  90 {
  91         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  92         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  93         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  94         long timeout = msecs_to_jiffies_timeout(1);
  95         int scanline, min, max, vblank_start;
  96         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  97         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  98                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  99         DEFINE_WAIT(wait);
 100
 101         vblank_start = adjusted_mode->crtc_vblank_start;
 102         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 103                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
 104
 105         /* FIXME needs to be calibrated sensibly */
 106         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 107                                                       VBLANK_EVASION_TIME_US);
 108         max = vblank_start - 1;
 109
 110         local_irq_disable();
 111
 112         if (min <= 0 || max <= 0)
 113                 return;
 114
 115         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 116                 return;
 117
 118         crtc->debug.min_vbl = min;
 119         crtc->debug.max_vbl = max;
 120         trace_i915_pipe_update_start(crtc);
 121
 122         for (;;) {
 123                 /*
 124                  * prepare_to_wait() has a memory barrier, which guarantees
 125                  * other CPUs can see the task state update by the time we
 126                  * read the scanline.
 127                  */
 128                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 129
 130                 scanline = intel_get_crtc_scanline(crtc);
 131                 if (scanline < min || scanline > max)
 132                         break;
 133
 134                 if (!timeout) {
 135                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 136                                   pipe_name(crtc->pipe));
 137                         break;
 138                 }
 139
 140                 local_irq_enable();
 141
 142                 timeout = schedule_timeout(timeout);
 143
 144                 local_irq_disable();
 145         }
 146
 147         finish_wait(wq, &wait);
 148
 149         drm_crtc_vblank_put(&crtc->base);
 150
 151         /*
 152          * On VLV/CHV DSI the scanline counter would appear to
 153          * increment approx. 1/3 of a scanline before start of vblank.
 154          * The registers still get latched at start of vblank however.
 155          * This means we must not write any registers on the first
 156          * line of vblank (since not the whole line is actually in
 157          * vblank). And unfortunately we can't use the interrupt to
 158          * wait here since it will fire too soon. We could use the
 159          * frame start interrupt instead since it will fire after the
 160          * critical scanline, but that would require more changes
 161          * in the interrupt code. So for now we'll just do the nasty
 162          * thing and poll for the bad scanline to pass us by.
 163          *
 164          * FIXME figure out if BXT+ DSI suffers from this as well
 165          */
 166         while (need_vlv_dsi_wa && scanline == vblank_start)
 167                 scanline = intel_get_crtc_scanline(crtc);
 168
 169         crtc->debug.scanline_start = scanline;
 170         crtc->debug.start_vbl_time = ktime_get();
 171         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 172
 173         trace_i915_pipe_update_vblank_evaded(crtc);
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 void
 234 skl_update_plane(struct intel_plane *plane,
 235                  const struct intel_crtc_state *crtc_state,
 236                  const struct intel_plane_state *plane_state)
 237 {
 238         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 239         const struct drm_framebuffer *fb = plane_state->base.fb;
 240         enum plane_id plane_id = plane->id;
 241         enum pipe pipe = plane->pipe;
 242         u32 plane_ctl = plane_state->ctl;
 243         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 244         u32 surf_addr = plane_state->main.offset;
 245         unsigned int rotation = plane_state->base.rotation;
 246         u32 stride = skl_plane_stride(fb, 0, rotation);
 247         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
 248         int crtc_x = plane_state->base.dst.x1;
 249         int crtc_y = plane_state->base.dst.y1;
 250         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 251         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 252         uint32_t x = plane_state->main.x;
 253         uint32_t y = plane_state->main.y;
 254         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 255         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 256         unsigned long irqflags;
 257
 258         /* Sizes are 0 based */
 259         src_w--;
 260         src_h--;
 261         crtc_w--;
 262         crtc_h--;
 263
 264         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 265
 266         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 267                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 268                               plane_state->color_ctl);
 269
 270         if (key->flags) {
 271                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 272                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 273                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 274         }
 275
 276         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 277         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 278         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 279         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 280                       (plane_state->aux.offset - surf_addr) | aux_stride);
 281         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 282                       (plane_state->aux.y << 16) | plane_state->aux.x);
 283
 284         /* program plane scaler */
 285         if (plane_state->scaler_id >= 0) {
 286                 int scaler_id = plane_state->scaler_id;
 287                 const struct intel_scaler *scaler;
 288
 289                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 290
 291                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 292                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 293                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 294                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 295                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 296                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 297
 298                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 299         } else {
 300                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 301         }
 302
 303         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 304         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 305                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 306         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 307
 308         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 309 }
 310
 311 void
 312 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 313 {
 314         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 315         enum plane_id plane_id = plane->id;
 316         enum pipe pipe = plane->pipe;
 317         unsigned long irqflags;
 318
 319         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 320
 321         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 322
 323         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 324         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 325
 326         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 327 }
 328
 329 bool
 330 skl_plane_get_hw_state(struct intel_plane *plane)
 331 {
 332         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 333         enum intel_display_power_domain power_domain;
 334         enum plane_id plane_id = plane->id;
 335         enum pipe pipe = plane->pipe;
 336         bool ret;
 337
 338         power_domain = POWER_DOMAIN_PIPE(pipe);
 339         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 340                 return false;
 341
 342         ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
 343
 344         intel_display_power_put(dev_priv, power_domain);
 345
 346         return ret;
 347 }
 348
 349 static void
 350 chv_update_csc(const struct intel_plane_state *plane_state)
 351 {
 352         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 353         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 354         const struct drm_framebuffer *fb = plane_state->base.fb;
 355         enum plane_id plane_id = plane->id;
 356         /*
 357          * |r|   | c0 c1 c2 |   |cr|
 358          * |g| = | c3 c4 c5 | x |y |
 359          * |b|   | c6 c7 c8 |   |cb|
 360          *
 361          * Coefficients are s3.12.
 362          *
 363          * Cb and Cr apparently come in as signed already, and
 364          * we always get full range data in on account of CLRC0/1.
 365          */
 366         static const s16 csc_matrix[][9] = {
 367                 /* BT.601 full range YCbCr -> full range RGB */
 368                 [DRM_COLOR_YCBCR_BT601] = {
 369                          5743, 4096,     0,
 370                         -2925, 4096, -1410,
 371                             0, 4096,  7258,
 372                 },
 373                 /* BT.709 full range YCbCr -> full range RGB */
 374                 [DRM_COLOR_YCBCR_BT709] = {
 375                          6450, 4096,     0,
 376                         -1917, 4096,  -767,
 377                             0, 4096,  7601,
 378                 },
 379         };
 380         const s16 *csc = csc_matrix[plane_state->base.color_encoding];
 381
 382         /* Seems RGB data bypasses the CSC always */
 383         if (!intel_format_is_yuv(fb->format->format))
 384                 return;
 385
 386         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 387         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 388         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 389
 390         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
 391         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
 392         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
 393         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
 394         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
 395
 396         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
 397         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 398         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 399
 400         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 401         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 402         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 403 }
 404
 405 #define SIN_0 0
 406 #define COS_0 1
 407
 408 static void
 409 vlv_update_clrc(const struct intel_plane_state *plane_state)
 410 {
 411         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 412         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 413         const struct drm_framebuffer *fb = plane_state->base.fb;
 414         enum pipe pipe = plane->pipe;
 415         enum plane_id plane_id = plane->id;
 416         int contrast, brightness, sh_scale, sh_sin, sh_cos;
 417
 418         if (intel_format_is_yuv(fb->format->format) &&
 419             plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 420                 /*
 421                  * Expand limited range to full range:
 422                  * Contrast is applied first and is used to expand Y range.
 423                  * Brightness is applied second and is used to remove the
 424                  * offset from Y. Saturation/hue is used to expand CbCr range.
 425                  */
 426                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
 427                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
 428                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
 429                 sh_sin = SIN_0 * sh_scale;
 430                 sh_cos = COS_0 * sh_scale;
 431         } else {
 432                 /* Pass-through everything. */
 433                 contrast = 1 << 6;
 434                 brightness = 0;
 435                 sh_scale = 1 << 7;
 436                 sh_sin = SIN_0 * sh_scale;
 437                 sh_cos = COS_0 * sh_scale;
 438         }
 439
 440         /* FIXME these register are single buffered :( */
 441         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
 442                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
 443         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
 444                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 445 }
 446
 447 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 448                           const struct intel_plane_state *plane_state)
 449 {
 450         const struct drm_framebuffer *fb = plane_state->base.fb;
 451         unsigned int rotation = plane_state->base.rotation;
 452         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 453         u32 sprctl;
 454
 455         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 456
 457         switch (fb->format->format) {
 458         case DRM_FORMAT_YUYV:
 459                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 460                 break;
 461         case DRM_FORMAT_YVYU:
 462                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 463                 break;
 464         case DRM_FORMAT_UYVY:
 465                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 466                 break;
 467         case DRM_FORMAT_VYUY:
 468                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 469                 break;
 470         case DRM_FORMAT_RGB565:
 471                 sprctl |= SP_FORMAT_BGR565;
 472                 break;
 473         case DRM_FORMAT_XRGB8888:
 474                 sprctl |= SP_FORMAT_BGRX8888;
 475                 break;
 476         case DRM_FORMAT_ARGB8888:
 477                 sprctl |= SP_FORMAT_BGRA8888;
 478                 break;
 479         case DRM_FORMAT_XBGR2101010:
 480                 sprctl |= SP_FORMAT_RGBX1010102;
 481                 break;
 482         case DRM_FORMAT_ABGR2101010:
 483                 sprctl |= SP_FORMAT_RGBA1010102;
 484                 break;
 485         case DRM_FORMAT_XBGR8888:
 486                 sprctl |= SP_FORMAT_RGBX8888;
 487                 break;
 488         case DRM_FORMAT_ABGR8888:
 489                 sprctl |= SP_FORMAT_RGBA8888;
 490                 break;
 491         default:
 492                 MISSING_CASE(fb->format->format);
 493                 return 0;
 494         }
 495
 496         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 497                 sprctl |= SP_YUV_FORMAT_BT709;
 498
 499         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 500                 sprctl |= SP_TILED;
 501
 502         if (rotation & DRM_MODE_ROTATE_180)
 503                 sprctl |= SP_ROTATE_180;
 504
 505         if (rotation & DRM_MODE_REFLECT_X)
 506                 sprctl |= SP_MIRROR;
 507
 508         if (key->flags & I915_SET_COLORKEY_SOURCE)
 509                 sprctl |= SP_SOURCE_KEY;
 510
 511         return sprctl;
 512 }
 513
 514 static void
 515 vlv_update_plane(struct intel_plane *plane,
 516                  const struct intel_crtc_state *crtc_state,
 517                  const struct intel_plane_state *plane_state)
 518 {
 519         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 520         const struct drm_framebuffer *fb = plane_state->base.fb;
 521         enum pipe pipe = plane->pipe;
 522         enum plane_id plane_id = plane->id;
 523         u32 sprctl = plane_state->ctl;
 524         u32 sprsurf_offset = plane_state->main.offset;
 525         u32 linear_offset;
 526         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 527         int crtc_x = plane_state->base.dst.x1;
 528         int crtc_y = plane_state->base.dst.y1;
 529         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 530         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 531         uint32_t x = plane_state->main.x;
 532         uint32_t y = plane_state->main.y;
 533         unsigned long irqflags;
 534
 535         /* Sizes are 0 based */
 536         crtc_w--;
 537         crtc_h--;
 538
 539         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 540
 541         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 542
 543         vlv_update_clrc(plane_state);
 544
 545         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 546                 chv_update_csc(plane_state);
 547
 548         if (key->flags) {
 549                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 550                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 551                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 552         }
 553         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 554         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 555
 556         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 557                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 558         else
 559                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 560
 561         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 562
 563         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 564         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 565         I915_WRITE_FW(SPSURF(pipe, plane_id),
 566                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 567         POSTING_READ_FW(SPSURF(pipe, plane_id));
 568
 569         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 570 }
 571
 572 static void
 573 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 574 {
 575         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 576         enum pipe pipe = plane->pipe;
 577         enum plane_id plane_id = plane->id;
 578         unsigned long irqflags;
 579
 580         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 581
 582         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 583
 584         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 585         POSTING_READ_FW(SPSURF(pipe, plane_id));
 586
 587         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 588 }
 589
 590 static bool
 591 vlv_plane_get_hw_state(struct intel_plane *plane)
 592 {
 593         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 594         enum intel_display_power_domain power_domain;
 595         enum plane_id plane_id = plane->id;
 596         enum pipe pipe = plane->pipe;
 597         bool ret;
 598
 599         power_domain = POWER_DOMAIN_PIPE(pipe);
 600         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 601                 return false;
 602
 603         ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
 604
 605         intel_display_power_put(dev_priv, power_domain);
 606
 607         return ret;
 608 }
 609
 610 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 611                           const struct intel_plane_state *plane_state)
 612 {
 613         struct drm_i915_private *dev_priv =
 614                 to_i915(plane_state->base.plane->dev);
 615         const struct drm_framebuffer *fb = plane_state->base.fb;
 616         unsigned int rotation = plane_state->base.rotation;
 617         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 618         u32 sprctl;
 619
 620         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 621
 622         if (IS_IVYBRIDGE(dev_priv))
 623                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 624
 625         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 626                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 627
 628         switch (fb->format->format) {
 629         case DRM_FORMAT_XBGR8888:
 630                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 631                 break;
 632         case DRM_FORMAT_XRGB8888:
 633                 sprctl |= SPRITE_FORMAT_RGBX888;
 634                 break;
 635         case DRM_FORMAT_YUYV:
 636                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 637                 break;
 638         case DRM_FORMAT_YVYU:
 639                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 640                 break;
 641         case DRM_FORMAT_UYVY:
 642                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 643                 break;
 644         case DRM_FORMAT_VYUY:
 645                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 646                 break;
 647         default:
 648                 MISSING_CASE(fb->format->format);
 649                 return 0;
 650         }
 651
 652         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 653                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 654
 655         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 656                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
 657
 658         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 659                 sprctl |= SPRITE_TILED;
 660
 661         if (rotation & DRM_MODE_ROTATE_180)
 662                 sprctl |= SPRITE_ROTATE_180;
 663
 664         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 665                 sprctl |= SPRITE_DEST_KEY;
 666         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 667                 sprctl |= SPRITE_SOURCE_KEY;
 668
 669         return sprctl;
 670 }
 671
 672 static void
 673 ivb_update_plane(struct intel_plane *plane,
 674                  const struct intel_crtc_state *crtc_state,
 675                  const struct intel_plane_state *plane_state)
 676 {
 677         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 678         const struct drm_framebuffer *fb = plane_state->base.fb;
 679         enum pipe pipe = plane->pipe;
 680         u32 sprctl = plane_state->ctl, sprscale = 0;
 681         u32 sprsurf_offset = plane_state->main.offset;
 682         u32 linear_offset;
 683         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 684         int crtc_x = plane_state->base.dst.x1;
 685         int crtc_y = plane_state->base.dst.y1;
 686         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 687         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 688         uint32_t x = plane_state->main.x;
 689         uint32_t y = plane_state->main.y;
 690         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 691         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 692         unsigned long irqflags;
 693
 694         /* Sizes are 0 based */
 695         src_w--;
 696         src_h--;
 697         crtc_w--;
 698         crtc_h--;
 699
 700         if (crtc_w != src_w || crtc_h != src_h)
 701                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 702
 703         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 704
 705         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 706
 707         if (key->flags) {
 708                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 709                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 710                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 711         }
 712
 713         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 714         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 715
 716         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 717          * register */
 718         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 719                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 720         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 721                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 722         else
 723                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 724
 725         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 726         if (plane->can_scale)
 727                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 728         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 729         I915_WRITE_FW(SPRSURF(pipe),
 730                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 731         POSTING_READ_FW(SPRSURF(pipe));
 732
 733         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 734 }
 735
 736 static void
 737 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 738 {
 739         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 740         enum pipe pipe = plane->pipe;
 741         unsigned long irqflags;
 742
 743         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 744
 745         I915_WRITE_FW(SPRCTL(pipe), 0);
 746         /* Can't leave the scaler enabled... */
 747         if (plane->can_scale)
 748                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 749
 750         I915_WRITE_FW(SPRSURF(pipe), 0);
 751         POSTING_READ_FW(SPRSURF(pipe));
 752
 753         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 754 }
 755
 756 static bool
 757 ivb_plane_get_hw_state(struct intel_plane *plane)
 758 {
 759         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 760         enum intel_display_power_domain power_domain;
 761         enum pipe pipe = plane->pipe;
 762         bool ret;
 763
 764         power_domain = POWER_DOMAIN_PIPE(pipe);
 765         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 766                 return false;
 767
 768         ret =  I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
 769
 770         intel_display_power_put(dev_priv, power_domain);
 771
 772         return ret;
 773 }
 774
 775 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 776                           const struct intel_plane_state *plane_state)
 777 {
 778         struct drm_i915_private *dev_priv =
 779                 to_i915(plane_state->base.plane->dev);
 780         const struct drm_framebuffer *fb = plane_state->base.fb;
 781         unsigned int rotation = plane_state->base.rotation;
 782         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 783         u32 dvscntr;
 784
 785         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 786
 787         if (IS_GEN6(dev_priv))
 788                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 789
 790         switch (fb->format->format) {
 791         case DRM_FORMAT_XBGR8888:
 792                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 793                 break;
 794         case DRM_FORMAT_XRGB8888:
 795                 dvscntr |= DVS_FORMAT_RGBX888;
 796                 break;
 797         case DRM_FORMAT_YUYV:
 798                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 799                 break;
 800         case DRM_FORMAT_YVYU:
 801                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 802                 break;
 803         case DRM_FORMAT_UYVY:
 804                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 805                 break;
 806         case DRM_FORMAT_VYUY:
 807                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 808                 break;
 809         default:
 810                 MISSING_CASE(fb->format->format);
 811                 return 0;
 812         }
 813
 814         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 815                 dvscntr |= DVS_YUV_FORMAT_BT709;
 816
 817         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 818                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
 819
 820         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 821                 dvscntr |= DVS_TILED;
 822
 823         if (rotation & DRM_MODE_ROTATE_180)
 824                 dvscntr |= DVS_ROTATE_180;
 825
 826         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 827                 dvscntr |= DVS_DEST_KEY;
 828         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 829                 dvscntr |= DVS_SOURCE_KEY;
 830
 831         return dvscntr;
 832 }
 833
 834 static void
 835 g4x_update_plane(struct intel_plane *plane,
 836                  const struct intel_crtc_state *crtc_state,
 837                  const struct intel_plane_state *plane_state)
 838 {
 839         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 840         const struct drm_framebuffer *fb = plane_state->base.fb;
 841         enum pipe pipe = plane->pipe;
 842         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 843         u32 dvssurf_offset = plane_state->main.offset;
 844         u32 linear_offset;
 845         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 846         int crtc_x = plane_state->base.dst.x1;
 847         int crtc_y = plane_state->base.dst.y1;
 848         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 849         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 850         uint32_t x = plane_state->main.x;
 851         uint32_t y = plane_state->main.y;
 852         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 853         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 854         unsigned long irqflags;
 855
 856         /* Sizes are 0 based */
 857         src_w--;
 858         src_h--;
 859         crtc_w--;
 860         crtc_h--;
 861
 862         if (crtc_w != src_w || crtc_h != src_h)
 863                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 864
 865         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 866
 867         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 868
 869         if (key->flags) {
 870                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 871                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 872                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 873         }
 874
 875         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 876         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 877
 878         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 879                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 880         else
 881                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 882
 883         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 884         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 885         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 886         I915_WRITE_FW(DVSSURF(pipe),
 887                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 888         POSTING_READ_FW(DVSSURF(pipe));
 889
 890         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 891 }
 892
 893 static void
 894 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 895 {
 896         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 897         enum pipe pipe = plane->pipe;
 898         unsigned long irqflags;
 899
 900         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 901
 902         I915_WRITE_FW(DVSCNTR(pipe), 0);
 903         /* Disable the scaler */
 904         I915_WRITE_FW(DVSSCALE(pipe), 0);
 905
 906         I915_WRITE_FW(DVSSURF(pipe), 0);
 907         POSTING_READ_FW(DVSSURF(pipe));
 908
 909         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 910 }
 911
 912 static bool
 913 g4x_plane_get_hw_state(struct intel_plane *plane)
 914 {
 915         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 916         enum intel_display_power_domain power_domain;
 917         enum pipe pipe = plane->pipe;
 918         bool ret;
 919
 920         power_domain = POWER_DOMAIN_PIPE(pipe);
 921         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 922                 return false;
 923
 924         ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
 925
 926         intel_display_power_put(dev_priv, power_domain);
 927
 928         return ret;
 929 }
 930
 931 static int
 932 intel_check_sprite_plane(struct intel_plane *plane,
 933                          struct intel_crtc_state *crtc_state,
 934                          struct intel_plane_state *state)
 935 {
 936         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 937         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 938         struct drm_framebuffer *fb = state->base.fb;
 939         int crtc_x, crtc_y;
 940         unsigned int crtc_w, crtc_h;
 941         uint32_t src_x, src_y, src_w, src_h;
 942         struct drm_rect *src = &state->base.src;
 943         struct drm_rect *dst = &state->base.dst;
 944         struct drm_rect clip = {};
 945         int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
 946         int hscale, vscale;
 947         int max_scale, min_scale;
 948         bool can_scale;
 949         int ret;
 950         uint32_t pixel_format = 0;
 951
 952         *src = drm_plane_state_src(&state->base);
 953         *dst = drm_plane_state_dest(&state->base);
 954
 955         if (!fb) {
 956                 state->base.visible = false;
 957                 return 0;
 958         }
 959
 960         /* Don't modify another pipe's plane */
 961         if (plane->pipe != crtc->pipe) {
 962                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 963                 return -EINVAL;
 964         }
 965
 966         /* FIXME check all gen limits */
 967         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > max_stride) {
 968                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 969                 return -EINVAL;
 970         }
 971
 972         /* setup can_scale, min_scale, max_scale */
 973         if (INTEL_GEN(dev_priv) >= 9) {
 974                 if (state->base.fb)
 975                         pixel_format = state->base.fb->format->format;
 976                 /* use scaler when colorkey is not required */
 977                 if (!state->ckey.flags) {
 978                         can_scale = 1;
 979                         min_scale = 1;
 980                         max_scale =
 981                                 skl_max_scale(crtc, crtc_state, pixel_format);
 982                 } else {
 983                         can_scale = 0;
 984                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 985                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 986                 }
 987         } else {
 988                 can_scale = plane->can_scale;
 989                 max_scale = plane->max_downscale << 16;
 990                 min_scale = plane->can_scale ? 1 : (1 << 16);
 991         }
 992
 993         /*
 994          * FIXME the following code does a bunch of fuzzy adjustments to the
 995          * coordinates and sizes. We probably need some way to decide whether
 996          * more strict checking should be done instead.
 997          */
 998         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 999                         state->base.rotation);
1000
1001         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
1002         BUG_ON(hscale < 0);
1003
1004         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
1005         BUG_ON(vscale < 0);
1006
1007         if (crtc_state->base.enable)
1008                 drm_mode_get_hv_timing(&crtc_state->base.mode,
1009                                        &clip.x2, &clip.y2);
1010
1011         state->base.visible = drm_rect_clip_scaled(src, dst, &clip, hscale, vscale);
1012
1013         crtc_x = dst->x1;
1014         crtc_y = dst->y1;
1015         crtc_w = drm_rect_width(dst);
1016         crtc_h = drm_rect_height(dst);
1017
1018         if (state->base.visible) {
1019                 /* check again in case clipping clamped the results */
1020                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
1021                 if (hscale < 0) {
1022                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
1023                         drm_rect_debug_print("src: ", src, true);
1024                         drm_rect_debug_print("dst: ", dst, false);
1025
1026                         return hscale;
1027                 }
1028
1029                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
1030                 if (vscale < 0) {
1031                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
1032                         drm_rect_debug_print("src: ", src, true);
1033                         drm_rect_debug_print("dst: ", dst, false);
1034
1035                         return vscale;
1036                 }
1037
1038                 /* Make the source viewport size an exact multiple of the scaling factors. */
1039                 drm_rect_adjust_size(src,
1040                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
1041                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
1042
1043                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
1044                                     state->base.rotation);
1045
1046                 /* sanity check to make sure the src viewport wasn't enlarged */
1047                 WARN_ON(src->x1 < (int) state->base.src_x ||
1048                         src->y1 < (int) state->base.src_y ||
1049                         src->x2 > (int) state->base.src_x + state->base.src_w ||
1050                         src->y2 > (int) state->base.src_y + state->base.src_h);
1051
1052                 /*
1053                  * Hardware doesn't handle subpixel coordinates.
1054                  * Adjust to (macro)pixel boundary, but be careful not to
1055                  * increase the source viewport size, because that could
1056                  * push the downscaling factor out of bounds.
1057                  */
1058                 src_x = src->x1 >> 16;
1059                 src_w = drm_rect_width(src) >> 16;
1060                 src_y = src->y1 >> 16;
1061                 src_h = drm_rect_height(src) >> 16;
1062
1063                 if (intel_format_is_yuv(fb->format->format) &&
1064                     fb->format->format != DRM_FORMAT_NV12) {
1065                         src_x &= ~1;
1066                         src_w &= ~1;
1067
1068                         /*
1069                          * Must keep src and dst the
1070                          * same if we can't scale.
1071                          */
1072                         if (!can_scale)
1073                                 crtc_w &= ~1;
1074
1075                         if (crtc_w == 0)
1076                                 state->base.visible = false;
1077                 }
1078         }
1079
1080         /* Check size restrictions when scaling */
1081         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
1082                 unsigned int width_bytes;
1083                 int cpp = fb->format->cpp[0];
1084
1085                 WARN_ON(!can_scale);
1086
1087                 /* FIXME interlacing min height is 6 */
1088
1089                 if (crtc_w < 3 || crtc_h < 3)
1090                         state->base.visible = false;
1091
1092                 if (src_w < 3 || src_h < 3)
1093                         state->base.visible = false;
1094
1095                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1096
1097                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
1098                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
1099                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1100                         return -EINVAL;
1101                 }
1102         }
1103
1104         if (state->base.visible) {
1105                 src->x1 = src_x << 16;
1106                 src->x2 = (src_x + src_w) << 16;
1107                 src->y1 = src_y << 16;
1108                 src->y2 = (src_y + src_h) << 16;
1109         }
1110
1111         dst->x1 = crtc_x;
1112         dst->x2 = crtc_x + crtc_w;
1113         dst->y1 = crtc_y;
1114         dst->y2 = crtc_y + crtc_h;
1115
1116         if (INTEL_GEN(dev_priv) >= 9) {
1117                 ret = skl_check_plane_surface(crtc_state, state);
1118                 if (ret)
1119                         return ret;
1120
1121                 state->ctl = skl_plane_ctl(crtc_state, state);
1122         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1123                 ret = i9xx_check_plane_surface(state);
1124                 if (ret)
1125                         return ret;
1126
1127                 state->ctl = vlv_sprite_ctl(crtc_state, state);
1128         } else if (INTEL_GEN(dev_priv) >= 7) {
1129                 ret = i9xx_check_plane_surface(state);
1130                 if (ret)
1131                         return ret;
1132
1133                 state->ctl = ivb_sprite_ctl(crtc_state, state);
1134         } else {
1135                 ret = i9xx_check_plane_surface(state);
1136                 if (ret)
1137                         return ret;
1138
1139                 state->ctl = g4x_sprite_ctl(crtc_state, state);
1140         }
1141
1142         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1143                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
1144
1145         return 0;
1146 }
1147
1148 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1149                                     struct drm_file *file_priv)
1150 {
1151         struct drm_i915_private *dev_priv = to_i915(dev);
1152         struct drm_intel_sprite_colorkey *set = data;
1153         struct drm_plane *plane;
1154         struct drm_plane_state *plane_state;
1155         struct drm_atomic_state *state;
1156         struct drm_modeset_acquire_ctx ctx;
1157         int ret = 0;
1158
1159         /* ignore the pointless "none" flag */
1160         set->flags &= ~I915_SET_COLORKEY_NONE;
1161
1162         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1163                 return -EINVAL;
1164
1165         /* Make sure we don't try to enable both src & dest simultaneously */
1166         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1167                 return -EINVAL;
1168
1169         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1170             set->flags & I915_SET_COLORKEY_DESTINATION)
1171                 return -EINVAL;
1172
1173         plane = drm_plane_find(dev, file_priv, set->plane_id);
1174         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1175                 return -ENOENT;
1176
1177         drm_modeset_acquire_init(&ctx, 0);
1178
1179         state = drm_atomic_state_alloc(plane->dev);
1180         if (!state) {
1181                 ret = -ENOMEM;
1182                 goto out;
1183         }
1184         state->acquire_ctx = &ctx;
1185
1186         while (1) {
1187                 plane_state = drm_atomic_get_plane_state(state, plane);
1188                 ret = PTR_ERR_OR_ZERO(plane_state);
1189                 if (!ret) {
1190                         to_intel_plane_state(plane_state)->ckey = *set;
1191                         ret = drm_atomic_commit(state);
1192                 }
1193
1194                 if (ret != -EDEADLK)
1195                         break;
1196
1197                 drm_atomic_state_clear(state);
1198                 drm_modeset_backoff(&ctx);
1199         }
1200
1201         drm_atomic_state_put(state);
1202 out:
1203         drm_modeset_drop_locks(&ctx);
1204         drm_modeset_acquire_fini(&ctx);
1205         return ret;
1206 }
1207
1208 static const uint32_t g4x_plane_formats[] = {
1209         DRM_FORMAT_XRGB8888,
1210         DRM_FORMAT_YUYV,
1211         DRM_FORMAT_YVYU,
1212         DRM_FORMAT_UYVY,
1213         DRM_FORMAT_VYUY,
1214 };
1215
1216 static const uint64_t i9xx_plane_format_modifiers[] = {
1217         I915_FORMAT_MOD_X_TILED,
1218         DRM_FORMAT_MOD_LINEAR,
1219         DRM_FORMAT_MOD_INVALID
1220 };
1221
1222 static const uint32_t snb_plane_formats[] = {
1223         DRM_FORMAT_XBGR8888,
1224         DRM_FORMAT_XRGB8888,
1225         DRM_FORMAT_YUYV,
1226         DRM_FORMAT_YVYU,
1227         DRM_FORMAT_UYVY,
1228         DRM_FORMAT_VYUY,
1229 };
1230
1231 static const uint32_t vlv_plane_formats[] = {
1232         DRM_FORMAT_RGB565,
1233         DRM_FORMAT_ABGR8888,
1234         DRM_FORMAT_ARGB8888,
1235         DRM_FORMAT_XBGR8888,
1236         DRM_FORMAT_XRGB8888,
1237         DRM_FORMAT_XBGR2101010,
1238         DRM_FORMAT_ABGR2101010,
1239         DRM_FORMAT_YUYV,
1240         DRM_FORMAT_YVYU,
1241         DRM_FORMAT_UYVY,
1242         DRM_FORMAT_VYUY,
1243 };
1244
1245 static uint32_t skl_plane_formats[] = {
1246         DRM_FORMAT_RGB565,
1247         DRM_FORMAT_ABGR8888,
1248         DRM_FORMAT_ARGB8888,
1249         DRM_FORMAT_XBGR8888,
1250         DRM_FORMAT_XRGB8888,
1251         DRM_FORMAT_YUYV,
1252         DRM_FORMAT_YVYU,
1253         DRM_FORMAT_UYVY,
1254         DRM_FORMAT_VYUY,
1255 };
1256
1257 static uint32_t skl_planar_formats[] = {
1258         DRM_FORMAT_RGB565,
1259         DRM_FORMAT_ABGR8888,
1260         DRM_FORMAT_ARGB8888,
1261         DRM_FORMAT_XBGR8888,
1262         DRM_FORMAT_XRGB8888,
1263         DRM_FORMAT_YUYV,
1264         DRM_FORMAT_YVYU,
1265         DRM_FORMAT_UYVY,
1266         DRM_FORMAT_VYUY,
1267         DRM_FORMAT_NV12,
1268 };
1269
1270 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1271         I915_FORMAT_MOD_Yf_TILED,
1272         I915_FORMAT_MOD_Y_TILED,
1273         I915_FORMAT_MOD_X_TILED,
1274         DRM_FORMAT_MOD_LINEAR,
1275         DRM_FORMAT_MOD_INVALID
1276 };
1277
1278 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1279         I915_FORMAT_MOD_Yf_TILED_CCS,
1280         I915_FORMAT_MOD_Y_TILED_CCS,
1281         I915_FORMAT_MOD_Yf_TILED,
1282         I915_FORMAT_MOD_Y_TILED,
1283         I915_FORMAT_MOD_X_TILED,
1284         DRM_FORMAT_MOD_LINEAR,
1285         DRM_FORMAT_MOD_INVALID
1286 };
1287
1288 static bool g4x_mod_supported(uint32_t format, uint64_t modifier)
1289 {
1290         switch (format) {
1291         case DRM_FORMAT_XRGB8888:
1292         case DRM_FORMAT_YUYV:
1293         case DRM_FORMAT_YVYU:
1294         case DRM_FORMAT_UYVY:
1295         case DRM_FORMAT_VYUY:
1296                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1297                     modifier == I915_FORMAT_MOD_X_TILED)
1298                         return true;
1299                 /* fall through */
1300         default:
1301                 return false;
1302         }
1303 }
1304
1305 static bool snb_mod_supported(uint32_t format, uint64_t modifier)
1306 {
1307         switch (format) {
1308         case DRM_FORMAT_XRGB8888:
1309         case DRM_FORMAT_XBGR8888:
1310         case DRM_FORMAT_YUYV:
1311         case DRM_FORMAT_YVYU:
1312         case DRM_FORMAT_UYVY:
1313         case DRM_FORMAT_VYUY:
1314                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1315                     modifier == I915_FORMAT_MOD_X_TILED)
1316                         return true;
1317                 /* fall through */
1318         default:
1319                 return false;
1320         }
1321 }
1322
1323 static bool vlv_mod_supported(uint32_t format, uint64_t modifier)
1324 {
1325         switch (format) {
1326         case DRM_FORMAT_RGB565:
1327         case DRM_FORMAT_ABGR8888:
1328         case DRM_FORMAT_ARGB8888:
1329         case DRM_FORMAT_XBGR8888:
1330         case DRM_FORMAT_XRGB8888:
1331         case DRM_FORMAT_XBGR2101010:
1332         case DRM_FORMAT_ABGR2101010:
1333         case DRM_FORMAT_YUYV:
1334         case DRM_FORMAT_YVYU:
1335         case DRM_FORMAT_UYVY:
1336         case DRM_FORMAT_VYUY:
1337                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1338                     modifier == I915_FORMAT_MOD_X_TILED)
1339                         return true;
1340                 /* fall through */
1341         default:
1342                 return false;
1343         }
1344 }
1345
1346 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
1347 {
1348         switch (format) {
1349         case DRM_FORMAT_XRGB8888:
1350         case DRM_FORMAT_XBGR8888:
1351         case DRM_FORMAT_ARGB8888:
1352         case DRM_FORMAT_ABGR8888:
1353                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
1354                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
1355                         return true;
1356                 /* fall through */
1357         case DRM_FORMAT_RGB565:
1358         case DRM_FORMAT_XRGB2101010:
1359         case DRM_FORMAT_XBGR2101010:
1360         case DRM_FORMAT_YUYV:
1361         case DRM_FORMAT_YVYU:
1362         case DRM_FORMAT_UYVY:
1363         case DRM_FORMAT_VYUY:
1364         case DRM_FORMAT_NV12:
1365                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1366                         return true;
1367                 /* fall through */
1368         case DRM_FORMAT_C8:
1369                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1370                     modifier == I915_FORMAT_MOD_X_TILED ||
1371                     modifier == I915_FORMAT_MOD_Y_TILED)
1372                         return true;
1373                 /* fall through */
1374         default:
1375                 return false;
1376         }
1377 }
1378
1379 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1380                                                     uint32_t format,
1381                                                     uint64_t modifier)
1382 {
1383         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1384
1385         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1386                 return false;
1387
1388         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1389             modifier != DRM_FORMAT_MOD_LINEAR)
1390                 return false;
1391
1392         if (INTEL_GEN(dev_priv) >= 9)
1393                 return skl_mod_supported(format, modifier);
1394         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1395                 return vlv_mod_supported(format, modifier);
1396         else if (INTEL_GEN(dev_priv) >= 6)
1397                 return snb_mod_supported(format, modifier);
1398         else
1399                 return g4x_mod_supported(format, modifier);
1400 }
1401
1402 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1403         .update_plane = drm_atomic_helper_update_plane,
1404         .disable_plane = drm_atomic_helper_disable_plane,
1405         .destroy = intel_plane_destroy,
1406         .atomic_get_property = intel_plane_atomic_get_property,
1407         .atomic_set_property = intel_plane_atomic_set_property,
1408         .atomic_duplicate_state = intel_plane_duplicate_state,
1409         .atomic_destroy_state = intel_plane_destroy_state,
1410         .format_mod_supported = intel_sprite_plane_format_mod_supported,
1411 };
1412
1413 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1414                        enum pipe pipe, enum plane_id plane_id)
1415 {
1416         if (plane_id == PLANE_CURSOR)
1417                 return false;
1418
1419         if (INTEL_GEN(dev_priv) >= 10)
1420                 return true;
1421
1422         if (IS_GEMINILAKE(dev_priv))
1423                 return pipe != PIPE_C;
1424
1425         return pipe != PIPE_C &&
1426                 (plane_id == PLANE_PRIMARY ||
1427                  plane_id == PLANE_SPRITE0);
1428 }
1429
1430 struct intel_plane *
1431 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1432                           enum pipe pipe, int plane)
1433 {
1434         struct intel_plane *intel_plane = NULL;
1435         struct intel_plane_state *state = NULL;
1436         unsigned long possible_crtcs;
1437         const uint32_t *plane_formats;
1438         const uint64_t *modifiers;
1439         unsigned int supported_rotations;
1440         int num_plane_formats;
1441         int ret;
1442
1443         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1444         if (!intel_plane) {
1445                 ret = -ENOMEM;
1446                 goto fail;
1447         }
1448
1449         state = intel_create_plane_state(&intel_plane->base);
1450         if (!state) {
1451                 ret = -ENOMEM;
1452                 goto fail;
1453         }
1454         intel_plane->base.state = &state->base;
1455
1456         if (INTEL_GEN(dev_priv) >= 9) {
1457                 intel_plane->can_scale = true;
1458                 state->scaler_id = -1;
1459
1460                 intel_plane->update_plane = skl_update_plane;
1461                 intel_plane->disable_plane = skl_disable_plane;
1462                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1463
1464                 if (skl_plane_has_planar(dev_priv, pipe,
1465                                          PLANE_SPRITE0 + plane)) {
1466                         plane_formats = skl_planar_formats;
1467                         num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1468                 } else {
1469                         plane_formats = skl_plane_formats;
1470                         num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1471                 }
1472
1473                 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
1474                         modifiers = skl_plane_format_modifiers_ccs;
1475                 else
1476                         modifiers = skl_plane_format_modifiers_noccs;
1477         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1478                 intel_plane->can_scale = false;
1479                 intel_plane->max_downscale = 1;
1480
1481                 intel_plane->update_plane = vlv_update_plane;
1482                 intel_plane->disable_plane = vlv_disable_plane;
1483                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1484
1485                 plane_formats = vlv_plane_formats;
1486                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1487                 modifiers = i9xx_plane_format_modifiers;
1488         } else if (INTEL_GEN(dev_priv) >= 7) {
1489                 if (IS_IVYBRIDGE(dev_priv)) {
1490                         intel_plane->can_scale = true;
1491                         intel_plane->max_downscale = 2;
1492                 } else {
1493                         intel_plane->can_scale = false;
1494                         intel_plane->max_downscale = 1;
1495                 }
1496
1497                 intel_plane->update_plane = ivb_update_plane;
1498                 intel_plane->disable_plane = ivb_disable_plane;
1499                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1500
1501                 plane_formats = snb_plane_formats;
1502                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1503                 modifiers = i9xx_plane_format_modifiers;
1504         } else {
1505                 intel_plane->can_scale = true;
1506                 intel_plane->max_downscale = 16;
1507
1508                 intel_plane->update_plane = g4x_update_plane;
1509                 intel_plane->disable_plane = g4x_disable_plane;
1510                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1511
1512                 modifiers = i9xx_plane_format_modifiers;
1513                 if (IS_GEN6(dev_priv)) {
1514                         plane_formats = snb_plane_formats;
1515                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1516                 } else {
1517                         plane_formats = g4x_plane_formats;
1518                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1519                 }
1520         }
1521
1522         if (INTEL_GEN(dev_priv) >= 9) {
1523                 supported_rotations =
1524                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1525                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1526         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1527                 supported_rotations =
1528                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1529                         DRM_MODE_REFLECT_X;
1530         } else {
1531                 supported_rotations =
1532                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1533         }
1534
1535         intel_plane->pipe = pipe;
1536         intel_plane->i9xx_plane = plane;
1537         intel_plane->id = PLANE_SPRITE0 + plane;
1538         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1539         intel_plane->check_plane = intel_check_sprite_plane;
1540
1541         possible_crtcs = (1 << pipe);
1542
1543         if (INTEL_GEN(dev_priv) >= 9)
1544                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1545                                                possible_crtcs, &intel_sprite_plane_funcs,
1546                                                plane_formats, num_plane_formats,
1547                                                modifiers,
1548                                                DRM_PLANE_TYPE_OVERLAY,
1549                                                "plane %d%c", plane + 2, pipe_name(pipe));
1550         else
1551                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1552                                                possible_crtcs, &intel_sprite_plane_funcs,
1553                                                plane_formats, num_plane_formats,
1554                                                modifiers,
1555                                                DRM_PLANE_TYPE_OVERLAY,
1556                                                "sprite %c", sprite_name(pipe, plane));
1557         if (ret)
1558                 goto fail;
1559
1560         drm_plane_create_rotation_property(&intel_plane->base,
1561                                            DRM_MODE_ROTATE_0,
1562                                            supported_rotations);
1563
1564         drm_plane_create_color_properties(&intel_plane->base,
1565                                           BIT(DRM_COLOR_YCBCR_BT601) |
1566                                           BIT(DRM_COLOR_YCBCR_BT709),
1567                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1568                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1569                                           DRM_COLOR_YCBCR_BT709,
1570                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1571
1572         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1573
1574         return intel_plane;
1575
1576 fail:
1577         kfree(state);
1578         kfree(intel_plane);
1579
1580         return ERR_PTR(ret);
1581 }