drivers/usb/gadget/mv_u3d_core.c

   1 /*
   2  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/dmapool.h>
  12 #include <linux/kernel.h>
  13 #include <linux/delay.h>
  14 #include <linux/ioport.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/errno.h>
  18 #include <linux/timer.h>
  19 #include <linux/list.h>
  20 #include <linux/notifier.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/device.h>
  24 #include <linux/usb/ch9.h>
  25 #include <linux/usb/gadget.h>
  26 #include <linux/pm.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/platform_data/mv_usb.h>
  31 #include <linux/clk.h>
  32
  33 #include "mv_u3d.h"
  34
  35 #define DRIVER_DESC             "Marvell PXA USB3.0 Device Controller driver"
  36
  37 static const char driver_name[] = "mv_u3d";
  38 static const char driver_desc[] = DRIVER_DESC;
  39
  40 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status);
  41 static void mv_u3d_stop_activity(struct mv_u3d *u3d,
  42                         struct usb_gadget_driver *driver);
  43
  44 /* for endpoint 0 operations */
  45 static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = {
  46         .bLength =              USB_DT_ENDPOINT_SIZE,
  47         .bDescriptorType =      USB_DT_ENDPOINT,
  48         .bEndpointAddress =     0,
  49         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  50         .wMaxPacketSize =       MV_U3D_EP0_MAX_PKT_SIZE,
  51 };
  52
  53 static void mv_u3d_ep0_reset(struct mv_u3d *u3d)
  54 {
  55         struct mv_u3d_ep *ep;
  56         u32 epxcr;
  57         int i;
  58
  59         for (i = 0; i < 2; i++) {
  60                 ep = &u3d->eps[i];
  61                 ep->u3d = u3d;
  62
  63                 /* ep0 ep context, ep0 in and out share the same ep context */
  64                 ep->ep_context = &u3d->ep_context[1];
  65         }
  66
  67         /* reset ep state machine */
  68         /* reset ep0 out */
  69         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
  70         epxcr |= MV_U3D_EPXCR_EP_INIT;
  71         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  72         udelay(5);
  73         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  74         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  75
  76         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  77                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  78                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  79                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  80                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  81         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1);
  82
  83         /* reset ep0 in */
  84         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
  85         epxcr |= MV_U3D_EPXCR_EP_INIT;
  86         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  87         udelay(5);
  88         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  89         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  90
  91         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  92                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  93                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  94                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  95                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  96         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1);
  97 }
  98
  99 static void mv_u3d_ep0_stall(struct mv_u3d *u3d)
 100 {
 101         u32 tmp;
 102         dev_dbg(u3d->dev, "%s\n", __func__);
 103
 104         /* set TX and RX to stall */
 105         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 106         tmp |= MV_U3D_EPXCR_EP_HALT;
 107         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 108
 109         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 110         tmp |= MV_U3D_EPXCR_EP_HALT;
 111         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 112
 113         /* update ep0 state */
 114         u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 115         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 116 }
 117
 118 static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index,
 119         struct mv_u3d_req *curr_req)
 120 {
 121         struct mv_u3d_trb       *curr_trb;
 122         dma_addr_t cur_deq_lo;
 123         struct mv_u3d_ep_context        *curr_ep_context;
 124         int trb_complete, actual, remaining_length = 0;
 125         int direction, ep_num;
 126         int retval = 0;
 127         u32 tmp, status, length;
 128
 129         curr_ep_context = &u3d->ep_context[index];
 130         direction = index % 2;
 131         ep_num = index / 2;
 132
 133         trb_complete = 0;
 134         actual = curr_req->req.length;
 135
 136         while (!list_empty(&curr_req->trb_list)) {
 137                 curr_trb = list_entry(curr_req->trb_list.next,
 138                                         struct mv_u3d_trb, trb_list);
 139                 if (!curr_trb->trb_hw->ctrl.own) {
 140                         dev_err(u3d->dev, "%s, TRB own error!\n",
 141                                 u3d->eps[index].name);
 142                         return 1;
 143                 }
 144
 145                 curr_trb->trb_hw->ctrl.own = 0;
 146                 if (direction == MV_U3D_EP_DIR_OUT) {
 147                         tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo);
 148                         cur_deq_lo =
 149                                 ioread32(&u3d->vuc_regs->rxst[ep_num].curdeqlo);
 150                 } else {
 151                         tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo);
 152                         cur_deq_lo =
 153                                 ioread32(&u3d->vuc_regs->txst[ep_num].curdeqlo);
 154                 }
 155
 156                 status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT;
 157                 length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK;
 158
 159                 if (status == MV_U3D_COMPLETE_SUCCESS ||
 160                         (status == MV_U3D_COMPLETE_SHORT_PACKET &&
 161                         direction == MV_U3D_EP_DIR_OUT)) {
 162                         remaining_length += length;
 163                         actual -= remaining_length;
 164                 } else {
 165                         dev_err(u3d->dev,
 166                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 167                                 index >> 1, direction ? "SEND" : "RECV",
 168                                 status);
 169                         retval = -EPROTO;
 170                 }
 171
 172                 list_del_init(&curr_trb->trb_list);
 173         }
 174         if (retval)
 175                 return retval;
 176
 177         curr_req->req.actual = actual;
 178         return 0;
 179 }
 180
 181 /*
 182  * mv_u3d_done() - retire a request; caller blocked irqs
 183  * @status : request status to be set, only works when
 184  * request is still in progress.
 185  */
 186 static
 187 void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status)
 188         __releases(&ep->udc->lock)
 189         __acquires(&ep->udc->lock)
 190 {
 191         struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d;
 192
 193         dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n");
 194         /* Removed the req from ep queue */
 195         list_del_init(&req->queue);
 196
 197         /* req.status should be set as -EINPROGRESS in ep_queue() */
 198         if (req->req.status == -EINPROGRESS)
 199                 req->req.status = status;
 200         else
 201                 status = req->req.status;
 202
 203         /* Free trb for the request */
 204         if (!req->chain)
 205                 dma_pool_free(u3d->trb_pool,
 206                         req->trb_head->trb_hw, req->trb_head->trb_dma);
 207         else {
 208                 dma_unmap_single(ep->u3d->gadget.dev.parent,
 209                         (dma_addr_t)req->trb_head->trb_dma,
 210                         req->trb_count * sizeof(struct mv_u3d_trb_hw),
 211                         DMA_BIDIRECTIONAL);
 212                 kfree(req->trb_head->trb_hw);
 213         }
 214         kfree(req->trb_head);
 215
 216         usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep));
 217
 218         if (status && (status != -ESHUTDOWN)) {
 219                 dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u",
 220                         ep->ep.name, &req->req, status,
 221                         req->req.actual, req->req.length);
 222         }
 223
 224         spin_unlock(&ep->u3d->lock);
 225         /*
 226          * complete() is from gadget layer,
 227          * eg fsg->bulk_in_complete()
 228          */
 229         if (req->req.complete)
 230                 req->req.complete(&ep->ep, &req->req);
 231
 232         spin_lock(&ep->u3d->lock);
 233 }
 234
 235 static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req)
 236 {
 237         u32 tmp, direction;
 238         struct mv_u3d *u3d;
 239         struct mv_u3d_ep_context *ep_context;
 240         int retval = 0;
 241
 242         u3d = ep->u3d;
 243         direction = mv_u3d_ep_dir(ep);
 244
 245         /* ep0 in and out share the same ep context slot 1*/
 246         if (ep->ep_num == 0)
 247                 ep_context = &(u3d->ep_context[1]);
 248         else
 249                 ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]);
 250
 251         /* check if the pipe is empty or not */
 252         if (!list_empty(&ep->queue)) {
 253                 dev_err(u3d->dev, "add trb to non-empty queue!\n");
 254                 retval = -ENOMEM;
 255                 WARN_ON(1);
 256         } else {
 257                 ep_context->rsvd0 = cpu_to_le32(1);
 258                 ep_context->rsvd1 = 0;
 259
 260                 /* Configure the trb address and set the DCS bit.
 261                  * Both DCS bit and own bit in trb should be set.
 262                  */
 263                 ep_context->trb_addr_lo =
 264                         cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE);
 265                 ep_context->trb_addr_hi = 0;
 266
 267                 /* Ensure that updates to the EP Context will
 268                  * occure before Ring Bell.
 269                  */
 270                 wmb();
 271
 272                 /* ring bell the ep */
 273                 if (ep->ep_num == 0)
 274                         tmp = 0x1;
 275                 else
 276                         tmp = ep->ep_num * 2
 277                                 + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1);
 278
 279                 iowrite32(tmp, &u3d->op_regs->doorbell);
 280         }
 281         return retval;
 282 }
 283
 284 static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req,
 285                                 unsigned *length, dma_addr_t *dma)
 286 {
 287         u32 temp;
 288         unsigned int direction;
 289         struct mv_u3d_trb *trb;
 290         struct mv_u3d_trb_hw *trb_hw;
 291         struct mv_u3d *u3d;
 292
 293         /* how big will this transfer be? */
 294         *length = req->req.length - req->req.actual;
 295         BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 296
 297         u3d = req->ep->u3d;
 298
 299         trb = kzalloc(sizeof(*trb), GFP_ATOMIC);
 300         if (!trb)
 301                 return NULL;
 302
 303         /*
 304          * Be careful that no _GFP_HIGHMEM is set,
 305          * or we can not use dma_to_virt
 306          * cannot use GFP_KERNEL in spin lock
 307          */
 308         trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma);
 309         if (!trb_hw) {
 310                 kfree(trb);
 311                 dev_err(u3d->dev,
 312                         "%s, dma_pool_alloc fail\n", __func__);
 313                 return NULL;
 314         }
 315         trb->trb_dma = *dma;
 316         trb->trb_hw = trb_hw;
 317
 318         /* initialize buffer page pointers */
 319         temp = (u32)(req->req.dma + req->req.actual);
 320
 321         trb_hw->buf_addr_lo = cpu_to_le32(temp);
 322         trb_hw->buf_addr_hi = 0;
 323         trb_hw->trb_len = cpu_to_le32(*length);
 324         trb_hw->ctrl.own = 1;
 325
 326         if (req->ep->ep_num == 0)
 327                 trb_hw->ctrl.type = TYPE_DATA;
 328         else
 329                 trb_hw->ctrl.type = TYPE_NORMAL;
 330
 331         req->req.actual += *length;
 332
 333         direction = mv_u3d_ep_dir(req->ep);
 334         if (direction == MV_U3D_EP_DIR_IN)
 335                 trb_hw->ctrl.dir = 1;
 336         else
 337                 trb_hw->ctrl.dir = 0;
 338
 339         /* Enable interrupt for the last trb of a request */
 340         if (!req->req.no_interrupt)
 341                 trb_hw->ctrl.ioc = 1;
 342
 343         trb_hw->ctrl.chain = 0;
 344
 345         wmb();
 346         return trb;
 347 }
 348
 349 static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length,
 350                 struct mv_u3d_trb *trb, int *is_last)
 351 {
 352         u32 temp;
 353         unsigned int direction;
 354         struct mv_u3d *u3d;
 355
 356         /* how big will this transfer be? */
 357         *length = min(req->req.length - req->req.actual,
 358                         (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 359
 360         u3d = req->ep->u3d;
 361
 362         trb->trb_dma = 0;
 363
 364         /* initialize buffer page pointers */
 365         temp = (u32)(req->req.dma + req->req.actual);
 366
 367         trb->trb_hw->buf_addr_lo = cpu_to_le32(temp);
 368         trb->trb_hw->buf_addr_hi = 0;
 369         trb->trb_hw->trb_len = cpu_to_le32(*length);
 370         trb->trb_hw->ctrl.own = 1;
 371
 372         if (req->ep->ep_num == 0)
 373                 trb->trb_hw->ctrl.type = TYPE_DATA;
 374         else
 375                 trb->trb_hw->ctrl.type = TYPE_NORMAL;
 376
 377         req->req.actual += *length;
 378
 379         direction = mv_u3d_ep_dir(req->ep);
 380         if (direction == MV_U3D_EP_DIR_IN)
 381                 trb->trb_hw->ctrl.dir = 1;
 382         else
 383                 trb->trb_hw->ctrl.dir = 0;
 384
 385         /* zlp is needed if req->req.zero is set */
 386         if (req->req.zero) {
 387                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 388                         *is_last = 1;
 389                 else
 390                         *is_last = 0;
 391         } else if (req->req.length == req->req.actual)
 392                 *is_last = 1;
 393         else
 394                 *is_last = 0;
 395
 396         /* Enable interrupt for the last trb of a request */
 397         if (*is_last && !req->req.no_interrupt)
 398                 trb->trb_hw->ctrl.ioc = 1;
 399
 400         if (*is_last)
 401                 trb->trb_hw->ctrl.chain = 0;
 402         else {
 403                 trb->trb_hw->ctrl.chain = 1;
 404                 dev_dbg(u3d->dev, "chain trb\n");
 405         }
 406
 407         wmb();
 408
 409         return 0;
 410 }
 411
 412 /* generate TRB linked list for a request
 413  * usb controller only supports continous trb chain,
 414  * that trb structure physical address should be continous.
 415  */
 416 static int mv_u3d_req_to_trb(struct mv_u3d_req *req)
 417 {
 418         unsigned count;
 419         int is_last;
 420         struct mv_u3d_trb *trb;
 421         struct mv_u3d_trb_hw *trb_hw;
 422         struct mv_u3d *u3d;
 423         dma_addr_t dma;
 424         unsigned length;
 425         unsigned trb_num;
 426
 427         u3d = req->ep->u3d;
 428
 429         INIT_LIST_HEAD(&req->trb_list);
 430
 431         length = req->req.length - req->req.actual;
 432         /* normally the request transfer length is less than 16KB.
 433          * we use buil_trb_one() to optimize it.
 434          */
 435         if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) {
 436                 trb = mv_u3d_build_trb_one(req, &count, &dma);
 437                 list_add_tail(&trb->trb_list, &req->trb_list);
 438                 req->trb_head = trb;
 439                 req->trb_count = 1;
 440                 req->chain = 0;
 441         } else {
 442                 trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER;
 443                 if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER)
 444                         trb_num++;
 445
 446                 trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC);
 447                 if (!trb)
 448                         return -ENOMEM;
 449
 450                 trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC);
 451                 if (!trb_hw) {
 452                         kfree(trb);
 453                         return -ENOMEM;
 454                 }
 455
 456                 do {
 457                         trb->trb_hw = trb_hw;
 458                         if (mv_u3d_build_trb_chain(req, &count,
 459                                                 trb, &is_last)) {
 460                                 dev_err(u3d->dev,
 461                                         "%s, mv_u3d_build_trb_chain fail\n",
 462                                         __func__);
 463                                 return -EIO;
 464                         }
 465
 466                         list_add_tail(&trb->trb_list, &req->trb_list);
 467                         req->trb_count++;
 468                         trb++;
 469                         trb_hw++;
 470                 } while (!is_last);
 471
 472                 req->trb_head = list_entry(req->trb_list.next,
 473                                         struct mv_u3d_trb, trb_list);
 474                 req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent,
 475                                         req->trb_head->trb_hw,
 476                                         trb_num * sizeof(*trb_hw),
 477                                         DMA_BIDIRECTIONAL);
 478
 479                 req->chain = 1;
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int
 486 mv_u3d_start_queue(struct mv_u3d_ep *ep)
 487 {
 488         struct mv_u3d *u3d = ep->u3d;
 489         struct mv_u3d_req *req;
 490         int ret;
 491
 492         if (!list_empty(&ep->req_list) && !ep->processing)
 493                 req = list_entry(ep->req_list.next, struct mv_u3d_req, list);
 494         else
 495                 return 0;
 496
 497         ep->processing = 1;
 498
 499         /* set up dma mapping */
 500         ret = usb_gadget_map_request(&u3d->gadget, &req->req,
 501                                         mv_u3d_ep_dir(ep));
 502         if (ret)
 503                 return ret;
 504
 505         req->req.status = -EINPROGRESS;
 506         req->req.actual = 0;
 507         req->trb_count = 0;
 508
 509         /* build trbs and push them to device queue */
 510         if (!mv_u3d_req_to_trb(req)) {
 511                 ret = mv_u3d_queue_trb(ep, req);
 512                 if (ret) {
 513                         ep->processing = 0;
 514                         return ret;
 515                 }
 516         } else {
 517                 ep->processing = 0;
 518                 dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__);
 519                 return -ENOMEM;
 520         }
 521
 522         /* irq handler advances the queue */
 523         if (req)
 524                 list_add_tail(&req->queue, &ep->queue);
 525
 526         return 0;
 527 }
 528
 529 static int mv_u3d_ep_enable(struct usb_ep *_ep,
 530                 const struct usb_endpoint_descriptor *desc)
 531 {
 532         struct mv_u3d *u3d;
 533         struct mv_u3d_ep *ep;
 534         struct mv_u3d_ep_context *ep_context;
 535         u16 max = 0;
 536         unsigned maxburst = 0;
 537         u32 epxcr, direction;
 538
 539         if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT)
 540                 return -EINVAL;
 541
 542         ep = container_of(_ep, struct mv_u3d_ep, ep);
 543         u3d = ep->u3d;
 544
 545         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN)
 546                 return -ESHUTDOWN;
 547
 548         direction = mv_u3d_ep_dir(ep);
 549         max = le16_to_cpu(desc->wMaxPacketSize);
 550
 551         if (!_ep->maxburst)
 552                 _ep->maxburst = 1;
 553         maxburst = _ep->maxburst;
 554
 555         /* Get the endpoint context address */
 556         ep_context = (struct mv_u3d_ep_context *)ep->ep_context;
 557
 558         /* Set the max burst size */
 559         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 560         case USB_ENDPOINT_XFER_BULK:
 561                 if (maxburst > 16) {
 562                         dev_dbg(u3d->dev,
 563                                 "max burst should not be greater "
 564                                 "than 16 on bulk ep\n");
 565                         maxburst = 1;
 566                         _ep->maxburst = maxburst;
 567                 }
 568                 dev_dbg(u3d->dev,
 569                         "maxburst: %d on bulk %s\n", maxburst, ep->name);
 570                 break;
 571         case USB_ENDPOINT_XFER_CONTROL:
 572                 /* control transfer only supports maxburst as one */
 573                 maxburst = 1;
 574                 _ep->maxburst = maxburst;
 575                 break;
 576         case USB_ENDPOINT_XFER_INT:
 577                 if (maxburst != 1) {
 578                         dev_dbg(u3d->dev,
 579                                 "max burst should be 1 on int ep "
 580                                 "if transfer size is not 1024\n");
 581                         maxburst = 1;
 582                         _ep->maxburst = maxburst;
 583                 }
 584                 break;
 585         case USB_ENDPOINT_XFER_ISOC:
 586                 if (maxburst != 1) {
 587                         dev_dbg(u3d->dev,
 588                                 "max burst should be 1 on isoc ep "
 589                                 "if transfer size is not 1024\n");
 590                         maxburst = 1;
 591                         _ep->maxburst = maxburst;
 592                 }
 593                 break;
 594         default:
 595                 goto en_done;
 596         }
 597
 598         ep->ep.maxpacket = max;
 599         ep->ep.desc = desc;
 600         ep->enabled = 1;
 601
 602         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 603         if (direction == MV_U3D_EP_DIR_OUT) {
 604                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 605                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 606                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 607                 udelay(5);
 608                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 609                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 610
 611                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 612                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 613                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 614                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 615                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 616         } else {
 617                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 618                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 619                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 620                 udelay(5);
 621                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 622                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 623
 624                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 625                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 626                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 627                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 628                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 629         }
 630
 631         return 0;
 632 en_done:
 633         return -EINVAL;
 634 }
 635
 636 static int  mv_u3d_ep_disable(struct usb_ep *_ep)
 637 {
 638         struct mv_u3d *u3d;
 639         struct mv_u3d_ep *ep;
 640         struct mv_u3d_ep_context *ep_context;
 641         u32 epxcr, direction;
 642         unsigned long flags;
 643
 644         if (!_ep)
 645                 return -EINVAL;
 646
 647         ep = container_of(_ep, struct mv_u3d_ep, ep);
 648         if (!ep->ep.desc)
 649                 return -EINVAL;
 650
 651         u3d = ep->u3d;
 652
 653         /* Get the endpoint context address */
 654         ep_context = ep->ep_context;
 655
 656         direction = mv_u3d_ep_dir(ep);
 657
 658         /* nuke all pending requests (does flush) */
 659         spin_lock_irqsave(&u3d->lock, flags);
 660         mv_u3d_nuke(ep, -ESHUTDOWN);
 661         spin_unlock_irqrestore(&u3d->lock, flags);
 662
 663         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 664         if (direction == MV_U3D_EP_DIR_OUT) {
 665                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 666                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 667                       | USB_ENDPOINT_XFERTYPE_MASK);
 668                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 669         } else {
 670                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 671                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 672                       | USB_ENDPOINT_XFERTYPE_MASK);
 673                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 674         }
 675
 676         ep->enabled = 0;
 677
 678         ep->ep.desc = NULL;
 679         return 0;
 680 }
 681
 682 static struct usb_request *
 683 mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 684 {
 685         struct mv_u3d_req *req = NULL;
 686
 687         req = kzalloc(sizeof *req, gfp_flags);
 688         if (!req)
 689                 return NULL;
 690
 691         INIT_LIST_HEAD(&req->queue);
 692
 693         return &req->req;
 694 }
 695
 696 static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req)
 697 {
 698         struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req);
 699
 700         kfree(req);
 701 }
 702
 703 static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep)
 704 {
 705         struct mv_u3d *u3d;
 706         u32 direction;
 707         struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep);
 708         unsigned int loops;
 709         u32 tmp;
 710
 711         /* if endpoint is not enabled, cannot flush endpoint */
 712         if (!ep->enabled)
 713                 return;
 714
 715         u3d = ep->u3d;
 716         direction = mv_u3d_ep_dir(ep);
 717
 718         /* ep0 need clear bit after flushing fifo. */
 719         if (!ep->ep_num) {
 720                 if (direction == MV_U3D_EP_DIR_OUT) {
 721                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 722                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 723                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 724                         udelay(10);
 725                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 726                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 727                 } else {
 728                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 729                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 730                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 731                         udelay(10);
 732                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 733                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 734                 }
 735                 return;
 736         }
 737
 738         if (direction == MV_U3D_EP_DIR_OUT) {
 739                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 740                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 741                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 742
 743                 /* Wait until flushing completed */
 744                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 745                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) &
 746                         MV_U3D_EPXCR_EP_FLUSH) {
 747                         /*
 748                          * EP_FLUSH bit should be cleared to indicate this
 749                          * operation is complete
 750                          */
 751                         if (loops == 0) {
 752                                 dev_dbg(u3d->dev,
 753                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 754                                     direction ? "in" : "out");
 755                                 return;
 756                         }
 757                         loops--;
 758                         udelay(LOOPS_USEC);
 759                 }
 760         } else {        /* EP_DIR_IN */
 761                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 762                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 763                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 764
 765                 /* Wait until flushing completed */
 766                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 767                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) &
 768                         MV_U3D_EPXCR_EP_FLUSH) {
 769                         /*
 770                         * EP_FLUSH bit should be cleared to indicate this
 771                         * operation is complete
 772                         */
 773                         if (loops == 0) {
 774                                 dev_dbg(u3d->dev,
 775                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 776                                     direction ? "in" : "out");
 777                                 return;
 778                         }
 779                         loops--;
 780                         udelay(LOOPS_USEC);
 781                 }
 782         }
 783 }
 784
 785 /* queues (submits) an I/O request to an endpoint */
 786 static int
 787 mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 788 {
 789         struct mv_u3d_ep *ep;
 790         struct mv_u3d_req *req;
 791         struct mv_u3d *u3d;
 792         unsigned long flags;
 793         int is_first_req = 0;
 794
 795         if (unlikely(!_ep || !_req))
 796                 return -EINVAL;
 797
 798         ep = container_of(_ep, struct mv_u3d_ep, ep);
 799         u3d = ep->u3d;
 800
 801         req = container_of(_req, struct mv_u3d_req, req);
 802
 803         if (!ep->ep_num
 804                 && u3d->ep0_state == MV_U3D_STATUS_STAGE
 805                 && !_req->length) {
 806                 dev_dbg(u3d->dev, "ep0 status stage\n");
 807                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 808                 return 0;
 809         }
 810
 811         dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n",
 812                         __func__, _ep->name, req);
 813
 814         /* catch various bogus parameters */
 815         if (!req->req.complete || !req->req.buf
 816                         || !list_empty(&req->queue)) {
 817                 dev_err(u3d->dev,
 818                         "%s, bad params, _req: 0x%p,"
 819                         "req->req.complete: 0x%p, req->req.buf: 0x%p,"
 820                         "list_empty: 0x%x\n",
 821                         __func__, _req,
 822                         req->req.complete, req->req.buf,
 823                         list_empty(&req->queue));
 824                 return -EINVAL;
 825         }
 826         if (unlikely(!ep->ep.desc)) {
 827                 dev_err(u3d->dev, "%s, bad ep\n", __func__);
 828                 return -EINVAL;
 829         }
 830         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 831                 if (req->req.length > ep->ep.maxpacket)
 832                         return -EMSGSIZE;
 833         }
 834
 835         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) {
 836                 dev_err(u3d->dev,
 837                         "bad params of driver/speed\n");
 838                 return -ESHUTDOWN;
 839         }
 840
 841         req->ep = ep;
 842
 843         /* Software list handles usb request. */
 844         spin_lock_irqsave(&ep->req_lock, flags);
 845         is_first_req = list_empty(&ep->req_list);
 846         list_add_tail(&req->list, &ep->req_list);
 847         spin_unlock_irqrestore(&ep->req_lock, flags);
 848         if (!is_first_req) {
 849                 dev_dbg(u3d->dev, "list is not empty\n");
 850                 return 0;
 851         }
 852
 853         dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n");
 854         spin_lock_irqsave(&u3d->lock, flags);
 855         mv_u3d_start_queue(ep);
 856         spin_unlock_irqrestore(&u3d->lock, flags);
 857         return 0;
 858 }
 859
 860 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 861 static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 862 {
 863         struct mv_u3d_ep *ep;
 864         struct mv_u3d_req *req;
 865         struct mv_u3d *u3d;
 866         struct mv_u3d_ep_context *ep_context;
 867         struct mv_u3d_req *next_req;
 868
 869         unsigned long flags;
 870         int ret = 0;
 871
 872         if (!_ep || !_req)
 873                 return -EINVAL;
 874
 875         ep = container_of(_ep, struct mv_u3d_ep, ep);
 876         u3d = ep->u3d;
 877
 878         spin_lock_irqsave(&ep->u3d->lock, flags);
 879
 880         /* make sure it's actually queued on this endpoint */
 881         list_for_each_entry(req, &ep->queue, queue) {
 882                 if (&req->req == _req)
 883                         break;
 884         }
 885         if (&req->req != _req) {
 886                 ret = -EINVAL;
 887                 goto out;
 888         }
 889
 890         /* The request is in progress, or completed but not dequeued */
 891         if (ep->queue.next == &req->queue) {
 892                 _req->status = -ECONNRESET;
 893                 mv_u3d_ep_fifo_flush(_ep);
 894
 895                 /* The request isn't the last request in this ep queue */
 896                 if (req->queue.next != &ep->queue) {
 897                         dev_dbg(u3d->dev,
 898                                 "it is the last request in this ep queue\n");
 899                         ep_context = ep->ep_context;
 900                         next_req = list_entry(req->queue.next,
 901                                         struct mv_u3d_req, queue);
 902
 903                         /* Point first TRB of next request to the EP context. */
 904                         iowrite32((unsigned long) next_req->trb_head,
 905                                         &ep_context->trb_addr_lo);
 906                 } else {
 907                         struct mv_u3d_ep_context *ep_context;
 908                         ep_context = ep->ep_context;
 909                         ep_context->trb_addr_lo = 0;
 910                         ep_context->trb_addr_hi = 0;
 911                 }
 912
 913         } else
 914                 WARN_ON(1);
 915
 916         mv_u3d_done(ep, req, -ECONNRESET);
 917
 918         /* remove the req from the ep req list */
 919         if (!list_empty(&ep->req_list)) {
 920                 struct mv_u3d_req *curr_req;
 921                 curr_req = list_entry(ep->req_list.next,
 922                                         struct mv_u3d_req, list);
 923                 if (curr_req == req) {
 924                         list_del_init(&req->list);
 925                         ep->processing = 0;
 926                 }
 927         }
 928
 929 out:
 930         spin_unlock_irqrestore(&ep->u3d->lock, flags);
 931         return ret;
 932 }
 933
 934 static void
 935 mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall)
 936 {
 937         u32 tmp;
 938         struct mv_u3d_ep *ep = u3d->eps;
 939
 940         dev_dbg(u3d->dev, "%s\n", __func__);
 941         if (direction == MV_U3D_EP_DIR_OUT) {
 942                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 943                 if (stall)
 944                         tmp |= MV_U3D_EPXCR_EP_HALT;
 945                 else
 946                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 947                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 948         } else {
 949                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 950                 if (stall)
 951                         tmp |= MV_U3D_EPXCR_EP_HALT;
 952                 else
 953                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 954                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 955         }
 956 }
 957
 958 static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 959 {
 960         struct mv_u3d_ep *ep;
 961         unsigned long flags = 0;
 962         int status = 0;
 963         struct mv_u3d *u3d;
 964
 965         ep = container_of(_ep, struct mv_u3d_ep, ep);
 966         u3d = ep->u3d;
 967         if (!ep->ep.desc) {
 968                 status = -EINVAL;
 969                 goto out;
 970         }
 971
 972         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 973                 status = -EOPNOTSUPP;
 974                 goto out;
 975         }
 976
 977         /*
 978          * Attempt to halt IN ep will fail if any transfer requests
 979          * are still queue
 980          */
 981         if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN)
 982                         && !list_empty(&ep->queue)) {
 983                 status = -EAGAIN;
 984                 goto out;
 985         }
 986
 987         spin_lock_irqsave(&ep->u3d->lock, flags);
 988         mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt);
 989         if (halt && wedge)
 990                 ep->wedge = 1;
 991         else if (!halt)
 992                 ep->wedge = 0;
 993         spin_unlock_irqrestore(&ep->u3d->lock, flags);
 994
 995         if (ep->ep_num == 0)
 996                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 997 out:
 998         return status;
 999 }
1000
1001 static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt)
1002 {
1003         return mv_u3d_ep_set_halt_wedge(_ep, halt, 0);
1004 }
1005
1006 static int mv_u3d_ep_set_wedge(struct usb_ep *_ep)
1007 {
1008         return mv_u3d_ep_set_halt_wedge(_ep, 1, 1);
1009 }
1010
1011 static struct usb_ep_ops mv_u3d_ep_ops = {
1012         .enable         = mv_u3d_ep_enable,
1013         .disable        = mv_u3d_ep_disable,
1014
1015         .alloc_request  = mv_u3d_alloc_request,
1016         .free_request   = mv_u3d_free_request,
1017
1018         .queue          = mv_u3d_ep_queue,
1019         .dequeue        = mv_u3d_ep_dequeue,
1020
1021         .set_wedge      = mv_u3d_ep_set_wedge,
1022         .set_halt       = mv_u3d_ep_set_halt,
1023         .fifo_flush     = mv_u3d_ep_fifo_flush,
1024 };
1025
1026 static void mv_u3d_controller_stop(struct mv_u3d *u3d)
1027 {
1028         u32 tmp;
1029
1030         if (!u3d->clock_gating && u3d->vbus_valid_detect)
1031                 iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID,
1032                                 &u3d->vuc_regs->intrenable);
1033         else
1034                 iowrite32(0, &u3d->vuc_regs->intrenable);
1035         iowrite32(~0x0, &u3d->vuc_regs->endcomplete);
1036         iowrite32(~0x0, &u3d->vuc_regs->trbunderrun);
1037         iowrite32(~0x0, &u3d->vuc_regs->trbcomplete);
1038         iowrite32(~0x0, &u3d->vuc_regs->linkchange);
1039         iowrite32(0x1, &u3d->vuc_regs->setuplock);
1040
1041         /* Reset the RUN bit in the command register to stop USB */
1042         tmp = ioread32(&u3d->op_regs->usbcmd);
1043         tmp &= ~MV_U3D_CMD_RUN_STOP;
1044         iowrite32(tmp, &u3d->op_regs->usbcmd);
1045         dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n",
1046                 ioread32(&u3d->op_regs->usbcmd));
1047 }
1048
1049 static void mv_u3d_controller_start(struct mv_u3d *u3d)
1050 {
1051         u32 usbintr;
1052         u32 temp;
1053
1054         /* enable link LTSSM state machine */
1055         temp = ioread32(&u3d->vuc_regs->ltssm);
1056         temp |= MV_U3D_LTSSM_PHY_INIT_DONE;
1057         iowrite32(temp, &u3d->vuc_regs->ltssm);
1058
1059         /* Enable interrupts */
1060         usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR |
1061                 MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE |
1062                 MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP |
1063                 (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0);
1064         iowrite32(usbintr, &u3d->vuc_regs->intrenable);
1065
1066         /* Enable ctrl ep */
1067         iowrite32(0x1, &u3d->vuc_regs->ctrlepenable);
1068
1069         /* Set the Run bit in the command register */
1070         iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd);
1071         dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n",
1072                 ioread32(&u3d->op_regs->usbcmd));
1073 }
1074
1075 static int mv_u3d_controller_reset(struct mv_u3d *u3d)
1076 {
1077         unsigned int loops;
1078         u32 tmp;
1079
1080         /* Stop the controller */
1081         tmp = ioread32(&u3d->op_regs->usbcmd);
1082         tmp &= ~MV_U3D_CMD_RUN_STOP;
1083         iowrite32(tmp, &u3d->op_regs->usbcmd);
1084
1085         /* Reset the controller to get default values */
1086         iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd);
1087
1088         /* wait for reset to complete */
1089         loops = LOOPS(MV_U3D_RESET_TIMEOUT);
1090         while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) {
1091                 if (loops == 0) {
1092                         dev_err(u3d->dev,
1093                                 "Wait for RESET completed TIMEOUT\n");
1094                         return -ETIMEDOUT;
1095                 }
1096                 loops--;
1097                 udelay(LOOPS_USEC);
1098         }
1099
1100         /* Configure the Endpoint Context Address */
1101         iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl);
1102         iowrite32(0, &u3d->op_regs->dcbaaph);
1103
1104         return 0;
1105 }
1106
1107 static int mv_u3d_enable(struct mv_u3d *u3d)
1108 {
1109         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1110         int retval;
1111
1112         if (u3d->active)
1113                 return 0;
1114
1115         if (!u3d->clock_gating) {
1116                 u3d->active = 1;
1117                 return 0;
1118         }
1119
1120         dev_dbg(u3d->dev, "enable u3d\n");
1121         clk_enable(u3d->clk);
1122         if (pdata->phy_init) {
1123                 retval = pdata->phy_init(u3d->phy_regs);
1124                 if (retval) {
1125                         dev_err(u3d->dev,
1126                                 "init phy error %d\n", retval);
1127                         clk_disable(u3d->clk);
1128                         return retval;
1129                 }
1130         }
1131         u3d->active = 1;
1132
1133         return 0;
1134 }
1135
1136 static void mv_u3d_disable(struct mv_u3d *u3d)
1137 {
1138         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1139         if (u3d->clock_gating && u3d->active) {
1140                 dev_dbg(u3d->dev, "disable u3d\n");
1141                 if (pdata->phy_deinit)
1142                         pdata->phy_deinit(u3d->phy_regs);
1143                 clk_disable(u3d->clk);
1144                 u3d->active = 0;
1145         }
1146 }
1147
1148 static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active)
1149 {
1150         struct mv_u3d *u3d;
1151         unsigned long flags;
1152         int retval = 0;
1153
1154         u3d = container_of(gadget, struct mv_u3d, gadget);
1155
1156         spin_lock_irqsave(&u3d->lock, flags);
1157
1158         u3d->vbus_active = (is_active != 0);
1159         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1160                 __func__, u3d->softconnect, u3d->vbus_active);
1161         /*
1162          * 1. external VBUS detect: we can disable/enable clock on demand.
1163          * 2. UDC VBUS detect: we have to enable clock all the time.
1164          * 3. No VBUS detect: we have to enable clock all the time.
1165          */
1166         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1167                 retval = mv_u3d_enable(u3d);
1168                 if (retval == 0) {
1169                         /*
1170                          * after clock is disabled, we lost all the register
1171                          *  context. We have to re-init registers
1172                          */
1173                         mv_u3d_controller_reset(u3d);
1174                         mv_u3d_ep0_reset(u3d);
1175                         mv_u3d_controller_start(u3d);
1176                 }
1177         } else if (u3d->driver && u3d->softconnect) {
1178                 if (!u3d->active)
1179                         goto out;
1180
1181                 /* stop all the transfer in queue*/
1182                 mv_u3d_stop_activity(u3d, u3d->driver);
1183                 mv_u3d_controller_stop(u3d);
1184                 mv_u3d_disable(u3d);
1185         }
1186
1187 out:
1188         spin_unlock_irqrestore(&u3d->lock, flags);
1189         return retval;
1190 }
1191
1192 /* constrain controller's VBUS power usage
1193  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1194  * reporting how much power the device may consume.  For example, this
1195  * could affect how quickly batteries are recharged.
1196  *
1197  * Returns zero on success, else negative errno.
1198  */
1199 static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1200 {
1201         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1202
1203         u3d->power = mA;
1204
1205         return 0;
1206 }
1207
1208 static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on)
1209 {
1210         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1211         unsigned long flags;
1212         int retval = 0;
1213
1214         spin_lock_irqsave(&u3d->lock, flags);
1215
1216         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1217                 __func__, u3d->softconnect, u3d->vbus_active);
1218         u3d->softconnect = (is_on != 0);
1219         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1220                 retval = mv_u3d_enable(u3d);
1221                 if (retval == 0) {
1222                         /*
1223                          * after clock is disabled, we lost all the register
1224                          *  context. We have to re-init registers
1225                          */
1226                         mv_u3d_controller_reset(u3d);
1227                         mv_u3d_ep0_reset(u3d);
1228                         mv_u3d_controller_start(u3d);
1229                 }
1230         } else if (u3d->driver && u3d->vbus_active) {
1231                 /* stop all the transfer in queue*/
1232                 mv_u3d_stop_activity(u3d, u3d->driver);
1233                 mv_u3d_controller_stop(u3d);
1234                 mv_u3d_disable(u3d);
1235         }
1236
1237         spin_unlock_irqrestore(&u3d->lock, flags);
1238
1239         return retval;
1240 }
1241
1242 static int mv_u3d_start(struct usb_gadget *g,
1243                 struct usb_gadget_driver *driver)
1244 {
1245         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1246         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1247         unsigned long flags;
1248
1249         if (u3d->driver)
1250                 return -EBUSY;
1251
1252         spin_lock_irqsave(&u3d->lock, flags);
1253
1254         if (!u3d->clock_gating) {
1255                 clk_enable(u3d->clk);
1256                 if (pdata->phy_init)
1257                         pdata->phy_init(u3d->phy_regs);
1258         }
1259
1260         /* hook up the driver ... */
1261         driver->driver.bus = NULL;
1262         u3d->driver = driver;
1263
1264         u3d->ep0_dir = USB_DIR_OUT;
1265
1266         spin_unlock_irqrestore(&u3d->lock, flags);
1267
1268         u3d->vbus_valid_detect = 1;
1269
1270         return 0;
1271 }
1272
1273 static int mv_u3d_stop(struct usb_gadget *g,
1274                 struct usb_gadget_driver *driver)
1275 {
1276         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1277         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1278         unsigned long flags;
1279
1280         u3d->vbus_valid_detect = 0;
1281         spin_lock_irqsave(&u3d->lock, flags);
1282
1283         /* enable clock to access controller register */
1284         clk_enable(u3d->clk);
1285         if (pdata->phy_init)
1286                 pdata->phy_init(u3d->phy_regs);
1287
1288         mv_u3d_controller_stop(u3d);
1289         /* stop all usb activities */
1290         u3d->gadget.speed = USB_SPEED_UNKNOWN;
1291         mv_u3d_stop_activity(u3d, driver);
1292         mv_u3d_disable(u3d);
1293
1294         if (pdata->phy_deinit)
1295                 pdata->phy_deinit(u3d->phy_regs);
1296         clk_disable(u3d->clk);
1297
1298         spin_unlock_irqrestore(&u3d->lock, flags);
1299
1300         u3d->driver = NULL;
1301
1302         return 0;
1303 }
1304
1305 /* device controller usb_gadget_ops structure */
1306 static const struct usb_gadget_ops mv_u3d_ops = {
1307         /* notify controller that VBUS is powered or not */
1308         .vbus_session   = mv_u3d_vbus_session,
1309
1310         /* constrain controller's VBUS power usage */
1311         .vbus_draw      = mv_u3d_vbus_draw,
1312
1313         .pullup         = mv_u3d_pullup,
1314         .udc_start      = mv_u3d_start,
1315         .udc_stop       = mv_u3d_stop,
1316 };
1317
1318 static int mv_u3d_eps_init(struct mv_u3d *u3d)
1319 {
1320         struct mv_u3d_ep        *ep;
1321         char name[14];
1322         int i;
1323
1324         /* initialize ep0, ep0 in/out use eps[1] */
1325         ep = &u3d->eps[1];
1326         ep->u3d = u3d;
1327         strncpy(ep->name, "ep0", sizeof(ep->name));
1328         ep->ep.name = ep->name;
1329         ep->ep.ops = &mv_u3d_ep_ops;
1330         ep->wedge = 0;
1331         usb_ep_set_maxpacket_limit(&ep->ep, MV_U3D_EP0_MAX_PKT_SIZE);
1332         ep->ep_num = 0;
1333         ep->ep.desc = &mv_u3d_ep0_desc;
1334         INIT_LIST_HEAD(&ep->queue);
1335         INIT_LIST_HEAD(&ep->req_list);
1336         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1337
1338         /* add ep0 ep_context */
1339         ep->ep_context = &u3d->ep_context[1];
1340
1341         /* initialize other endpoints */
1342         for (i = 2; i < u3d->max_eps * 2; i++) {
1343                 ep = &u3d->eps[i];
1344                 if (i & 1) {
1345                         snprintf(name, sizeof(name), "ep%din", i >> 1);
1346                         ep->direction = MV_U3D_EP_DIR_IN;
1347                 } else {
1348                         snprintf(name, sizeof(name), "ep%dout", i >> 1);
1349                         ep->direction = MV_U3D_EP_DIR_OUT;
1350                 }
1351                 ep->u3d = u3d;
1352                 strncpy(ep->name, name, sizeof(ep->name));
1353                 ep->ep.name = ep->name;
1354
1355                 ep->ep.ops = &mv_u3d_ep_ops;
1356                 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
1357                 ep->ep_num = i / 2;
1358
1359                 INIT_LIST_HEAD(&ep->queue);
1360                 list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list);
1361
1362                 INIT_LIST_HEAD(&ep->req_list);
1363                 spin_lock_init(&ep->req_lock);
1364                 ep->ep_context = &u3d->ep_context[i];
1365         }
1366
1367         return 0;
1368 }
1369
1370 /* delete all endpoint requests, called with spinlock held */
1371 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status)
1372 {
1373         /* endpoint fifo flush */
1374         mv_u3d_ep_fifo_flush(&ep->ep);
1375
1376         while (!list_empty(&ep->queue)) {
1377                 struct mv_u3d_req *req = NULL;
1378                 req = list_entry(ep->queue.next, struct mv_u3d_req, queue);
1379                 mv_u3d_done(ep, req, status);
1380         }
1381 }
1382
1383 /* stop all USB activities */
1384 static
1385 void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver)
1386 {
1387         struct mv_u3d_ep        *ep;
1388
1389         mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN);
1390
1391         list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) {
1392                 mv_u3d_nuke(ep, -ESHUTDOWN);
1393         }
1394
1395         /* report disconnect; the driver is already quiesced */
1396         if (driver) {
1397                 spin_unlock(&u3d->lock);
1398                 driver->disconnect(&u3d->gadget);
1399                 spin_lock(&u3d->lock);
1400         }
1401 }
1402
1403 static void mv_u3d_irq_process_error(struct mv_u3d *u3d)
1404 {
1405         /* Increment the error count */
1406         u3d->errors++;
1407         dev_err(u3d->dev, "%s\n", __func__);
1408 }
1409
1410 static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d)
1411 {
1412         u32 linkchange;
1413
1414         linkchange = ioread32(&u3d->vuc_regs->linkchange);
1415         iowrite32(linkchange, &u3d->vuc_regs->linkchange);
1416
1417         dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange);
1418
1419         if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) {
1420                 dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n",
1421                         ioread32(&u3d->vuc_regs->ltssmstate));
1422
1423                 u3d->usb_state = USB_STATE_DEFAULT;
1424                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1425                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
1426
1427                 /* set speed */
1428                 u3d->gadget.speed = USB_SPEED_SUPER;
1429         }
1430
1431         if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) {
1432                 dev_dbg(u3d->dev, "link suspend\n");
1433                 u3d->resume_state = u3d->usb_state;
1434                 u3d->usb_state = USB_STATE_SUSPENDED;
1435         }
1436
1437         if (linkchange & MV_U3D_LINK_CHANGE_RESUME) {
1438                 dev_dbg(u3d->dev, "link resume\n");
1439                 u3d->usb_state = u3d->resume_state;
1440                 u3d->resume_state = 0;
1441         }
1442
1443         if (linkchange & MV_U3D_LINK_CHANGE_WRESET) {
1444                 dev_dbg(u3d->dev, "warm reset\n");
1445                 u3d->usb_state = USB_STATE_POWERED;
1446         }
1447
1448         if (linkchange & MV_U3D_LINK_CHANGE_HRESET) {
1449                 dev_dbg(u3d->dev, "hot reset\n");
1450                 u3d->usb_state = USB_STATE_DEFAULT;
1451         }
1452
1453         if (linkchange & MV_U3D_LINK_CHANGE_INACT)
1454                 dev_dbg(u3d->dev, "inactive\n");
1455
1456         if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0)
1457                 dev_dbg(u3d->dev, "ss.disabled\n");
1458
1459         if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) {
1460                 dev_dbg(u3d->dev, "vbus invalid\n");
1461                 u3d->usb_state = USB_STATE_ATTACHED;
1462                 u3d->vbus_valid_detect = 1;
1463                 /* if external vbus detect is not supported,
1464                  * we handle it here.
1465                  */
1466                 if (!u3d->vbus) {
1467                         spin_unlock(&u3d->lock);
1468                         mv_u3d_vbus_session(&u3d->gadget, 0);
1469                         spin_lock(&u3d->lock);
1470                 }
1471         }
1472 }
1473
1474 static void mv_u3d_ch9setaddress(struct mv_u3d *u3d,
1475                                 struct usb_ctrlrequest *setup)
1476 {
1477         u32 tmp;
1478
1479         if (u3d->usb_state != USB_STATE_DEFAULT) {
1480                 dev_err(u3d->dev,
1481                         "%s, cannot setaddr in this state (%d)\n",
1482                         __func__, u3d->usb_state);
1483                 goto err;
1484         }
1485
1486         u3d->dev_addr = (u8)setup->wValue;
1487
1488         dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr);
1489
1490         if (u3d->dev_addr > 127) {
1491                 dev_err(u3d->dev,
1492                         "%s, u3d address is wrong (out of range)\n", __func__);
1493                 u3d->dev_addr = 0;
1494                 goto err;
1495         }
1496
1497         /* update usb state */
1498         u3d->usb_state = USB_STATE_ADDRESS;
1499
1500         /* set the new address */
1501         tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr);
1502         tmp &= ~0x7F;
1503         tmp |= (u32)u3d->dev_addr;
1504         iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr);
1505
1506         return;
1507 err:
1508         mv_u3d_ep0_stall(u3d);
1509 }
1510
1511 static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup)
1512 {
1513         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1514                 if (setup->bRequest == USB_REQ_SET_CONFIGURATION)
1515                         return 1;
1516
1517         return 0;
1518 }
1519
1520 static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num,
1521         struct usb_ctrlrequest *setup)
1522         __releases(&u3c->lock)
1523         __acquires(&u3c->lock)
1524 {
1525         bool delegate = false;
1526
1527         mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN);
1528
1529         dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1530                         setup->bRequestType, setup->bRequest,
1531                         setup->wValue, setup->wIndex, setup->wLength);
1532
1533         /* We process some stardard setup requests here */
1534         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1535                 switch (setup->bRequest) {
1536                 case USB_REQ_GET_STATUS:
1537                         delegate = true;
1538                         break;
1539
1540                 case USB_REQ_SET_ADDRESS:
1541                         mv_u3d_ch9setaddress(u3d, setup);
1542                         break;
1543
1544                 case USB_REQ_CLEAR_FEATURE:
1545                         delegate = true;
1546                         break;
1547
1548                 case USB_REQ_SET_FEATURE:
1549                         delegate = true;
1550                         break;
1551
1552                 default:
1553                         delegate = true;
1554                 }
1555         } else
1556                 delegate = true;
1557
1558         /* delegate USB standard requests to the gadget driver */
1559         if (delegate == true) {
1560                 /* USB requests handled by gadget */
1561                 if (setup->wLength) {
1562                         /* DATA phase from gadget, STATUS phase from u3d */
1563                         u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1564                                         ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT;
1565                         spin_unlock(&u3d->lock);
1566                         if (u3d->driver->setup(&u3d->gadget,
1567                                 &u3d->local_setup_buff) < 0) {
1568                                 dev_err(u3d->dev, "setup error!\n");
1569                                 mv_u3d_ep0_stall(u3d);
1570                         }
1571                         spin_lock(&u3d->lock);
1572                 } else {
1573                         /* no DATA phase, STATUS phase from gadget */
1574                         u3d->ep0_dir = MV_U3D_EP_DIR_IN;
1575                         u3d->ep0_state = MV_U3D_STATUS_STAGE;
1576                         spin_unlock(&u3d->lock);
1577                         if (u3d->driver->setup(&u3d->gadget,
1578                                 &u3d->local_setup_buff) < 0)
1579                                 mv_u3d_ep0_stall(u3d);
1580                         spin_lock(&u3d->lock);
1581                 }
1582
1583                 if (mv_u3d_is_set_configuration(setup)) {
1584                         dev_dbg(u3d->dev, "u3d configured\n");
1585                         u3d->usb_state = USB_STATE_CONFIGURED;
1586                 }
1587         }
1588 }
1589
1590 static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr)
1591 {
1592         struct mv_u3d_ep_context *epcontext;
1593
1594         epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN];
1595
1596         /* Copy the setup packet to local buffer */
1597         memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8);
1598 }
1599
1600 static void mv_u3d_irq_process_setup(struct mv_u3d *u3d)
1601 {
1602         u32 tmp, i;
1603         /* Process all Setup packet received interrupts */
1604         tmp = ioread32(&u3d->vuc_regs->setuplock);
1605         if (tmp) {
1606                 for (i = 0; i < u3d->max_eps; i++) {
1607                         if (tmp & (1 << i)) {
1608                                 mv_u3d_get_setup_data(u3d, i,
1609                                         (u8 *)(&u3d->local_setup_buff));
1610                                 mv_u3d_handle_setup_packet(u3d, i,
1611                                         &u3d->local_setup_buff);
1612                         }
1613                 }
1614         }
1615
1616         iowrite32(tmp, &u3d->vuc_regs->setuplock);
1617 }
1618
1619 static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d)
1620 {
1621         u32 tmp, bit_pos;
1622         int i, ep_num = 0, direction = 0;
1623         struct mv_u3d_ep        *curr_ep;
1624         struct mv_u3d_req *curr_req, *temp_req;
1625         int status;
1626
1627         tmp = ioread32(&u3d->vuc_regs->endcomplete);
1628
1629         dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp);
1630         if (!tmp)
1631                 return;
1632         iowrite32(tmp, &u3d->vuc_regs->endcomplete);
1633
1634         for (i = 0; i < u3d->max_eps * 2; i++) {
1635                 ep_num = i >> 1;
1636                 direction = i % 2;
1637
1638                 bit_pos = 1 << (ep_num + 16 * direction);
1639
1640                 if (!(bit_pos & tmp))
1641                         continue;
1642
1643                 if (i == 0)
1644                         curr_ep = &u3d->eps[1];
1645                 else
1646                         curr_ep = &u3d->eps[i];
1647
1648                 /* remove req out of ep request list after completion */
1649                 dev_dbg(u3d->dev, "tr comp: check req_list\n");
1650                 spin_lock(&curr_ep->req_lock);
1651                 if (!list_empty(&curr_ep->req_list)) {
1652                         struct mv_u3d_req *req;
1653                         req = list_entry(curr_ep->req_list.next,
1654                                                 struct mv_u3d_req, list);
1655                         list_del_init(&req->list);
1656                         curr_ep->processing = 0;
1657                 }
1658                 spin_unlock(&curr_ep->req_lock);
1659
1660                 /* process the req queue until an uncomplete request */
1661                 list_for_each_entry_safe(curr_req, temp_req,
1662                         &curr_ep->queue, queue) {
1663                         status = mv_u3d_process_ep_req(u3d, i, curr_req);
1664                         if (status)
1665                                 break;
1666                         /* write back status to req */
1667                         curr_req->req.status = status;
1668
1669                         /* ep0 request completion */
1670                         if (ep_num == 0) {
1671                                 mv_u3d_done(curr_ep, curr_req, 0);
1672                                 break;
1673                         } else {
1674                                 mv_u3d_done(curr_ep, curr_req, status);
1675                         }
1676                 }
1677
1678                 dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n");
1679                 mv_u3d_start_queue(curr_ep);
1680         }
1681 }
1682
1683 static irqreturn_t mv_u3d_irq(int irq, void *dev)
1684 {
1685         struct mv_u3d *u3d = (struct mv_u3d *)dev;
1686         u32 status, intr;
1687         u32 bridgesetting;
1688         u32 trbunderrun;
1689
1690         spin_lock(&u3d->lock);
1691
1692         status = ioread32(&u3d->vuc_regs->intrcause);
1693         intr = ioread32(&u3d->vuc_regs->intrenable);
1694         status &= intr;
1695
1696         if (status == 0) {
1697                 spin_unlock(&u3d->lock);
1698                 dev_err(u3d->dev, "irq error!\n");
1699                 return IRQ_NONE;
1700         }
1701
1702         if (status & MV_U3D_USBINT_VBUS_VALID) {
1703                 bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting);
1704                 if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) {
1705                         /* write vbus valid bit of bridge setting to clear */
1706                         bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID;
1707                         iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting);
1708                         dev_dbg(u3d->dev, "vbus valid\n");
1709
1710                         u3d->usb_state = USB_STATE_POWERED;
1711                         u3d->vbus_valid_detect = 0;
1712                         /* if external vbus detect is not supported,
1713                          * we handle it here.
1714                          */
1715                         if (!u3d->vbus) {
1716                                 spin_unlock(&u3d->lock);
1717                                 mv_u3d_vbus_session(&u3d->gadget, 1);
1718                                 spin_lock(&u3d->lock);
1719                         }
1720                 } else
1721                         dev_err(u3d->dev, "vbus bit is not set\n");
1722         }
1723
1724         /* RX data is already in the 16KB FIFO.*/
1725         if (status & MV_U3D_USBINT_UNDER_RUN) {
1726                 trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun);
1727                 dev_err(u3d->dev, "under run, ep%d\n", trbunderrun);
1728                 iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun);
1729                 mv_u3d_irq_process_error(u3d);
1730         }
1731
1732         if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) {
1733                 /* write one to clear */
1734                 iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR
1735                         | MV_U3D_USBINT_TXDESC_ERR),
1736                         &u3d->vuc_regs->intrcause);
1737                 dev_err(u3d->dev, "desc err 0x%x\n", status);
1738                 mv_u3d_irq_process_error(u3d);
1739         }
1740
1741         if (status & MV_U3D_USBINT_LINK_CHG)
1742                 mv_u3d_irq_process_link_change(u3d);
1743
1744         if (status & MV_U3D_USBINT_TX_COMPLETE)
1745                 mv_u3d_irq_process_tr_complete(u3d);
1746
1747         if (status & MV_U3D_USBINT_RX_COMPLETE)
1748                 mv_u3d_irq_process_tr_complete(u3d);
1749
1750         if (status & MV_U3D_USBINT_SETUP)
1751                 mv_u3d_irq_process_setup(u3d);
1752
1753         spin_unlock(&u3d->lock);
1754         return IRQ_HANDLED;
1755 }
1756
1757 static int mv_u3d_remove(struct platform_device *dev)
1758 {
1759         struct mv_u3d *u3d = platform_get_drvdata(dev);
1760
1761         BUG_ON(u3d == NULL);
1762
1763         usb_del_gadget_udc(&u3d->gadget);
1764
1765         /* free memory allocated in probe */
1766         if (u3d->trb_pool)
1767                 dma_pool_destroy(u3d->trb_pool);
1768
1769         if (u3d->ep_context)
1770                 dma_free_coherent(&dev->dev, u3d->ep_context_size,
1771                         u3d->ep_context, u3d->ep_context_dma);
1772
1773         kfree(u3d->eps);
1774
1775         if (u3d->irq)
1776                 free_irq(u3d->irq, u3d);
1777
1778         if (u3d->cap_regs)
1779                 iounmap(u3d->cap_regs);
1780         u3d->cap_regs = NULL;
1781
1782         kfree(u3d->status_req);
1783
1784         clk_put(u3d->clk);
1785
1786         kfree(u3d);
1787
1788         return 0;
1789 }
1790
1791 static int mv_u3d_probe(struct platform_device *dev)
1792 {
1793         struct mv_u3d *u3d = NULL;
1794         struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev);
1795         int retval = 0;
1796         struct resource *r;
1797         size_t size;
1798
1799         if (!dev_get_platdata(&dev->dev)) {
1800                 dev_err(&dev->dev, "missing platform_data\n");
1801                 retval = -ENODEV;
1802                 goto err_pdata;
1803         }
1804
1805         u3d = kzalloc(sizeof(*u3d), GFP_KERNEL);
1806         if (!u3d) {
1807                 retval = -ENOMEM;
1808                 goto err_alloc_private;
1809         }
1810
1811         spin_lock_init(&u3d->lock);
1812
1813         platform_set_drvdata(dev, u3d);
1814
1815         u3d->dev = &dev->dev;
1816         u3d->vbus = pdata->vbus;
1817
1818         u3d->clk = clk_get(&dev->dev, NULL);
1819         if (IS_ERR(u3d->clk)) {
1820                 retval = PTR_ERR(u3d->clk);
1821                 goto err_get_clk;
1822         }
1823
1824         r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs");
1825         if (!r) {
1826                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1827                 retval = -ENODEV;
1828                 goto err_get_cap_regs;
1829         }
1830
1831         u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *)
1832                 ioremap(r->start, resource_size(r));
1833         if (!u3d->cap_regs) {
1834                 dev_err(&dev->dev, "failed to map I/O memory\n");
1835                 retval = -EBUSY;
1836                 goto err_map_cap_regs;
1837         } else {
1838                 dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n",
1839                         (unsigned long) r->start,
1840                         (unsigned long) u3d->cap_regs);
1841         }
1842
1843         /* we will access controller register, so enable the u3d controller */
1844         clk_enable(u3d->clk);
1845
1846         if (pdata->phy_init) {
1847                 retval = pdata->phy_init(u3d->phy_regs);
1848                 if (retval) {
1849                         dev_err(&dev->dev, "init phy error %d\n", retval);
1850                         goto err_u3d_enable;
1851                 }
1852         }
1853
1854         u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs
1855                 + MV_U3D_USB3_OP_REGS_OFFSET);
1856
1857         u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs
1858                 + ioread32(&u3d->cap_regs->vuoff));
1859
1860         u3d->max_eps = 16;
1861
1862         /*
1863          * some platform will use usb to download image, it may not disconnect
1864          * usb gadget before loading kernel. So first stop u3d here.
1865          */
1866         mv_u3d_controller_stop(u3d);
1867         iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause);
1868
1869         if (pdata->phy_deinit)
1870                 pdata->phy_deinit(u3d->phy_regs);
1871         clk_disable(u3d->clk);
1872
1873         size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2;
1874         size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1)
1875                 & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1);
1876         u3d->ep_context = dma_alloc_coherent(&dev->dev, size,
1877                                         &u3d->ep_context_dma, GFP_KERNEL);
1878         if (!u3d->ep_context) {
1879                 dev_err(&dev->dev, "allocate ep context memory failed\n");
1880                 retval = -ENOMEM;
1881                 goto err_alloc_ep_context;
1882         }
1883         u3d->ep_context_size = size;
1884
1885         /* create TRB dma_pool resource */
1886         u3d->trb_pool = dma_pool_create("u3d_trb",
1887                         &dev->dev,
1888                         sizeof(struct mv_u3d_trb_hw),
1889                         MV_U3D_TRB_ALIGNMENT,
1890                         MV_U3D_DMA_BOUNDARY);
1891
1892         if (!u3d->trb_pool) {
1893                 retval = -ENOMEM;
1894                 goto err_alloc_trb_pool;
1895         }
1896
1897         size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2;
1898         u3d->eps = kzalloc(size, GFP_KERNEL);
1899         if (!u3d->eps) {
1900                 retval = -ENOMEM;
1901                 goto err_alloc_eps;
1902         }
1903
1904         /* initialize ep0 status request structure */
1905         u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL);
1906         if (!u3d->status_req) {
1907                 retval = -ENOMEM;
1908                 goto err_alloc_status_req;
1909         }
1910         INIT_LIST_HEAD(&u3d->status_req->queue);
1911
1912         /* allocate a small amount of memory to get valid address */
1913         u3d->status_req->req.buf = (char *)u3d->status_req
1914                                         + sizeof(struct mv_u3d_req);
1915         u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf);
1916
1917         u3d->resume_state = USB_STATE_NOTATTACHED;
1918         u3d->usb_state = USB_STATE_ATTACHED;
1919         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1920         u3d->remote_wakeup = 0;
1921
1922         r = platform_get_resource(dev, IORESOURCE_IRQ, 0);
1923         if (!r) {
1924                 dev_err(&dev->dev, "no IRQ resource defined\n");
1925                 retval = -ENODEV;
1926                 goto err_get_irq;
1927         }
1928         u3d->irq = r->start;
1929         if (request_irq(u3d->irq, mv_u3d_irq,
1930                 IRQF_SHARED, driver_name, u3d)) {
1931                 u3d->irq = 0;
1932                 dev_err(&dev->dev, "Request irq %d for u3d failed\n",
1933                         u3d->irq);
1934                 retval = -ENODEV;
1935                 goto err_request_irq;
1936         }
1937
1938         /* initialize gadget structure */
1939         u3d->gadget.ops = &mv_u3d_ops;  /* usb_gadget_ops */
1940         u3d->gadget.ep0 = &u3d->eps[1].ep;      /* gadget ep0 */
1941         INIT_LIST_HEAD(&u3d->gadget.ep_list);   /* ep_list */
1942         u3d->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
1943
1944         /* the "gadget" abstracts/virtualizes the controller */
1945         u3d->gadget.name = driver_name;         /* gadget name */
1946
1947         mv_u3d_eps_init(u3d);
1948
1949         /* external vbus detection */
1950         if (u3d->vbus) {
1951                 u3d->clock_gating = 1;
1952                 dev_err(&dev->dev, "external vbus detection\n");
1953         }
1954
1955         if (!u3d->clock_gating)
1956                 u3d->vbus_active = 1;
1957
1958         /* enable usb3 controller vbus detection */
1959         u3d->vbus_valid_detect = 1;
1960
1961         retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget);
1962         if (retval)
1963                 goto err_unregister;
1964
1965         dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n",
1966                 u3d->clock_gating ? "with" : "without");
1967
1968         return 0;
1969
1970 err_unregister:
1971         free_irq(u3d->irq, u3d);
1972 err_request_irq:
1973 err_get_irq:
1974         kfree(u3d->status_req);
1975 err_alloc_status_req:
1976         kfree(u3d->eps);
1977 err_alloc_eps:
1978         dma_pool_destroy(u3d->trb_pool);
1979 err_alloc_trb_pool:
1980         dma_free_coherent(&dev->dev, u3d->ep_context_size,
1981                 u3d->ep_context, u3d->ep_context_dma);
1982 err_alloc_ep_context:
1983         if (pdata->phy_deinit)
1984                 pdata->phy_deinit(u3d->phy_regs);
1985         clk_disable(u3d->clk);
1986 err_u3d_enable:
1987         iounmap(u3d->cap_regs);
1988 err_map_cap_regs:
1989 err_get_cap_regs:
1990 err_get_clk:
1991         clk_put(u3d->clk);
1992         kfree(u3d);
1993 err_alloc_private:
1994 err_pdata:
1995         return retval;
1996 }
1997
1998 #ifdef CONFIG_PM_SLEEP
1999 static int mv_u3d_suspend(struct device *dev)
2000 {
2001         struct mv_u3d *u3d = dev_get_drvdata(dev);
2002
2003         /*
2004          * only cable is unplugged, usb can suspend.
2005          * So do not care about clock_gating == 1, it is handled by
2006          * vbus session.
2007          */
2008         if (!u3d->clock_gating) {
2009                 mv_u3d_controller_stop(u3d);
2010
2011                 spin_lock_irq(&u3d->lock);
2012                 /* stop all usb activities */
2013                 mv_u3d_stop_activity(u3d, u3d->driver);
2014                 spin_unlock_irq(&u3d->lock);
2015
2016                 mv_u3d_disable(u3d);
2017         }
2018
2019         return 0;
2020 }
2021
2022 static int mv_u3d_resume(struct device *dev)
2023 {
2024         struct mv_u3d *u3d = dev_get_drvdata(dev);
2025         int retval;
2026
2027         if (!u3d->clock_gating) {
2028                 retval = mv_u3d_enable(u3d);
2029                 if (retval)
2030                         return retval;
2031
2032                 if (u3d->driver && u3d->softconnect) {
2033                         mv_u3d_controller_reset(u3d);
2034                         mv_u3d_ep0_reset(u3d);
2035                         mv_u3d_controller_start(u3d);
2036                 }
2037         }
2038
2039         return 0;
2040 }
2041 #endif
2042
2043 static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume);
2044
2045 static void mv_u3d_shutdown(struct platform_device *dev)
2046 {
2047         struct mv_u3d *u3d = platform_get_drvdata(dev);
2048         u32 tmp;
2049
2050         tmp = ioread32(&u3d->op_regs->usbcmd);
2051         tmp &= ~MV_U3D_CMD_RUN_STOP;
2052         iowrite32(tmp, &u3d->op_regs->usbcmd);
2053 }
2054
2055 static struct platform_driver mv_u3d_driver = {
2056         .probe          = mv_u3d_probe,
2057         .remove         = mv_u3d_remove,
2058         .shutdown       = mv_u3d_shutdown,
2059         .driver         = {
2060                 .owner  = THIS_MODULE,
2061                 .name   = "mv-u3d",
2062                 .pm     = &mv_u3d_pm_ops,
2063         },
2064 };
2065
2066 module_platform_driver(mv_u3d_driver);
2067 MODULE_ALIAS("platform:mv-u3d");
2068 MODULE_DESCRIPTION(DRIVER_DESC);
2069 MODULE_AUTHOR("Yu Xu <[email protected]>");
2070 MODULE_LICENSE("GPL");