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1 /*
2  * Copyright (c) 2000-2013 LSI Corporation.
3  *
4  *
5  *          Name:  mpi2_cnfg.h
6  *         Title:  MPI Configuration messages and pages
7  * Creation Date:  November 10, 2006
8  *
9  *   mpi2_cnfg.h Version:  02.00.24
10  *
11  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12  *       prefix are for use only on MPI v2.5 products, and must not be used
13  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
14  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
15  *
16  * Version History
17  * ---------------
18  *
19  * Date      Version   Description
20  * --------  --------  ------------------------------------------------------
21  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
22  * 06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
23  *                     Added Manufacturing Page 11.
24  *                     Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
25  *                     define.
26  * 06-26-07  02.00.02  Adding generic structure for product-specific
27  *                     Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
28  *                     Rework of BIOS Page 2 configuration page.
29  *                     Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
30  *                     forms.
31  *                     Added configuration pages IOC Page 8 and Driver
32  *                     Persistent Mapping Page 0.
33  * 08-31-07  02.00.03  Modified configuration pages dealing with Integrated
34  *                     RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
35  *                     RAID Physical Disk Pages 0 and 1, RAID Configuration
36  *                     Page 0).
37  *                     Added new value for AccessStatus field of SAS Device
38  *                     Page 0 (_SATA_NEEDS_INITIALIZATION).
39  * 10-31-07  02.00.04  Added missing SEPDevHandle field to
40  *                     MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
41  * 12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
42  *                     NVDATA.
43  *                     Modified IOC Page 7 to use masks and added field for
44  *                     SASBroadcastPrimitiveMasks.
45  *                     Added MPI2_CONFIG_PAGE_BIOS_4.
46  *                     Added MPI2_CONFIG_PAGE_LOG_0.
47  * 02-29-08  02.00.06  Modified various names to make them 32-character unique.
48  *                     Added SAS Device IDs.
49  *                     Updated Integrated RAID configuration pages including
50  *                     Manufacturing Page 4, IOC Page 6, and RAID Configuration
51  *                     Page 0.
52  * 05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
53  *                     Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
54  *                     Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
55  *                     Added missing MaxNumRoutedSasAddresses field to
56  *                     MPI2_CONFIG_PAGE_EXPANDER_0.
57  *                     Added SAS Port Page 0.
58  *                     Modified structure layout for
59  *                     MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
60  * 06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
61  *                     MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
62  * 10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
63  *                     to 0x000000FF.
64  *                     Added two new values for the Physical Disk Coercion Size
65  *                     bits in the Flags field of Manufacturing Page 4.
66  *                     Added product-specific Manufacturing pages 16 to 31.
67  *                     Modified Flags bits for controlling write cache on SATA
68  *                     drives in IO Unit Page 1.
69  *                     Added new bit to AdditionalControlFlags of SAS IO Unit
70  *                     Page 1 to control Invalid Topology Correction.
71  *                     Added additional defines for RAID Volume Page 0
72  *                     VolumeStatusFlags field.
73  *                     Modified meaning of RAID Volume Page 0 VolumeSettings
74  *                     define for auto-configure of hot-swap drives.
75  *                     Added SupportedPhysDisks field to RAID Volume Page 1 and
76  *                     added related defines.
77  *                     Added PhysDiskAttributes field (and related defines) to
78  *                     RAID Physical Disk Page 0.
79  *                     Added MPI2_SAS_PHYINFO_PHY_VACANT define.
80  *                     Added three new DiscoveryStatus bits for SAS IO Unit
81  *                     Page 0 and SAS Expander Page 0.
82  *                     Removed multiplexing information from SAS IO Unit pages.
83  *                     Added BootDeviceWaitTime field to SAS IO Unit Page 4.
84  *                     Removed Zone Address Resolved bit from PhyInfo and from
85  *                     Expander Page 0 Flags field.
86  *                     Added two new AccessStatus values to SAS Device Page 0
87  *                     for indicating routing problems. Added 3 reserved words
88  *                     to this page.
89  * 01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
90  *                     Inserted missing reserved field into structure for IOC
91  *                     Page 6.
92  *                     Added more pending task bits to RAID Volume Page 0
93  *                     VolumeStatusFlags defines.
94  *                     Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
95  *                     Added a new DiscoveryStatus bit for SAS IO Unit Page 0
96  *                     and SAS Expander Page 0 to flag a downstream initiator
97  *                     when in simplified routing mode.
98  *                     Removed SATA Init Failure defines for DiscoveryStatus
99  *                     fields of SAS IO Unit Page 0 and SAS Expander Page 0.
100  *                     Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
101  *                     Added PortGroups, DmaGroup, and ControlGroup fields to
102  *                     SAS Device Page 0.
103  * 05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
104  *                     Unit Page 6.
105  *                     Added expander reduced functionality data to SAS
106  *                     Expander Page 0.
107  *                     Added SAS PHY Page 2 and SAS PHY Page 3.
108  * 07-30-09  02.00.12  Added IO Unit Page 7.
109  *                     Added new device ids.
110  *                     Added SAS IO Unit Page 5.
111  *                     Added partial and slumber power management capable flags
112  *                     to SAS Device Page 0 Flags field.
113  *                     Added PhyInfo defines for power condition.
114  *                     Added Ethernet configuration pages.
115  * 10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
116  *                     Added SAS PHY Page 4 structure and defines.
117  * 02-10-10  02.00.14  Modified the comments for the configuration page
118  *                     structures that contain an array of data. The host
119  *                     should use the "count" field in the page data (e.g. the
120  *                     NumPhys field) to determine the number of valid elements
121  *                     in the array.
122  *                     Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
123  *                     Added PowerManagementCapabilities to IO Unit Page 7.
124  *                     Added PortWidthModGroup field to
125  *                     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
126  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
127  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
128  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
129  * 05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
130  *                     define.
131  *                     Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
132  *                     Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
133  * 08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
134  *                     defines.
135  * 11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
136  *                     MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
137  *                     the Pinout field.
138  *                     Added BoardTemperature and BoardTemperatureUnits fields
139  *                     to MPI2_CONFIG_PAGE_IO_UNIT_7.
140  *                     Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
141  *                     and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
142  * 02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
143  *                     Added IO Unit Page 8, IO Unit Page 9,
144  *                     and IO Unit Page 10.
145  *                     Added SASNotifyPrimitiveMasks field to
146  *                     MPI2_CONFIG_PAGE_IOC_7.
147  * 03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
148  * 05-25-11  02.00.20  Cleaned up a few comments.
149  * 08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
150  *                     for PCIe link as obsolete.
151  *                     Added SpinupFlags field containing a Disable Spin-up bit
152  *                     to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
153  *                     Unit Page 4.
154  * 11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
155  *                     Added UEFIVersion field to BIOS Page 1 and defined new
156  *                     BiosOptions bits.
157  *                     Incorporating additions for MPI v2.5.
158  * 11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
159  *                     Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
160  * 12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
161  *                     obsolete for MPI v2.5 and later.
162  *                     Added some defines for 12G SAS speeds.
163  * --------------------------------------------------------------------------
164  */
165
166 #ifndef MPI2_CNFG_H
167 #define MPI2_CNFG_H
168
169 /*****************************************************************************
170 *  Configuration Page Header and defines
171 *****************************************************************************/
172
173 /*Config Page Header */
174 typedef struct _MPI2_CONFIG_PAGE_HEADER {
175         U8                 PageVersion;                /*0x00 */
176         U8                 PageLength;                 /*0x01 */
177         U8                 PageNumber;                 /*0x02 */
178         U8                 PageType;                   /*0x03 */
179 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
180         Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
181
182 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
183         MPI2_CONFIG_PAGE_HEADER  Struct;
184         U8                       Bytes[4];
185         U16                      Word16[2];
186         U32                      Word32;
187 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
188         Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
189
190 /*Extended Config Page Header */
191 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
192         U8                  PageVersion;                /*0x00 */
193         U8                  Reserved1;                  /*0x01 */
194         U8                  PageNumber;                 /*0x02 */
195         U8                  PageType;                   /*0x03 */
196         U16                 ExtPageLength;              /*0x04 */
197         U8                  ExtPageType;                /*0x06 */
198         U8                  Reserved2;                  /*0x07 */
199 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
200         *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
201         Mpi2ConfigExtendedPageHeader_t,
202         *pMpi2ConfigExtendedPageHeader_t;
203
204 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
205         MPI2_CONFIG_PAGE_HEADER          Struct;
206         MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
207         U8                               Bytes[8];
208         U16                              Word16[4];
209         U32                              Word32[2];
210 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
211         *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
212         Mpi2ConfigPageExtendedHeaderUnion,
213         *pMpi2ConfigPageExtendedHeaderUnion;
214
215
216 /*PageType field values */
217 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
218 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
219 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
220 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
221
222 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
223 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
224 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
225 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
226 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
227 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
228 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
229 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
230
231 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
232
233
234 /*ExtPageType field values */
235 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
236 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
237 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
238 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
239 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
240 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
241 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
242 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
243 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
244 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
245 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
246
247
248 /*****************************************************************************
249 *  PageAddress defines
250 *****************************************************************************/
251
252 /*RAID Volume PageAddress format */
253 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
254 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
255 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
256
257 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
258
259
260 /*RAID Physical Disk PageAddress format */
261 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
262 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
263 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
264 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
265
266 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
267 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
268
269
270 /*SAS Expander PageAddress format */
271 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
272 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
273 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
274 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
275
276 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
277 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
278 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
279
280
281 /*SAS Device PageAddress format */
282 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
283 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
284 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
285
286 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
287
288
289 /*SAS PHY PageAddress format */
290 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
291 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
292 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
293
294 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
295 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
296
297
298 /*SAS Port PageAddress format */
299 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
300 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
301 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
302
303 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
304
305
306 /*SAS Enclosure PageAddress format */
307 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
308 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
309 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
310
311 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
312
313
314 /*RAID Configuration PageAddress format */
315 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
316 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
317 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
318 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
319
320 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
321
322
323 /*Driver Persistent Mapping PageAddress format */
324 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
325 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
326
327 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
328 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
329 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
330
331
332 /*Ethernet PageAddress format */
333 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
334 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
335
336 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
337
338
339
340 /****************************************************************************
341 *  Configuration messages
342 ****************************************************************************/
343
344 /*Configuration Request Message */
345 typedef struct _MPI2_CONFIG_REQUEST {
346         U8                      Action;                     /*0x00 */
347         U8                      SGLFlags;                   /*0x01 */
348         U8                      ChainOffset;                /*0x02 */
349         U8                      Function;                   /*0x03 */
350         U16                     ExtPageLength;              /*0x04 */
351         U8                      ExtPageType;                /*0x06 */
352         U8                      MsgFlags;                   /*0x07 */
353         U8                      VP_ID;                      /*0x08 */
354         U8                      VF_ID;                      /*0x09 */
355         U16                     Reserved1;                  /*0x0A */
356         U8                      Reserved2;                  /*0x0C */
357         U8                      ProxyVF_ID;                 /*0x0D */
358         U16                     Reserved4;                  /*0x0E */
359         U32                     Reserved3;                  /*0x10 */
360         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
361         U32                     PageAddress;                /*0x18 */
362         MPI2_SGE_IO_UNION       PageBufferSGE;              /*0x1C */
363 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
364         Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
365
366 /*values for the Action field */
367 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
368 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
369 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
370 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
371 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
372 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
373 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
374 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
375
376 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
377
378
379 /*Config Reply Message */
380 typedef struct _MPI2_CONFIG_REPLY {
381         U8                      Action;                     /*0x00 */
382         U8                      SGLFlags;                   /*0x01 */
383         U8                      MsgLength;                  /*0x02 */
384         U8                      Function;                   /*0x03 */
385         U16                     ExtPageLength;              /*0x04 */
386         U8                      ExtPageType;                /*0x06 */
387         U8                      MsgFlags;                   /*0x07 */
388         U8                      VP_ID;                      /*0x08 */
389         U8                      VF_ID;                      /*0x09 */
390         U16                     Reserved1;                  /*0x0A */
391         U16                     Reserved2;                  /*0x0C */
392         U16                     IOCStatus;                  /*0x0E */
393         U32                     IOCLogInfo;                 /*0x10 */
394         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
395 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
396         Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
397
398
399
400 /*****************************************************************************
401 *
402 *              C o n f i g u r a t i o n    P a g e s
403 *
404 *****************************************************************************/
405
406 /****************************************************************************
407 *  Manufacturing Config pages
408 ****************************************************************************/
409
410 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
411
412 /*MPI v2.0 SAS products */
413 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
414 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
415 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
416 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
417 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
418 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
419 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
420
421 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
422
423 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
424 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
425 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
426 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
427 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
428 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
429 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
430 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
431 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
432
433 /*MPI v2.5 SAS products */
434 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
435 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
436 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
437 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
438 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
439 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
440
441
442
443
444 /*Manufacturing Page 0 */
445
446 typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
447         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
448         U8                      ChipName[16];               /*0x04 */
449         U8                      ChipRevision[8];            /*0x14 */
450         U8                      BoardName[16];              /*0x1C */
451         U8                      BoardAssembly[16];          /*0x2C */
452         U8                      BoardTracerNumber[16];      /*0x3C */
453 } MPI2_CONFIG_PAGE_MAN_0,
454         *PTR_MPI2_CONFIG_PAGE_MAN_0,
455         Mpi2ManufacturingPage0_t,
456         *pMpi2ManufacturingPage0_t;
457
458 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
459
460
461 /*Manufacturing Page 1 */
462
463 typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
464         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
465         U8                      VPD[256];                   /*0x04 */
466 } MPI2_CONFIG_PAGE_MAN_1,
467         *PTR_MPI2_CONFIG_PAGE_MAN_1,
468         Mpi2ManufacturingPage1_t,
469         *pMpi2ManufacturingPage1_t;
470
471 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
472
473
474 typedef struct _MPI2_CHIP_REVISION_ID {
475         U16 DeviceID;                                       /*0x00 */
476         U8  PCIRevisionID;                                  /*0x02 */
477         U8  Reserved;                                       /*0x03 */
478 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
479         Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
480
481
482 /*Manufacturing Page 2 */
483
484 /*
485  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
486  *one and check Header.PageLength at runtime.
487  */
488 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
489 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
490 #endif
491
492 typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
493         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
494         MPI2_CHIP_REVISION_ID   ChipId;                     /*0x04 */
495         U32
496                 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
497 } MPI2_CONFIG_PAGE_MAN_2,
498         *PTR_MPI2_CONFIG_PAGE_MAN_2,
499         Mpi2ManufacturingPage2_t,
500         *pMpi2ManufacturingPage2_t;
501
502 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
503
504
505 /*Manufacturing Page 3 */
506
507 /*
508  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
509  *one and check Header.PageLength at runtime.
510  */
511 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
512 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
513 #endif
514
515 typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
516         MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
517         MPI2_CHIP_REVISION_ID               ChipId;         /*0x04 */
518         U32
519                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
520 } MPI2_CONFIG_PAGE_MAN_3,
521         *PTR_MPI2_CONFIG_PAGE_MAN_3,
522         Mpi2ManufacturingPage3_t,
523         *pMpi2ManufacturingPage3_t;
524
525 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
526
527
528 /*Manufacturing Page 4 */
529
530 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
531         U8                          PowerSaveFlags;                 /*0x00 */
532         U8                          InternalOperationsSleepTime;    /*0x01 */
533         U8                          InternalOperationsRunTime;      /*0x02 */
534         U8                          HostIdleTime;                   /*0x03 */
535 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
536         *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
537         Mpi2ManPage4PwrSaveSettings_t,
538         *pMpi2ManPage4PwrSaveSettings_t;
539
540 /*defines for the PowerSaveFlags field */
541 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
542 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
543 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
544 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
545
546 typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
547         MPI2_CONFIG_PAGE_HEADER             Header;                 /*0x00 */
548         U32                                 Reserved1;              /*0x04 */
549         U32                                 Flags;                  /*0x08 */
550         U8                                  InquirySize;            /*0x0C */
551         U8                                  Reserved2;              /*0x0D */
552         U16                                 Reserved3;              /*0x0E */
553         U8                                  InquiryData[56];        /*0x10 */
554         U32                                 RAID0VolumeSettings;    /*0x48 */
555         U32                                 RAID1EVolumeSettings;   /*0x4C */
556         U32                                 RAID1VolumeSettings;    /*0x50 */
557         U32                                 RAID10VolumeSettings;   /*0x54 */
558         U32                                 Reserved4;              /*0x58 */
559         U32                                 Reserved5;              /*0x5C */
560         MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /*0x60 */
561         U8                                  MaxOCEDisks;            /*0x64 */
562         U8                                  ResyncRate;             /*0x65 */
563         U16                                 DataScrubDuration;      /*0x66 */
564         U8                                  MaxHotSpares;           /*0x68 */
565         U8                                  MaxPhysDisksPerVol;     /*0x69 */
566         U8                                  MaxPhysDisks;           /*0x6A */
567         U8                                  MaxVolumes;             /*0x6B */
568 } MPI2_CONFIG_PAGE_MAN_4,
569         *PTR_MPI2_CONFIG_PAGE_MAN_4,
570         Mpi2ManufacturingPage4_t,
571         *pMpi2ManufacturingPage4_t;
572
573 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
574
575 /*Manufacturing Page 4 Flags field */
576 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
577 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
578
579 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
580 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
581 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
582
583 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
584 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
585 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
586 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
587 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
588
589 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
590 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
591 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
592 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
593
594 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
595 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
596 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
597 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
598 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
599 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
600 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
601 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
602
603
604 /*Manufacturing Page 5 */
605
606 /*
607  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
608  *one and check the value returned for NumPhys at runtime.
609  */
610 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
611 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
612 #endif
613
614 typedef struct _MPI2_MANUFACTURING5_ENTRY {
615         U64                                 WWID;           /*0x00 */
616         U64                                 DeviceName;     /*0x08 */
617 } MPI2_MANUFACTURING5_ENTRY,
618         *PTR_MPI2_MANUFACTURING5_ENTRY,
619         Mpi2Manufacturing5Entry_t,
620         *pMpi2Manufacturing5Entry_t;
621
622 typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
623         MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
624         U8                                  NumPhys;        /*0x04 */
625         U8                                  Reserved1;      /*0x05 */
626         U16                                 Reserved2;      /*0x06 */
627         U32                                 Reserved3;      /*0x08 */
628         U32                                 Reserved4;      /*0x0C */
629         MPI2_MANUFACTURING5_ENTRY
630                 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
631 } MPI2_CONFIG_PAGE_MAN_5,
632         *PTR_MPI2_CONFIG_PAGE_MAN_5,
633         Mpi2ManufacturingPage5_t,
634         *pMpi2ManufacturingPage5_t;
635
636 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
637
638
639 /*Manufacturing Page 6 */
640
641 typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
642         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
643         U32                             ProductSpecificInfo;/*0x04 */
644 } MPI2_CONFIG_PAGE_MAN_6,
645         *PTR_MPI2_CONFIG_PAGE_MAN_6,
646         Mpi2ManufacturingPage6_t,
647         *pMpi2ManufacturingPage6_t;
648
649 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
650
651
652 /*Manufacturing Page 7 */
653
654 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
655         U32                         Pinout;                 /*0x00 */
656         U8                          Connector[16];          /*0x04 */
657         U8                          Location;               /*0x14 */
658         U8                          ReceptacleID;           /*0x15 */
659         U16                         Slot;                   /*0x16 */
660         U32                         Reserved2;              /*0x18 */
661 } MPI2_MANPAGE7_CONNECTOR_INFO,
662         *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
663         Mpi2ManPage7ConnectorInfo_t,
664         *pMpi2ManPage7ConnectorInfo_t;
665
666 /*defines for the Pinout field */
667 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
668 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
669
670 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
671 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
672 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
673 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
674 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
675 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
676 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
677 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
678 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
679 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
680 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
681 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
682 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
683 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
684 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
685
686 /*defines for the Location field */
687 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
688 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
689 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
690 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
691 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
692 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
693 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
694
695 /*
696  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
697  *one and check the value returned for NumPhys at runtime.
698  */
699 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
700 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
701 #endif
702
703 typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
704         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
705         U32                             Reserved1;          /*0x04 */
706         U32                             Reserved2;          /*0x08 */
707         U32                             Flags;              /*0x0C */
708         U8                              EnclosureName[16];  /*0x10 */
709         U8                              NumPhys;            /*0x20 */
710         U8                              Reserved3;          /*0x21 */
711         U16                             Reserved4;          /*0x22 */
712         MPI2_MANPAGE7_CONNECTOR_INFO
713         ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
714 } MPI2_CONFIG_PAGE_MAN_7,
715         *PTR_MPI2_CONFIG_PAGE_MAN_7,
716         Mpi2ManufacturingPage7_t,
717         *pMpi2ManufacturingPage7_t;
718
719 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
720
721 /*defines for the Flags field */
722 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
723 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
724
725
726 /*
727  *Generic structure to use for product-specific manufacturing pages
728  *(currently Manufacturing Page 8 through Manufacturing Page 31).
729  */
730
731 typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
732         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
733         U32                             ProductSpecificInfo;/*0x04 */
734 } MPI2_CONFIG_PAGE_MAN_PS,
735         *PTR_MPI2_CONFIG_PAGE_MAN_PS,
736         Mpi2ManufacturingPagePS_t,
737         *pMpi2ManufacturingPagePS_t;
738
739 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
740 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
741 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
742 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
743 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
744 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
745 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
746 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
747 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
748 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
749 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
750 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
751 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
752 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
753 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
754 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
755 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
756 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
757 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
758 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
759 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
760 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
761 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
762 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
763
764
765 /****************************************************************************
766 *  IO Unit Config Pages
767 ****************************************************************************/
768
769 /*IO Unit Page 0 */
770
771 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
772         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
773         U64                     UniqueValue;                /*0x04 */
774         MPI2_VERSION_UNION      NvdataVersionDefault;       /*0x08 */
775         MPI2_VERSION_UNION      NvdataVersionPersistent;    /*0x0A */
776 } MPI2_CONFIG_PAGE_IO_UNIT_0,
777         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
778         Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
779
780 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
781
782
783 /*IO Unit Page 1 */
784
785 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
786         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
787         U32                     Flags;                      /*0x04 */
788 } MPI2_CONFIG_PAGE_IO_UNIT_1,
789         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
790         Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
791
792 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
793
794 /*IO Unit Page 1 Flags defines */
795 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
796 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
797 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
798 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
799 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
800 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
801 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
802 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
803 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
804 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
805 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
806 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
807
808
809 /*IO Unit Page 3 */
810
811 /*
812  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
813  *one and check the value returned for GPIOCount at runtime.
814  */
815 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
816 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
817 #endif
818
819 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
820         MPI2_CONFIG_PAGE_HEADER Header;                  /*0x00 */
821         U8                      GPIOCount;               /*0x04 */
822         U8                      Reserved1;               /*0x05 */
823         U16                     Reserved2;               /*0x06 */
824         U16
825                 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
826 } MPI2_CONFIG_PAGE_IO_UNIT_3,
827         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
828         Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
829
830 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
831
832 /*defines for IO Unit Page 3 GPIOVal field */
833 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
834 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
835 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
836 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
837
838
839 /*IO Unit Page 5 */
840
841 /*
842  *Upper layer code (drivers, utilities, etc.) should leave this define set to
843  *one and check the value returned for NumDmaEngines at runtime.
844  */
845 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
846 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
847 #endif
848
849 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
850         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
851         U64
852                 RaidAcceleratorBufferBaseAddress;           /*0x04 */
853         U64
854                 RaidAcceleratorBufferSize;                  /*0x0C */
855         U64
856                 RaidAcceleratorControlBaseAddress;          /*0x14 */
857         U8                      RAControlSize;              /*0x1C */
858         U8                      NumDmaEngines;              /*0x1D */
859         U8                      RAMinControlSize;           /*0x1E */
860         U8                      RAMaxControlSize;           /*0x1F */
861         U32                     Reserved1;                  /*0x20 */
862         U32                     Reserved2;                  /*0x24 */
863         U32                     Reserved3;                  /*0x28 */
864         U32
865         DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
866 } MPI2_CONFIG_PAGE_IO_UNIT_5,
867         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
868         Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
869
870 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
871
872 /*defines for IO Unit Page 5 DmaEngineCapabilities field */
873 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFF00)
874 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
875
876 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
877 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
878 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
879 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
880
881
882 /*IO Unit Page 6 */
883
884 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
885         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
886         U16                     Flags;                  /*0x04 */
887         U8                      RAHostControlSize;      /*0x06 */
888         U8                      Reserved0;              /*0x07 */
889         U64
890                 RaidAcceleratorHostControlBaseAddress;  /*0x08 */
891         U32                     Reserved1;              /*0x10 */
892         U32                     Reserved2;              /*0x14 */
893         U32                     Reserved3;              /*0x18 */
894 } MPI2_CONFIG_PAGE_IO_UNIT_6,
895         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
896         Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
897
898 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
899
900 /*defines for IO Unit Page 6 Flags field */
901 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
902
903
904 /*IO Unit Page 7 */
905
906 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
907         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
908         U8                      CurrentPowerMode;       /*0x04 */
909         U8                      PreviousPowerMode;      /*0x05 */
910         U8                      PCIeWidth;              /*0x06 */
911         U8                      PCIeSpeed;              /*0x07 */
912         U32                     ProcessorState;         /*0x08 */
913         U32
914                 PowerManagementCapabilities;            /*0x0C */
915         U16                     IOCTemperature;         /*0x10 */
916         U8
917                 IOCTemperatureUnits;                    /*0x12 */
918         U8                      IOCSpeed;               /*0x13 */
919         U16                     BoardTemperature;       /*0x14 */
920         U8
921                 BoardTemperatureUnits;                  /*0x16 */
922         U8                      Reserved3;              /*0x17 */
923 } MPI2_CONFIG_PAGE_IO_UNIT_7,
924         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
925         Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
926
927 #define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x02)
928
929 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
930 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
931 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
932 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
933 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
934 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
935
936 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
937 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
938 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
939 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
940 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
941 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
942
943
944 /*defines for IO Unit Page 7 PCIeWidth field */
945 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
946 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
947 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
948 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
949
950 /*defines for IO Unit Page 7 PCIeSpeed field */
951 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
952 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
953 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
954
955 /*defines for IO Unit Page 7 ProcessorState field */
956 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
957 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
958
959 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
960 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
961 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
962
963 /*defines for IO Unit Page 7 PowerManagementCapabilities field */
964 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
965 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
966 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
967 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
968 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
969 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
970 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
971 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
972 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
973 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
974 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
975 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
976 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
977 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
978 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
979 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008)
980 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004)
981 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002)
982 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001)
983
984 /*obsolete names for the PowerManagementCapabilities bits (above) */
985 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
986 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
987 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
988 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /*obsolete */
989 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /*obsolete */
990
991
992 /*defines for IO Unit Page 7 IOCTemperatureUnits field */
993 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
994 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
995 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
996
997 /*defines for IO Unit Page 7 IOCSpeed field */
998 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
999 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
1000 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
1001 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
1002
1003 /*defines for IO Unit Page 7 BoardTemperatureUnits field */
1004 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
1005 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
1006 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
1007
1008
1009 /*IO Unit Page 8 */
1010
1011 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
1012
1013 typedef struct _MPI2_IOUNIT8_SENSOR {
1014         U16                     Flags;                  /*0x00 */
1015         U16                     Reserved1;              /*0x02 */
1016         U16
1017                 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1018         U32                     Reserved2;              /*0x0C */
1019         U32                     Reserved3;              /*0x10 */
1020         U32                     Reserved4;              /*0x14 */
1021 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1022         Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1023
1024 /*defines for IO Unit Page 8 Sensor Flags field */
1025 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
1026 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
1027 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
1028 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
1029
1030 /*
1031  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1032  *one and check the value returned for NumSensors at runtime.
1033  */
1034 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1035 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
1036 #endif
1037
1038 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1039         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1040         U32                     Reserved1;              /*0x04 */
1041         U32                     Reserved2;              /*0x08 */
1042         U8                      NumSensors;             /*0x0C */
1043         U8                      PollingInterval;        /*0x0D */
1044         U16                     Reserved3;              /*0x0E */
1045         MPI2_IOUNIT8_SENSOR
1046                 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1047 } MPI2_CONFIG_PAGE_IO_UNIT_8,
1048         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1049         Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1050
1051 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
1052
1053
1054 /*IO Unit Page 9 */
1055
1056 typedef struct _MPI2_IOUNIT9_SENSOR {
1057         U16                     CurrentTemperature;     /*0x00 */
1058         U16                     Reserved1;              /*0x02 */
1059         U8                      Flags;                  /*0x04 */
1060         U8                      Reserved2;              /*0x05 */
1061         U16                     Reserved3;              /*0x06 */
1062         U32                     Reserved4;              /*0x08 */
1063         U32                     Reserved5;              /*0x0C */
1064 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1065         Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1066
1067 /*defines for IO Unit Page 9 Sensor Flags field */
1068 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
1069
1070 /*
1071  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1072  *one and check the value returned for NumSensors at runtime.
1073  */
1074 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1075 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
1076 #endif
1077
1078 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1079         MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1080         U32                     Reserved1;              /*0x04 */
1081         U32                     Reserved2;              /*0x08 */
1082         U8                      NumSensors;             /*0x0C */
1083         U8                      Reserved4;              /*0x0D */
1084         U16                     Reserved3;              /*0x0E */
1085         MPI2_IOUNIT9_SENSOR
1086                 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1087 } MPI2_CONFIG_PAGE_IO_UNIT_9,
1088         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1089         Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1090
1091 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1092
1093
1094 /*IO Unit Page 10 */
1095
1096 typedef struct _MPI2_IOUNIT10_FUNCTION {
1097         U8                      CreditPercent;      /*0x00 */
1098         U8                      Reserved1;          /*0x01 */
1099         U16                     Reserved2;          /*0x02 */
1100 } MPI2_IOUNIT10_FUNCTION,
1101         *PTR_MPI2_IOUNIT10_FUNCTION,
1102         Mpi2IOUnit10Function_t,
1103         *pMpi2IOUnit10Function_t;
1104
1105 /*
1106  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1107  *one and check the value returned for NumFunctions at runtime.
1108  */
1109 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1110 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1111 #endif
1112
1113 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1114         MPI2_CONFIG_PAGE_HEADER Header;                      /*0x00 */
1115         U8                      NumFunctions;                /*0x04 */
1116         U8                      Reserved1;                   /*0x05 */
1117         U16                     Reserved2;                   /*0x06 */
1118         U32                     Reserved3;                   /*0x08 */
1119         U32                     Reserved4;                   /*0x0C */
1120         MPI2_IOUNIT10_FUNCTION
1121                 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1122 } MPI2_CONFIG_PAGE_IO_UNIT_10,
1123         *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1124         Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1125
1126 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1127
1128
1129
1130 /****************************************************************************
1131 *  IOC Config Pages
1132 ****************************************************************************/
1133
1134 /*IOC Page 0 */
1135
1136 typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1137         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1138         U32                     Reserved1;                  /*0x04 */
1139         U32                     Reserved2;                  /*0x08 */
1140         U16                     VendorID;                   /*0x0C */
1141         U16                     DeviceID;                   /*0x0E */
1142         U8                      RevisionID;                 /*0x10 */
1143         U8                      Reserved3;                  /*0x11 */
1144         U16                     Reserved4;                  /*0x12 */
1145         U32                     ClassCode;                  /*0x14 */
1146         U16                     SubsystemVendorID;          /*0x18 */
1147         U16                     SubsystemID;                /*0x1A */
1148 } MPI2_CONFIG_PAGE_IOC_0,
1149         *PTR_MPI2_CONFIG_PAGE_IOC_0,
1150         Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1151
1152 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1153
1154
1155 /*IOC Page 1 */
1156
1157 typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1158         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1159         U32                     Flags;                      /*0x04 */
1160         U32                     CoalescingTimeout;          /*0x08 */
1161         U8                      CoalescingDepth;            /*0x0C */
1162         U8                      PCISlotNum;                 /*0x0D */
1163         U8                      PCIBusNum;                  /*0x0E */
1164         U8                      PCIDomainSegment;           /*0x0F */
1165         U32                     Reserved1;                  /*0x10 */
1166         U32                     Reserved2;                  /*0x14 */
1167 } MPI2_CONFIG_PAGE_IOC_1,
1168         *PTR_MPI2_CONFIG_PAGE_IOC_1,
1169         Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1170
1171 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1172
1173 /*defines for IOC Page 1 Flags field */
1174 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1175
1176 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1177 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1178 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1179
1180 /*IOC Page 6 */
1181
1182 typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1183         MPI2_CONFIG_PAGE_HEADER Header;         /*0x00 */
1184         U32
1185                 CapabilitiesFlags;              /*0x04 */
1186         U8                      MaxDrivesRAID0; /*0x08 */
1187         U8                      MaxDrivesRAID1; /*0x09 */
1188         U8
1189                  MaxDrivesRAID1E;                /*0x0A */
1190         U8
1191                  MaxDrivesRAID10;               /*0x0B */
1192         U8                      MinDrivesRAID0; /*0x0C */
1193         U8                      MinDrivesRAID1; /*0x0D */
1194         U8
1195                  MinDrivesRAID1E;                /*0x0E */
1196         U8
1197                  MinDrivesRAID10;                /*0x0F */
1198         U32                     Reserved1;      /*0x10 */
1199         U8
1200                  MaxGlobalHotSpares;             /*0x14 */
1201         U8                      MaxPhysDisks;   /*0x15 */
1202         U8                      MaxVolumes;     /*0x16 */
1203         U8                      MaxConfigs;     /*0x17 */
1204         U8                      MaxOCEDisks;    /*0x18 */
1205         U8                      Reserved2;      /*0x19 */
1206         U16                     Reserved3;      /*0x1A */
1207         U32
1208                 SupportedStripeSizeMapRAID0;    /*0x1C */
1209         U32
1210                 SupportedStripeSizeMapRAID1E;   /*0x20 */
1211         U32
1212                 SupportedStripeSizeMapRAID10;   /*0x24 */
1213         U32                     Reserved4;      /*0x28 */
1214         U32                     Reserved5;      /*0x2C */
1215         U16
1216                 DefaultMetadataSize;            /*0x30 */
1217         U16                     Reserved6;      /*0x32 */
1218         U16
1219                 MaxBadBlockTableEntries;        /*0x34 */
1220         U16                     Reserved7;      /*0x36 */
1221         U32
1222                 IRNvsramVersion;                /*0x38 */
1223 } MPI2_CONFIG_PAGE_IOC_6,
1224         *PTR_MPI2_CONFIG_PAGE_IOC_6,
1225         Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1226
1227 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
1228
1229 /*defines for IOC Page 6 CapabilitiesFlags */
1230 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
1231 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1232 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1233 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1234 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1235 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1236
1237
1238 /*IOC Page 7 */
1239
1240 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1241
1242 typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1243         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1244         U32                     Reserved1;                  /*0x04 */
1245         U32
1246                 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1247         U16                     SASBroadcastPrimitiveMasks; /*0x18 */
1248         U16                     SASNotifyPrimitiveMasks;    /*0x1A */
1249         U32                     Reserved3;                  /*0x1C */
1250 } MPI2_CONFIG_PAGE_IOC_7,
1251         *PTR_MPI2_CONFIG_PAGE_IOC_7,
1252         Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1253
1254 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1255
1256
1257 /*IOC Page 8 */
1258
1259 typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1260         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1261         U8                      NumDevsPerEnclosure;        /*0x04 */
1262         U8                      Reserved1;                  /*0x05 */
1263         U16                     Reserved2;                  /*0x06 */
1264         U16                     MaxPersistentEntries;       /*0x08 */
1265         U16                     MaxNumPhysicalMappedIDs;    /*0x0A */
1266         U16                     Flags;                      /*0x0C */
1267         U16                     Reserved3;                  /*0x0E */
1268         U16                     IRVolumeMappingFlags;       /*0x10 */
1269         U16                     Reserved4;                  /*0x12 */
1270         U32                     Reserved5;                  /*0x14 */
1271 } MPI2_CONFIG_PAGE_IOC_8,
1272         *PTR_MPI2_CONFIG_PAGE_IOC_8,
1273         Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1274
1275 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1276
1277 /*defines for IOC Page 8 Flags field */
1278 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1279 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1280
1281 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1282 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1283 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1284
1285 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1286 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1287
1288 /*defines for IOC Page 8 IRVolumeMappingFlags */
1289 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1290 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1291 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1292
1293
1294 /****************************************************************************
1295 *  BIOS Config Pages
1296 ****************************************************************************/
1297
1298 /*BIOS Page 1 */
1299
1300 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1301         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1302         U32                     BiosOptions;                /*0x04 */
1303         U32                     IOCSettings;                /*0x08 */
1304         U32                     Reserved1;                  /*0x0C */
1305         U32                     DeviceSettings;             /*0x10 */
1306         U16                     NumberOfDevices;            /*0x14 */
1307         U16                     UEFIVersion;                /*0x16 */
1308         U16                     IOTimeoutBlockDevicesNonRM; /*0x18 */
1309         U16                     IOTimeoutSequential;        /*0x1A */
1310         U16                     IOTimeoutOther;             /*0x1C */
1311         U16                     IOTimeoutBlockDevicesRM;    /*0x1E */
1312 } MPI2_CONFIG_PAGE_BIOS_1,
1313         *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1314         Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1315
1316 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x05)
1317
1318 /*values for BIOS Page 1 BiosOptions field */
1319 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                  (0x000000F0)
1320 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                   (0x00000000)
1321
1322 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION   (0x00000006)
1323 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII              (0x00000000)
1324 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII             (0x00000002)
1325 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII       (0x00000004)
1326
1327 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                 (0x00000001)
1328
1329 /*values for BIOS Page 1 IOCSettings field */
1330 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1331 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1332 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1333
1334 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1335 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1336 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1337 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1338
1339 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1340 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1341 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1342 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1343 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1344
1345 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1346
1347 /*values for BIOS Page 1 DeviceSettings field */
1348 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1349 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1350 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1351 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1352 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1353
1354 /*defines for BIOS Page 1 UEFIVersion field */
1355 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
1356 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
1357 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
1358 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
1359
1360
1361
1362 /*BIOS Page 2 */
1363
1364 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1365         U32         Reserved1;                              /*0x00 */
1366         U32         Reserved2;                              /*0x04 */
1367         U32         Reserved3;                              /*0x08 */
1368         U32         Reserved4;                              /*0x0C */
1369         U32         Reserved5;                              /*0x10 */
1370         U32         Reserved6;                              /*0x14 */
1371 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1372         *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1373         Mpi2BootDeviceAdapterOrder_t,
1374         *pMpi2BootDeviceAdapterOrder_t;
1375
1376 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1377         U64         SASAddress;                             /*0x00 */
1378         U8          LUN[8];                                 /*0x08 */
1379         U32         Reserved1;                              /*0x10 */
1380         U32         Reserved2;                              /*0x14 */
1381 } MPI2_BOOT_DEVICE_SAS_WWID,
1382         *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1383         Mpi2BootDeviceSasWwid_t,
1384         *pMpi2BootDeviceSasWwid_t;
1385
1386 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1387         U64         EnclosureLogicalID;                     /*0x00 */
1388         U32         Reserved1;                              /*0x08 */
1389         U32         Reserved2;                              /*0x0C */
1390         U16         SlotNumber;                             /*0x10 */
1391         U16         Reserved3;                              /*0x12 */
1392         U32         Reserved4;                              /*0x14 */
1393 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1394         *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1395         Mpi2BootDeviceEnclosureSlot_t,
1396         *pMpi2BootDeviceEnclosureSlot_t;
1397
1398 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1399         U64         DeviceName;                             /*0x00 */
1400         U8          LUN[8];                                 /*0x08 */
1401         U32         Reserved1;                              /*0x10 */
1402         U32         Reserved2;                              /*0x14 */
1403 } MPI2_BOOT_DEVICE_DEVICE_NAME,
1404         *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1405         Mpi2BootDeviceDeviceName_t,
1406         *pMpi2BootDeviceDeviceName_t;
1407
1408 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1409         MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1410         MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1411         MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1412         MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1413 } MPI2_BIOSPAGE2_BOOT_DEVICE,
1414         *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1415         Mpi2BiosPage2BootDevice_t,
1416         *pMpi2BiosPage2BootDevice_t;
1417
1418 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1419         MPI2_CONFIG_PAGE_HEADER     Header;                 /*0x00 */
1420         U32                         Reserved1;              /*0x04 */
1421         U32                         Reserved2;              /*0x08 */
1422         U32                         Reserved3;              /*0x0C */
1423         U32                         Reserved4;              /*0x10 */
1424         U32                         Reserved5;              /*0x14 */
1425         U32                         Reserved6;              /*0x18 */
1426         U8                          ReqBootDeviceForm;      /*0x1C */
1427         U8                          Reserved7;              /*0x1D */
1428         U16                         Reserved8;              /*0x1E */
1429         MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /*0x20 */
1430         U8                          ReqAltBootDeviceForm;   /*0x38 */
1431         U8                          Reserved9;              /*0x39 */
1432         U16                         Reserved10;             /*0x3A */
1433         MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /*0x3C */
1434         U8                          CurrentBootDeviceForm;  /*0x58 */
1435         U8                          Reserved11;             /*0x59 */
1436         U16                         Reserved12;             /*0x5A */
1437         MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /*0x58 */
1438 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1439         Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1440
1441 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1442
1443 /*values for BIOS Page 2 BootDeviceForm fields */
1444 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1445 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1446 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1447 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1448 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1449
1450
1451 /*BIOS Page 3 */
1452
1453 typedef struct _MPI2_ADAPTER_INFO {
1454         U8      PciBusNumber;                        /*0x00 */
1455         U8      PciDeviceAndFunctionNumber;          /*0x01 */
1456         U16     AdapterFlags;                        /*0x02 */
1457 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1458         Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1459
1460 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1461 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1462
1463 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1464         MPI2_CONFIG_PAGE_HEADER Header;              /*0x00 */
1465         U32                     GlobalFlags;         /*0x04 */
1466         U32                     BiosVersion;         /*0x08 */
1467         MPI2_ADAPTER_INFO       AdapterOrder[4];     /*0x0C */
1468         U32                     Reserved1;           /*0x1C */
1469 } MPI2_CONFIG_PAGE_BIOS_3,
1470         *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1471         Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1472
1473 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x00)
1474
1475 /*values for BIOS Page 3 GlobalFlags */
1476 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1477 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1478 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1479
1480 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1481 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1482 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1483 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1484
1485
1486 /*BIOS Page 4 */
1487
1488 /*
1489  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1490  *one and check the value returned for NumPhys at runtime.
1491  */
1492 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1493 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1494 #endif
1495
1496 typedef struct _MPI2_BIOS4_ENTRY {
1497         U64                     ReassignmentWWID;       /*0x00 */
1498         U64                     ReassignmentDeviceName; /*0x08 */
1499 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1500         Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1501
1502 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1503         MPI2_CONFIG_PAGE_HEADER Header;             /*0x00 */
1504         U8                      NumPhys;            /*0x04 */
1505         U8                      Reserved1;          /*0x05 */
1506         U16                     Reserved2;          /*0x06 */
1507         MPI2_BIOS4_ENTRY
1508                 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /*0x08 */
1509 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1510         Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1511
1512 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1513
1514
1515 /****************************************************************************
1516 *  RAID Volume Config Pages
1517 ****************************************************************************/
1518
1519 /*RAID Volume Page 0 */
1520
1521 typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1522         U8                      RAIDSetNum;        /*0x00 */
1523         U8                      PhysDiskMap;       /*0x01 */
1524         U8                      PhysDiskNum;       /*0x02 */
1525         U8                      Reserved;          /*0x03 */
1526 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1527         Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1528
1529 /*defines for the PhysDiskMap field */
1530 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1531 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1532
1533 typedef struct _MPI2_RAIDVOL0_SETTINGS {
1534         U16                     Settings;          /*0x00 */
1535         U8                      HotSparePool;      /*0x01 */
1536         U8                      Reserved;          /*0x02 */
1537 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1538         Mpi2RaidVol0Settings_t,
1539         *pMpi2RaidVol0Settings_t;
1540
1541 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1542 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1543 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1544 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1545 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1546 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1547 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1548 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1549 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1550
1551 /*RAID Volume Page 0 VolumeSettings defines */
1552 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1553 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1554
1555 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1556 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1557 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1558 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1559
1560 /*
1561  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1562  *one and check the value returned for NumPhysDisks at runtime.
1563  */
1564 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1565 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1566 #endif
1567
1568 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1569         MPI2_CONFIG_PAGE_HEADER Header;            /*0x00 */
1570         U16                     DevHandle;         /*0x04 */
1571         U8                      VolumeState;       /*0x06 */
1572         U8                      VolumeType;        /*0x07 */
1573         U32                     VolumeStatusFlags; /*0x08 */
1574         MPI2_RAIDVOL0_SETTINGS  VolumeSettings;    /*0x0C */
1575         U64                     MaxLBA;            /*0x10 */
1576         U32                     StripeSize;        /*0x18 */
1577         U16                     BlockSize;         /*0x1C */
1578         U16                     Reserved1;         /*0x1E */
1579         U8                      SupportedPhysDisks;/*0x20 */
1580         U8                      ResyncRate;        /*0x21 */
1581         U16                     DataScrubDuration; /*0x22 */
1582         U8                      NumPhysDisks;      /*0x24 */
1583         U8                      Reserved2;         /*0x25 */
1584         U8                      Reserved3;         /*0x26 */
1585         U8                      InactiveStatus;    /*0x27 */
1586         MPI2_RAIDVOL0_PHYS_DISK
1587         PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1588 } MPI2_CONFIG_PAGE_RAID_VOL_0,
1589         *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1590         Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1591
1592 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1593
1594 /*values for RAID VolumeState */
1595 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1596 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1597 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1598 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1599 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1600 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1601
1602 /*values for RAID VolumeType */
1603 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1604 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1605 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1606 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1607 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1608
1609 /*values for RAID Volume Page 0 VolumeStatusFlags field */
1610 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1611 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1612 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1613 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1614 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1615 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1616 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1617 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1618 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1619 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1620 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1621 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1622 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1623 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1624 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1625 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1626 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1627 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1628 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1629
1630 /*values for RAID Volume Page 0 SupportedPhysDisks field */
1631 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1632 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1633 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1634 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1635
1636 /*values for RAID Volume Page 0 InactiveStatus field */
1637 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1638 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1639 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1640 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1641 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1642 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1643 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1644
1645
1646 /*RAID Volume Page 1 */
1647
1648 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1649         MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1650         U16                     DevHandle;                  /*0x04 */
1651         U16                     Reserved0;                  /*0x06 */
1652         U8                      GUID[24];                   /*0x08 */
1653         U8                      Name[16];                   /*0x20 */
1654         U64                     WWID;                       /*0x30 */
1655         U32                     Reserved1;                  /*0x38 */
1656         U32                     Reserved2;                  /*0x3C */
1657 } MPI2_CONFIG_PAGE_RAID_VOL_1,
1658         *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1659         Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1660
1661 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1662
1663
1664 /****************************************************************************
1665 *  RAID Physical Disk Config Pages
1666 ****************************************************************************/
1667
1668 /*RAID Physical Disk Page 0 */
1669
1670 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1671         U16                     Reserved1;                  /*0x00 */
1672         U8                      HotSparePool;               /*0x02 */
1673         U8                      Reserved2;                  /*0x03 */
1674 } MPI2_RAIDPHYSDISK0_SETTINGS,
1675         *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1676         Mpi2RaidPhysDisk0Settings_t,
1677         *pMpi2RaidPhysDisk0Settings_t;
1678
1679 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1680
1681 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1682         U8                      VendorID[8];                /*0x00 */
1683         U8                      ProductID[16];              /*0x08 */
1684         U8                      ProductRevLevel[4];         /*0x18 */
1685         U8                      SerialNum[32];              /*0x1C */
1686 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1687         *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1688         Mpi2RaidPhysDisk0InquiryData_t,
1689         *pMpi2RaidPhysDisk0InquiryData_t;
1690
1691 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1692         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
1693         U16                             DevHandle;          /*0x04 */
1694         U8                              Reserved1;          /*0x06 */
1695         U8                              PhysDiskNum;        /*0x07 */
1696         MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;   /*0x08 */
1697         U32                             Reserved2;          /*0x0C */
1698         MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;        /*0x10 */
1699         U32                             Reserved3;          /*0x4C */
1700         U8                              PhysDiskState;      /*0x50 */
1701         U8                              OfflineReason;      /*0x51 */
1702         U8                              IncompatibleReason; /*0x52 */
1703         U8                              PhysDiskAttributes; /*0x53 */
1704         U32                             PhysDiskStatusFlags;/*0x54 */
1705         U64                             DeviceMaxLBA;       /*0x58 */
1706         U64                             HostMaxLBA;         /*0x60 */
1707         U64                             CoercedMaxLBA;      /*0x68 */
1708         U16                             BlockSize;          /*0x70 */
1709         U16                             Reserved5;          /*0x72 */
1710         U32                             Reserved6;          /*0x74 */
1711 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1712         *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1713         Mpi2RaidPhysDiskPage0_t,
1714         *pMpi2RaidPhysDiskPage0_t;
1715
1716 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1717
1718 /*PhysDiskState defines */
1719 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1720 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1721 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1722 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1723 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1724 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1725 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1726 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1727
1728 /*OfflineReason defines */
1729 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
1730 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1731 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1732 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1733 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1734 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1735 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1736
1737 /*IncompatibleReason defines */
1738 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1739 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1740 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1741 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1742 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1743 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1744 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
1745 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1746
1747 /*PhysDiskAttributes defines */
1748 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
1749 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1750 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1751
1752 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
1753 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1754 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1755
1756 /*PhysDiskStatusFlags defines */
1757 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1758 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1759 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1760 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1761 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1762 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1763 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1764 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1765
1766
1767 /*RAID Physical Disk Page 1 */
1768
1769 /*
1770  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1771  *one and check the value returned for NumPhysDiskPaths at runtime.
1772  */
1773 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1774 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
1775 #endif
1776
1777 typedef struct _MPI2_RAIDPHYSDISK1_PATH {
1778         U16             DevHandle;          /*0x00 */
1779         U16             Reserved1;          /*0x02 */
1780         U64             WWID;               /*0x04 */
1781         U64             OwnerWWID;          /*0x0C */
1782         U8              OwnerIdentifier;    /*0x14 */
1783         U8              Reserved2;          /*0x15 */
1784         U16             Flags;              /*0x16 */
1785 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
1786         Mpi2RaidPhysDisk1Path_t,
1787         *pMpi2RaidPhysDisk1Path_t;
1788
1789 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1790 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
1791 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
1792 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
1793
1794 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
1795         MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
1796         U8                              NumPhysDiskPaths;   /*0x04 */
1797         U8                              PhysDiskNum;        /*0x05 */
1798         U16                             Reserved1;          /*0x06 */
1799         U32                             Reserved2;          /*0x08 */
1800         MPI2_RAIDPHYSDISK1_PATH
1801                 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
1802 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1803         *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1804         Mpi2RaidPhysDiskPage1_t,
1805         *pMpi2RaidPhysDiskPage1_t;
1806
1807 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
1808
1809
1810 /****************************************************************************
1811 *  values for fields used by several types of SAS Config Pages
1812 ****************************************************************************/
1813
1814 /*values for NegotiatedLinkRates fields */
1815 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
1816 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
1817 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
1818 /*link rates used for Negotiated Physical and Logical Link Rate */
1819 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
1820 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
1821 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
1822 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
1823 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
1824 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
1825 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
1826 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
1827 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
1828 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
1829 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
1830
1831
1832 /*values for AttachedPhyInfo fields */
1833 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
1834 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
1835 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
1836
1837 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
1838 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
1839 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
1840 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
1841 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
1842 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
1843 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
1844 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
1845 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
1846 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
1847
1848
1849 /*values for PhyInfo fields */
1850 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
1851
1852 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
1853 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
1854 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
1855 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
1856 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
1857
1858 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
1859 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
1860 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
1861 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
1862 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
1863 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
1864
1865 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
1866 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
1867 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
1868 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
1869 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
1870 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
1871 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
1872 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
1873 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
1874 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
1875
1876 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
1877 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
1878 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
1879 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
1880
1881 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
1882 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
1883
1884 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
1885 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
1886 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
1887 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
1888
1889
1890 /*values for SAS ProgrammedLinkRate fields */
1891 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
1892 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
1893 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
1894 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
1895 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
1896 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
1897 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
1898 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
1899 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
1900 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
1901 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
1902 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
1903
1904
1905 /*values for SAS HwLinkRate fields */
1906 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
1907 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
1908 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
1909 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
1910 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
1911 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
1912 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
1913 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
1914 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
1915 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
1916
1917
1918
1919 /****************************************************************************
1920 *  SAS IO Unit Config Pages
1921 ****************************************************************************/
1922
1923 /*SAS IO Unit Page 0 */
1924
1925 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
1926         U8          Port;                   /*0x00 */
1927         U8          PortFlags;              /*0x01 */
1928         U8          PhyFlags;               /*0x02 */
1929         U8          NegotiatedLinkRate;     /*0x03 */
1930         U32         ControllerPhyDeviceInfo;/*0x04 */
1931         U16         AttachedDevHandle;      /*0x08 */
1932         U16         ControllerDevHandle;    /*0x0A */
1933         U32         DiscoveryStatus;        /*0x0C */
1934         U32         Reserved;               /*0x10 */
1935 } MPI2_SAS_IO_UNIT0_PHY_DATA,
1936         *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1937         Mpi2SasIOUnit0PhyData_t,
1938         *pMpi2SasIOUnit0PhyData_t;
1939
1940 /*
1941  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1942  *one and check the value returned for NumPhys at runtime.
1943  */
1944 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1945 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
1946 #endif
1947
1948 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
1949         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
1950         U32                                 Reserved1;/*0x08 */
1951         U8                                  NumPhys;  /*0x0C */
1952         U8                                  Reserved2;/*0x0D */
1953         U16                                 Reserved3;/*0x0E */
1954         MPI2_SAS_IO_UNIT0_PHY_DATA
1955                 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];    /*0x10 */
1956 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1957         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1958         Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
1959
1960 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
1961
1962 /*values for SAS IO Unit Page 0 PortFlags */
1963 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
1964 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
1965
1966 /*values for SAS IO Unit Page 0 PhyFlags */
1967 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
1968 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
1969
1970 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1971
1972 /*see mpi2_sas.h for values for
1973  *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1974
1975 /*values for SAS IO Unit Page 0 DiscoveryStatus */
1976 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
1977 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
1978 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
1979 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
1980 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
1981 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
1982 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
1983 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
1984 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
1985 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
1986 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
1987 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
1988 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
1989 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
1990 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
1991 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
1992 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
1993 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
1994 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
1995 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
1996
1997
1998 /*SAS IO Unit Page 1 */
1999
2000 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2001         U8          Port;                       /*0x00 */
2002         U8          PortFlags;                  /*0x01 */
2003         U8          PhyFlags;                   /*0x02 */
2004         U8          MaxMinLinkRate;             /*0x03 */
2005         U32         ControllerPhyDeviceInfo;    /*0x04 */
2006         U16         MaxTargetPortConnectTime;   /*0x08 */
2007         U16         Reserved1;                  /*0x0A */
2008 } MPI2_SAS_IO_UNIT1_PHY_DATA,
2009         *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2010         Mpi2SasIOUnit1PhyData_t,
2011         *pMpi2SasIOUnit1PhyData_t;
2012
2013 /*
2014  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2015  *one and check the value returned for NumPhys at runtime.
2016  */
2017 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2018 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
2019 #endif
2020
2021 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2022         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
2023         U16
2024                 ControlFlags;                       /*0x08 */
2025         U16
2026                 SASNarrowMaxQueueDepth;             /*0x0A */
2027         U16
2028                 AdditionalControlFlags;             /*0x0C */
2029         U16
2030                 SASWideMaxQueueDepth;               /*0x0E */
2031         U8
2032                 NumPhys;                            /*0x10 */
2033         U8
2034                 SATAMaxQDepth;                      /*0x11 */
2035         U8
2036                 ReportDeviceMissingDelay;           /*0x12 */
2037         U8
2038                 IODeviceMissingDelay;               /*0x13 */
2039         MPI2_SAS_IO_UNIT1_PHY_DATA
2040                 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /*0x14 */
2041 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2042         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2043         Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2044
2045 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
2046
2047 /*values for SAS IO Unit Page 1 ControlFlags */
2048 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
2049 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
2050 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000)
2051 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
2052
2053 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
2054 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
2055 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
2056 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
2057 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
2058
2059 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
2060 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
2061 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
2062 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
2063 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
2064 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
2065 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
2066 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001)
2067
2068 /*values for SAS IO Unit Page 1 AdditionalControlFlags */
2069 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2070 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2071 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
2072 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2073 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2074 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2075 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2076 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2077
2078 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2079 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
2080 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
2081
2082 /*values for SAS IO Unit Page 1 PortFlags */
2083 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
2084
2085 /*values for SAS IO Unit Page 1 PhyFlags */
2086 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
2087 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
2088
2089 /*values for SAS IO Unit Page 1 MaxMinLinkRate */
2090 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
2091 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
2092 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
2093 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
2094 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
2095 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
2096 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
2097 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
2098 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
2099 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
2100
2101 /*see mpi2_sas.h for values for
2102  *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2103
2104
2105 /*SAS IO Unit Page 4 */
2106
2107 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2108         U8          MaxTargetSpinup;            /*0x00 */
2109         U8          SpinupDelay;                /*0x01 */
2110         U8          SpinupFlags;                /*0x02 */
2111         U8          Reserved1;                  /*0x03 */
2112 } MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2113         *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2114         Mpi2SasIOUnit4SpinupGroup_t,
2115         *pMpi2SasIOUnit4SpinupGroup_t;
2116 /*defines for SAS IO Unit Page 4 SpinupFlags */
2117 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
2118
2119
2120 /*
2121  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2122  *one and check the value returned for NumPhys at runtime.
2123  */
2124 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2125 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
2126 #endif
2127
2128 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2129         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;/*0x00 */
2130         MPI2_SAS_IOUNIT4_SPINUP_GROUP
2131                 SpinupGroupParameters[4];       /*0x08 */
2132         U32
2133                 Reserved1;                      /*0x18 */
2134         U32
2135                 Reserved2;                      /*0x1C */
2136         U32
2137                 Reserved3;                      /*0x20 */
2138         U8
2139                 BootDeviceWaitTime;             /*0x24 */
2140         U8
2141                 Reserved4;                      /*0x25 */
2142         U16
2143                 Reserved5;                      /*0x26 */
2144         U8
2145                 NumPhys;                        /*0x28 */
2146         U8
2147                 PEInitialSpinupDelay;           /*0x29 */
2148         U8
2149                 PEReplyDelay;                   /*0x2A */
2150         U8
2151                 Flags;                          /*0x2B */
2152         U8
2153                 PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /*0x2C */
2154 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2155         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2156         Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2157
2158 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2159
2160 /*defines for Flags field */
2161 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2162
2163 /*defines for PHY field */
2164 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2165
2166
2167 /*SAS IO Unit Page 5 */
2168
2169 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2170         U8          ControlFlags;               /*0x00 */
2171         U8          PortWidthModGroup;          /*0x01 */
2172         U16         InactivityTimerExponent;    /*0x02 */
2173         U8          SATAPartialTimeout;         /*0x04 */
2174         U8          Reserved2;                  /*0x05 */
2175         U8          SATASlumberTimeout;         /*0x06 */
2176         U8          Reserved3;                  /*0x07 */
2177         U8          SASPartialTimeout;          /*0x08 */
2178         U8          Reserved4;                  /*0x09 */
2179         U8          SASSlumberTimeout;          /*0x0A */
2180         U8          Reserved5;                  /*0x0B */
2181 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2182         *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2183         Mpi2SasIOUnit5PhyPmSettings_t,
2184         *pMpi2SasIOUnit5PhyPmSettings_t;
2185
2186 /*defines for ControlFlags field */
2187 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2188 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2189 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2190 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2191
2192 /*defines for PortWidthModeGroup field */
2193 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2194
2195 /*defines for InactivityTimerExponent field */
2196 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2197 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2198 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2199 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2200 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2201 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2202 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2203 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2204
2205 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2206 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2207 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2208 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2209 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2210 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2211 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2212 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2213
2214 /*
2215  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2216  *one and check the value returned for NumPhys at runtime.
2217  */
2218 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2219 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2220 #endif
2221
2222 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2223         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
2224         U8                                  NumPhys;  /*0x08 */
2225         U8                                  Reserved1;/*0x09 */
2226         U16                                 Reserved2;/*0x0A */
2227         U32                                 Reserved3;/*0x0C */
2228         MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2229         SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2230 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2231         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2232         Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2233
2234 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2235
2236
2237 /*SAS IO Unit Page 6 */
2238
2239 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2240         U8          CurrentStatus;              /*0x00 */
2241         U8          CurrentModulation;          /*0x01 */
2242         U8          CurrentUtilization;         /*0x02 */
2243         U8          Reserved1;                  /*0x03 */
2244         U32         Reserved2;                  /*0x04 */
2245 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2246         *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2247         Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2248         *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2249
2250 /*defines for CurrentStatus field */
2251 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2252 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2253 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2254 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2255 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2256 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2257 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2258 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2259
2260 /*defines for CurrentModulation field */
2261 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2262 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2263 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2264 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2265
2266 /*
2267  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2268  *one and check the value returned for NumGroups at runtime.
2269  */
2270 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2271 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2272 #endif
2273
2274 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2275         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /*0x00 */
2276         U32                                 Reserved1;              /*0x08 */
2277         U32                                 Reserved2;              /*0x0C */
2278         U8                                  NumGroups;              /*0x10 */
2279         U8                                  Reserved3;              /*0x11 */
2280         U16                                 Reserved4;              /*0x12 */
2281         MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2282         PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2283 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2284         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2285         Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2286
2287 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2288
2289
2290 /*SAS IO Unit Page 7 */
2291
2292 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2293         U8          Flags;                      /*0x00 */
2294         U8          Reserved1;                  /*0x01 */
2295         U16         Reserved2;                  /*0x02 */
2296         U8          Threshold75Pct;             /*0x04 */
2297         U8          Threshold50Pct;             /*0x05 */
2298         U8          Threshold25Pct;             /*0x06 */
2299         U8          Reserved3;                  /*0x07 */
2300 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2301         *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2302         Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2303         *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2304
2305 /*defines for Flags field */
2306 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2307
2308
2309 /*
2310  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2311  *one and check the value returned for NumGroups at runtime.
2312  */
2313 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2314 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2315 #endif
2316
2317 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2318         MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;             /*0x00 */
2319         U8                               SamplingInterval;   /*0x08 */
2320         U8                               WindowLength;       /*0x09 */
2321         U16                              Reserved1;          /*0x0A */
2322         U32                              Reserved2;          /*0x0C */
2323         U32                              Reserved3;          /*0x10 */
2324         U8                               NumGroups;          /*0x14 */
2325         U8                               Reserved4;          /*0x15 */
2326         U16                              Reserved5;          /*0x16 */
2327         MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2328         PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2329 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2330         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2331         Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2332
2333 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2334
2335
2336 /*SAS IO Unit Page 8 */
2337
2338 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2339         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2340                 Header;                         /*0x00 */
2341         U32
2342                 Reserved1;                      /*0x08 */
2343         U32
2344                 PowerManagementCapabilities;    /*0x0C */
2345         U8
2346                 TxRxSleepStatus;                /*0x10 */
2347         U8
2348                 Reserved2;                      /*0x11 */
2349         U16
2350                 Reserved3;                      /*0x12 */
2351 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2352         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2353         Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2354
2355 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2356
2357 /*defines for PowerManagementCapabilities field */
2358 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2359 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2360 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2361 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2362 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2363 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2364 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2365 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2366 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2367 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2368
2369 /*defines for TxRxSleepStatus field */
2370 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
2371 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
2372 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
2373 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
2374
2375
2376
2377 /*SAS IO Unit Page 16 */
2378
2379 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2380         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2381                 Header;                             /*0x00 */
2382         U64
2383                 TimeStamp;                          /*0x08 */
2384         U32
2385                 Reserved1;                          /*0x10 */
2386         U32
2387                 Reserved2;                          /*0x14 */
2388         U32
2389                 FastPathPendedRequests;             /*0x18 */
2390         U32
2391                 FastPathUnPendedRequests;           /*0x1C */
2392         U32
2393                 FastPathHostRequestStarts;          /*0x20 */
2394         U32
2395                 FastPathFirmwareRequestStarts;      /*0x24 */
2396         U32
2397                 FastPathHostCompletions;            /*0x28 */
2398         U32
2399                 FastPathFirmwareCompletions;        /*0x2C */
2400         U32
2401                 NonFastPathRequestStarts;           /*0x30 */
2402         U32
2403                 NonFastPathHostCompletions;         /*0x30 */
2404 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2405         *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2406         Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2407
2408 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
2409
2410
2411 /****************************************************************************
2412 *  SAS Expander Config Pages
2413 ****************************************************************************/
2414
2415 /*SAS Expander Page 0 */
2416
2417 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2418         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2419                 Header;                     /*0x00 */
2420         U8
2421                 PhysicalPort;               /*0x08 */
2422         U8
2423                 ReportGenLength;            /*0x09 */
2424         U16
2425                 EnclosureHandle;            /*0x0A */
2426         U64
2427                 SASAddress;                 /*0x0C */
2428         U32
2429                 DiscoveryStatus;            /*0x14 */
2430         U16
2431                 DevHandle;                  /*0x18 */
2432         U16
2433                 ParentDevHandle;            /*0x1A */
2434         U16
2435                 ExpanderChangeCount;        /*0x1C */
2436         U16
2437                 ExpanderRouteIndexes;       /*0x1E */
2438         U8
2439                 NumPhys;                    /*0x20 */
2440         U8
2441                 SASLevel;                   /*0x21 */
2442         U16
2443                 Flags;                      /*0x22 */
2444         U16
2445                 STPBusInactivityTimeLimit;  /*0x24 */
2446         U16
2447                 STPMaxConnectTimeLimit;     /*0x26 */
2448         U16
2449                 STP_SMP_NexusLossTime;      /*0x28 */
2450         U16
2451                 MaxNumRoutedSasAddresses;   /*0x2A */
2452         U64
2453                 ActiveZoneManagerSASAddress;/*0x2C */
2454         U16
2455                 ZoneLockInactivityLimit;    /*0x34 */
2456         U16
2457                 Reserved1;                  /*0x36 */
2458         U8
2459                 TimeToReducedFunc;          /*0x38 */
2460         U8
2461                 InitialTimeToReducedFunc;   /*0x39 */
2462         U8
2463                 MaxReducedFuncTime;         /*0x3A */
2464         U8
2465                 Reserved2;                  /*0x3B */
2466 } MPI2_CONFIG_PAGE_EXPANDER_0,
2467         *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2468         Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2469
2470 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2471
2472 /*values for SAS Expander Page 0 DiscoveryStatus field */
2473 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2474 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2475 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2476 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2477 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2478 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2479 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2480 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2481 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2482 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2483 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2484 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2485 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2486 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2487 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2488 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2489 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2490 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2491 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2492 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2493
2494 /*values for SAS Expander Page 0 Flags field */
2495 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2496 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2497 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2498 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2499 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2500 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2501 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2502 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2503 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2504 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2505 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2506
2507
2508 /*SAS Expander Page 1 */
2509
2510 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2511         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2512                 Header;                     /*0x00 */
2513         U8
2514                 PhysicalPort;               /*0x08 */
2515         U8
2516                 Reserved1;                  /*0x09 */
2517         U16
2518                 Reserved2;                  /*0x0A */
2519         U8
2520                 NumPhys;                    /*0x0C */
2521         U8
2522                 Phy;                        /*0x0D */
2523         U16
2524                 NumTableEntriesProgrammed;  /*0x0E */
2525         U8
2526                 ProgrammedLinkRate;         /*0x10 */
2527         U8
2528                 HwLinkRate;                 /*0x11 */
2529         U16
2530                 AttachedDevHandle;          /*0x12 */
2531         U32
2532                 PhyInfo;                    /*0x14 */
2533         U32
2534                 AttachedDeviceInfo;         /*0x18 */
2535         U16
2536                 ExpanderDevHandle;          /*0x1C */
2537         U8
2538                 ChangeCount;                /*0x1E */
2539         U8
2540                 NegotiatedLinkRate;         /*0x1F */
2541         U8
2542                 PhyIdentifier;              /*0x20 */
2543         U8
2544                 AttachedPhyIdentifier;      /*0x21 */
2545         U8
2546                 Reserved3;                  /*0x22 */
2547         U8
2548                 DiscoveryInfo;              /*0x23 */
2549         U32
2550                 AttachedPhyInfo;            /*0x24 */
2551         U8
2552                 ZoneGroup;                  /*0x28 */
2553         U8
2554                 SelfConfigStatus;           /*0x29 */
2555         U16
2556                 Reserved4;                  /*0x2A */
2557 } MPI2_CONFIG_PAGE_EXPANDER_1,
2558         *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2559         Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2560
2561 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2562
2563 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2564
2565 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2566
2567 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2568
2569 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2570  *used for the AttachedDeviceInfo field */
2571
2572 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2573
2574 /*values for SAS Expander Page 1 DiscoveryInfo field */
2575 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2576 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2577 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2578
2579 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2580
2581
2582 /****************************************************************************
2583 *  SAS Device Config Pages
2584 ****************************************************************************/
2585
2586 /*SAS Device Page 0 */
2587
2588 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2589         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2590                 Header;                 /*0x00 */
2591         U16
2592                 Slot;                   /*0x08 */
2593         U16
2594                 EnclosureHandle;        /*0x0A */
2595         U64
2596                 SASAddress;             /*0x0C */
2597         U16
2598                 ParentDevHandle;        /*0x14 */
2599         U8
2600                 PhyNum;                 /*0x16 */
2601         U8
2602                 AccessStatus;           /*0x17 */
2603         U16
2604                 DevHandle;              /*0x18 */
2605         U8
2606                 AttachedPhyIdentifier;  /*0x1A */
2607         U8
2608                 ZoneGroup;              /*0x1B */
2609         U32
2610                 DeviceInfo;             /*0x1C */
2611         U16
2612                 Flags;                  /*0x20 */
2613         U8
2614                 PhysicalPort;           /*0x22 */
2615         U8
2616                 MaxPortConnections;     /*0x23 */
2617         U64
2618                 DeviceName;             /*0x24 */
2619         U8
2620                 PortGroups;             /*0x2C */
2621         U8
2622                 DmaGroup;               /*0x2D */
2623         U8
2624                 ControlGroup;           /*0x2E */
2625         U8
2626                 Reserved1;              /*0x2F */
2627         U32
2628                 Reserved2;              /*0x30 */
2629         U32
2630                 Reserved3;              /*0x34 */
2631 } MPI2_CONFIG_PAGE_SAS_DEV_0,
2632         *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2633         Mpi2SasDevicePage0_t,
2634         *pMpi2SasDevicePage0_t;
2635
2636 #define MPI2_SASDEVICE0_PAGEVERSION         (0x08)
2637
2638 /*values for SAS Device Page 0 AccessStatus field */
2639 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2640 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2641 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2642 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2643 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2644 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2645 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2646 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2647 /*specific values for SATA Init failures */
2648 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2649 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2650 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2651 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2652 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2653 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2654 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2655 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2656 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2657 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2658 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2659
2660 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2661
2662 /*values for SAS Device Page 0 Flags field */
2663 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2664 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
2665 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
2666 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2667 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2668 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2669 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2670 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2671 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2672 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2673 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2674 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2675 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2676 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2677
2678
2679 /*SAS Device Page 1 */
2680
2681 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2682         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2683                 Header;                 /*0x00 */
2684         U32
2685                 Reserved1;              /*0x08 */
2686         U64
2687                 SASAddress;             /*0x0C */
2688         U32
2689                 Reserved2;              /*0x14 */
2690         U16
2691                 DevHandle;              /*0x18 */
2692         U16
2693                 Reserved3;              /*0x1A */
2694         U8
2695                 InitialRegDeviceFIS[20];/*0x1C */
2696 } MPI2_CONFIG_PAGE_SAS_DEV_1,
2697         *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2698         Mpi2SasDevicePage1_t,
2699         *pMpi2SasDevicePage1_t;
2700
2701 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2702
2703
2704 /****************************************************************************
2705 *  SAS PHY Config Pages
2706 ****************************************************************************/
2707
2708 /*SAS PHY Page 0 */
2709
2710 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2711         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2712                 Header;                 /*0x00 */
2713         U16
2714                 OwnerDevHandle;         /*0x08 */
2715         U16
2716                 Reserved1;              /*0x0A */
2717         U16
2718                 AttachedDevHandle;      /*0x0C */
2719         U8
2720                 AttachedPhyIdentifier;  /*0x0E */
2721         U8
2722                 Reserved2;              /*0x0F */
2723         U32
2724                 AttachedPhyInfo;        /*0x10 */
2725         U8
2726                 ProgrammedLinkRate;     /*0x14 */
2727         U8
2728                 HwLinkRate;             /*0x15 */
2729         U8
2730                 ChangeCount;            /*0x16 */
2731         U8
2732                 Flags;                  /*0x17 */
2733         U32
2734                 PhyInfo;                /*0x18 */
2735         U8
2736                 NegotiatedLinkRate;     /*0x1C */
2737         U8
2738                 Reserved3;              /*0x1D */
2739         U16
2740                 Reserved4;              /*0x1E */
2741 } MPI2_CONFIG_PAGE_SAS_PHY_0,
2742         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2743         Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2744
2745 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
2746
2747 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2748
2749 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2750
2751 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2752
2753 /*values for SAS PHY Page 0 Flags field */
2754 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2755
2756 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2757
2758 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2759
2760
2761 /*SAS PHY Page 1 */
2762
2763 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
2764         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2765                 Header;                     /*0x00 */
2766         U32
2767                 Reserved1;                  /*0x08 */
2768         U32
2769                 InvalidDwordCount;          /*0x0C */
2770         U32
2771                 RunningDisparityErrorCount; /*0x10 */
2772         U32
2773                 LossDwordSynchCount;        /*0x14 */
2774         U32
2775                 PhyResetProblemCount;       /*0x18 */
2776 } MPI2_CONFIG_PAGE_SAS_PHY_1,
2777         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2778         Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
2779
2780 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
2781
2782
2783 /*SAS PHY Page 2 */
2784
2785 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2786         U8          PhyEventCode;       /*0x00 */
2787         U8          Reserved1;          /*0x01 */
2788         U16         Reserved2;          /*0x02 */
2789         U32         PhyEventInfo;       /*0x04 */
2790 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
2791         Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
2792
2793 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2794
2795
2796 /*
2797  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2798  *one and check the value returned for NumPhyEvents at runtime.
2799  */
2800 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2801 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
2802 #endif
2803
2804 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2805         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2806                 Header;                     /*0x00 */
2807         U32
2808                 Reserved1;                  /*0x08 */
2809         U8
2810                 NumPhyEvents;               /*0x0C */
2811         U8
2812                 Reserved2;                  /*0x0D */
2813         U16
2814                 Reserved3;                  /*0x0E */
2815         MPI2_SASPHY2_PHY_EVENT
2816                 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
2817 } MPI2_CONFIG_PAGE_SAS_PHY_2,
2818         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2819         Mpi2SasPhyPage2_t,
2820         *pMpi2SasPhyPage2_t;
2821
2822 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
2823
2824
2825 /*SAS PHY Page 3 */
2826
2827 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2828         U8          PhyEventCode;       /*0x00 */
2829         U8          Reserved1;          /*0x01 */
2830         U16         Reserved2;          /*0x02 */
2831         U8          CounterType;        /*0x04 */
2832         U8          ThresholdWindow;    /*0x05 */
2833         U8          TimeUnits;          /*0x06 */
2834         U8          Reserved3;          /*0x07 */
2835         U32         EventThreshold;     /*0x08 */
2836         U16         ThresholdFlags;     /*0x0C */
2837         U16         Reserved4;          /*0x0E */
2838 } MPI2_SASPHY3_PHY_EVENT_CONFIG,
2839         *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2840         Mpi2SasPhy3PhyEventConfig_t,
2841         *pMpi2SasPhy3PhyEventConfig_t;
2842
2843 /*values for PhyEventCode field */
2844 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
2845 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
2846 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
2847 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
2848 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
2849 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
2850 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
2851 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
2852 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
2853 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
2854 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
2855 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
2856 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
2857 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
2858 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
2859 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
2860 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
2861 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
2862 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
2863 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
2864 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
2865 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
2866 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
2867 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
2868 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
2869 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
2870 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
2871 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
2872 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
2873 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
2874 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
2875 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
2876 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
2877 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
2878 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
2879 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
2880 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
2881
2882 /*values for the CounterType field */
2883 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
2884 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
2885 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
2886
2887 /*values for the TimeUnits field */
2888 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
2889 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
2890 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
2891 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
2892
2893 /*values for the ThresholdFlags field */
2894 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
2895 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
2896
2897 /*
2898  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2899  *one and check the value returned for NumPhyEvents at runtime.
2900  */
2901 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2902 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
2903 #endif
2904
2905 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2906         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2907                 Header;                     /*0x00 */
2908         U32
2909                 Reserved1;                  /*0x08 */
2910         U8
2911                 NumPhyEvents;               /*0x0C */
2912         U8
2913                 Reserved2;                  /*0x0D */
2914         U16
2915                 Reserved3;                  /*0x0E */
2916         MPI2_SASPHY3_PHY_EVENT_CONFIG
2917                 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
2918 } MPI2_CONFIG_PAGE_SAS_PHY_3,
2919         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2920         Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
2921
2922 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
2923
2924
2925 /*SAS PHY Page 4 */
2926
2927 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2928         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2929                 Header;                     /*0x00 */
2930         U16
2931                 Reserved1;                  /*0x08 */
2932         U8
2933                 Reserved2;                  /*0x0A */
2934         U8
2935                 Flags;                      /*0x0B */
2936         U8
2937                 InitialFrame[28];           /*0x0C */
2938 } MPI2_CONFIG_PAGE_SAS_PHY_4,
2939         *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2940         Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
2941
2942 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
2943
2944 /*values for the Flags field */
2945 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
2946 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
2947
2948
2949
2950
2951 /****************************************************************************
2952 *  SAS Port Config Pages
2953 ****************************************************************************/
2954
2955 /*SAS Port Page 0 */
2956
2957 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
2958         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2959                 Header;                     /*0x00 */
2960         U8
2961                 PortNumber;                 /*0x08 */
2962         U8
2963                 PhysicalPort;               /*0x09 */
2964         U8
2965                 PortWidth;                  /*0x0A */
2966         U8
2967                 PhysicalPortWidth;          /*0x0B */
2968         U8
2969                 ZoneGroup;                  /*0x0C */
2970         U8
2971                 Reserved1;                  /*0x0D */
2972         U16
2973                 Reserved2;                  /*0x0E */
2974         U64
2975                 SASAddress;                 /*0x10 */
2976         U32
2977                 DeviceInfo;                 /*0x18 */
2978         U32
2979                 Reserved3;                  /*0x1C */
2980         U32
2981                 Reserved4;                  /*0x20 */
2982 } MPI2_CONFIG_PAGE_SAS_PORT_0,
2983         *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2984         Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
2985
2986 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
2987
2988 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2989
2990
2991 /****************************************************************************
2992 *  SAS Enclosure Config Pages
2993 ****************************************************************************/
2994
2995 /*SAS Enclosure Page 0 */
2996
2997 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
2998         MPI2_CONFIG_EXTENDED_PAGE_HEADER
2999                 Header;                     /*0x00 */
3000         U32
3001                 Reserved1;                  /*0x08 */
3002         U64
3003                 EnclosureLogicalID;         /*0x0C */
3004         U16
3005                 Flags;                      /*0x14 */
3006         U16
3007                 EnclosureHandle;            /*0x16 */
3008         U16
3009                 NumSlots;                   /*0x18 */
3010         U16
3011                 StartSlot;                  /*0x1A */
3012         U16
3013                 Reserved2;                  /*0x1C */
3014         U16
3015                 SEPDevHandle;               /*0x1E */
3016         U32
3017                 Reserved3;                  /*0x20 */
3018         U32
3019                 Reserved4;                  /*0x24 */
3020 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3021         *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3022         Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t;
3023
3024 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x03)
3025
3026 /*values for SAS Enclosure Page 0 Flags field */
3027 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
3028 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
3029 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
3030 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
3031 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
3032 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
3033 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
3034
3035
3036 /****************************************************************************
3037 *  Log Config Page
3038 ****************************************************************************/
3039
3040 /*Log Page 0 */
3041
3042 /*
3043  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3044  *one and check the value returned for NumLogEntries at runtime.
3045  */
3046 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3047 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
3048 #endif
3049
3050 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
3051
3052 typedef struct _MPI2_LOG_0_ENTRY {
3053         U64         TimeStamp;                      /*0x00 */
3054         U32         Reserved1;                      /*0x08 */
3055         U16         LogSequence;                    /*0x0C */
3056         U16         LogEntryQualifier;              /*0x0E */
3057         U8          VP_ID;                          /*0x10 */
3058         U8          VF_ID;                          /*0x11 */
3059         U16         Reserved2;                      /*0x12 */
3060         U8
3061                 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3062 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3063         Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3064
3065 /*values for Log Page 0 LogEntry LogEntryQualifier field */
3066 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
3067 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
3068 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
3069 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
3070 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
3071
3072 typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3073         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;       /*0x00 */
3074         U32                                 Reserved1;    /*0x08 */
3075         U32                                 Reserved2;    /*0x0C */
3076         U16                                 NumLogEntries;/*0x10 */
3077         U16                                 Reserved3;    /*0x12 */
3078         MPI2_LOG_0_ENTRY
3079                 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3080 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3081         Mpi2LogPage0_t, *pMpi2LogPage0_t;
3082
3083 #define MPI2_LOG_0_PAGEVERSION              (0x02)
3084
3085
3086 /****************************************************************************
3087 *  RAID Config Page
3088 ****************************************************************************/
3089
3090 /*RAID Page 0 */
3091
3092 /*
3093  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3094  *one and check the value returned for NumElements at runtime.
3095  */
3096 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3097 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
3098 #endif
3099
3100 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3101         U16                     ElementFlags;             /*0x00 */
3102         U16                     VolDevHandle;             /*0x02 */
3103         U8                      HotSparePool;             /*0x04 */
3104         U8                      PhysDiskNum;              /*0x05 */
3105         U16                     PhysDiskDevHandle;        /*0x06 */
3106 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3107         *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3108         Mpi2RaidConfig0ConfigElement_t,
3109         *pMpi2RaidConfig0ConfigElement_t;
3110
3111 /*values for the ElementFlags field */
3112 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
3113 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
3114 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
3115 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
3116 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
3117
3118
3119 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3120         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;         /*0x00 */
3121         U8                                  NumHotSpares;   /*0x08 */
3122         U8                                  NumPhysDisks;   /*0x09 */
3123         U8                                  NumVolumes;     /*0x0A */
3124         U8                                  ConfigNum;      /*0x0B */
3125         U32                                 Flags;          /*0x0C */
3126         U8                                  ConfigGUID[24]; /*0x10 */
3127         U32                                 Reserved1;      /*0x28 */
3128         U8                                  NumElements;    /*0x2C */
3129         U8                                  Reserved2;      /*0x2D */
3130         U16                                 Reserved3;      /*0x2E */
3131         MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3132                 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3133 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3134         *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3135         Mpi2RaidConfigurationPage0_t,
3136         *pMpi2RaidConfigurationPage0_t;
3137
3138 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
3139
3140 /*values for RAID Configuration Page 0 Flags field */
3141 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
3142
3143
3144 /****************************************************************************
3145 *  Driver Persistent Mapping Config Pages
3146 ****************************************************************************/
3147
3148 /*Driver Persistent Mapping Page 0 */
3149
3150 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3151         U64     PhysicalIdentifier;         /*0x00 */
3152         U16     MappingInformation;         /*0x08 */
3153         U16     DeviceIndex;                /*0x0A */
3154         U32     PhysicalBitsMapping;        /*0x0C */
3155         U32     Reserved1;                  /*0x10 */
3156 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3157         *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3158         Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3159
3160 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3161         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
3162         MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;  /*0x08 */
3163 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3164         *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3165         Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3166
3167 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
3168
3169 /*values for Driver Persistent Mapping Page 0 MappingInformation field */
3170 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
3171 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
3172 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
3173
3174
3175 /****************************************************************************
3176 *  Ethernet Config Pages
3177 ****************************************************************************/
3178
3179 /*Ethernet Page 0 */
3180
3181 /*IP address (union of IPv4 and IPv6) */
3182 typedef union _MPI2_ETHERNET_IP_ADDR {
3183         U32     IPv4Addr;
3184         U32     IPv6Addr[4];
3185 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3186         Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3187
3188 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
3189
3190 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3191         MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;          /*0x00 */
3192         U8                                  NumInterfaces;   /*0x08 */
3193         U8                                  Reserved0;       /*0x09 */
3194         U16                                 Reserved1;       /*0x0A */
3195         U32                                 Status;          /*0x0C */
3196         U8                                  MediaState;      /*0x10 */
3197         U8                                  Reserved2;       /*0x11 */
3198         U16                                 Reserved3;       /*0x12 */
3199         U8                                  MacAddress[6];   /*0x14 */
3200         U8                                  Reserved4;       /*0x1A */
3201         U8                                  Reserved5;       /*0x1B */
3202         MPI2_ETHERNET_IP_ADDR               IpAddress;       /*0x1C */
3203         MPI2_ETHERNET_IP_ADDR               SubnetMask;      /*0x2C */
3204         MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;/*0x3C */
3205         MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;   /*0x4C */
3206         MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;   /*0x5C */
3207         MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;   /*0x6C */
3208         U8
3209                 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3210 } MPI2_CONFIG_PAGE_ETHERNET_0,
3211         *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3212         Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3213
3214 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
3215
3216 /*values for Ethernet Page 0 Status field */
3217 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
3218 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
3219 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
3220 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
3221 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
3222 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
3223 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
3224 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
3225 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
3226 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
3227 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
3228 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
3229
3230 /*values for Ethernet Page 0 MediaState field */
3231 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
3232 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
3233 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
3234
3235 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
3236 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
3237 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
3238 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
3239 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
3240
3241
3242 /*Ethernet Page 1 */
3243
3244 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3245         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3246                 Header;                 /*0x00 */
3247         U32
3248                 Reserved0;              /*0x08 */
3249         U32
3250                 Flags;                  /*0x0C */
3251         U8
3252                 MediaState;             /*0x10 */
3253         U8
3254                 Reserved1;              /*0x11 */
3255         U16
3256                 Reserved2;              /*0x12 */
3257         U8
3258                 MacAddress[6];          /*0x14 */
3259         U8
3260                 Reserved3;              /*0x1A */
3261         U8
3262                 Reserved4;              /*0x1B */
3263         MPI2_ETHERNET_IP_ADDR
3264                 StaticIpAddress;        /*0x1C */
3265         MPI2_ETHERNET_IP_ADDR
3266                 StaticSubnetMask;       /*0x2C */
3267         MPI2_ETHERNET_IP_ADDR
3268                 StaticGatewayIpAddress; /*0x3C */
3269         MPI2_ETHERNET_IP_ADDR
3270                 StaticDNS1IpAddress;    /*0x4C */
3271         MPI2_ETHERNET_IP_ADDR
3272                 StaticDNS2IpAddress;    /*0x5C */
3273         U32
3274                 Reserved5;              /*0x6C */
3275         U32
3276                 Reserved6;              /*0x70 */
3277         U32
3278                 Reserved7;              /*0x74 */
3279         U32
3280                 Reserved8;              /*0x78 */
3281         U8
3282                 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3283 } MPI2_CONFIG_PAGE_ETHERNET_1,
3284         *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3285         Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3286
3287 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
3288
3289 /*values for Ethernet Page 1 Flags field */
3290 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
3291 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
3292 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
3293 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
3294 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
3295 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
3296 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
3297 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
3298 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
3299
3300 /*values for Ethernet Page 1 MediaState field */
3301 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
3302 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
3303 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
3304
3305 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
3306 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
3307 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
3308 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
3309 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
3310
3311
3312 /****************************************************************************
3313 *  Extended Manufacturing Config Pages
3314 ****************************************************************************/
3315
3316 /*
3317  *Generic structure to use for product-specific extended manufacturing pages
3318  *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3319  *Page 60).
3320  */
3321
3322 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3323         MPI2_CONFIG_EXTENDED_PAGE_HEADER
3324                 Header;                 /*0x00 */
3325         U32
3326                 ProductSpecificInfo;    /*0x08 */
3327 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3328         *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3329         Mpi2ExtManufacturingPagePS_t,
3330         *pMpi2ExtManufacturingPagePS_t;
3331
3332 /*PageVersion should be provided by product-specific code */
3333
3334 #endif
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