drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <[email protected]>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <[email protected]>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL8723E_PWRSEQ_H__
  31 #define __RTL8723E_PWRSEQ_H__
  32
  33 /*
  34         Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
  35         There are 6 HW Power States:
  36         0: POFF--Power Off
  37         1: PDN--Power Down
  38         2: CARDEMU--Card Emulation
  39         3: ACT--Active Mode
  40         4: LPS--Low Power State
  41         5: SUS--Suspend
  42
  43         The transision from different states are defined below
  44         TRANS_CARDEMU_TO_ACT
  45         TRANS_ACT_TO_CARDEMU
  46         TRANS_CARDEMU_TO_SUS
  47         TRANS_SUS_TO_CARDEMU
  48         TRANS_CARDEMU_TO_PDN
  49         TRANS_ACT_TO_LPS
  50         TRANS_LPS_TO_ACT
  51
  52         TRANS_END
  53 */
  54
  55 #define RTL8723A_TRANS_CARDEMU_TO_ACT_STPS      10
  56 #define RTL8723A_TRANS_ACT_TO_CARDEMU_STPS      10
  57 #define RTL8723A_TRANS_CARDEMU_TO_SUS_STPS      10
  58 #define RTL8723A_TRANS_SUS_TO_CARDEMU_STPS      10
  59 #define RTL8723A_TRANS_CARDEMU_TO_PDN_STPS      10
  60 #define RTL8723A_TRANS_PDN_TO_CARDEMU_STPS      10
  61 #define RTL8723A_TRANS_ACT_TO_LPS_STPS          15
  62 #define RTL8723A_TRANS_LPS_TO_ACT_STPS          15
  63 #define RTL8723A_TRANS_END_STPS                 1
  64
  65
  66 #define RTL8723A_TRANS_CARDEMU_TO_ACT                                   \
  67         /* format */                                                    \
  68         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
  69          *  comments here*/                                             \
  70         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  71                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},            \
  72                 /* disable SW LPS 0x04[10]=0*/                          \
  73         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  74                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},     \
  75                 /* wait till 0x04[17] = 1    power ready*/              \
  76         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  77                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},       \
  78                 /* release WLON reset  0x04[16]=1*/                     \
  79         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  80                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},            \
  81                 /* disable HWPDN 0x04[15]=0*/                           \
  82         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  83                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},   \
  84         /* disable WL suspend*/                                         \
  85         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  86                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},       \
  87                 /* polling until return 0*/                             \
  88         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  89                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}
  90
  91 #define RTL8723A_TRANS_ACT_TO_CARDEMU                                   \
  92         /* format */                                                    \
  93         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
  94          *  comments here*/                                             \
  95         {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  96                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},              \
  97                 /*0x1F[7:0] = 0 turn off RF*/                           \
  98         {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  99                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},            \
 100         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 101                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},       \
 102         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 103                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}
 104
 105 #define RTL8723A_TRANS_CARDEMU_TO_SUS                                   \
 106         /* format */                                                    \
 107         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
 108          *  comments here*/                                             \
 109         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 110                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3),         \
 111                 (BIT(4)|BIT(3))},                                       \
 112                 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/      \
 113         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK |   \
 114                 PWR_INTF_SDIO_MSK,                                      \
 115                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\
 116                  /*0x04[12:11] = 2b'01 enable WL suspend*/              \
 117         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 118                 PWR_BASEADDR_MAC,                                       \
 119                 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)},           \
 120                  /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/     \
 121         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 122                 PWR_BASEADDR_SDIO,                                      \
 123                 PWR_CMD_WRITE, BIT(0), BIT(0)},                         \
 124                 /*Set SDIO suspend local register*/                     \
 125         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 126                 PWR_BASEADDR_SDIO,                                      \
 127                 PWR_CMD_POLLING, BIT(1), 0}                             \
 128                 /*wait power state to suspend*/
 129
 130 #define RTL8723A_TRANS_SUS_TO_CARDEMU                                   \
 131         /* format */                                                    \
 132         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 133         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 134                 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},           \
 135                 /*Set SDIO suspend local register*/                     \
 136         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 137                 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},    \
 138                 /*wait power state to suspend*/                         \
 139         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 140                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}      \
 141                 /*0x04[12:11] = 2b'01enable WL suspend*/
 142
 143 #define RTL8723A_TRANS_CARDEMU_TO_CARDDIS                               \
 144         /* format */                                                    \
 145         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 146         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 147         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 148                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\
 149                 /*0x04[12:11] = 2b'01 enable WL suspend*/               \
 150         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 151                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)},       \
 152                 /*0x04[10] = 1, enable SW LPS*/                         \
 153         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 154                 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},      \
 155                 /*Set SDIO suspend local register*/                     \
 156         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 157                 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}          \
 158                 /*wait power state to suspend*/
 159
 160 #define RTL8723A_TRANS_CARDDIS_TO_CARDEMU                               \
 161         /* format */                                                    \
 162         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 163         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 164                 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},           \
 165                 /*Set SDIO suspend local register*/                     \
 166         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 167                 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},    \
 168                 /*wait power state to suspend*/                         \
 169         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 170                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},     \
 171                 /*0x04[12:11] = 2b'00enable WL suspend*/                \
 172         {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 173                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}               \
 174                 /*PCIe DMA start*/
 175
 176 #define RTL8723A_TRANS_CARDEMU_TO_PDN                                   \
 177         /* format */                                                    \
 178         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 179         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 180                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},            \
 181                 /* 0x04[16] = 0*/\
 182         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 183                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}        \
 184                 /* 0x04[15] = 1*/
 185
 186 #define RTL8723A_TRANS_PDN_TO_CARDEMU                                   \
 187         /* format */                                                    \
 188         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 189         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 190                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}             \
 191                 /* 0x04[15] = 0*/
 192
 193 #define RTL8723A_TRANS_ACT_TO_LPS                                       \
 194         /* format */                                                    \
 195         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 196         {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 197                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},           \
 198                 /*PCIe DMA stop*/                                       \
 199         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 200                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},           \
 201                 /*Tx Pause*/                                            \
 202         {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 203                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 204                 /*Should be zero if no packet is transmitting*/         \
 205         {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 206                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 207                 /*Should be zero if no packet is transmitting*/         \
 208         {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 209                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 210                 /*Should be zero if no packet is transmitting*/         \
 211         {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 212                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},            \
 213                 /*Should be zero if no packet is transmitting*/         \
 214         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 215                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},            \
 216                 /*CCK and OFDM are disabled,and clock are gated*/       \
 217         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 218                 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},   \
 219                 /*Delay 1us*/                                           \
 220         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 221                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},            \
 222                 /*Whole BB is reset*/                                   \
 223         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 224                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},           \
 225                 /*Reset MAC TRX*/                                       \
 226         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 227                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},            \
 228                 /*check if removed later*/                              \
 229         {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 230                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}        \
 231                 /*Respond TxOK to scheduler*/
 232
 233 #define RTL8723A_TRANS_LPS_TO_ACT                                       \
 234         /* format */                                                    \
 235         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 236         {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 237                  PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},         \
 238                  /*SDIO RPWM*/                                          \
 239         {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 240                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},           \
 241                 /*USB RPWM*/                                            \
 242         {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 243                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},           \
 244                 /*PCIe RPWM*/                                           \
 245         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 246                  PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},  \
 247                 /*Delay*/                                               \
 248         {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 249                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},            \
 250                 /* 0x08[4] = 0 switch TSF to 40M*/                      \
 251         {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 252                 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},          \
 253                 /*Polling 0x109[7]=0  TSF in 40M*/                      \
 254         {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 255                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0},     \
 256                 /*.     0x29[7:6] = 2b'00        enable BB clock*/      \
 257         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 258                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},       \
 259                 /*.     0x101[1] = 1*/                                  \
 260         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 261                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},           \
 262                 /* 0x100[7:0] = 0xFF enable WMAC TRX*/                  \
 263         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 264                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0),         \
 265                 BIT(1)|BIT(0)},                                         \
 266                 /* 0x02[1:0] = 2b'11  enable BB macro*/                 \
 267         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 268                 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}               \
 269                 /*.     0x522 = 0*/
 270
 271 #define RTL8723A_TRANS_END                                              \
 272         /* format */                                                    \
 273         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 274         {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 275         0, PWR_CMD_END, 0, 0}
 276
 277 extern struct
 278 wlan_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STPS
 279                                     + RTL8723A_TRANS_END_STPS];
 280 extern struct
 281 wlan_pwr_cfg rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 282                                      + RTL8723A_TRANS_END_STPS];
 283 extern struct
 284 wlan_pwr_cfg rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 285                                         + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
 286                                         + RTL8723A_TRANS_END_STPS];
 287 extern struct
 288 wlan_pwr_cfg rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 289                                        + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
 290                                        + RTL8723A_TRANS_END_STPS];
 291 extern struct
 292 wlan_pwr_cfg rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 293                                    + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
 294                                    + RTL8723A_TRANS_END_STPS];
 295 extern struct
 296 wlan_pwr_cfg rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 297                                   + RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
 298                                   + RTL8723A_TRANS_END_STPS];
 299 extern struct
 300 wlan_pwr_cfg rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
 301                                  + RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
 302                                  + RTL8723A_TRANS_END_STPS];
 303 extern struct
 304 wlan_pwr_cfg rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STPS
 305                                      + RTL8723A_TRANS_END_STPS];
 306 extern struct
 307 wlan_pwr_cfg rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STPS
 308                                      + RTL8723A_TRANS_END_STPS];
 309
 310 /* RTL8723 Power Configuration CMDs for PCIe interface */
 311 #define Rtl8723_NIC_PWR_ON_FLOW         rtl8723A_power_on_flow
 312 #define Rtl8723_NIC_RF_OFF_FLOW         rtl8723A_radio_off_flow
 313 #define Rtl8723_NIC_DISABLE_FLOW        rtl8723A_card_disable_flow
 314 #define Rtl8723_NIC_ENABLE_FLOW         rtl8723A_card_enable_flow
 315 #define Rtl8723_NIC_SUSPEND_FLOW        rtl8723A_suspend_flow
 316 #define Rtl8723_NIC_RESUME_FLOW         rtl8723A_resume_flow
 317 #define Rtl8723_NIC_PDN_FLOW            rtl8723A_hwpdn_flow
 318 #define Rtl8723_NIC_LPS_ENTER_FLOW      rtl8723A_enter_lps_flow
 319 #define Rtl8723_NIC_LPS_LEAVE_FLOW      rtl8723A_leave_lps_flow
 320
 321 #endif