drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <[email protected]>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <[email protected]>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL8723E_PWRSEQ_H__
  31 #define __RTL8723E_PWRSEQ_H__
  32
  33 /*
  34         Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
  35         There are 6 HW Power States:
  36         0: POFF--Power Off
  37         1: PDN--Power Down
  38         2: CARDEMU--Card Emulation
  39         3: ACT--Active Mode
  40         4: LPS--Low Power State
  41         5: SUS--Suspend
  42
  43         The transision from different states are defined below
  44         TRANS_CARDEMU_TO_ACT
  45         TRANS_ACT_TO_CARDEMU
  46         TRANS_CARDEMU_TO_SUS
  47         TRANS_SUS_TO_CARDEMU
  48         TRANS_CARDEMU_TO_PDN
  49         TRANS_ACT_TO_LPS
  50         TRANS_LPS_TO_ACT
  51
  52         TRANS_END
  53         PWR SEQ Version: rtl8188e_PwrSeq_V09.h
  54 */
  55
  56 #define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS     10
  57 #define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS     10
  58 #define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS     10
  59 #define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS     10
  60 #define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS     10
  61 #define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS     10
  62 #define RTL8188E_TRANS_ACT_TO_LPS_STEPS         15
  63 #define RTL8188E_TRANS_LPS_TO_ACT_STEPS         15
  64 #define RTL8188E_TRANS_END_STEPS                1
  65
  66
  67 #define RTL8188E_TRANS_CARDEMU_TO_ACT                                   \
  68         /* format */                                                    \
  69         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
  70         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  71         /* wait till 0x04[17] = 1    power ready*/                      \
  72         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},             \
  73         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  74         /* 0x02[1:0] = 0        reset BB*/                              \
  75         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0},             \
  76         {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  77         /*0x24[23] = 2b'01 schmit trigger */                            \
  78         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
  79         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  80         /* 0x04[15] = 0 disable HWPDN (control by DRV)*/                \
  81         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},                    \
  82         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  83         /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
  84         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0},             \
  85         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  86         /*0x04[8] = 1 polling until return 0*/                          \
  87         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},               \
  88         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  89         /*wait till 0x04[8] = 0*/                                       \
  90         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},                  \
  91         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  92         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*LDO normal mode*/\
  93         {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
  94         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO Driving*/\
  95
  96 #define RTL8188E_TRANS_ACT_TO_CARDEMU                                   \
  97         /* format */                                                    \
  98         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
  99         {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 100         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\
 101         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 102         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*LDO Sleep mode*/\
 103         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 104         /*0x04[9] = 1 turn off MAC by HW state machine*/                \
 105         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
 106         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 107         /*wait till 0x04[9] = 0 polling until return 0 to disable*/     \
 108         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},                  \
 109
 110
 111 #define RTL8188E_TRANS_CARDEMU_TO_SUS                                   \
 112         /* format */                                                    \
 113         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 114         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 115         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 116         /*0x04[12:11] = 2b'01enable WL suspend*/                        \
 117         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},        \
 118         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 119         /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/               \
 120         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)},\
 121         {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 122         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 123         /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
 124         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)},                 \
 125         {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 126         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 127         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
 128         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
 129         {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 130         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 131         /*Set USB suspend enable local register  0xfe10[4]= 1 */        \
 132         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
 133         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 134         /*Set SDIO suspend local register*/                             \
 135         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
 136         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 137         /*wait power state to suspend*/                                 \
 138         PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
 139
 140 #define RTL8188E_TRANS_SUS_TO_CARDEMU                                   \
 141         /* format */                                                    \
 142         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 143         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 144         /*Set SDIO suspend local register*/                             \
 145         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},                   \
 146         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 147         /*wait power state to suspend*/                                 \
 148         PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},            \
 149         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 150         /*0x04[12:11] = 2b'01enable WL suspend*/                        \
 151         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
 152
 153 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS                               \
 154         /* format */                                                    \
 155         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 156         {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 157         /*0x24[23] = 2b'01 schmit trigger */                            \
 158         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
 159         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 160         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 161         /*0x04[12:11] = 2b'01 enable WL suspend*/                       \
 162         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},        \
 163         {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 164         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 165         /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
 166         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},                      \
 167         {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 168         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 169         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
 170         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
 171         {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 172         /*Set USB suspend enable local register  0xfe10[4]= 1 */        \
 173         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
 174         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 175         /*Set SDIO suspend local register*/                             \
 176         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
 177         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 178         PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
 179
 180 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU                               \
 181         /* format */                                                    \
 182         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 183         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 184         PWR_BASEADDR_SDIO,\
 185         PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/  \
 186         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 187         PWR_BASEADDR_SDIO,\
 188         PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
 189         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 190         PWR_BASEADDR_MAC,                                               \
 191         PWR_CMD_WRITE, BIT(3)|BIT(4), 0},                               \
 192         /*0x04[12:11] = 2b'01enable WL suspend*/
 193
 194
 195 #define RTL8188E_TRANS_CARDEMU_TO_PDN                                   \
 196         /* format */                                                    \
 197         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 198         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 199         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/   \
 200         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 201         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
 202
 203
 204 #define RTL8188E_TRANS_PDN_TO_CARDEMU                                   \
 205         /* format */                                                    \
 206         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 207         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 208         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
 209
 210
 211 #define RTL8188E_TRANS_ACT_TO_LPS                                       \
 212         /* format */                                                    \
 213         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 214         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 215         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/       \
 216         {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 217         /*zero if no pkt is tx*/\
 218         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 219         {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 220         /*Should be zero if no packet is transmitting*/ \
 221         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 222         {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 223         /*Should be zero if no packet is transmitting*/                 \
 224         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 225         {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 226         /*Should be zero if no packet is transmitting*/                 \
 227         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 228         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 229         /*CCK and OFDM are disabled, and clock are gated*/              \
 230         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                    \
 231         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 232         PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
 233         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 234         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/  \
 235         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 236         /*check if removed later*/                                      \
 237         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},                    \
 238         {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 239         /*Respond TxOK to scheduler*/                                   \
 240         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},               \
 241
 242
 243 #define RTL8188E_TRANS_LPS_TO_ACT                                       \
 244         /* format */                                                    \
 245         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 246         {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 247         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/    \
 248         {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 249         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/      \
 250         {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 251         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/     \
 252         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 253         PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
 254         {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 255         /*.     0x08[4] = 0              switch TSF to 40M*/            \
 256         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
 257         {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 258         /*Polling 0x109[7]= 0  TSF in 40M*/                             \
 259         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},                  \
 260         {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 261         /*. 0x29[7:6] = 2b'00    enable BB clock*/                      \
 262         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0},             \
 263         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 264         /*.     0x101[1] = 1*/\
 265         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
 266         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 267         /*.     0x100[7:0] = 0xFF        enable WMAC TRX*/\
 268         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},                   \
 269         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 270         /*. 0x02[1:0] = 2b'11  enable BB macro*/\
 271         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, \
 272         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 273         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.  0x522 = 0*/
 274
 275
 276 #define RTL8188E_TRANS_END                                              \
 277         /* format */                                                    \
 278         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 279         {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 280         0, PWR_CMD_END, 0, 0}
 281
 282 extern struct wlan_pwr_cfg rtl8188e_power_on_flow
 283                 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
 284                 RTL8188E_TRANS_END_STEPS];
 285 extern struct wlan_pwr_cfg rtl8188e_radio_off_flow
 286                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 287                 RTL8188E_TRANS_END_STEPS];
 288 extern struct wlan_pwr_cfg rtl8188e_card_disable_flow
 289                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 290                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 291                 RTL8188E_TRANS_END_STEPS];
 292 extern struct wlan_pwr_cfg rtl8188e_card_enable_flow
 293                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 294                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 295                 RTL8188E_TRANS_END_STEPS];
 296 extern struct wlan_pwr_cfg rtl8188e_suspend_flow
 297                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 298                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 299                 RTL8188E_TRANS_END_STEPS];
 300 extern struct wlan_pwr_cfg rtl8188e_resume_flow
 301                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 302                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 303                 RTL8188E_TRANS_END_STEPS];
 304 extern struct wlan_pwr_cfg rtl8188e_hwpdn_flow
 305                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 306                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 307                 RTL8188E_TRANS_END_STEPS];
 308 extern struct wlan_pwr_cfg rtl8188e_enter_lps_flow
 309                 [RTL8188E_TRANS_ACT_TO_LPS_STEPS +
 310                 RTL8188E_TRANS_END_STEPS];
 311 extern struct wlan_pwr_cfg rtl8188e_leave_lps_flow
 312                 [RTL8188E_TRANS_LPS_TO_ACT_STEPS +
 313                 RTL8188E_TRANS_END_STEPS];
 314
 315 /* RTL8723 Power Configuration CMDs for PCIe interface */
 316 #define Rtl8188E_NIC_PWR_ON_FLOW        rtl8188e_power_on_flow
 317 #define Rtl8188E_NIC_RF_OFF_FLOW        rtl8188e_radio_off_flow
 318 #define Rtl8188E_NIC_DISABLE_FLOW       rtl8188e_card_disable_flow
 319 #define Rtl8188E_NIC_ENABLE_FLOW        rtl8188e_card_enable_flow
 320 #define Rtl8188E_NIC_SUSPEND_FLOW       rtl8188e_suspend_flow
 321 #define Rtl8188E_NIC_RESUME_FLOW        rtl8188e_resume_flow
 322 #define Rtl8188E_NIC_PDN_FLOW           rtl8188e_hwpdn_flow
 323 #define Rtl8188E_NIC_LPS_ENTER_FLOW     rtl8188e_enter_lps_flow
 324 #define Rtl8188E_NIC_LPS_LEAVE_FLOW     rtl8188e_leave_lps_flow
 325
 326 #endif