drivers/net/wireless/rtlwifi/rtl8188ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <[email protected]>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <[email protected]>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44 #include "pwrseq.h"
  45
  46 #define LLT_CONFIG              5
  47
  48 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  49                                       u8 set_bits, u8 clear_bits)
  50 {
  51         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  52         struct rtl_priv *rtlpriv = rtl_priv(hw);
  53
  54         rtlpci->reg_bcn_ctrl_val |= set_bits;
  55         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  56
  57         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  58 }
  59
  60 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
  61 {
  62         struct rtl_priv *rtlpriv = rtl_priv(hw);
  63         u8 tmp1byte;
  64
  65         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  66         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  68         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  69         tmp1byte &= ~(BIT(0));
  70         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  71 }
  72
  73 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
  74 {
  75         struct rtl_priv *rtlpriv = rtl_priv(hw);
  76         u8 tmp1byte;
  77
  78         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  79         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  81         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  82         tmp1byte |= BIT(0);
  83         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  84 }
  85
  86 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  87 {
  88         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  89 }
  90
  91 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  92 {
  93         struct rtl_priv *rtlpriv = rtl_priv(hw);
  94         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  95         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  96
  97         while (skb_queue_len(&ring->queue)) {
  98                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  99                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
 100
 101                 pci_unmap_single(rtlpci->pdev,
 102                                  rtlpriv->cfg->ops->get_desc(
 103                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 104                                  skb->len, PCI_DMA_TODEVICE);
 105                 kfree_skb(skb);
 106                 ring->idx = (ring->idx + 1) % ring->entries;
 107         }
 108 }
 109
 110 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 111 {
 112         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 113 }
 114
 115 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
 116                                      u8 rpwm_val, bool need_turn_off_ckk)
 117 {
 118         struct rtl_priv *rtlpriv = rtl_priv(hw);
 119         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 120         bool support_remote_wake_up;
 121         u32 count = 0, isr_regaddr, content;
 122         bool schedule_timer = need_turn_off_ckk;
 123
 124         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 125                                       (u8 *)(&support_remote_wake_up));
 126         if (!rtlhal->fw_ready)
 127                 return;
 128         if (!rtlpriv->psc.fw_current_inpsmode)
 129                 return;
 130
 131         while (1) {
 132                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 133                 if (rtlhal->fw_clk_change_in_progress) {
 134                         while (rtlhal->fw_clk_change_in_progress) {
 135                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 136                                 udelay(100);
 137                                 if (++count > 1000)
 138                                         return;
 139                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 140                         }
 141                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 142                 } else {
 143                         rtlhal->fw_clk_change_in_progress = false;
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                         break;
 146                 }
 147         }
 148
 149         if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
 150                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 151                 if (FW_PS_IS_ACK(rpwm_val)) {
 152                         isr_regaddr = REG_HISR;
 153                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 154                         while (!(content & IMR_CPWM) && (count < 500)) {
 155                                 udelay(50);
 156                                 count++;
 157                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         }
 159
 160                         if (content & IMR_CPWM) {
 161                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 162                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
 163                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 164                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 165                                          rtlhal->fw_ps_state);
 166                         }
 167                 }
 168
 169                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 170                 rtlhal->fw_clk_change_in_progress = false;
 171                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 172                 if (schedule_timer) {
 173                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 174                                   jiffies + MSECS(10));
 175                 }
 176         } else  {
 177                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 178                 rtlhal->fw_clk_change_in_progress = false;
 179                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 180         }
 181 }
 182
 183 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
 184                                       u8 rpwm_val)
 185 {
 186         struct rtl_priv *rtlpriv = rtl_priv(hw);
 187         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 188         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 189         struct rtl8192_tx_ring *ring;
 190         enum rf_pwrstate rtstate;
 191         bool schedule_timer = false;
 192         u8 queue;
 193
 194         if (!rtlhal->fw_ready)
 195                 return;
 196         if (!rtlpriv->psc.fw_current_inpsmode)
 197                 return;
 198         if (!rtlhal->allow_sw_to_change_hwclc)
 199                 return;
 200         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 201         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 202                 return;
 203
 204         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 205                 ring = &rtlpci->tx_ring[queue];
 206                 if (skb_queue_len(&ring->queue)) {
 207                         schedule_timer = true;
 208                         break;
 209                 }
 210         }
 211
 212         if (schedule_timer) {
 213                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 214                           jiffies + MSECS(10));
 215                 return;
 216         }
 217
 218         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 219             FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
 220                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 221                 if (!rtlhal->fw_clk_change_in_progress) {
 222                         rtlhal->fw_clk_change_in_progress = true;
 223                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 224                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 225                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 226                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 227                                                       &rpwm_val);
 228                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 229                         rtlhal->fw_clk_change_in_progress = false;
 230                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 231                 } else {
 232                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 233                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 234                                   jiffies + MSECS(10));
 235                 }
 236         }
 237 }
 238
 239 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 240 {
 241         u8 rpwm_val = 0;
 242
 243         rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
 244         _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
 245 }
 246
 247 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 248 {
 249         u8 rpwm_val = 0;
 250
 251         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
 252         _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 253 }
 254
 255 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
 256 {
 257         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 258
 259         _rtl88ee_set_fw_ps_rf_off_low_power(hw);
 260 }
 261
 262 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
 263 {
 264         struct rtl_priv *rtlpriv = rtl_priv(hw);
 265         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 266         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 267         bool fw_current_inps = false;
 268         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 269
 270         if (ppsc->low_power_enable) {
 271                 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
 272                 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
 273                 rtlhal->allow_sw_to_change_hwclc = false;
 274                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 275                                               &fw_pwrmode);
 276                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 277                                               (u8 *)(&fw_current_inps));
 278         } else {
 279                 rpwm_val = FW_PS_STATE_ALL_ON_88E;      /* RF on */
 280                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               &fw_pwrmode);
 283                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 284                                               (u8 *)(&fw_current_inps));
 285         }
 286 }
 287
 288 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
 289 {
 290         struct rtl_priv *rtlpriv = rtl_priv(hw);
 291         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 292         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 293         bool fw_current_inps = true;
 294         u8 rpwm_val;
 295
 296         if (ppsc->low_power_enable) {
 297                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;      /* RF off */
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 299                                               (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 301                                               &ppsc->fwctrl_psmode);
 302                 rtlhal->allow_sw_to_change_hwclc = true;
 303                 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 304         } else {
 305                 rpwm_val = FW_PS_STATE_RF_OFF_88E;      /* RF off */
 306                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 307                                               (u8 *)(&fw_current_inps));
 308                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 309                                               &ppsc->fwctrl_psmode);
 310                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 311         }
 312 }
 313
 314 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 315 {
 316         struct rtl_priv *rtlpriv = rtl_priv(hw);
 317         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 318         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 319
 320         switch (variable) {
 321         case HW_VAR_RCR:
 322                 *((u32 *)(val)) = rtlpci->receive_config;
 323                 break;
 324         case HW_VAR_RF_STATE:
 325                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 326                 break;
 327         case HW_VAR_FWLPS_RF_ON:{
 328                         enum rf_pwrstate rfstate;
 329                         u32 val_rcr;
 330
 331                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 332                                                       (u8 *)(&rfstate));
 333                         if (rfstate == ERFOFF) {
 334                                 *((bool *)(val)) = true;
 335                         } else {
 336                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 337                                 val_rcr &= 0x00070000;
 338                                 if (val_rcr)
 339                                         *((bool *)(val)) = false;
 340                                 else
 341                                         *((bool *)(val)) = true;
 342                         }
 343                         break;
 344                 }
 345         case HW_VAR_FW_PSMODE_STATUS:
 346                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 347                 break;
 348         case HW_VAR_CORRECT_TSF:{
 349                 u64 tsf;
 350                 u32 *ptsf_low = (u32 *)&tsf;
 351                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 352
 353                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 354                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 355
 356                 *((u64 *)(val)) = tsf;
 357                 break; }
 358         default:
 359                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 360                          "switch case not process %x\n", variable);
 361                 break;
 362         }
 363 }
 364
 365 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 366 {
 367         struct rtl_priv *rtlpriv = rtl_priv(hw);
 368         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 369         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 370         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 371         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 372         u8 idx;
 373
 374         switch (variable) {
 375         case HW_VAR_ETHER_ADDR:
 376                 for (idx = 0; idx < ETH_ALEN; idx++)
 377                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 378                 break;
 379         case HW_VAR_BASIC_RATE:{
 380                 u16 rate_cfg = ((u16 *)val)[0];
 381                 u8 rate_index = 0;
 382                 rate_cfg = rate_cfg & 0x15f;
 383                 rate_cfg |= 0x01;
 384                 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 385                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (rate_cfg >> 8) & 0xff);
 386                 while (rate_cfg > 0x1) {
 387                         rate_cfg = (rate_cfg >> 1);
 388                         rate_index++;
 389                 }
 390                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
 391                 break; }
 392         case HW_VAR_BSSID:
 393                 for (idx = 0; idx < ETH_ALEN; idx++)
 394                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 395                 break;
 396         case HW_VAR_SIFS:
 397                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 398                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 399
 400                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 401                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 402
 403                 if (!mac->ht_enable)
 404                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 405                 else
 406                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 407                                        *((u16 *)val));
 408                 break;
 409         case HW_VAR_SLOT_TIME:{
 410                 u8 e_aci;
 411
 412                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 413                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 414
 415                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 416
 417                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 418                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 419                                                       &e_aci);
 420                 }
 421                 break; }
 422         case HW_VAR_ACK_PREAMBLE:{
 423                 u8 reg_tmp;
 424                 u8 short_preamble = (bool)*val;
 425                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 426                 if (short_preamble) {
 427                         reg_tmp |= 0x02;
 428                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 429                 } else {
 430                         reg_tmp |= 0xFD;
 431                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 432                 }
 433                 break; }
 434         case HW_VAR_WPA_CONFIG:
 435                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 436                 break;
 437         case HW_VAR_AMPDU_MIN_SPACE:{
 438                 u8 min_spacing_to_set;
 439                 u8 sec_min_space;
 440
 441                 min_spacing_to_set = *val;
 442                 if (min_spacing_to_set <= 7) {
 443                         sec_min_space = 0;
 444
 445                         if (min_spacing_to_set < sec_min_space)
 446                                 min_spacing_to_set = sec_min_space;
 447
 448                         mac->min_space_cfg = ((mac->min_space_cfg &
 449                                                0xf8) | min_spacing_to_set);
 450
 451                         *val = min_spacing_to_set;
 452
 453                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 454                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 455                                   mac->min_space_cfg);
 456
 457                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 458                                        mac->min_space_cfg);
 459                 }
 460                 break; }
 461         case HW_VAR_SHORTGI_DENSITY:{
 462                 u8 density_to_set;
 463
 464                 density_to_set = *val;
 465                 mac->min_space_cfg |= (density_to_set << 3);
 466
 467                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 468                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 469                           mac->min_space_cfg);
 470
 471                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 472                                mac->min_space_cfg);
 473                 break; }
 474         case HW_VAR_AMPDU_FACTOR:{
 475                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 476                 u8 factor;
 477                 u8 *reg = NULL;
 478                 u8 id = 0;
 479
 480                 reg = regtoset_normal;
 481
 482                 factor = *val;
 483                 if (factor <= 3) {
 484                         factor = (1 << (factor + 2));
 485                         if (factor > 0xf)
 486                                 factor = 0xf;
 487
 488                         for (id = 0; id < 4; id++) {
 489                                 if ((reg[id] & 0xf0) > (factor << 4))
 490                                         reg[id] = (reg[id] & 0x0f) |
 491                                                   (factor << 4);
 492
 493                                 if ((reg[id] & 0x0f) > factor)
 494                                         reg[id] = (reg[id] & 0xf0) | (factor);
 495
 496                                 rtl_write_byte(rtlpriv, (REG_AGGLEN_LMT + id),
 497                                                reg[id]);
 498                         }
 499
 500                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 501                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n", factor);
 502                 }
 503                 break; }
 504         case HW_VAR_AC_PARAM:{
 505                 u8 e_aci = *val;
 506                 rtl88e_dm_init_edca_turbo(hw);
 507
 508                 if (rtlpci->acm_method != EACMWAY2_SW)
 509                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 510                                                       &e_aci);
 511                 break; }
 512         case HW_VAR_ACM_CTRL:{
 513                 u8 e_aci = *val;
 514                 union aci_aifsn *p_aci_aifsn =
 515                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 516                 u8 acm = p_aci_aifsn->f.acm;
 517                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 518
 519                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 520
 521                 if (acm) {
 522                         switch (e_aci) {
 523                         case AC0_BE:
 524                                 acm_ctrl |= ACMHW_BEQEN;
 525                                 break;
 526                         case AC2_VI:
 527                                 acm_ctrl |= ACMHW_VIQEN;
 528                                 break;
 529                         case AC3_VO:
 530                                 acm_ctrl |= ACMHW_VOQEN;
 531                                 break;
 532                         default:
 533                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 534                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 535                                          acm);
 536                                 break;
 537                         }
 538                 } else {
 539                         switch (e_aci) {
 540                         case AC0_BE:
 541                                 acm_ctrl &= (~ACMHW_BEQEN);
 542                                 break;
 543                         case AC2_VI:
 544                                 acm_ctrl &= (~ACMHW_VIQEN);
 545                                 break;
 546                         case AC3_VO:
 547                                 acm_ctrl &= (~ACMHW_BEQEN);
 548                                 break;
 549                         default:
 550                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 551                                          "switch case not process\n");
 552                                 break;
 553                         }
 554                 }
 555
 556                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 557                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 558                          acm_ctrl);
 559                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 560                 break; }
 561         case HW_VAR_RCR:
 562                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 563                 rtlpci->receive_config = ((u32 *)(val))[0];
 564                 break;
 565         case HW_VAR_RETRY_LIMIT:{
 566                 u8 retry_limit = *val;
 567
 568                 rtl_write_word(rtlpriv, REG_RL,
 569                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 570                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 571                 break; }
 572         case HW_VAR_DUAL_TSF_RST:
 573                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 574                 break;
 575         case HW_VAR_EFUSE_BYTES:
 576                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 577                 break;
 578         case HW_VAR_EFUSE_USAGE:
 579                 rtlefuse->efuse_usedpercentage = *val;
 580                 break;
 581         case HW_VAR_IO_CMD:
 582                 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 583                 break;
 584         case HW_VAR_SET_RPWM:{
 585                 u8 rpwm_val;
 586
 587                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 588                 udelay(1);
 589
 590                 if (rpwm_val & BIT(7)) {
 591                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 592                 } else {
 593                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
 594                 }
 595                 break; }
 596         case HW_VAR_H2C_FW_PWRMODE:
 597                 rtl88e_set_fw_pwrmode_cmd(hw, *val);
 598                 break;
 599         case HW_VAR_FW_PSMODE_STATUS:
 600                 ppsc->fw_current_inpsmode = *((bool *)val);
 601                 break;
 602         case HW_VAR_RESUME_CLK_ON:
 603                 _rtl88ee_set_fw_ps_rf_on(hw);
 604                 break;
 605         case HW_VAR_FW_LPS_ACTION:{
 606                 bool enter_fwlps = *((bool *)val);
 607
 608                 if (enter_fwlps)
 609                         _rtl88ee_fwlps_enter(hw);
 610                  else
 611                         _rtl88ee_fwlps_leave(hw);
 612                  break; }
 613         case HW_VAR_H2C_FW_JOINBSSRPT:{
 614                 u8 mstatus = *val;
 615                 u8 tmp, tmp_reg422, uval;
 616                 u8 count = 0, dlbcn_count = 0;
 617                 bool recover = false;
 618
 619                 if (mstatus == RT_MEDIA_CONNECT) {
 620                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 621
 622                         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
 623                         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(0)));
 624
 625                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 626                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 627
 628                         tmp_reg422 = rtl_read_byte(rtlpriv,
 629                                                    REG_FWHW_TXQ_CTRL + 2);
 630                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 631                                        tmp_reg422 & (~BIT(6)));
 632                         if (tmp_reg422 & BIT(6))
 633                                 recover = true;
 634
 635                         do {
 636                                 uval = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 637                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
 638                                                (uval | BIT(0)));
 639                                 _rtl88ee_return_beacon_queue_skb(hw);
 640
 641                                 rtl88e_set_fw_rsvdpagepkt(hw, 0);
 642                                 uval = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 643                                 count = 0;
 644                                 while (!(uval & BIT(0)) && count < 20) {
 645                                         count++;
 646                                         udelay(10);
 647                                         uval = rtl_read_byte(rtlpriv,
 648                                                              REG_TDECTRL+2);
 649                                 }
 650                                 dlbcn_count++;
 651                         } while (!(uval & BIT(0)) && dlbcn_count < 5);
 652
 653                         if (uval & BIT(0))
 654                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 655
 656                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 657                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 658
 659                         if (recover) {
 660                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 661                                                tmp_reg422);
 662                         }
 663                         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & ~(BIT(0))));
 664                 }
 665                 rtl88e_set_fw_joinbss_report_cmd(hw, *val);
 666                 break; }
 667         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 668                 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
 669                 break;
 670         case HW_VAR_AID:{
 671                 u16 u2btmp;
 672                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 673                 u2btmp &= 0xC000;
 674                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 675                                mac->assoc_id));
 676                 break; }
 677         case HW_VAR_CORRECT_TSF:{
 678                 u8 btype_ibss = *val;
 679
 680                 if (btype_ibss == true)
 681                         _rtl88ee_stop_tx_beacon(hw);
 682
 683                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 684
 685                 rtl_write_dword(rtlpriv, REG_TSFTR,
 686                                 (u32) (mac->tsf & 0xffffffff));
 687                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 688                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 689
 690                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 691
 692                 if (btype_ibss == true)
 693                         _rtl88ee_resume_tx_beacon(hw);
 694                 break; }
 695         default:
 696                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 697                          "switch case not process %x\n", variable);
 698                 break;
 699         }
 700 }
 701
 702 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 703 {
 704         struct rtl_priv *rtlpriv = rtl_priv(hw);
 705         bool status = true;
 706         long count = 0;
 707         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 708                     _LLT_OP(_LLT_WRITE_ACCESS);
 709
 710         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 711
 712         do {
 713                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 714                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 715                         break;
 716
 717                 if (count > POLLING_LLT_THRESHOLD) {
 718                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 719                                  "Failed to polling write LLT done at address %d!\n",
 720                                  address);
 721                         status = false;
 722                         break;
 723                 }
 724         } while (++count);
 725
 726         return status;
 727 }
 728
 729 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
 730 {
 731         struct rtl_priv *rtlpriv = rtl_priv(hw);
 732         unsigned short i;
 733         u8 txpktbuf_bndy;
 734         u8 maxpage;
 735         bool status;
 736
 737         maxpage = 0xAF;
 738         txpktbuf_bndy = 0xAB;
 739
 740         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
 741         rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
 742
 743
 744         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
 745         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 746
 747         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 748         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 749
 750         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 751         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 752         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 753
 754         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 755                 status = _rtl88ee_llt_write(hw, i, i + 1);
 756                 if (true != status)
 757                         return status;
 758         }
 759
 760         status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 761         if (true != status)
 762                 return status;
 763
 764         for (i = txpktbuf_bndy; i < maxpage; i++) {
 765                 status = _rtl88ee_llt_write(hw, i, (i + 1));
 766                 if (true != status)
 767                         return status;
 768         }
 769
 770         status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
 771         if (true != status)
 772                 return status;
 773
 774         return true;
 775 }
 776
 777 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 778 {
 779         struct rtl_priv *rtlpriv = rtl_priv(hw);
 780         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 781         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 782         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 783
 784         if (rtlpriv->rtlhal.up_first_time)
 785                 return;
 786
 787         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 788                 rtl88ee_sw_led_on(hw, pLed0);
 789         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 790                 rtl88ee_sw_led_on(hw, pLed0);
 791         else
 792                 rtl88ee_sw_led_off(hw, pLed0);
 793 }
 794
 795 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
 796 {
 797         struct rtl_priv *rtlpriv = rtl_priv(hw);
 798         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 799         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 800         u8 bytetmp;
 801         u16 wordtmp;
 802
 803         /*Disable XTAL OUTPUT for power saving. YJ, add, 111206. */
 804         bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
 805         rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
 806         /*Auto Power Down to CHIP-off State*/
 807         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 808         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 809
 810         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 811         /* HW Power on sequence */
 812         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 813                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 814                                       Rtl8188E_NIC_ENABLE_FLOW)) {
 815                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 816                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 817                 return false;
 818         }
 819
 820         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 821         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 822
 823         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 824         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
 825
 826         bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
 827         rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
 828
 829         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
 830         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
 831
 832         bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
 833         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
 834         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
 835         rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
 836
 837         /*Add for wake up online*/
 838         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 839
 840         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
 841         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
 842         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
 843         rtl_write_byte(rtlpriv, 0x367, 0x80);
 844
 845         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 846         rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
 847         rtl_write_byte(rtlpriv, REG_CR+2, 0x00);
 848
 849         if (!rtlhal->mac_func_enable) {
 850                 if (_rtl88ee_llt_table_init(hw) == false) {
 851                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 852                                  "LLT table init fail\n");
 853                         return false;
 854                 }
 855         }
 856
 857
 858         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 859         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 860
 861         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 862         wordtmp &= 0xf;
 863         wordtmp |= 0xE771;
 864         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 865
 866         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 867         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 868         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 869
 870         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 871                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 872                         DMA_BIT_MASK(32));
 873         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 874                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 875                         DMA_BIT_MASK(32));
 876         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 877                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 878         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 879                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 880         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 881                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 882         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 883                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 884         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 885                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 886                         DMA_BIT_MASK(32));
 887         rtl_write_dword(rtlpriv, REG_RX_DESA,
 888                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 889                         DMA_BIT_MASK(32));
 890
 891         /* if we want to support 64 bit DMA, we should set it here,
 892          * but at the moment we do not support 64 bit DMA
 893          */
 894
 895         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 896
 897         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 898         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
 899
 900         if (rtlhal->earlymode_enable) {/*Early mode enable*/
 901                 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
 902                 bytetmp |= 0x1f;
 903                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
 904                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
 905         }
 906         _rtl88ee_gen_refresh_led_state(hw);
 907         return true;
 908 }
 909
 910 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
 911 {
 912         struct rtl_priv *rtlpriv = rtl_priv(hw);
 913         u32 reg_prsr;
 914
 915         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 916
 917         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 918         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 919 }
 920
 921 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
 922 {
 923         struct rtl_priv *rtlpriv = rtl_priv(hw);
 924         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 925         u8 tmp1byte = 0;
 926         u32 tmp4Byte = 0, count;
 927
 928         rtl_write_word(rtlpriv, 0x354, 0x8104);
 929         rtl_write_word(rtlpriv, 0x358, 0x24);
 930
 931         rtl_write_word(rtlpriv, 0x350, 0x70c);
 932         rtl_write_byte(rtlpriv, 0x352, 0x2);
 933         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 934         count = 0;
 935         while (tmp1byte && count < 20) {
 936                 udelay(10);
 937                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 938                 count++;
 939         }
 940         if (0 == tmp1byte) {
 941                 tmp4Byte = rtl_read_dword(rtlpriv, 0x34c);
 942                 rtl_write_dword(rtlpriv, 0x348, tmp4Byte|BIT(31));
 943                 rtl_write_word(rtlpriv, 0x350, 0xf70c);
 944                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 945         }
 946
 947         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 948         count = 0;
 949         while (tmp1byte && count < 20) {
 950                 udelay(10);
 951                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 952                 count++;
 953         }
 954
 955         rtl_write_word(rtlpriv, 0x350, 0x718);
 956         rtl_write_byte(rtlpriv, 0x352, 0x2);
 957         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 958         count = 0;
 959         while (tmp1byte && count < 20) {
 960                 udelay(10);
 961                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 962                 count++;
 963         }
 964         if (ppsc->support_backdoor || (0 == tmp1byte)) {
 965                 tmp4Byte = rtl_read_dword(rtlpriv, 0x34c);
 966                 rtl_write_dword(rtlpriv, 0x348, tmp4Byte|BIT(11)|BIT(12));
 967                 rtl_write_word(rtlpriv, 0x350, 0xf718);
 968                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 969         }
 970         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 971         count = 0;
 972         while (tmp1byte && count < 20) {
 973                 udelay(10);
 974                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 975                 count++;
 976         }
 977 }
 978
 979 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
 980 {
 981         struct rtl_priv *rtlpriv = rtl_priv(hw);
 982         u8 sec_reg_value;
 983
 984         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 985                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 986                  rtlpriv->sec.pairwise_enc_algorithm,
 987                  rtlpriv->sec.group_enc_algorithm);
 988
 989         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 990                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 991                          "not open hw encryption\n");
 992                 return;
 993         }
 994         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
 995
 996         if (rtlpriv->sec.use_defaultkey) {
 997                 sec_reg_value |= SCR_TXUSEDK;
 998                 sec_reg_value |= SCR_RXUSEDK;
 999         }
1000
1001         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1002
1003         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1004
1005         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1006                  "The SECR-value %x\n", sec_reg_value);
1007         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1008 }
1009
1010 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1011 {
1012         struct rtl_priv *rtlpriv = rtl_priv(hw);
1013         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1014         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1015         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1016         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1017         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1018         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1019         bool rtstatus = true;
1020         int err = 0;
1021         u8 tmp_u1b, u1byte;
1022         unsigned long flags;
1023
1024         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Rtl8188EE hw init\n");
1025         rtlpriv->rtlhal.being_init_adapter = true;
1026         /* As this function can take a very long time (up to 350 ms)
1027          * and can be called with irqs disabled, reenable the irqs
1028          * to let the other devices continue being serviced.
1029          *
1030          * It is safe doing so since our own interrupts will only be enabled
1031          * in a subsequent step.
1032          */
1033         local_save_flags(flags);
1034         local_irq_enable();
1035
1036         rtlpriv->intf_ops->disable_aspm(hw);
1037
1038         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1039         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1040         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1041                 rtlhal->mac_func_enable = true;
1042         } else {
1043                 rtlhal->mac_func_enable = false;
1044                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1045         }
1046
1047         rtstatus = _rtl88ee_init_mac(hw);
1048         if (rtstatus != true) {
1049                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1050                 err = 1;
1051                 goto exit;
1052         }
1053
1054         err = rtl88e_download_fw(hw, false);
1055         if (err) {
1056                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1057                          "Failed to download FW. Init HW without FW now..\n");
1058                 err = 1;
1059                 goto exit;
1060         } else {
1061                 rtlhal->fw_ready = true;
1062         }
1063         /*fw related variable initialize */
1064         rtlhal->last_hmeboxnum = 0;
1065         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1066         rtlhal->fw_clk_change_in_progress = false;
1067         rtlhal->allow_sw_to_change_hwclc = false;
1068         ppsc->fw_current_inpsmode = false;
1069
1070         rtl88e_phy_mac_config(hw);
1071         /* because last function modifies RCR, we update
1072          * rcr var here, or TP will be unstable for receive_config
1073          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1074          * RCR_APP_ICV will cause mac80211 disassoc for cisco 1252
1075          */
1076         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1077         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1078
1079         rtl88e_phy_bb_config(hw);
1080         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1081         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1082
1083         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1084         rtl88e_phy_rf_config(hw);
1085
1086         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1087                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1088         rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1089
1090         _rtl88ee_hw_configure(hw);
1091         rtl_cam_reset_all_entry(hw);
1092         rtl88ee_enable_hw_security_config(hw);
1093
1094         rtlhal->mac_func_enable = true;
1095         ppsc->rfpwr_state = ERFON;
1096
1097         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1098         _rtl88ee_enable_aspm_back_door(hw);
1099         rtlpriv->intf_ops->enable_aspm(hw);
1100
1101         if (ppsc->rfpwr_state == ERFON) {
1102                 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1103                     ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1104                     (rtlhal->oem_id == RT_CID_819X_HP))) {
1105                         rtl88e_phy_set_rfpath_switch(hw, true);
1106                         rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1107                 } else {
1108                         rtl88e_phy_set_rfpath_switch(hw, false);
1109                         rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1110                 }
1111                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1112                          "rx idle ant %s\n",
1113                          (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1114                          ("MAIN_ANT") : ("AUX_ANT"));
1115
1116                 if (rtlphy->iqk_initialized) {
1117                         rtl88e_phy_iq_calibrate(hw, true);
1118                 } else {
1119                         rtl88e_phy_iq_calibrate(hw, false);
1120                         rtlphy->iqk_initialized = true;
1121                 }
1122                 rtl88e_dm_check_txpower_tracking(hw);
1123                 rtl88e_phy_lc_calibrate(hw);
1124         }
1125
1126         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1127         if (!(tmp_u1b & BIT(0))) {
1128                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1129                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1130         }
1131
1132         if (!(tmp_u1b & BIT(4))) {
1133                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1134                 tmp_u1b &= 0x0F;
1135                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1136                 udelay(10);
1137                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1138                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1139         }
1140         rtl_write_byte(rtlpriv, REG_NAV_CTRL+2,  ((30000+127)/128));
1141         rtl88e_dm_init(hw);
1142 exit:
1143         local_irq_restore(flags);
1144         rtlpriv->rtlhal.being_init_adapter = false;
1145         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "end of Rtl8188EE hw init %x\n",
1146                  err);
1147         return err;
1148 }
1149
1150 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1151 {
1152         struct rtl_priv *rtlpriv = rtl_priv(hw);
1153         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1154         enum version_8188e version = VERSION_UNKNOWN;
1155         u32 value32;
1156
1157         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1158         if (value32 & TRP_VAUX_EN) {
1159                 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1160         } else {
1161                 version = NORMAL_CHIP;
1162                 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1163                 version = version | ((value32 & VENDOR_ID) ?
1164                           CHIP_VENDOR_UMC : 0);
1165         }
1166
1167         rtlphy->rf_type = RF_1T1R;
1168         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1169                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1170                  "RF_2T2R" : "RF_1T1R");
1171
1172         return version;
1173 }
1174
1175 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1176                                      enum nl80211_iftype type)
1177 {
1178         struct rtl_priv *rtlpriv = rtl_priv(hw);
1179         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1180         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1181         bt_msr &= 0xfc;
1182
1183         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1184             type == NL80211_IFTYPE_STATION) {
1185                 _rtl88ee_stop_tx_beacon(hw);
1186                 _rtl88ee_enable_bcn_sub_func(hw);
1187         } else if (type == NL80211_IFTYPE_ADHOC ||
1188                 type == NL80211_IFTYPE_AP ||
1189                 type == NL80211_IFTYPE_MESH_POINT) {
1190                 _rtl88ee_resume_tx_beacon(hw);
1191                 _rtl88ee_disable_bcn_sub_func(hw);
1192         } else {
1193                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1194                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1195                          type);
1196         }
1197
1198         switch (type) {
1199         case NL80211_IFTYPE_UNSPECIFIED:
1200                 bt_msr |= MSR_NOLINK;
1201                 ledaction = LED_CTL_LINK;
1202                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1203                          "Set Network type to NO LINK!\n");
1204                 break;
1205         case NL80211_IFTYPE_ADHOC:
1206                 bt_msr |= MSR_ADHOC;
1207                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1208                          "Set Network type to Ad Hoc!\n");
1209                 break;
1210         case NL80211_IFTYPE_STATION:
1211                 bt_msr |= MSR_INFRA;
1212                 ledaction = LED_CTL_LINK;
1213                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1214                          "Set Network type to STA!\n");
1215                 break;
1216         case NL80211_IFTYPE_AP:
1217                 bt_msr |= MSR_AP;
1218                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1219                          "Set Network type to AP!\n");
1220                 break;
1221         case NL80211_IFTYPE_MESH_POINT:
1222                 bt_msr |= MSR_ADHOC;
1223                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1224                          "Set Network type to Mesh Point!\n");
1225                 break;
1226         default:
1227                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1228                          "Network type %d not support!\n", type);
1229                 return 1;
1230         }
1231
1232         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1233         rtlpriv->cfg->ops->led_control(hw, ledaction);
1234         if ((bt_msr & 0xfc) == MSR_AP)
1235                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1236         else
1237                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1238         return 0;
1239 }
1240
1241 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1242 {
1243         struct rtl_priv *rtlpriv = rtl_priv(hw);
1244         u32 reg_rcr;
1245
1246         if (rtlpriv->psc.rfpwr_state != ERFON)
1247                 return;
1248
1249         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1250
1251         if (check_bssid == true) {
1252                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1253                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1254                                               (u8 *)(&reg_rcr));
1255                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1256         } else if (check_bssid == false) {
1257                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1258                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1259                 rtlpriv->cfg->ops->set_hw_reg(hw,
1260                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1261         }
1262 }
1263
1264 int rtl88ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1265 {
1266         struct rtl_priv *rtlpriv = rtl_priv(hw);
1267
1268         if (_rtl88ee_set_media_status(hw, type))
1269                 return -EOPNOTSUPP;
1270
1271         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1272                 if (type != NL80211_IFTYPE_AP &&
1273                     type != NL80211_IFTYPE_MESH_POINT)
1274                         rtl88ee_set_check_bssid(hw, true);
1275         } else {
1276                 rtl88ee_set_check_bssid(hw, false);
1277         }
1278
1279         return 0;
1280 }
1281
1282 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1283 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1284 {
1285         struct rtl_priv *rtlpriv = rtl_priv(hw);
1286         rtl88e_dm_init_edca_turbo(hw);
1287         switch (aci) {
1288         case AC1_BK:
1289                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1290                 break;
1291         case AC0_BE:
1292                 break;
1293         case AC2_VI:
1294                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1295                 break;
1296         case AC3_VO:
1297                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1298                 break;
1299         default:
1300                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1301                 break;
1302         }
1303 }
1304
1305 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1306 {
1307         struct rtl_priv *rtlpriv = rtl_priv(hw);
1308         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1309
1310         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1311         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1312         rtlpci->irq_enabled = true;
1313         /* there are some C2H CMDs have been sent before system interrupt
1314          * is enabled, e.g., C2H, CPWM.
1315          * So we need to clear all C2H events that FW has notified, otherwise
1316          * FW won't schedule any commands anymore.
1317          */
1318         rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1319         /*enable system interrupt*/
1320         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1321 }
1322
1323 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1324 {
1325         struct rtl_priv *rtlpriv = rtl_priv(hw);
1326         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1327
1328         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1329         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1330         rtlpci->irq_enabled = false;
1331         synchronize_irq(rtlpci->pdev->irq);
1332 }
1333
1334 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1335 {
1336         struct rtl_priv *rtlpriv = rtl_priv(hw);
1337         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1338         u8 u1b_tmp;
1339         u32 count = 0;
1340         rtlhal->mac_func_enable = false;
1341         rtlpriv->intf_ops->enable_aspm(hw);
1342
1343         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1344         u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1345         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1346
1347         u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1348         while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1349                 udelay(10);
1350                 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1351                 count++;
1352         }
1353         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1354
1355         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1356                                  PWR_INTF_PCI_MSK,
1357                                  Rtl8188E_NIC_LPS_ENTER_FLOW);
1358
1359         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1360
1361         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1362                 rtl88e_firmware_selfreset(hw);
1363
1364         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1365         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1366         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1367
1368         u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1369         rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1370
1371         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1372                                  PWR_INTF_PCI_MSK, Rtl8188E_NIC_DISABLE_FLOW);
1373
1374         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1375         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1376         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1377         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1378
1379         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1380
1381         u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1382         rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1383         rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1384
1385         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1386         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1387         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1388         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1389
1390         rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1391 }
1392
1393 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1394 {
1395         struct rtl_priv *rtlpriv = rtl_priv(hw);
1396         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1397         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1398         enum nl80211_iftype opmode;
1399
1400         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1401
1402         mac->link_state = MAC80211_NOLINK;
1403         opmode = NL80211_IFTYPE_UNSPECIFIED;
1404
1405         _rtl88ee_set_media_status(hw, opmode);
1406
1407         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1408             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1409                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1410
1411         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1412         _rtl88ee_poweroff_adapter(hw);
1413
1414         /* after power off we should do iqk again */
1415         rtlpriv->phy.iqk_initialized = false;
1416 }
1417
1418 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1419                                   u32 *p_inta, u32 *p_intb)
1420 {
1421         struct rtl_priv *rtlpriv = rtl_priv(hw);
1422         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1423
1424         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1425         rtl_write_dword(rtlpriv, ISR, *p_inta);
1426
1427         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1428         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1429 }
1430
1431 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1432 {
1433         struct rtl_priv *rtlpriv = rtl_priv(hw);
1434         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1435         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1436         u16 bcn_interval, atim_window;
1437
1438         bcn_interval = mac->beacon_interval;
1439         atim_window = 2;        /*FIX MERGE */
1440         rtl88ee_disable_interrupt(hw);
1441         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1442         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1443         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1444         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1445         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1446         rtl_write_byte(rtlpriv, 0x606, 0x30);
1447         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1448         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1449         /*rtl88ee_enable_interrupt(hw);*/
1450 }
1451
1452 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1453 {
1454         struct rtl_priv *rtlpriv = rtl_priv(hw);
1455         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1456         u16 bcn_interval = mac->beacon_interval;
1457
1458         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1459                  "beacon_interval:%d\n", bcn_interval);
1460         /*rtl88ee_disable_interrupt(hw);*/
1461         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1462         /*rtl88ee_enable_interrupt(hw);*/
1463 }
1464
1465 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1466                                    u32 add_msr, u32 rm_msr)
1467 {
1468         struct rtl_priv *rtlpriv = rtl_priv(hw);
1469         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1470
1471         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1472                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1473
1474         rtl88ee_disable_interrupt(hw);
1475         if (add_msr)
1476                 rtlpci->irq_mask[0] |= add_msr;
1477         if (rm_msr)
1478                 rtlpci->irq_mask[0] &= (~rm_msr);
1479         rtl88ee_enable_interrupt(hw);
1480 }
1481
1482 static inline u8 get_chnl_group(u8 chnl)
1483 {
1484         u8 group;
1485
1486         group = chnl / 3;
1487         if (chnl == 14)
1488                 group = 5;
1489
1490         return group;
1491 }
1492
1493 static void set_diff0_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1494                          u32 i, u32 eadr)
1495 {
1496         pwr2g->bw40_diff[path][i] = 0;
1497         if (hwinfo[eadr] == 0xFF) {
1498                 pwr2g->bw20_diff[path][i] = 0x02;
1499         } else {
1500                 pwr2g->bw20_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1501                 /*bit sign number to 8 bit sign number*/
1502                 if (pwr2g->bw20_diff[path][i] & BIT(3))
1503                         pwr2g->bw20_diff[path][i] |= 0xF0;
1504         }
1505
1506         if (hwinfo[eadr] == 0xFF) {
1507                 pwr2g->ofdm_diff[path][i] = 0x04;
1508         } else {
1509                 pwr2g->ofdm_diff[path][i] = (hwinfo[eadr] & 0x0f);
1510                 /*bit sign number to 8 bit sign number*/
1511                 if (pwr2g->ofdm_diff[path][i] & BIT(3))
1512                         pwr2g->ofdm_diff[path][i] |= 0xF0;
1513         }
1514         pwr2g->cck_diff[path][i] = 0;
1515 }
1516
1517 static void set_diff0_5g(struct txpower_info_5g *pwr5g, u8 *hwinfo, u32 path,
1518                          u32 i, u32 eadr)
1519 {
1520         pwr5g->bw40_diff[path][i] = 0;
1521         if (hwinfo[eadr] == 0xFF) {
1522                 pwr5g->bw20_diff[path][i] = 0;
1523         } else {
1524                 pwr5g->bw20_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1525                 /*bit sign number to 8 bit sign number*/
1526                 if (pwr5g->bw20_diff[path][i] & BIT(3))
1527                         pwr5g->bw20_diff[path][i] |= 0xF0;
1528         }
1529
1530         if (hwinfo[eadr] == 0xFF) {
1531                 pwr5g->ofdm_diff[path][i] = 0x04;
1532         } else {
1533                 pwr5g->ofdm_diff[path][i] = (hwinfo[eadr] & 0x0f);
1534                 /*bit sign number to 8 bit sign number*/
1535                 if (pwr5g->ofdm_diff[path][i] & BIT(3))
1536                         pwr5g->ofdm_diff[path][i] |= 0xF0;
1537         }
1538 }
1539
1540 static void set_diff1_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1541                          u32 i, u32 eadr)
1542 {
1543         if (hwinfo[eadr] == 0xFF) {
1544                 pwr2g->bw40_diff[path][i] = 0xFE;
1545         } else {
1546                 pwr2g->bw40_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1547                 if (pwr2g->bw40_diff[path][i] & BIT(3))
1548                         pwr2g->bw40_diff[path][i] |= 0xF0;
1549         }
1550
1551         if (hwinfo[eadr] == 0xFF) {
1552                 pwr2g->bw20_diff[path][i] = 0xFE;
1553         } else {
1554                 pwr2g->bw20_diff[path][i] = (hwinfo[eadr]&0x0f);
1555                 if (pwr2g->bw20_diff[path][i] & BIT(3))
1556                         pwr2g->bw20_diff[path][i] |= 0xF0;
1557         }
1558 }
1559
1560 static void set_diff1_5g(struct txpower_info_5g *pwr5g, u8 *hwinfo, u32 path,
1561                          u32 i, u32 eadr)
1562 {
1563         if (hwinfo[eadr] == 0xFF) {
1564                 pwr5g->bw40_diff[path][i] = 0xFE;
1565         } else {
1566                 pwr5g->bw40_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1567                 if (pwr5g->bw40_diff[path][i] & BIT(3))
1568                         pwr5g->bw40_diff[path][i] |= 0xF0;
1569         }
1570
1571         if (hwinfo[eadr] == 0xFF) {
1572                 pwr5g->bw20_diff[path][i] = 0xFE;
1573         } else {
1574                 pwr5g->bw20_diff[path][i] = (hwinfo[eadr] & 0x0f);
1575                 if (pwr5g->bw20_diff[path][i] & BIT(3))
1576                         pwr5g->bw20_diff[path][i] |= 0xF0;
1577         }
1578 }
1579
1580 static void set_diff2_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1581                          u32 i, u32 eadr)
1582 {
1583         if (hwinfo[eadr] == 0xFF) {
1584                 pwr2g->ofdm_diff[path][i] = 0xFE;
1585         } else {
1586                 pwr2g->ofdm_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1587                 if (pwr2g->ofdm_diff[path][i] & BIT(3))
1588                         pwr2g->ofdm_diff[path][i] |= 0xF0;
1589         }
1590
1591         if (hwinfo[eadr] == 0xFF) {
1592                 pwr2g->cck_diff[path][i] = 0xFE;
1593         } else {
1594                 pwr2g->cck_diff[path][i] = (hwinfo[eadr]&0x0f);
1595                 if (pwr2g->cck_diff[path][i] & BIT(3))
1596                         pwr2g->cck_diff[path][i] |= 0xF0;
1597         }
1598 }
1599
1600 static void _rtl8188e_read_power_value_fromprom(struct ieee80211_hw *hw,
1601                                                 struct txpower_info_2g *pwr2g,
1602                                                 struct txpower_info_5g *pwr5g,
1603                                                 bool autoload_fail,
1604                                                 u8 *hwinfo)
1605 {
1606         struct rtl_priv *rtlpriv = rtl_priv(hw);
1607         u32 path, eadr = EEPROM_TX_PWR_INX, i;
1608
1609         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1610                  "hal_ReadPowerValueFromPROM88E(): PROMContent[0x%x]= 0x%x\n",
1611                  (eadr+1), hwinfo[eadr+1]);
1612         if (0xFF == hwinfo[eadr+1])
1613                 autoload_fail = true;
1614
1615         if (autoload_fail) {
1616                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1617                          "auto load fail : Use Default value!\n");
1618                 for (path = 0; path < MAX_RF_PATH; path++) {
1619                         /* 2.4G default value */
1620                         for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1621                                 pwr2g->index_cck_base[path][i] = 0x2D;
1622                                 pwr2g->index_bw40_base[path][i] = 0x2D;
1623                         }
1624                         for (i = 0; i < MAX_TX_COUNT; i++) {
1625                                 if (i == 0) {
1626                                         pwr2g->bw20_diff[path][0] = 0x02;
1627                                         pwr2g->ofdm_diff[path][0] = 0x04;
1628                                 } else {
1629                                         pwr2g->bw20_diff[path][i] = 0xFE;
1630                                         pwr2g->bw40_diff[path][i] = 0xFE;
1631                                         pwr2g->cck_diff[path][i] = 0xFE;
1632                                         pwr2g->ofdm_diff[path][i] = 0xFE;
1633                                 }
1634                         }
1635                 }
1636                 return;
1637         }
1638
1639         for (path = 0; path < MAX_RF_PATH; path++) {
1640                 /*2.4G default value*/
1641                 for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1642                         pwr2g->index_cck_base[path][i] = hwinfo[eadr++];
1643                         if (pwr2g->index_cck_base[path][i] == 0xFF)
1644                                 pwr2g->index_cck_base[path][i] = 0x2D;
1645                 }
1646                 for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1647                         pwr2g->index_bw40_base[path][i] = hwinfo[eadr++];
1648                         if (pwr2g->index_bw40_base[path][i] == 0xFF)
1649                                 pwr2g->index_bw40_base[path][i] = 0x2D;
1650                 }
1651                 for (i = 0; i < MAX_TX_COUNT; i++) {
1652                         if (i == 0) {
1653                                 set_diff0_2g(pwr2g, hwinfo, path, i, eadr);
1654                                 eadr++;
1655                         } else {
1656                                 set_diff1_2g(pwr2g, hwinfo, path, i, eadr);
1657                                 eadr++;
1658
1659                                 set_diff2_2g(pwr2g, hwinfo, path, i, eadr);
1660                                 eadr++;
1661                         }
1662                 }
1663
1664                 /*5G default value*/
1665                 for (i = 0; i < MAX_CHNL_GROUP_5G; i++) {
1666                         pwr5g->index_bw40_base[path][i] = hwinfo[eadr++];
1667                         if (pwr5g->index_bw40_base[path][i] == 0xFF)
1668                                 pwr5g->index_bw40_base[path][i] = 0xFE;
1669                 }
1670
1671                 for (i = 0; i < MAX_TX_COUNT; i++) {
1672                         if (i == 0) {
1673                                 set_diff0_5g(pwr5g, hwinfo, path, i, eadr);
1674                                 eadr++;
1675                         } else {
1676                                 set_diff1_5g(pwr5g, hwinfo, path, i, eadr);
1677                                 eadr++;
1678                         }
1679                 }
1680
1681                 if (hwinfo[eadr] == 0xFF) {
1682                         pwr5g->ofdm_diff[path][1] = 0xFE;
1683                         pwr5g->ofdm_diff[path][2] = 0xFE;
1684                 } else {
1685                         pwr5g->ofdm_diff[path][1] = (hwinfo[eadr] & 0xf0) >> 4;
1686                         pwr5g->ofdm_diff[path][2] = (hwinfo[eadr] & 0x0f);
1687                 }
1688                 eadr++;
1689
1690                 if (hwinfo[eadr] == 0xFF)
1691                         pwr5g->ofdm_diff[path][3] = 0xFE;
1692                 else
1693                         pwr5g->ofdm_diff[path][3] = (hwinfo[eadr]&0x0f);
1694                 eadr++;
1695
1696                 for (i = 1; i < MAX_TX_COUNT; i++) {
1697                         if (pwr5g->ofdm_diff[path][i] == 0xFF)
1698                                 pwr5g->ofdm_diff[path][i] = 0xFE;
1699                         else if (pwr5g->ofdm_diff[path][i] & BIT(3))
1700                                 pwr5g->ofdm_diff[path][i] |= 0xF0;
1701                 }
1702         }
1703 }
1704
1705 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1706                                                  bool autoload_fail,
1707                                                  u8 *hwinfo)
1708 {
1709         struct rtl_priv *rtlpriv = rtl_priv(hw);
1710         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1711         struct txpower_info_2g pwrinfo24g;
1712         struct txpower_info_5g pwrinfo5g;
1713         u8 rf_path, index;
1714         u8 i;
1715         int jj = EEPROM_RF_BOARD_OPTION_88E;
1716         int kk = EEPROM_THERMAL_METER_88E;
1717
1718         _rtl8188e_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g,
1719                                             autoload_fail, hwinfo);
1720
1721         for (rf_path = 0; rf_path < 2; rf_path++) {
1722                 for (i = 0; i < 14; i++) {
1723                         index = get_chnl_group(i+1);
1724
1725                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1726                                  pwrinfo24g.index_cck_base[rf_path][index];
1727                         if (i == 13)
1728                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1729                                      pwrinfo24g.index_bw40_base[rf_path][4];
1730                         else
1731                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1732                                      pwrinfo24g.index_bw40_base[rf_path][index];
1733                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1734                                  pwrinfo24g.bw20_diff[rf_path][0];
1735                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1736                                  pwrinfo24g.ofdm_diff[rf_path][0];
1737                 }
1738
1739                 for (i = 0; i < 14; i++) {
1740                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1741                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = "
1742                                 "[0x%x / 0x%x ]\n", rf_path, i,
1743                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1744                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1745                 }
1746         }
1747
1748         if (!autoload_fail)
1749                 rtlefuse->eeprom_thermalmeter = hwinfo[kk];
1750         else
1751                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1752
1753         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1754                 rtlefuse->apk_thermalmeterignore = true;
1755                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1756         }
1757
1758         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1759         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1760                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1761
1762         if (!autoload_fail) {
1763                 rtlefuse->eeprom_regulatory = hwinfo[jj] & 0x07;/*bit0~2*/
1764                 if (hwinfo[jj] == 0xFF)
1765                         rtlefuse->eeprom_regulatory = 0;
1766         } else {
1767                 rtlefuse->eeprom_regulatory = 0;
1768         }
1769         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1770                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1771 }
1772
1773 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1774 {
1775         struct rtl_priv *rtlpriv = rtl_priv(hw);
1776         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1777         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1778         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
1779         u16 i, usvalue;
1780         u8 hwinfo[HWSET_MAX_SIZE];
1781         u16 eeprom_id;
1782         int jj = EEPROM_RF_BOARD_OPTION_88E;
1783         int kk = EEPROM_RF_FEATURE_OPTION_88E;
1784
1785         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1786                 rtl_efuse_shadow_map_update(hw);
1787
1788                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1789                        HWSET_MAX_SIZE);
1790         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1791                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1792                          "RTL819X Not boot from eeprom, check it !!");
1793         }
1794
1795         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1796                       hwinfo, HWSET_MAX_SIZE);
1797
1798         eeprom_id = *((u16 *)&hwinfo[0]);
1799         if (eeprom_id != RTL8188E_EEPROM_ID) {
1800                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1801                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1802                 rtlefuse->autoload_failflag = true;
1803         } else {
1804                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1805                 rtlefuse->autoload_failflag = false;
1806         }
1807
1808         if (rtlefuse->autoload_failflag == true)
1809                 return;
1810         /*VID DID SVID SDID*/
1811         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1812         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1813         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1814         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1815         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1816                  "EEPROMId = 0x%4x\n", eeprom_id);
1817         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1818                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1819         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1820                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1821         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1822                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1823         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1824                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1825         /*customer ID*/
1826         rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
1827         if (rtlefuse->eeprom_oemid == 0xFF)
1828                 rtlefuse->eeprom_oemid = 0;
1829
1830         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1831                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1832         /*EEPROM version*/
1833         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1834         /*mac address*/
1835         for (i = 0; i < 6; i += 2) {
1836                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1837                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1838         }
1839
1840         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1841                  "dev_addr: %pM\n", rtlefuse->dev_addr);
1842         /*channel plan */
1843         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1844         /* set channel paln to world wide 13 */
1845         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1846         /*tx power*/
1847         _rtl88ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1848                                              hwinfo);
1849         rtlefuse->txpwr_fromeprom = true;
1850
1851         rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1852                                                  rtlefuse->autoload_failflag,
1853                                                  hwinfo);
1854         /*board type*/
1855         rtlefuse->board_type = (hwinfo[jj] & 0xE0) >> 5;
1856         /*Wake on wlan*/
1857         rtlefuse->wowlan_enable = ((hwinfo[kk] & 0x40) >> 6);
1858         /*parse xtal*/
1859         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1860         if (hwinfo[EEPROM_XTAL_88E])
1861                 rtlefuse->crystalcap = 0x20;
1862         /*antenna diversity*/
1863         rtlefuse->antenna_div_cfg = (hwinfo[jj] & 0x18) >> 3;
1864         if (hwinfo[jj] == 0xFF)
1865                 rtlefuse->antenna_div_cfg = 0;
1866         if (rppriv->bt_coexist.eeprom_bt_coexist != 0 &&
1867             rppriv->bt_coexist.eeprom_bt_ant_num == ANT_X1)
1868                 rtlefuse->antenna_div_cfg = 0;
1869
1870         rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1871         if (rtlefuse->antenna_div_type == 0xFF)
1872                 rtlefuse->antenna_div_type = 0x01;
1873         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1874             rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1875                 rtlefuse->antenna_div_cfg = 1;
1876
1877         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1878                 switch (rtlefuse->eeprom_oemid) {
1879                 case EEPROM_CID_DEFAULT:
1880                         if (rtlefuse->eeprom_did == 0x8179) {
1881                                 if (rtlefuse->eeprom_svid == 0x1025) {
1882                                         rtlhal->oem_id = RT_CID_819X_ACER;
1883                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1884                                             rtlefuse->eeprom_smid == 0x0179) ||
1885                                             (rtlefuse->eeprom_svid == 0x17AA &&
1886                                             rtlefuse->eeprom_smid == 0x0179)) {
1887                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
1888                                 } else if (rtlefuse->eeprom_svid == 0x103c &&
1889                                          rtlefuse->eeprom_smid == 0x197d) {
1890                                         rtlhal->oem_id = RT_CID_819X_HP;
1891                                 } else {
1892                                         rtlhal->oem_id = RT_CID_DEFAULT;
1893                                 }
1894                         } else {
1895                                 rtlhal->oem_id = RT_CID_DEFAULT;
1896                         }
1897                         break;
1898                 case EEPROM_CID_TOSHIBA:
1899                         rtlhal->oem_id = RT_CID_TOSHIBA;
1900                         break;
1901                 case EEPROM_CID_QMI:
1902                         rtlhal->oem_id = RT_CID_819X_QMI;
1903                         break;
1904                 case EEPROM_CID_WHQL:
1905                 default:
1906                         rtlhal->oem_id = RT_CID_DEFAULT;
1907                         break;
1908                 }
1909         }
1910 }
1911
1912 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1913 {
1914         struct rtl_priv *rtlpriv = rtl_priv(hw);
1915         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1916         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1917
1918         pcipriv->ledctl.led_opendrain = true;
1919
1920         switch (rtlhal->oem_id) {
1921         case RT_CID_819X_HP:
1922                 pcipriv->ledctl.led_opendrain = true;
1923                 break;
1924         case RT_CID_819X_LENOVO:
1925         case RT_CID_DEFAULT:
1926         case RT_CID_TOSHIBA:
1927         case RT_CID_CCX:
1928         case RT_CID_819X_ACER:
1929         case RT_CID_WHQL:
1930         default:
1931                 break;
1932         }
1933         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1934                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1935 }
1936
1937 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1938 {
1939         struct rtl_priv *rtlpriv = rtl_priv(hw);
1940         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1941         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1942         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1943         u8 tmp_u1b;
1944
1945         rtlhal->version = _rtl88ee_read_chip_version(hw);
1946         if (get_rf_type(rtlphy) == RF_1T1R) {
1947                 rtlpriv->dm.rfpath_rxenable[0] = true;
1948         } else {
1949                 rtlpriv->dm.rfpath_rxenable[0] = true;
1950                 rtlpriv->dm.rfpath_rxenable[1] = true;
1951         }
1952         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1953                  rtlhal->version);
1954         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1955         if (tmp_u1b & BIT(4)) {
1956                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1957                 rtlefuse->epromtype = EEPROM_93C46;
1958         } else {
1959                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1960                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1961         }
1962         if (tmp_u1b & BIT(5)) {
1963                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1964                 rtlefuse->autoload_failflag = false;
1965                 _rtl88ee_read_adapter_info(hw);
1966         } else {
1967                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1968         }
1969         _rtl88ee_hal_customized_behavior(hw);
1970 }
1971
1972 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1973                                           struct ieee80211_sta *sta)
1974 {
1975         struct rtl_priv *rtlpriv = rtl_priv(hw);
1976         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
1977         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1978         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1979         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1980         u32 ratr_value;
1981         u8 ratr_index = 0;
1982         u8 nmode = mac->ht_enable;
1983         u8 mimo_ps = IEEE80211_SMPS_OFF;
1984         u16 shortgi_rate;
1985         u32 tmp_ratr_value;
1986         u8 ctx40 = mac->bw_40;
1987         u16 cap = sta->ht_cap.cap;
1988         u8 short40 = (cap & IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
1989         u8 short20 = (cap & IEEE80211_HT_CAP_SGI_20) ?  1 : 0;
1990         enum wireless_mode wirelessmode = mac->mode;
1991
1992         if (rtlhal->current_bandtype == BAND_ON_5G)
1993                 ratr_value = sta->supp_rates[1] << 4;
1994         else
1995                 ratr_value = sta->supp_rates[0];
1996         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1997                 ratr_value = 0xfff;
1998         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1999                         sta->ht_cap.mcs.rx_mask[0] << 12);
2000         switch (wirelessmode) {
2001         case WIRELESS_MODE_B:
2002                 if (ratr_value & 0x0000000c)
2003                         ratr_value &= 0x0000000d;
2004                 else
2005                         ratr_value &= 0x0000000f;
2006                 break;
2007         case WIRELESS_MODE_G:
2008                 ratr_value &= 0x00000FF5;
2009                 break;
2010         case WIRELESS_MODE_N_24G:
2011         case WIRELESS_MODE_N_5G:
2012                 nmode = 1;
2013                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2014                         ratr_value &= 0x0007F005;
2015                 } else {
2016                         u32 ratr_mask;
2017
2018                         if (get_rf_type(rtlphy) == RF_1T2R ||
2019                             get_rf_type(rtlphy) == RF_1T1R)
2020                                 ratr_mask = 0x000ff005;
2021                         else
2022                                 ratr_mask = 0x0f0ff005;
2023
2024                         ratr_value &= ratr_mask;
2025                 }
2026                 break;
2027         default:
2028                 if (rtlphy->rf_type == RF_1T2R)
2029                         ratr_value &= 0x000ff0ff;
2030                 else
2031                         ratr_value &= 0x0f0ff0ff;
2032
2033                 break;
2034         }
2035
2036         if ((rppriv->bt_coexist.bt_coexistence) &&
2037             (rppriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
2038             (rppriv->bt_coexist.bt_cur_state) &&
2039             (rppriv->bt_coexist.bt_ant_isolation) &&
2040             ((rppriv->bt_coexist.bt_service == BT_SCO) ||
2041             (rppriv->bt_coexist.bt_service == BT_BUSY)))
2042                 ratr_value &= 0x0fffcfc0;
2043         else
2044                 ratr_value &= 0x0FFFFFFF;
2045
2046         if (nmode && ((ctx40 && short40) ||
2047                       (!ctx40 && short20))) {
2048                 ratr_value |= 0x10000000;
2049                 tmp_ratr_value = (ratr_value >> 12);
2050
2051                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2052                         if ((1 << shortgi_rate) & tmp_ratr_value)
2053                                 break;
2054                 }
2055
2056                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2057                     (shortgi_rate << 4) | (shortgi_rate);
2058         }
2059
2060         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2061
2062         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2063                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2064 }
2065
2066 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2067                                          struct ieee80211_sta *sta, u8 rssi)
2068 {
2069         struct rtl_priv *rtlpriv = rtl_priv(hw);
2070         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2071         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2072         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2073         struct rtl_sta_info *sta_entry = NULL;
2074         u32 ratr_bitmap;
2075         u8 ratr_index;
2076         u16 cap = sta->ht_cap.cap;
2077         u8 ctx40 = (cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2078         u8 short40 = (cap & IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
2079         u8 short20 = (cap & IEEE80211_HT_CAP_SGI_20) ?  1 : 0;
2080         enum wireless_mode wirelessmode = 0;
2081         bool shortgi = false;
2082         u8 rate_mask[5];
2083         u8 macid = 0;
2084         u8 mimo_ps = IEEE80211_SMPS_OFF;
2085
2086         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2087         wirelessmode = sta_entry->wireless_mode;
2088         if (mac->opmode == NL80211_IFTYPE_STATION ||
2089             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2090                 ctx40 = mac->bw_40;
2091         else if (mac->opmode == NL80211_IFTYPE_AP ||
2092                  mac->opmode == NL80211_IFTYPE_ADHOC)
2093                 macid = sta->aid + 1;
2094
2095         if (rtlhal->current_bandtype == BAND_ON_5G)
2096                 ratr_bitmap = sta->supp_rates[1] << 4;
2097         else
2098                 ratr_bitmap = sta->supp_rates[0];
2099         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2100                 ratr_bitmap = 0xfff;
2101         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2102                         sta->ht_cap.mcs.rx_mask[0] << 12);
2103         switch (wirelessmode) {
2104         case WIRELESS_MODE_B:
2105                 ratr_index = RATR_INX_WIRELESS_B;
2106                 if (ratr_bitmap & 0x0000000c)
2107                         ratr_bitmap &= 0x0000000d;
2108                 else
2109                         ratr_bitmap &= 0x0000000f;
2110                 break;
2111         case WIRELESS_MODE_G:
2112                 ratr_index = RATR_INX_WIRELESS_GB;
2113
2114                 if (rssi == 1)
2115                         ratr_bitmap &= 0x00000f00;
2116                 else if (rssi == 2)
2117                         ratr_bitmap &= 0x00000ff0;
2118                 else
2119                         ratr_bitmap &= 0x00000ff5;
2120                 break;
2121         case WIRELESS_MODE_A:
2122                 ratr_index = RATR_INX_WIRELESS_A;
2123                 ratr_bitmap &= 0x00000ff0;
2124                 break;
2125         case WIRELESS_MODE_N_24G:
2126         case WIRELESS_MODE_N_5G:
2127                 ratr_index = RATR_INX_WIRELESS_NGB;
2128
2129                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2130                         if (rssi == 1)
2131                                 ratr_bitmap &= 0x00070000;
2132                         else if (rssi == 2)
2133                                 ratr_bitmap &= 0x0007f000;
2134                         else
2135                                 ratr_bitmap &= 0x0007f005;
2136                 } else {
2137                         if (rtlphy->rf_type == RF_1T2R ||
2138                             rtlphy->rf_type == RF_1T1R) {
2139                                 if (ctx40) {
2140                                         if (rssi == 1)
2141                                                 ratr_bitmap &= 0x000f0000;
2142                                         else if (rssi == 2)
2143                                                 ratr_bitmap &= 0x000ff000;
2144                                         else
2145                                                 ratr_bitmap &= 0x000ff015;
2146                                 } else {
2147                                         if (rssi == 1)
2148                                                 ratr_bitmap &= 0x000f0000;
2149                                         else if (rssi == 2)
2150                                                 ratr_bitmap &= 0x000ff000;
2151                                         else
2152                                                 ratr_bitmap &= 0x000ff005;
2153                                 }
2154                         } else {
2155                                 if (ctx40) {
2156                                         if (rssi == 1)
2157                                                 ratr_bitmap &= 0x0f8f0000;
2158                                         else if (rssi == 2)
2159                                                 ratr_bitmap &= 0x0f8ff000;
2160                                         else
2161                                                 ratr_bitmap &= 0x0f8ff015;
2162                                 } else {
2163                                         if (rssi == 1)
2164                                                 ratr_bitmap &= 0x0f8f0000;
2165                                         else if (rssi == 2)
2166                                                 ratr_bitmap &= 0x0f8ff000;
2167                                         else
2168                                                 ratr_bitmap &= 0x0f8ff005;
2169                                 }
2170                         }
2171                 }
2172
2173                 if ((ctx40 && short40) || (!ctx40 && short20)) {
2174                         if (macid == 0)
2175                                 shortgi = true;
2176                         else if (macid == 1)
2177                                 shortgi = false;
2178                 }
2179                 break;
2180         default:
2181                 ratr_index = RATR_INX_WIRELESS_NGB;
2182
2183                 if (rtlphy->rf_type == RF_1T2R)
2184                         ratr_bitmap &= 0x000ff0ff;
2185                 else
2186                         ratr_bitmap &= 0x0f0ff0ff;
2187                 break;
2188         }
2189         sta_entry->ratr_index = ratr_index;
2190
2191         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2192                  "ratr_bitmap :%x\n", ratr_bitmap);
2193         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2194                              (ratr_index << 28);
2195         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2196         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2197                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2198                  ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2199                  rate_mask[2], rate_mask[3], rate_mask[4]);
2200         rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2201         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2202 }
2203
2204 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2205                 struct ieee80211_sta *sta, u8 rssi)
2206 {
2207         struct rtl_priv *rtlpriv = rtl_priv(hw);
2208
2209         if (rtlpriv->dm.useramask)
2210                 rtl88ee_update_hal_rate_mask(hw, sta, rssi);
2211         else
2212                 rtl88ee_update_hal_rate_table(hw, sta);
2213 }
2214
2215 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2216 {
2217         struct rtl_priv *rtlpriv = rtl_priv(hw);
2218         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2219         u16 sifs_timer;
2220
2221         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2222         if (!mac->ht_enable)
2223                 sifs_timer = 0x0a0a;
2224         else
2225                 sifs_timer = 0x0e0e;
2226         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2227 }
2228
2229 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2230 {
2231         struct rtl_priv *rtlpriv = rtl_priv(hw);
2232         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2233         enum rf_pwrstate state_toset;
2234         u32 u4tmp;
2235         bool actuallyset = false;
2236
2237         if (rtlpriv->rtlhal.being_init_adapter)
2238                 return false;
2239
2240         if (ppsc->swrf_processing)
2241                 return false;
2242
2243         spin_lock(&rtlpriv->locks.rf_ps_lock);
2244         if (ppsc->rfchange_inprogress) {
2245                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2246                 return false;
2247         } else {
2248                 ppsc->rfchange_inprogress = true;
2249                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2250         }
2251
2252         u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2253         state_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2254
2255
2256         if ((ppsc->hwradiooff == true) && (state_toset == ERFON)) {
2257                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2258                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2259
2260                 state_toset = ERFON;
2261                 ppsc->hwradiooff = false;
2262                 actuallyset = true;
2263         } else if ((ppsc->hwradiooff == false) && (state_toset == ERFOFF)) {
2264                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2265                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2266
2267                 state_toset = ERFOFF;
2268                 ppsc->hwradiooff = true;
2269                 actuallyset = true;
2270         }
2271
2272         if (actuallyset) {
2273                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2274                 ppsc->rfchange_inprogress = false;
2275                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2276         } else {
2277                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2278                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2279
2280                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2281                 ppsc->rfchange_inprogress = false;
2282                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2283         }
2284
2285         *valid = 1;
2286         return !ppsc->hwradiooff;
2287 }
2288
2289 static void add_one_key(struct ieee80211_hw *hw, u8 *macaddr,
2290                         struct rtl_mac *mac, u32 key, u32 id,
2291                         u8 enc_algo, bool is_pairwise)
2292 {
2293         struct rtl_priv *rtlpriv = rtl_priv(hw);
2294         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2295
2296         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "add one entry\n");
2297         if (is_pairwise) {
2298                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "set Pairwise key\n");
2299
2300                 rtl_cam_add_one_entry(hw, macaddr, key, id, enc_algo,
2301                                       CAM_CONFIG_NO_USEDK,
2302                                       rtlpriv->sec.key_buf[key]);
2303         } else {
2304                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "set group key\n");
2305
2306                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2307                         rtl_cam_add_one_entry(hw, rtlefuse->dev_addr,
2308                                               PAIRWISE_KEYIDX,
2309                                               CAM_PAIRWISE_KEY_POSITION,
2310                                               enc_algo,
2311                                               CAM_CONFIG_NO_USEDK,
2312                                               rtlpriv->sec.key_buf[id]);
2313                 }
2314
2315                 rtl_cam_add_one_entry(hw, macaddr, key, id, enc_algo,
2316                                       CAM_CONFIG_NO_USEDK,
2317                                       rtlpriv->sec.key_buf[id]);
2318         }
2319 }
2320
2321 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key,
2322                      u8 *mac_ad, bool is_group, u8 enc_algo,
2323                      bool is_wepkey, bool clear_all)
2324 {
2325         struct rtl_priv *rtlpriv = rtl_priv(hw);
2326         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2327         u8 *macaddr = mac_ad;
2328         u32 id = 0;
2329         bool is_pairwise = false;
2330
2331         static u8 cam_const_addr[4][6] = {
2332                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2333                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2334                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2335                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2336         };
2337         static u8 cam_const_broad[] = {
2338                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2339         };
2340
2341         if (clear_all) {
2342                 u8 idx = 0;
2343                 u8 cam_offset = 0;
2344                 u8 clear_number = 5;
2345
2346                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2347
2348                 for (idx = 0; idx < clear_number; idx++) {
2349                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2350                         rtl_cam_empty_entry(hw, cam_offset + idx);
2351
2352                         if (idx < 5) {
2353                                 memset(rtlpriv->sec.key_buf[idx], 0,
2354                                        MAX_KEY_LEN);
2355                                 rtlpriv->sec.key_len[idx] = 0;
2356                         }
2357                 }
2358
2359         } else {
2360                 switch (enc_algo) {
2361                 case WEP40_ENCRYPTION:
2362                         enc_algo = CAM_WEP40;
2363                         break;
2364                 case WEP104_ENCRYPTION:
2365                         enc_algo = CAM_WEP104;
2366                         break;
2367                 case TKIP_ENCRYPTION:
2368                         enc_algo = CAM_TKIP;
2369                         break;
2370                 case AESCCMP_ENCRYPTION:
2371                         enc_algo = CAM_AES;
2372                         break;
2373                 default:
2374                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2375                                  "switch case not processed\n");
2376                         enc_algo = CAM_TKIP;
2377                         break;
2378                 }
2379
2380                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2381                         macaddr = cam_const_addr[key];
2382                         id = key;
2383                 } else {
2384                         if (is_group) {
2385                                 macaddr = cam_const_broad;
2386                                 id = key;
2387                         } else {
2388                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2389                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2390                                         id = rtl_cam_get_free_entry(hw, mac_ad);
2391                                         if (id >=  TOTAL_CAM_ENTRY) {
2392                                                 RT_TRACE(rtlpriv, COMP_SEC,
2393                                                          DBG_EMERG,
2394                                                          "Can not find free hw security cam entry\n");
2395                                                 return;
2396                                         }
2397                                 } else {
2398                                         id = CAM_PAIRWISE_KEY_POSITION;
2399                                 }
2400
2401                                 key = PAIRWISE_KEYIDX;
2402                                 is_pairwise = true;
2403                         }
2404                 }
2405
2406                 if (rtlpriv->sec.key_len[key] == 0) {
2407                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2408                                  "delete one entry, id is %d\n", id);
2409                         if (mac->opmode == NL80211_IFTYPE_AP ||
2410                             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2411                                 rtl_cam_del_entry(hw, mac_ad);
2412                         rtl_cam_delete_one_entry(hw, mac_ad, id);
2413                 } else {
2414                         add_one_key(hw, macaddr, mac, key, id, enc_algo,
2415                                     is_pairwise);
2416                 }
2417         }
2418 }
2419
2420 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2421 {
2422         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2423         struct bt_coexist_info coexist = rppriv->bt_coexist;
2424
2425         coexist.bt_coexistence = rppriv->bt_coexist.eeprom_bt_coexist;
2426         coexist.bt_ant_num = coexist.eeprom_bt_ant_num;
2427         coexist.bt_coexist_type = coexist.eeprom_bt_type;
2428
2429         if (coexist.reg_bt_iso == 2)
2430                 coexist.bt_ant_isolation = coexist.eeprom_bt_ant_isol;
2431         else
2432                 coexist.bt_ant_isolation = coexist.reg_bt_iso;
2433
2434         coexist.bt_radio_shared_type = coexist.eeprom_bt_radio_shared;
2435
2436         if (coexist.bt_coexistence) {
2437                 if (coexist.reg_bt_sco == 1)
2438                         coexist.bt_service = BT_OTHER_ACTION;
2439                 else if (coexist.reg_bt_sco == 2)
2440                         coexist.bt_service = BT_SCO;
2441                 else if (coexist.reg_bt_sco == 4)
2442                         coexist.bt_service = BT_BUSY;
2443                 else if (coexist.reg_bt_sco == 5)
2444                         coexist.bt_service = BT_OTHERBUSY;
2445                 else
2446                         coexist.bt_service = BT_IDLE;
2447
2448                 coexist.bt_edca_ul = 0;
2449                 coexist.bt_edca_dl = 0;
2450                 coexist.bt_rssi_state = 0xff;
2451         }
2452 }
2453
2454 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2455                                               bool auto_load_fail, u8 *hwinfo)
2456 {
2457         rtl8188ee_bt_var_init(hw);
2458 }
2459
2460 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2461 {
2462         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2463
2464         /* 0:Low, 1:High, 2:From Efuse. */
2465         rppriv->bt_coexist.reg_bt_iso = 2;
2466         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2467         rppriv->bt_coexist.reg_bt_sco = 3;
2468         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2469         rppriv->bt_coexist.reg_bt_sco = 0;
2470 }
2471
2472 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2473 {
2474         struct rtl_priv *rtlpriv = rtl_priv(hw);
2475         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2476         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2477         struct bt_coexist_info coexist = rppriv->bt_coexist;
2478         u8 u1_tmp;
2479
2480         if (coexist.bt_coexistence &&
2481             ((coexist.bt_coexist_type == BT_CSR_BC4) ||
2482               coexist.bt_coexist_type == BT_CSR_BC8)) {
2483                 if (coexist.bt_ant_isolation)
2484                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2485
2486                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2487                                        BIT_OFFSET_LEN_MASK_32(0, 1);
2488                 u1_tmp = u1_tmp | ((coexist.bt_ant_isolation == 1) ?
2489                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2490                          ((coexist.bt_service == BT_SCO) ?
2491                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2492                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2493
2494                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2495                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2496                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2497
2498                 /* Config to 1T1R. */
2499                 if (rtlphy->rf_type == RF_1T1R) {
2500                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2501                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2502                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2503
2504                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2505                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2506                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2507                 }
2508         }
2509 }
2510
2511 void rtl88ee_suspend(struct ieee80211_hw *hw)
2512 {
2513 }
2514
2515 void rtl88ee_resume(struct ieee80211_hw *hw)
2516 {
2517 }