drivers/net/ethernet/sfc/tx.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/tcp.h>
  13 #include <linux/ip.h>
  14 #include <linux/in.h>
  15 #include <linux/ipv6.h>
  16 #include <linux/slab.h>
  17 #include <net/ipv6.h>
  18 #include <linux/if_ether.h>
  19 #include <linux/highmem.h>
  20 #include <linux/cache.h>
  21 #include "net_driver.h"
  22 #include "efx.h"
  23 #include "io.h"
  24 #include "nic.h"
  25 #include "workarounds.h"
  26 #include "ef10_regs.h"
  27
  28 #ifdef EFX_USE_PIO
  29
  30 #define EFX_PIOBUF_SIZE_MAX ER_DZ_TX_PIOBUF_SIZE
  31 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
  32 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
  33
  34 #endif /* EFX_USE_PIO */
  35
  36 static inline unsigned int
  37 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
  38 {
  39         return tx_queue->insert_count & tx_queue->ptr_mask;
  40 }
  41
  42 static inline struct efx_tx_buffer *
  43 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
  44 {
  45         return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
  46 }
  47
  48 static inline struct efx_tx_buffer *
  49 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
  50 {
  51         struct efx_tx_buffer *buffer =
  52                 __efx_tx_queue_get_insert_buffer(tx_queue);
  53
  54         EFX_BUG_ON_PARANOID(buffer->len);
  55         EFX_BUG_ON_PARANOID(buffer->flags);
  56         EFX_BUG_ON_PARANOID(buffer->unmap_len);
  57
  58         return buffer;
  59 }
  60
  61 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  62                                struct efx_tx_buffer *buffer,
  63                                unsigned int *pkts_compl,
  64                                unsigned int *bytes_compl)
  65 {
  66         if (buffer->unmap_len) {
  67                 struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
  68                 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
  69                 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
  70                         dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
  71                                          DMA_TO_DEVICE);
  72                 else
  73                         dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
  74                                        DMA_TO_DEVICE);
  75                 buffer->unmap_len = 0;
  76         }
  77
  78         if (buffer->flags & EFX_TX_BUF_SKB) {
  79                 (*pkts_compl)++;
  80                 (*bytes_compl) += buffer->skb->len;
  81                 dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  82                 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
  83                            "TX queue %d transmission id %x complete\n",
  84                            tx_queue->queue, tx_queue->read_count);
  85         } else if (buffer->flags & EFX_TX_BUF_HEAP) {
  86                 kfree(buffer->heap_buf);
  87         }
  88
  89         buffer->len = 0;
  90         buffer->flags = 0;
  91 }
  92
  93 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  94                                struct sk_buff *skb);
  95
  96 static inline unsigned
  97 efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
  98 {
  99         /* Depending on the NIC revision, we can use descriptor
 100          * lengths up to 8K or 8K-1.  However, since PCI Express
 101          * devices must split read requests at 4K boundaries, there is
 102          * little benefit from using descriptors that cross those
 103          * boundaries and we keep things simple by not doing so.
 104          */
 105         unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
 106
 107         /* Work around hardware bug for unaligned buffers. */
 108         if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
 109                 len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
 110
 111         return len;
 112 }
 113
 114 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
 115 {
 116         /* Header and payload descriptor for each output segment, plus
 117          * one for every input fragment boundary within a segment
 118          */
 119         unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
 120
 121         /* Possibly one more per segment for the alignment workaround,
 122          * or for option descriptors
 123          */
 124         if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
 125                 max_descs += EFX_TSO_MAX_SEGS;
 126
 127         /* Possibly more for PCIe page boundaries within input fragments */
 128         if (PAGE_SIZE > EFX_PAGE_SIZE)
 129                 max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
 130                                    DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
 131
 132         return max_descs;
 133 }
 134
 135 /* Get partner of a TX queue, seen as part of the same net core queue */
 136 static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
 137 {
 138         if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
 139                 return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
 140         else
 141                 return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
 142 }
 143
 144 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
 145 {
 146         /* We need to consider both queues that the net core sees as one */
 147         struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1);
 148         struct efx_nic *efx = txq1->efx;
 149         unsigned int fill_level;
 150
 151         fill_level = max(txq1->insert_count - txq1->old_read_count,
 152                          txq2->insert_count - txq2->old_read_count);
 153         if (likely(fill_level < efx->txq_stop_thresh))
 154                 return;
 155
 156         /* We used the stale old_read_count above, which gives us a
 157          * pessimistic estimate of the fill level (which may even
 158          * validly be >= efx->txq_entries).  Now try again using
 159          * read_count (more likely to be a cache miss).
 160          *
 161          * If we read read_count and then conditionally stop the
 162          * queue, it is possible for the completion path to race with
 163          * us and complete all outstanding descriptors in the middle,
 164          * after which there will be no more completions to wake it.
 165          * Therefore we stop the queue first, then read read_count
 166          * (with a memory barrier to ensure the ordering), then
 167          * restart the queue if the fill level turns out to be low
 168          * enough.
 169          */
 170         netif_tx_stop_queue(txq1->core_txq);
 171         smp_mb();
 172         txq1->old_read_count = ACCESS_ONCE(txq1->read_count);
 173         txq2->old_read_count = ACCESS_ONCE(txq2->read_count);
 174
 175         fill_level = max(txq1->insert_count - txq1->old_read_count,
 176                          txq2->insert_count - txq2->old_read_count);
 177         EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries);
 178         if (likely(fill_level < efx->txq_stop_thresh)) {
 179                 smp_mb();
 180                 if (likely(!efx->loopback_selftest))
 181                         netif_tx_start_queue(txq1->core_txq);
 182         }
 183 }
 184
 185 #ifdef EFX_USE_PIO
 186
 187 struct efx_short_copy_buffer {
 188         int used;
 189         u8 buf[L1_CACHE_BYTES];
 190 };
 191
 192 /* Copy in explicit 64-bit writes. */
 193 static void efx_memcpy_64(void __iomem *dest, void *src, size_t len)
 194 {
 195         u64 *src64 = src;
 196         u64 __iomem *dest64 = dest;
 197         size_t l64 = len / 8;
 198         size_t i;
 199
 200         for (i = 0; i < l64; i++)
 201                 writeq(src64[i], &dest64[i]);
 202 }
 203
 204 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
 205  * Advances piobuf pointer. Leaves additional data in the copy buffer.
 206  */
 207 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
 208                                     u8 *data, int len,
 209                                     struct efx_short_copy_buffer *copy_buf)
 210 {
 211         int block_len = len & ~(sizeof(copy_buf->buf) - 1);
 212
 213         efx_memcpy_64(*piobuf, data, block_len);
 214         *piobuf += block_len;
 215         len -= block_len;
 216
 217         if (len) {
 218                 data += block_len;
 219                 BUG_ON(copy_buf->used);
 220                 BUG_ON(len > sizeof(copy_buf->buf));
 221                 memcpy(copy_buf->buf, data, len);
 222                 copy_buf->used = len;
 223         }
 224 }
 225
 226 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
 227  * Advances piobuf pointer. Leaves additional data in the copy buffer.
 228  */
 229 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
 230                                        u8 *data, int len,
 231                                        struct efx_short_copy_buffer *copy_buf)
 232 {
 233         if (copy_buf->used) {
 234                 /* if the copy buffer is partially full, fill it up and write */
 235                 int copy_to_buf =
 236                         min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
 237
 238                 memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
 239                 copy_buf->used += copy_to_buf;
 240
 241                 /* if we didn't fill it up then we're done for now */
 242                 if (copy_buf->used < sizeof(copy_buf->buf))
 243                         return;
 244
 245                 efx_memcpy_64(*piobuf, copy_buf->buf, sizeof(copy_buf->buf));
 246                 *piobuf += sizeof(copy_buf->buf);
 247                 data += copy_to_buf;
 248                 len -= copy_to_buf;
 249                 copy_buf->used = 0;
 250         }
 251
 252         efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
 253 }
 254
 255 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
 256                                   struct efx_short_copy_buffer *copy_buf)
 257 {
 258         /* if there's anything in it, write the whole buffer, including junk */
 259         if (copy_buf->used)
 260                 efx_memcpy_64(piobuf, copy_buf->buf, sizeof(copy_buf->buf));
 261 }
 262
 263 /* Traverse skb structure and copy fragments in to PIO buffer.
 264  * Advances piobuf pointer.
 265  */
 266 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
 267                                      u8 __iomem **piobuf,
 268                                      struct efx_short_copy_buffer *copy_buf)
 269 {
 270         int i;
 271
 272         efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
 273                                 copy_buf);
 274
 275         for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
 276                 skb_frag_t *f = &skb_shinfo(skb)->frags[i];
 277                 u8 *vaddr;
 278
 279                 vaddr = kmap_atomic(skb_frag_page(f));
 280
 281                 efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + f->page_offset,
 282                                            skb_frag_size(f), copy_buf);
 283                 kunmap_atomic(vaddr);
 284         }
 285
 286         EFX_BUG_ON_PARANOID(skb_shinfo(skb)->frag_list);
 287 }
 288
 289 static struct efx_tx_buffer *
 290 efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
 291 {
 292         struct efx_tx_buffer *buffer =
 293                 efx_tx_queue_get_insert_buffer(tx_queue);
 294         u8 __iomem *piobuf = tx_queue->piobuf;
 295
 296         /* Copy to PIO buffer. Ensure the writes are padded to the end
 297          * of a cache line, as this is required for write-combining to be
 298          * effective on at least x86.
 299          */
 300
 301         if (skb_shinfo(skb)->nr_frags) {
 302                 /* The size of the copy buffer will ensure all writes
 303                  * are the size of a cache line.
 304                  */
 305                 struct efx_short_copy_buffer copy_buf;
 306
 307                 copy_buf.used = 0;
 308
 309                 efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
 310                                          &piobuf, &copy_buf);
 311                 efx_flush_copy_buffer(tx_queue->efx, piobuf, &copy_buf);
 312         } else {
 313                 /* Pad the write to the size of a cache line.
 314                  * We can do this because we know the skb_shared_info sruct is
 315                  * after the source, and the destination buffer is big enough.
 316                  */
 317                 BUILD_BUG_ON(L1_CACHE_BYTES >
 318                              SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
 319                 efx_memcpy_64(tx_queue->piobuf, skb->data,
 320                               ALIGN(skb->len, L1_CACHE_BYTES));
 321         }
 322
 323         EFX_POPULATE_QWORD_5(buffer->option,
 324                              ESF_DZ_TX_DESC_IS_OPT, 1,
 325                              ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
 326                              ESF_DZ_TX_PIO_CONT, 0,
 327                              ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
 328                              ESF_DZ_TX_PIO_BUF_ADDR,
 329                              tx_queue->piobuf_offset);
 330         ++tx_queue->pio_packets;
 331         ++tx_queue->insert_count;
 332         return buffer;
 333 }
 334 #endif /* EFX_USE_PIO */
 335
 336 /*
 337  * Add a socket buffer to a TX queue
 338  *
 339  * This maps all fragments of a socket buffer for DMA and adds them to
 340  * the TX queue.  The queue's insert pointer will be incremented by
 341  * the number of fragments in the socket buffer.
 342  *
 343  * If any DMA mapping fails, any mapped fragments will be unmapped,
 344  * the queue's insert pointer will be restored to its original value.
 345  *
 346  * This function is split out from efx_hard_start_xmit to allow the
 347  * loopback test to direct packets via specific TX queues.
 348  *
 349  * Returns NETDEV_TX_OK.
 350  * You must hold netif_tx_lock() to call this function.
 351  */
 352 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
 353 {
 354         struct efx_nic *efx = tx_queue->efx;
 355         struct device *dma_dev = &efx->pci_dev->dev;
 356         struct efx_tx_buffer *buffer;
 357         skb_frag_t *fragment;
 358         unsigned int len, unmap_len = 0;
 359         dma_addr_t dma_addr, unmap_addr = 0;
 360         unsigned int dma_len;
 361         unsigned short dma_flags;
 362         int i = 0;
 363
 364         EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
 365
 366         if (skb_shinfo(skb)->gso_size)
 367                 return efx_enqueue_skb_tso(tx_queue, skb);
 368
 369         /* Get size of the initial fragment */
 370         len = skb_headlen(skb);
 371
 372         /* Pad if necessary */
 373         if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
 374                 EFX_BUG_ON_PARANOID(skb->data_len);
 375                 len = 32 + 1;
 376                 if (skb_pad(skb, len - skb->len))
 377                         return NETDEV_TX_OK;
 378         }
 379
 380         /* Consider using PIO for short packets */
 381 #ifdef EFX_USE_PIO
 382         if (skb->len <= efx_piobuf_size && tx_queue->piobuf &&
 383             efx_nic_tx_is_empty(tx_queue) &&
 384             efx_nic_tx_is_empty(efx_tx_queue_partner(tx_queue))) {
 385                 buffer = efx_enqueue_skb_pio(tx_queue, skb);
 386                 dma_flags = EFX_TX_BUF_OPTION;
 387                 goto finish_packet;
 388         }
 389 #endif
 390
 391         /* Map for DMA.  Use dma_map_single rather than dma_map_page
 392          * since this is more efficient on machines with sparse
 393          * memory.
 394          */
 395         dma_flags = EFX_TX_BUF_MAP_SINGLE;
 396         dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE);
 397
 398         /* Process all fragments */
 399         while (1) {
 400                 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
 401                         goto dma_err;
 402
 403                 /* Store fields for marking in the per-fragment final
 404                  * descriptor */
 405                 unmap_len = len;
 406                 unmap_addr = dma_addr;
 407
 408                 /* Add to TX queue, splitting across DMA boundaries */
 409                 do {
 410                         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
 411
 412                         dma_len = efx_max_tx_len(efx, dma_addr);
 413                         if (likely(dma_len >= len))
 414                                 dma_len = len;
 415
 416                         /* Fill out per descriptor fields */
 417                         buffer->len = dma_len;
 418                         buffer->dma_addr = dma_addr;
 419                         buffer->flags = EFX_TX_BUF_CONT;
 420                         len -= dma_len;
 421                         dma_addr += dma_len;
 422                         ++tx_queue->insert_count;
 423                 } while (len);
 424
 425                 /* Transfer ownership of the unmapping to the final buffer */
 426                 buffer->flags = EFX_TX_BUF_CONT | dma_flags;
 427                 buffer->unmap_len = unmap_len;
 428                 buffer->dma_offset = buffer->dma_addr - unmap_addr;
 429                 unmap_len = 0;
 430
 431                 /* Get address and size of next fragment */
 432                 if (i >= skb_shinfo(skb)->nr_frags)
 433                         break;
 434                 fragment = &skb_shinfo(skb)->frags[i];
 435                 len = skb_frag_size(fragment);
 436                 i++;
 437                 /* Map for DMA */
 438                 dma_flags = 0;
 439                 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
 440                                             DMA_TO_DEVICE);
 441         }
 442
 443         /* Transfer ownership of the skb to the final buffer */
 444 #ifdef EFX_USE_PIO
 445 finish_packet:
 446 #endif
 447         buffer->skb = skb;
 448         buffer->flags = EFX_TX_BUF_SKB | dma_flags;
 449
 450         netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
 451
 452         /* Pass off to hardware */
 453         efx_nic_push_buffers(tx_queue);
 454
 455         efx_tx_maybe_stop_queue(tx_queue);
 456
 457         return NETDEV_TX_OK;
 458
 459  dma_err:
 460         netif_err(efx, tx_err, efx->net_dev,
 461                   " TX queue %d could not map skb with %d bytes %d "
 462                   "fragments for DMA\n", tx_queue->queue, skb->len,
 463                   skb_shinfo(skb)->nr_frags + 1);
 464
 465         /* Mark the packet as transmitted, and free the SKB ourselves */
 466         dev_kfree_skb_any(skb);
 467
 468         /* Work backwards until we hit the original insert pointer value */
 469         while (tx_queue->insert_count != tx_queue->write_count) {
 470                 unsigned int pkts_compl = 0, bytes_compl = 0;
 471                 --tx_queue->insert_count;
 472                 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
 473                 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
 474         }
 475
 476         /* Free the fragment we were mid-way through pushing */
 477         if (unmap_len) {
 478                 if (dma_flags & EFX_TX_BUF_MAP_SINGLE)
 479                         dma_unmap_single(dma_dev, unmap_addr, unmap_len,
 480                                          DMA_TO_DEVICE);
 481                 else
 482                         dma_unmap_page(dma_dev, unmap_addr, unmap_len,
 483                                        DMA_TO_DEVICE);
 484         }
 485
 486         return NETDEV_TX_OK;
 487 }
 488
 489 /* Remove packets from the TX queue
 490  *
 491  * This removes packets from the TX queue, up to and including the
 492  * specified index.
 493  */
 494 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
 495                                 unsigned int index,
 496                                 unsigned int *pkts_compl,
 497                                 unsigned int *bytes_compl)
 498 {
 499         struct efx_nic *efx = tx_queue->efx;
 500         unsigned int stop_index, read_ptr;
 501
 502         stop_index = (index + 1) & tx_queue->ptr_mask;
 503         read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
 504
 505         while (read_ptr != stop_index) {
 506                 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
 507
 508                 if (!(buffer->flags & EFX_TX_BUF_OPTION) &&
 509                     unlikely(buffer->len == 0)) {
 510                         netif_err(efx, tx_err, efx->net_dev,
 511                                   "TX queue %d spurious TX completion id %x\n",
 512                                   tx_queue->queue, read_ptr);
 513                         efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
 514                         return;
 515                 }
 516
 517                 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
 518
 519                 ++tx_queue->read_count;
 520                 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
 521         }
 522 }
 523
 524 /* Initiate a packet transmission.  We use one channel per CPU
 525  * (sharing when we have more CPUs than channels).  On Falcon, the TX
 526  * completion events will be directed back to the CPU that transmitted
 527  * the packet, which should be cache-efficient.
 528  *
 529  * Context: non-blocking.
 530  * Note that returning anything other than NETDEV_TX_OK will cause the
 531  * OS to free the skb.
 532  */
 533 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
 534                                 struct net_device *net_dev)
 535 {
 536         struct efx_nic *efx = netdev_priv(net_dev);
 537         struct efx_tx_queue *tx_queue;
 538         unsigned index, type;
 539
 540         EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
 541
 542         /* PTP "event" packet */
 543         if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
 544             unlikely(efx_ptp_is_ptp_tx(efx, skb))) {
 545                 return efx_ptp_tx(efx, skb);
 546         }
 547
 548         index = skb_get_queue_mapping(skb);
 549         type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0;
 550         if (index >= efx->n_tx_channels) {
 551                 index -= efx->n_tx_channels;
 552                 type |= EFX_TXQ_TYPE_HIGHPRI;
 553         }
 554         tx_queue = efx_get_tx_queue(efx, index, type);
 555
 556         return efx_enqueue_skb(tx_queue, skb);
 557 }
 558
 559 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
 560 {
 561         struct efx_nic *efx = tx_queue->efx;
 562
 563         /* Must be inverse of queue lookup in efx_hard_start_xmit() */
 564         tx_queue->core_txq =
 565                 netdev_get_tx_queue(efx->net_dev,
 566                                     tx_queue->queue / EFX_TXQ_TYPES +
 567                                     ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
 568                                      efx->n_tx_channels : 0));
 569 }
 570
 571 int efx_setup_tc(struct net_device *net_dev, u8 num_tc)
 572 {
 573         struct efx_nic *efx = netdev_priv(net_dev);
 574         struct efx_channel *channel;
 575         struct efx_tx_queue *tx_queue;
 576         unsigned tc;
 577         int rc;
 578
 579         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC)
 580                 return -EINVAL;
 581
 582         if (num_tc == net_dev->num_tc)
 583                 return 0;
 584
 585         for (tc = 0; tc < num_tc; tc++) {
 586                 net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
 587                 net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
 588         }
 589
 590         if (num_tc > net_dev->num_tc) {
 591                 /* Initialise high-priority queues as necessary */
 592                 efx_for_each_channel(channel, efx) {
 593                         efx_for_each_possible_channel_tx_queue(tx_queue,
 594                                                                channel) {
 595                                 if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI))
 596                                         continue;
 597                                 if (!tx_queue->buffer) {
 598                                         rc = efx_probe_tx_queue(tx_queue);
 599                                         if (rc)
 600                                                 return rc;
 601                                 }
 602                                 if (!tx_queue->initialised)
 603                                         efx_init_tx_queue(tx_queue);
 604                                 efx_init_tx_queue_core_txq(tx_queue);
 605                         }
 606                 }
 607         } else {
 608                 /* Reduce number of classes before number of queues */
 609                 net_dev->num_tc = num_tc;
 610         }
 611
 612         rc = netif_set_real_num_tx_queues(net_dev,
 613                                           max_t(int, num_tc, 1) *
 614                                           efx->n_tx_channels);
 615         if (rc)
 616                 return rc;
 617
 618         /* Do not destroy high-priority queues when they become
 619          * unused.  We would have to flush them first, and it is
 620          * fairly difficult to flush a subset of TX queues.  Leave
 621          * it to efx_fini_channels().
 622          */
 623
 624         net_dev->num_tc = num_tc;
 625         return 0;
 626 }
 627
 628 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
 629 {
 630         unsigned fill_level;
 631         struct efx_nic *efx = tx_queue->efx;
 632         struct efx_tx_queue *txq2;
 633         unsigned int pkts_compl = 0, bytes_compl = 0;
 634
 635         EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
 636
 637         efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
 638         netdev_tx_completed_queue(tx_queue->core_txq, pkts_compl, bytes_compl);
 639
 640         if (pkts_compl > 1)
 641                 ++tx_queue->merge_events;
 642
 643         /* See if we need to restart the netif queue.  This memory
 644          * barrier ensures that we write read_count (inside
 645          * efx_dequeue_buffers()) before reading the queue status.
 646          */
 647         smp_mb();
 648         if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
 649             likely(efx->port_enabled) &&
 650             likely(netif_device_present(efx->net_dev))) {
 651                 txq2 = efx_tx_queue_partner(tx_queue);
 652                 fill_level = max(tx_queue->insert_count - tx_queue->read_count,
 653                                  txq2->insert_count - txq2->read_count);
 654                 if (fill_level <= efx->txq_wake_thresh)
 655                         netif_tx_wake_queue(tx_queue->core_txq);
 656         }
 657
 658         /* Check whether the hardware queue is now empty */
 659         if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
 660                 tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count);
 661                 if (tx_queue->read_count == tx_queue->old_write_count) {
 662                         smp_mb();
 663                         tx_queue->empty_read_count =
 664                                 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
 665                 }
 666         }
 667 }
 668
 669 /* Size of page-based TSO header buffers.  Larger blocks must be
 670  * allocated from the heap.
 671  */
 672 #define TSOH_STD_SIZE   128
 673 #define TSOH_PER_PAGE   (PAGE_SIZE / TSOH_STD_SIZE)
 674
 675 /* At most half the descriptors in the queue at any time will refer to
 676  * a TSO header buffer, since they must always be followed by a
 677  * payload descriptor referring to an skb.
 678  */
 679 static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue)
 680 {
 681         return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE);
 682 }
 683
 684 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
 685 {
 686         struct efx_nic *efx = tx_queue->efx;
 687         unsigned int entries;
 688         int rc;
 689
 690         /* Create the smallest power-of-two aligned ring */
 691         entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
 692         EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
 693         tx_queue->ptr_mask = entries - 1;
 694
 695         netif_dbg(efx, probe, efx->net_dev,
 696                   "creating TX queue %d size %#x mask %#x\n",
 697                   tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
 698
 699         /* Allocate software ring */
 700         tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
 701                                    GFP_KERNEL);
 702         if (!tx_queue->buffer)
 703                 return -ENOMEM;
 704
 705         if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) {
 706                 tx_queue->tsoh_page =
 707                         kcalloc(efx_tsoh_page_count(tx_queue),
 708                                 sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL);
 709                 if (!tx_queue->tsoh_page) {
 710                         rc = -ENOMEM;
 711                         goto fail1;
 712                 }
 713         }
 714
 715         /* Allocate hardware ring */
 716         rc = efx_nic_probe_tx(tx_queue);
 717         if (rc)
 718                 goto fail2;
 719
 720         return 0;
 721
 722 fail2:
 723         kfree(tx_queue->tsoh_page);
 724         tx_queue->tsoh_page = NULL;
 725 fail1:
 726         kfree(tx_queue->buffer);
 727         tx_queue->buffer = NULL;
 728         return rc;
 729 }
 730
 731 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
 732 {
 733         netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
 734                   "initialising TX queue %d\n", tx_queue->queue);
 735
 736         tx_queue->insert_count = 0;
 737         tx_queue->write_count = 0;
 738         tx_queue->old_write_count = 0;
 739         tx_queue->read_count = 0;
 740         tx_queue->old_read_count = 0;
 741         tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
 742
 743         /* Set up TX descriptor ring */
 744         efx_nic_init_tx(tx_queue);
 745
 746         tx_queue->initialised = true;
 747 }
 748
 749 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
 750 {
 751         struct efx_tx_buffer *buffer;
 752
 753         netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
 754                   "shutting down TX queue %d\n", tx_queue->queue);
 755
 756         if (!tx_queue->buffer)
 757                 return;
 758
 759         /* Free any buffers left in the ring */
 760         while (tx_queue->read_count != tx_queue->write_count) {
 761                 unsigned int pkts_compl = 0, bytes_compl = 0;
 762                 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
 763                 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
 764
 765                 ++tx_queue->read_count;
 766         }
 767         netdev_tx_reset_queue(tx_queue->core_txq);
 768 }
 769
 770 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
 771 {
 772         int i;
 773
 774         if (!tx_queue->buffer)
 775                 return;
 776
 777         netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
 778                   "destroying TX queue %d\n", tx_queue->queue);
 779         efx_nic_remove_tx(tx_queue);
 780
 781         if (tx_queue->tsoh_page) {
 782                 for (i = 0; i < efx_tsoh_page_count(tx_queue); i++)
 783                         efx_nic_free_buffer(tx_queue->efx,
 784                                             &tx_queue->tsoh_page[i]);
 785                 kfree(tx_queue->tsoh_page);
 786                 tx_queue->tsoh_page = NULL;
 787         }
 788
 789         kfree(tx_queue->buffer);
 790         tx_queue->buffer = NULL;
 791 }
 792
 793
 794 /* Efx TCP segmentation acceleration.
 795  *
 796  * Why?  Because by doing it here in the driver we can go significantly
 797  * faster than the GSO.
 798  *
 799  * Requires TX checksum offload support.
 800  */
 801
 802 #define PTR_DIFF(p1, p2)  ((u8 *)(p1) - (u8 *)(p2))
 803
 804 /**
 805  * struct tso_state - TSO state for an SKB
 806  * @out_len: Remaining length in current segment
 807  * @seqnum: Current sequence number
 808  * @ipv4_id: Current IPv4 ID, host endian
 809  * @packet_space: Remaining space in current packet
 810  * @dma_addr: DMA address of current position
 811  * @in_len: Remaining length in current SKB fragment
 812  * @unmap_len: Length of SKB fragment
 813  * @unmap_addr: DMA address of SKB fragment
 814  * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0
 815  * @protocol: Network protocol (after any VLAN header)
 816  * @ip_off: Offset of IP header
 817  * @tcp_off: Offset of TCP header
 818  * @header_len: Number of bytes of header
 819  * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload
 820  * @header_dma_addr: Header DMA address, when using option descriptors
 821  * @header_unmap_len: Header DMA mapped length, or 0 if not using option
 822  *      descriptors
 823  *
 824  * The state used during segmentation.  It is put into this data structure
 825  * just to make it easy to pass into inline functions.
 826  */
 827 struct tso_state {
 828         /* Output position */
 829         unsigned out_len;
 830         unsigned seqnum;
 831         u16 ipv4_id;
 832         unsigned packet_space;
 833
 834         /* Input position */
 835         dma_addr_t dma_addr;
 836         unsigned in_len;
 837         unsigned unmap_len;
 838         dma_addr_t unmap_addr;
 839         unsigned short dma_flags;
 840
 841         __be16 protocol;
 842         unsigned int ip_off;
 843         unsigned int tcp_off;
 844         unsigned header_len;
 845         unsigned int ip_base_len;
 846         dma_addr_t header_dma_addr;
 847         unsigned int header_unmap_len;
 848 };
 849
 850
 851 /*
 852  * Verify that our various assumptions about sk_buffs and the conditions
 853  * under which TSO will be attempted hold true.  Return the protocol number.
 854  */
 855 static __be16 efx_tso_check_protocol(struct sk_buff *skb)
 856 {
 857         __be16 protocol = skb->protocol;
 858
 859         EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
 860                             protocol);
 861         if (protocol == htons(ETH_P_8021Q)) {
 862                 struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
 863                 protocol = veh->h_vlan_encapsulated_proto;
 864         }
 865
 866         if (protocol == htons(ETH_P_IP)) {
 867                 EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
 868         } else {
 869                 EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
 870                 EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
 871         }
 872         EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
 873                              + (tcp_hdr(skb)->doff << 2u)) >
 874                             skb_headlen(skb));
 875
 876         return protocol;
 877 }
 878
 879 static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue,
 880                                struct efx_tx_buffer *buffer, unsigned int len)
 881 {
 882         u8 *result;
 883
 884         EFX_BUG_ON_PARANOID(buffer->len);
 885         EFX_BUG_ON_PARANOID(buffer->flags);
 886         EFX_BUG_ON_PARANOID(buffer->unmap_len);
 887
 888         if (likely(len <= TSOH_STD_SIZE - NET_IP_ALIGN)) {
 889                 unsigned index =
 890                         (tx_queue->insert_count & tx_queue->ptr_mask) / 2;
 891                 struct efx_buffer *page_buf =
 892                         &tx_queue->tsoh_page[index / TSOH_PER_PAGE];
 893                 unsigned offset =
 894                         TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + NET_IP_ALIGN;
 895
 896                 if (unlikely(!page_buf->addr) &&
 897                     efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
 898                                          GFP_ATOMIC))
 899                         return NULL;
 900
 901                 result = (u8 *)page_buf->addr + offset;
 902                 buffer->dma_addr = page_buf->dma_addr + offset;
 903                 buffer->flags = EFX_TX_BUF_CONT;
 904         } else {
 905                 tx_queue->tso_long_headers++;
 906
 907                 buffer->heap_buf = kmalloc(NET_IP_ALIGN + len, GFP_ATOMIC);
 908                 if (unlikely(!buffer->heap_buf))
 909                         return NULL;
 910                 result = (u8 *)buffer->heap_buf + NET_IP_ALIGN;
 911                 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP;
 912         }
 913
 914         buffer->len = len;
 915
 916         return result;
 917 }
 918
 919 /**
 920  * efx_tx_queue_insert - push descriptors onto the TX queue
 921  * @tx_queue:           Efx TX queue
 922  * @dma_addr:           DMA address of fragment
 923  * @len:                Length of fragment
 924  * @final_buffer:       The final buffer inserted into the queue
 925  *
 926  * Push descriptors onto the TX queue.
 927  */
 928 static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
 929                                 dma_addr_t dma_addr, unsigned len,
 930                                 struct efx_tx_buffer **final_buffer)
 931 {
 932         struct efx_tx_buffer *buffer;
 933         struct efx_nic *efx = tx_queue->efx;
 934         unsigned dma_len;
 935
 936         EFX_BUG_ON_PARANOID(len <= 0);
 937
 938         while (1) {
 939                 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
 940                 ++tx_queue->insert_count;
 941
 942                 EFX_BUG_ON_PARANOID(tx_queue->insert_count -
 943                                     tx_queue->read_count >=
 944                                     efx->txq_entries);
 945
 946                 buffer->dma_addr = dma_addr;
 947
 948                 dma_len = efx_max_tx_len(efx, dma_addr);
 949
 950                 /* If there is enough space to send then do so */
 951                 if (dma_len >= len)
 952                         break;
 953
 954                 buffer->len = dma_len;
 955                 buffer->flags = EFX_TX_BUF_CONT;
 956                 dma_addr += dma_len;
 957                 len -= dma_len;
 958         }
 959
 960         EFX_BUG_ON_PARANOID(!len);
 961         buffer->len = len;
 962         *final_buffer = buffer;
 963 }
 964
 965
 966 /*
 967  * Put a TSO header into the TX queue.
 968  *
 969  * This is special-cased because we know that it is small enough to fit in
 970  * a single fragment, and we know it doesn't cross a page boundary.  It
 971  * also allows us to not worry about end-of-packet etc.
 972  */
 973 static int efx_tso_put_header(struct efx_tx_queue *tx_queue,
 974                               struct efx_tx_buffer *buffer, u8 *header)
 975 {
 976         if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) {
 977                 buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev,
 978                                                   header, buffer->len,
 979                                                   DMA_TO_DEVICE);
 980                 if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev,
 981                                                buffer->dma_addr))) {
 982                         kfree(buffer->heap_buf);
 983                         buffer->len = 0;
 984                         buffer->flags = 0;
 985                         return -ENOMEM;
 986                 }
 987                 buffer->unmap_len = buffer->len;
 988                 buffer->dma_offset = 0;
 989                 buffer->flags |= EFX_TX_BUF_MAP_SINGLE;
 990         }
 991
 992         ++tx_queue->insert_count;
 993         return 0;
 994 }
 995
 996
 997 /* Remove buffers put into a tx_queue.  None of the buffers must have
 998  * an skb attached.
 999  */
1000 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
1001 {
1002         struct efx_tx_buffer *buffer;
1003
1004         /* Work backwards until we hit the original insert pointer value */
1005         while (tx_queue->insert_count != tx_queue->write_count) {
1006                 --tx_queue->insert_count;
1007                 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
1008                 efx_dequeue_buffer(tx_queue, buffer, NULL, NULL);
1009         }
1010 }
1011
1012
1013 /* Parse the SKB header and initialise state. */
1014 static int tso_start(struct tso_state *st, struct efx_nic *efx,
1015                      const struct sk_buff *skb)
1016 {
1017         bool use_opt_desc = efx_nic_rev(efx) >= EFX_REV_HUNT_A0;
1018         struct device *dma_dev = &efx->pci_dev->dev;
1019         unsigned int header_len, in_len;
1020         dma_addr_t dma_addr;
1021
1022         st->ip_off = skb_network_header(skb) - skb->data;
1023         st->tcp_off = skb_transport_header(skb) - skb->data;
1024         header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u);
1025         in_len = skb_headlen(skb) - header_len;
1026         st->header_len = header_len;
1027         st->in_len = in_len;
1028         if (st->protocol == htons(ETH_P_IP)) {
1029                 st->ip_base_len = st->header_len - st->ip_off;
1030                 st->ipv4_id = ntohs(ip_hdr(skb)->id);
1031         } else {
1032                 st->ip_base_len = st->header_len - st->tcp_off;
1033                 st->ipv4_id = 0;
1034         }
1035         st->seqnum = ntohl(tcp_hdr(skb)->seq);
1036
1037         EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
1038         EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
1039         EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
1040
1041         st->out_len = skb->len - header_len;
1042
1043         if (!use_opt_desc) {
1044                 st->header_unmap_len = 0;
1045
1046                 if (likely(in_len == 0)) {
1047                         st->dma_flags = 0;
1048                         st->unmap_len = 0;
1049                         return 0;
1050                 }
1051
1052                 dma_addr = dma_map_single(dma_dev, skb->data + header_len,
1053                                           in_len, DMA_TO_DEVICE);
1054                 st->dma_flags = EFX_TX_BUF_MAP_SINGLE;
1055                 st->dma_addr = dma_addr;
1056                 st->unmap_addr = dma_addr;
1057                 st->unmap_len = in_len;
1058         } else {
1059                 dma_addr = dma_map_single(dma_dev, skb->data,
1060                                           skb_headlen(skb), DMA_TO_DEVICE);
1061                 st->header_dma_addr = dma_addr;
1062                 st->header_unmap_len = skb_headlen(skb);
1063                 st->dma_flags = 0;
1064                 st->dma_addr = dma_addr + header_len;
1065                 st->unmap_len = 0;
1066         }
1067
1068         return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0;
1069 }
1070
1071 static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
1072                             skb_frag_t *frag)
1073 {
1074         st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0,
1075                                           skb_frag_size(frag), DMA_TO_DEVICE);
1076         if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) {
1077                 st->dma_flags = 0;
1078                 st->unmap_len = skb_frag_size(frag);
1079                 st->in_len = skb_frag_size(frag);
1080                 st->dma_addr = st->unmap_addr;
1081                 return 0;
1082         }
1083         return -ENOMEM;
1084 }
1085
1086
1087 /**
1088  * tso_fill_packet_with_fragment - form descriptors for the current fragment
1089  * @tx_queue:           Efx TX queue
1090  * @skb:                Socket buffer
1091  * @st:                 TSO state
1092  *
1093  * Form descriptors for the current fragment, until we reach the end
1094  * of fragment or end-of-packet.
1095  */
1096 static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
1097                                           const struct sk_buff *skb,
1098                                           struct tso_state *st)
1099 {
1100         struct efx_tx_buffer *buffer;
1101         int n;
1102
1103         if (st->in_len == 0)
1104                 return;
1105         if (st->packet_space == 0)
1106                 return;
1107
1108         EFX_BUG_ON_PARANOID(st->in_len <= 0);
1109         EFX_BUG_ON_PARANOID(st->packet_space <= 0);
1110
1111         n = min(st->in_len, st->packet_space);
1112
1113         st->packet_space -= n;
1114         st->out_len -= n;
1115         st->in_len -= n;
1116
1117         efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
1118
1119         if (st->out_len == 0) {
1120                 /* Transfer ownership of the skb */
1121                 buffer->skb = skb;
1122                 buffer->flags = EFX_TX_BUF_SKB;
1123         } else if (st->packet_space != 0) {
1124                 buffer->flags = EFX_TX_BUF_CONT;
1125         }
1126
1127         if (st->in_len == 0) {
1128                 /* Transfer ownership of the DMA mapping */
1129                 buffer->unmap_len = st->unmap_len;
1130                 buffer->dma_offset = buffer->unmap_len - buffer->len;
1131                 buffer->flags |= st->dma_flags;
1132                 st->unmap_len = 0;
1133         }
1134
1135         st->dma_addr += n;
1136 }
1137
1138
1139 /**
1140  * tso_start_new_packet - generate a new header and prepare for the new packet
1141  * @tx_queue:           Efx TX queue
1142  * @skb:                Socket buffer
1143  * @st:                 TSO state
1144  *
1145  * Generate a new header and prepare for the new packet.  Return 0 on
1146  * success, or -%ENOMEM if failed to alloc header.
1147  */
1148 static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
1149                                 const struct sk_buff *skb,
1150                                 struct tso_state *st)
1151 {
1152         struct efx_tx_buffer *buffer =
1153                 efx_tx_queue_get_insert_buffer(tx_queue);
1154         bool is_last = st->out_len <= skb_shinfo(skb)->gso_size;
1155         u8 tcp_flags_clear;
1156
1157         if (!is_last) {
1158                 st->packet_space = skb_shinfo(skb)->gso_size;
1159                 tcp_flags_clear = 0x09; /* mask out FIN and PSH */
1160         } else {
1161                 st->packet_space = st->out_len;
1162                 tcp_flags_clear = 0x00;
1163         }
1164
1165         if (!st->header_unmap_len) {
1166                 /* Allocate and insert a DMA-mapped header buffer. */
1167                 struct tcphdr *tsoh_th;
1168                 unsigned ip_length;
1169                 u8 *header;
1170                 int rc;
1171
1172                 header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len);
1173                 if (!header)
1174                         return -ENOMEM;
1175
1176                 tsoh_th = (struct tcphdr *)(header + st->tcp_off);
1177
1178                 /* Copy and update the headers. */
1179                 memcpy(header, skb->data, st->header_len);
1180
1181                 tsoh_th->seq = htonl(st->seqnum);
1182                 ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear;
1183
1184                 ip_length = st->ip_base_len + st->packet_space;
1185
1186                 if (st->protocol == htons(ETH_P_IP)) {
1187                         struct iphdr *tsoh_iph =
1188                                 (struct iphdr *)(header + st->ip_off);
1189
1190                         tsoh_iph->tot_len = htons(ip_length);
1191                         tsoh_iph->id = htons(st->ipv4_id);
1192                 } else {
1193                         struct ipv6hdr *tsoh_iph =
1194                                 (struct ipv6hdr *)(header + st->ip_off);
1195
1196                         tsoh_iph->payload_len = htons(ip_length);
1197                 }
1198
1199                 rc = efx_tso_put_header(tx_queue, buffer, header);
1200                 if (unlikely(rc))
1201                         return rc;
1202         } else {
1203                 /* Send the original headers with a TSO option descriptor
1204                  * in front
1205                  */
1206                 u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear;
1207
1208                 buffer->flags = EFX_TX_BUF_OPTION;
1209                 buffer->len = 0;
1210                 buffer->unmap_len = 0;
1211                 EFX_POPULATE_QWORD_5(buffer->option,
1212                                      ESF_DZ_TX_DESC_IS_OPT, 1,
1213                                      ESF_DZ_TX_OPTION_TYPE,
1214                                      ESE_DZ_TX_OPTION_DESC_TSO,
1215                                      ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
1216                                      ESF_DZ_TX_TSO_IP_ID, st->ipv4_id,
1217                                      ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum);
1218                 ++tx_queue->insert_count;
1219
1220                 /* We mapped the headers in tso_start().  Unmap them
1221                  * when the last segment is completed.
1222                  */
1223                 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
1224                 buffer->dma_addr = st->header_dma_addr;
1225                 buffer->len = st->header_len;
1226                 if (is_last) {
1227                         buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE;
1228                         buffer->unmap_len = st->header_unmap_len;
1229                         buffer->dma_offset = 0;
1230                         /* Ensure we only unmap them once in case of a
1231                          * later DMA mapping error and rollback
1232                          */
1233                         st->header_unmap_len = 0;
1234                 } else {
1235                         buffer->flags = EFX_TX_BUF_CONT;
1236                         buffer->unmap_len = 0;
1237                 }
1238                 ++tx_queue->insert_count;
1239         }
1240
1241         st->seqnum += skb_shinfo(skb)->gso_size;
1242
1243         /* Linux leaves suitable gaps in the IP ID space for us to fill. */
1244         ++st->ipv4_id;
1245
1246         ++tx_queue->tso_packets;
1247
1248         return 0;
1249 }
1250
1251
1252 /**
1253  * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
1254  * @tx_queue:           Efx TX queue
1255  * @skb:                Socket buffer
1256  *
1257  * Context: You must hold netif_tx_lock() to call this function.
1258  *
1259  * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
1260  * @skb was not enqueued.  In all cases @skb is consumed.  Return
1261  * %NETDEV_TX_OK.
1262  */
1263 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
1264                                struct sk_buff *skb)
1265 {
1266         struct efx_nic *efx = tx_queue->efx;
1267         int frag_i, rc;
1268         struct tso_state state;
1269
1270         /* Find the packet protocol and sanity-check it */
1271         state.protocol = efx_tso_check_protocol(skb);
1272
1273         EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
1274
1275         rc = tso_start(&state, efx, skb);
1276         if (rc)
1277                 goto mem_err;
1278
1279         if (likely(state.in_len == 0)) {
1280                 /* Grab the first payload fragment. */
1281                 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
1282                 frag_i = 0;
1283                 rc = tso_get_fragment(&state, efx,
1284                                       skb_shinfo(skb)->frags + frag_i);
1285                 if (rc)
1286                         goto mem_err;
1287         } else {
1288                 /* Payload starts in the header area. */
1289                 frag_i = -1;
1290         }
1291
1292         if (tso_start_new_packet(tx_queue, skb, &state) < 0)
1293                 goto mem_err;
1294
1295         while (1) {
1296                 tso_fill_packet_with_fragment(tx_queue, skb, &state);
1297
1298                 /* Move onto the next fragment? */
1299                 if (state.in_len == 0) {
1300                         if (++frag_i >= skb_shinfo(skb)->nr_frags)
1301                                 /* End of payload reached. */
1302                                 break;
1303                         rc = tso_get_fragment(&state, efx,
1304                                               skb_shinfo(skb)->frags + frag_i);
1305                         if (rc)
1306                                 goto mem_err;
1307                 }
1308
1309                 /* Start at new packet? */
1310                 if (state.packet_space == 0 &&
1311                     tso_start_new_packet(tx_queue, skb, &state) < 0)
1312                         goto mem_err;
1313         }
1314
1315         netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
1316
1317         /* Pass off to hardware */
1318         efx_nic_push_buffers(tx_queue);
1319
1320         efx_tx_maybe_stop_queue(tx_queue);
1321
1322         tx_queue->tso_bursts++;
1323         return NETDEV_TX_OK;
1324
1325  mem_err:
1326         netif_err(efx, tx_err, efx->net_dev,
1327                   "Out of memory for TSO headers, or DMA mapping error\n");
1328         dev_kfree_skb_any(skb);
1329
1330         /* Free the DMA mapping we were in the process of writing out */
1331         if (state.unmap_len) {
1332                 if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE)
1333                         dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr,
1334                                          state.unmap_len, DMA_TO_DEVICE);
1335                 else
1336                         dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr,
1337                                        state.unmap_len, DMA_TO_DEVICE);
1338         }
1339
1340         /* Free the header DMA mapping, if using option descriptors */
1341         if (state.header_unmap_len)
1342                 dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr,
1343                                  state.header_unmap_len, DMA_TO_DEVICE);
1344
1345         efx_enqueue_unwind(tx_queue);
1346         return NETDEV_TX_OK;
1347 }