1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/ptp_classify.h>
32 * The 82599 and the X540 do not have true 64bit nanosecond scale
33 * counter registers. Instead, SYSTIME is defined by a fixed point
34 * system which allows the user to define the scale counter increment
35 * value at every level change of the oscillator driving the SYSTIME
36 * value. For both devices the TIMINCA:IV field defines this
37 * increment. On the X540 device, 31 bits are provided. However on the
38 * 82599 only provides 24 bits. The time unit is determined by the
39 * clock frequency of the oscillator in combination with the TIMINCA
40 * register. When these devices link at 10Gb the oscillator has a
41 * period of 6.4ns. In order to convert the scale counter into
42 * nanoseconds the cyclecounter and timecounter structures are
43 * used. The SYSTIME registers need to be converted to ns values by use
44 * of only a right shift (division by power of 2). The following math
45 * determines the largest incvalue that will fit into the available
46 * bits in the TIMINCA register.
48 * PeriodWidth: Number of bits to store the clock period
49 * MaxWidth: The maximum width value of the TIMINCA register
50 * Period: The clock period for the oscillator
51 * round(): discard the fractional portion of the calculation
53 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
55 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
56 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
58 * The period also changes based on the link speed:
59 * At 10Gb link or no link, the period remains the same.
60 * At 1Gb link, the period is multiplied by 10. (64ns)
61 * At 100Mb link, the period is multiplied by 100. (640ns)
63 * The calculated value allows us to right shift the SYSTIME register
64 * value in order to quickly convert it into a nanosecond clock,
65 * while allowing for the maximum possible adjustment value.
67 * These diagrams are only for the 10Gb link period
70 * +--------------+ +--------------+
71 * X540 | 32 | | 1 | 3 | 28 |
72 * *--------------+ +--------------+
73 * \________ 36 bits ______/ fract
75 * +--------------+ +--------------+
76 * 82599 | 32 | | 8 | 3 | 21 |
77 * *--------------+ +--------------+
78 * \________ 43 bits ______/ fract
80 * The 36 bit X540 SYSTIME overflows every
81 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
83 * The 43 bit 82599 SYSTIME overflows every
84 * 2^43 * 10^-9 / 3600 = 2.4 hours
86 #define IXGBE_INCVAL_10GB 0x66666666
87 #define IXGBE_INCVAL_1GB 0x40000000
88 #define IXGBE_INCVAL_100 0x50000000
90 #define IXGBE_INCVAL_SHIFT_10GB 28
91 #define IXGBE_INCVAL_SHIFT_1GB 24
92 #define IXGBE_INCVAL_SHIFT_100 21
94 #define IXGBE_INCVAL_SHIFT_82599 7
95 #define IXGBE_INCPER_SHIFT_82599 24
96 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
101 #ifndef NSECS_PER_SEC
102 #define NSECS_PER_SEC 1000000000ULL
106 * ixgbe_ptp_setup_sdp
107 * @hw: the hardware private structure
109 * this function enables or disables the clock out feature on SDP0 for
110 * the X540 device. It will create a 1second periodic output that can
111 * be used as the PPS (via an interrupt).
113 * It calculates when the systime will be on an exact second, and then
114 * aligns the start of the PPS signal to that value. The shift is
115 * necessary because it can change based on the link speed.
117 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
119 struct ixgbe_hw *hw = &adapter->hw;
120 int shift = adapter->cc.shift;
121 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
122 u64 ns = 0, clock_edge = 0;
124 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
125 (hw->mac.type == ixgbe_mac_X540)) {
127 /* disable the pin first */
128 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
129 IXGBE_WRITE_FLUSH(hw);
131 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
134 * enable the SDP0 pin as output, and connected to the
135 * native function for Timesync (ClockOut)
137 esdp |= (IXGBE_ESDP_SDP0_DIR |
138 IXGBE_ESDP_SDP0_NATIVE);
141 * enable the Clock Out feature on SDP0, and allow
142 * interrupts to occur when the pin changes
144 tsauxc = (IXGBE_TSAUXC_EN_CLK |
145 IXGBE_TSAUXC_SYNCLK |
146 IXGBE_TSAUXC_SDP0_INT);
148 /* clock period (or pulse length) */
149 clktiml = (u32)(NSECS_PER_SEC << shift);
150 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
153 * Account for the cyclecounter wrap-around value by
154 * using the converted ns value of the current time to
155 * check for when the next aligned second would occur.
157 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
158 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
159 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
161 div_u64_rem(ns, NSECS_PER_SEC, &rem);
162 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
164 /* specify the initial clock start time */
165 trgttiml = (u32)clock_edge;
166 trgttimh = (u32)(clock_edge >> 32);
168 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
169 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
170 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
171 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
173 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
174 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
176 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
179 IXGBE_WRITE_FLUSH(hw);
183 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
184 * @cc: the cyclecounter structure
186 * this function reads the cyclecounter registers and is called by the
187 * cyclecounter structure used to construct a ns counter from the
188 * arbitrary fixed point registers
190 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
192 struct ixgbe_adapter *adapter =
193 container_of(cc, struct ixgbe_adapter, cc);
194 struct ixgbe_hw *hw = &adapter->hw;
197 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
198 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
205 * @ptp: the ptp clock structure
206 * @ppb: parts per billion adjustment from base
208 * adjust the frequency of the ptp cycle counter by the
209 * indicated ppb from the base frequency.
211 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
213 struct ixgbe_adapter *adapter =
214 container_of(ptp, struct ixgbe_adapter, ptp_caps);
215 struct ixgbe_hw *hw = &adapter->hw;
226 incval = ACCESS_ONCE(adapter->base_incval);
230 diff = div_u64(freq, 1000000000ULL);
232 incval = neg_adj ? (incval - diff) : (incval + diff);
234 switch (hw->mac.type) {
236 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
238 case ixgbe_mac_82599EB:
239 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
240 (1 << IXGBE_INCPER_SHIFT_82599) |
252 * @ptp: the ptp clock structure
253 * @delta: offset to adjust the cycle counter by
255 * adjust the timer by resetting the timecounter structure.
257 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
259 struct ixgbe_adapter *adapter =
260 container_of(ptp, struct ixgbe_adapter, ptp_caps);
264 spin_lock_irqsave(&adapter->tmreg_lock, flags);
266 now = timecounter_read(&adapter->tc);
269 /* reset the timecounter */
270 timecounter_init(&adapter->tc,
274 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
276 ixgbe_ptp_setup_sdp(adapter);
283 * @ptp: the ptp clock structure
284 * @ts: timespec structure to hold the current time value
286 * read the timecounter and return the correct value on ns,
287 * after converting it into a struct timespec.
289 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
291 struct ixgbe_adapter *adapter =
292 container_of(ptp, struct ixgbe_adapter, ptp_caps);
297 spin_lock_irqsave(&adapter->tmreg_lock, flags);
298 ns = timecounter_read(&adapter->tc);
299 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
301 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
302 ts->tv_nsec = remainder;
309 * @ptp: the ptp clock structure
310 * @ts: the timespec containing the new time for the cycle counter
312 * reset the timecounter to use a new base value instead of the kernel
315 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
316 const struct timespec *ts)
318 struct ixgbe_adapter *adapter =
319 container_of(ptp, struct ixgbe_adapter, ptp_caps);
323 ns = ts->tv_sec * 1000000000ULL;
326 /* reset the timecounter */
327 spin_lock_irqsave(&adapter->tmreg_lock, flags);
328 timecounter_init(&adapter->tc, &adapter->cc, ns);
329 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
331 ixgbe_ptp_setup_sdp(adapter);
336 * ixgbe_ptp_feature_enable
337 * @ptp: the ptp clock structure
338 * @rq: the requested feature to change
339 * @on: whether to enable or disable the feature
341 * enable (or disable) ancillary features of the phc subsystem.
342 * our driver only supports the PPS feature on the X540
344 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
345 struct ptp_clock_request *rq, int on)
347 struct ixgbe_adapter *adapter =
348 container_of(ptp, struct ixgbe_adapter, ptp_caps);
351 * When PPS is enabled, unmask the interrupt for the ClockOut
352 * feature, so that the interrupt handler can send the PPS
353 * event when the clock SDP triggers. Clear mask when PPS is
356 if (rq->type == PTP_CLK_REQ_PPS) {
357 switch (adapter->hw.mac.type) {
360 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
362 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
364 ixgbe_ptp_setup_sdp(adapter);
375 * ixgbe_ptp_check_pps_event
376 * @adapter: the private adapter structure
377 * @eicr: the interrupt cause register value
379 * This function is called by the interrupt routine when checking for
380 * interrupts. It will check and handle a pps event.
382 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
384 struct ixgbe_hw *hw = &adapter->hw;
385 struct ptp_clock_event event;
387 event.type = PTP_CLOCK_PPS;
389 /* this check is necessary in case the interrupt was enabled via some
390 * alternative means (ex. debug_fs). Better to check here than
391 * everywhere that calls this function.
393 if (!adapter->ptp_clock)
396 switch (hw->mac.type) {
398 ptp_clock_event(adapter->ptp_clock, &event);
406 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
407 * @adapter: private adapter struct
409 * this watchdog task periodically reads the timecounter
410 * in order to prevent missing when the system time registers wrap
411 * around. This needs to be run approximately twice a minute.
413 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
415 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
416 IXGBE_OVERFLOW_PERIOD);
420 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
421 adapter->last_overflow_check = jiffies;
426 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
427 * @adapter: private network adapter structure
429 * this watchdog task is scheduled to detect error case where hardware has
430 * dropped an Rx packet that was timestamped when the ring is full. The
431 * particular error is rare but leaves the device in a state unable to timestamp
432 * any future packets.
434 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
436 struct ixgbe_hw *hw = &adapter->hw;
437 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
438 unsigned long rx_event;
440 /* if we don't have a valid timestamp in the registers, just update the
441 * timeout counter and exit
443 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
444 adapter->last_rx_ptp_check = jiffies;
448 /* determine the most recent watchdog or rx_timestamp event */
449 rx_event = adapter->last_rx_ptp_check;
450 if (time_after(adapter->last_rx_timestamp, rx_event))
451 rx_event = adapter->last_rx_timestamp;
453 /* only need to read the high RXSTMP register to clear the lock */
454 if (time_is_before_jiffies(rx_event + 5*HZ)) {
455 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
456 adapter->last_rx_ptp_check = jiffies;
458 e_warn(drv, "clearing RX Timestamp hang\n");
463 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
464 * @adapter: the private adapter struct
466 * if the timestamp is valid, we convert it into the timecounter ns
467 * value, then store that result into the shhwtstamps structure which
468 * is passed up the network stack
470 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
472 struct ixgbe_hw *hw = &adapter->hw;
473 struct skb_shared_hwtstamps shhwtstamps;
477 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
478 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
480 spin_lock_irqsave(&adapter->tmreg_lock, flags);
481 ns = timecounter_cyc2time(&adapter->tc, regval);
482 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
484 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
485 shhwtstamps.hwtstamp = ns_to_ktime(ns);
486 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
488 dev_kfree_skb_any(adapter->ptp_tx_skb);
489 adapter->ptp_tx_skb = NULL;
490 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
494 * ixgbe_ptp_tx_hwtstamp_work
495 * @work: pointer to the work struct
497 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
498 * timestamp has been taken for the current skb. It is necesary, because the
499 * descriptor's "done" bit does not correlate with the timestamp event.
501 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
503 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
505 struct ixgbe_hw *hw = &adapter->hw;
506 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
507 IXGBE_PTP_TX_TIMEOUT);
511 dev_kfree_skb_any(adapter->ptp_tx_skb);
512 adapter->ptp_tx_skb = NULL;
513 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
514 e_warn(drv, "clearing Tx Timestamp hang\n");
518 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
519 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
520 ixgbe_ptp_tx_hwtstamp(adapter);
522 /* reschedule to keep checking if it's not available yet */
523 schedule_work(&adapter->ptp_tx_work);
527 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
528 * @adapter: pointer to adapter struct
529 * @skb: particular skb to send timestamp with
531 * if the timestamp is valid, we convert it into the timecounter ns
532 * value, then store that result into the shhwtstamps structure which
533 * is passed up the network stack
535 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb)
537 struct ixgbe_hw *hw = &adapter->hw;
538 struct skb_shared_hwtstamps *shhwtstamps;
543 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
544 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
547 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
548 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
550 spin_lock_irqsave(&adapter->tmreg_lock, flags);
551 ns = timecounter_cyc2time(&adapter->tc, regval);
552 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
554 shhwtstamps = skb_hwtstamps(skb);
555 shhwtstamps->hwtstamp = ns_to_ktime(ns);
557 /* Update the last_rx_timestamp timer in order to enable watchdog check
558 * for error case of latched timestamp on a dropped packet.
560 adapter->last_rx_timestamp = jiffies;
563 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
565 struct hwtstamp_config *config = &adapter->tstamp_config;
567 return copy_to_user(ifr->ifr_data, config,
568 sizeof(*config)) ? -EFAULT : 0;
572 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
573 * @adapter: the private ixgbe adapter structure
574 * @config: the hwtstamp configuration requested
576 * Outgoing time stamping can be enabled and disabled. Play nice and
577 * disable it when requested, although it shouldn't cause any overhead
578 * when no packet needs it. At most one packet in the queue may be
579 * marked for time stamping, otherwise it would be impossible to tell
580 * for sure to which packet the hardware time stamp belongs.
582 * Incoming time stamping has to be configured via the hardware
583 * filters. Not all combinations are supported, in particular event
584 * type has to be specified. Matching the kind of event packet is
585 * not supported, with the exception of "all V2 events regardless of
588 * Since hardware always timestamps Path delay packets when timestamping V2
589 * packets, regardless of the type specified in the register, only use V2
590 * Event mode. This more accurately tells the user what the hardware is going
593 * Note: this may modify the hwtstamp configuration towards a more general
594 * mode, if required to support the specifically requested mode.
596 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
597 struct hwtstamp_config *config)
599 struct ixgbe_hw *hw = &adapter->hw;
600 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
601 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
602 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
606 /* reserved for future extensions */
610 switch (config->tx_type) {
611 case HWTSTAMP_TX_OFF:
619 switch (config->rx_filter) {
620 case HWTSTAMP_FILTER_NONE:
624 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
625 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
626 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
628 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
629 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
630 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
632 case HWTSTAMP_FILTER_PTP_V2_EVENT:
633 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
634 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
635 case HWTSTAMP_FILTER_PTP_V2_SYNC:
636 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
637 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
638 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
639 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
640 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
641 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
643 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
645 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
646 case HWTSTAMP_FILTER_ALL:
649 * register RXMTRL must be set in order to do V1 packets,
650 * therefore it is not possible to time stamp both V1 Sync and
651 * Delay_Req messages and hardware does not support
652 * timestamping all packets => return error
654 config->rx_filter = HWTSTAMP_FILTER_NONE;
658 if (hw->mac.type == ixgbe_mac_82598EB) {
659 if (tsync_rx_ctl | tsync_tx_ctl)
664 /* define ethertype filter for timestamping L2 packets */
666 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
667 (IXGBE_ETQF_FILTER_EN | /* enable filter */
668 IXGBE_ETQF_1588 | /* enable timestamping */
669 ETH_P_1588)); /* 1588 eth protocol type */
671 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
673 /* enable/disable TX */
674 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
675 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
676 regval |= tsync_tx_ctl;
677 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
679 /* enable/disable RX */
680 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
681 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
682 regval |= tsync_rx_ctl;
683 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
685 /* define which PTP packets are time stamped */
686 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
688 IXGBE_WRITE_FLUSH(hw);
690 /* clear TX/RX time stamp registers, just to be sure */
691 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
692 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
698 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
699 * @adapter: pointer to adapter struct
702 * Set hardware to requested mode. If unsupported, return an error with no
703 * changes. Otherwise, store the mode for future reference.
705 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
707 struct hwtstamp_config config;
710 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
713 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
717 /* save these settings for future reference */
718 memcpy(&adapter->tstamp_config, &config,
719 sizeof(adapter->tstamp_config));
721 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
726 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
727 * @adapter: pointer to the adapter structure
729 * This function should be called to set the proper values for the TIMINCA
730 * register and tell the cyclecounter structure what the tick rate of SYSTIME
731 * is. It does not directly modify SYSTIME registers or the timecounter
732 * structure. It should be called whenever a new TIMINCA value is necessary,
733 * such as during initialization or when the link speed changes.
735 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
737 struct ixgbe_hw *hw = &adapter->hw;
743 * Scale the NIC cycle counter by a large factor so that
744 * relatively small corrections to the frequency can be added
745 * or subtracted. The drawbacks of a large factor include
746 * (a) the clock register overflows more quickly, (b) the cycle
747 * counter structure must be able to convert the systime value
748 * to nanoseconds using only a multiplier and a right-shift,
749 * and (c) the value must fit within the timinca register space
750 * => math based on internal DMA clock rate and available bits
752 * Note that when there is no link, internal DMA clock is same as when
753 * link speed is 10Gb. Set the registers correctly even when link is
754 * down to preserve the clock setting
756 switch (adapter->link_speed) {
757 case IXGBE_LINK_SPEED_100_FULL:
758 incval = IXGBE_INCVAL_100;
759 shift = IXGBE_INCVAL_SHIFT_100;
761 case IXGBE_LINK_SPEED_1GB_FULL:
762 incval = IXGBE_INCVAL_1GB;
763 shift = IXGBE_INCVAL_SHIFT_1GB;
765 case IXGBE_LINK_SPEED_10GB_FULL:
767 incval = IXGBE_INCVAL_10GB;
768 shift = IXGBE_INCVAL_SHIFT_10GB;
773 * Modify the calculated values to fit within the correct
774 * number of bits specified by the hardware. The 82599 doesn't
775 * have the same space as the X540, so bitshift the calculated
778 switch (hw->mac.type) {
780 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
782 case ixgbe_mac_82599EB:
783 incval >>= IXGBE_INCVAL_SHIFT_82599;
784 shift -= IXGBE_INCVAL_SHIFT_82599;
785 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
786 (1 << IXGBE_INCPER_SHIFT_82599) |
790 /* other devices aren't supported */
794 /* update the base incval used to calculate frequency adjustment */
795 ACCESS_ONCE(adapter->base_incval) = incval;
798 /* need lock to prevent incorrect read while modifying cyclecounter */
799 spin_lock_irqsave(&adapter->tmreg_lock, flags);
801 memset(&adapter->cc, 0, sizeof(adapter->cc));
802 adapter->cc.read = ixgbe_ptp_read;
803 adapter->cc.mask = CLOCKSOURCE_MASK(64);
804 adapter->cc.shift = shift;
805 adapter->cc.mult = 1;
807 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
812 * @adapter: the ixgbe private board structure
814 * When the MAC resets, all the hardware bits for timesync are reset. This
815 * function is used to re-enable the device for PTP based on current settings.
816 * We do lose the current clock time, so just reset the cyclecounter to the
817 * system real clock time.
819 * This function will maintain hwtstamp_config settings, and resets the SDP
820 * output if it was enabled.
822 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
824 struct ixgbe_hw *hw = &adapter->hw;
827 /* set SYSTIME registers to 0 just in case */
828 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
829 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
830 IXGBE_WRITE_FLUSH(hw);
832 /* reset the hardware timestamping mode */
833 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
835 ixgbe_ptp_start_cyclecounter(adapter);
837 spin_lock_irqsave(&adapter->tmreg_lock, flags);
839 /* reset the ns time counter */
840 timecounter_init(&adapter->tc, &adapter->cc,
841 ktime_to_ns(ktime_get_real()));
843 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
846 * Now that the shift has been calculated and the systime
847 * registers reset, (re-)enable the Clock out feature
849 ixgbe_ptp_setup_sdp(adapter);
853 * ixgbe_ptp_create_clock
854 * @adapter: the ixgbe private adapter structure
856 * This function performs setup of the user entry point function table and
857 * initializes the PTP clock device, which is used to access the clock-like
858 * features of the PTP core. It will be called by ixgbe_ptp_init, only if
859 * there isn't already a clock device (such as after a suspend/resume cycle,
860 * where the clock device wasn't destroyed).
862 static int ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
864 struct net_device *netdev = adapter->netdev;
867 /* do nothing if we already have a clock device */
868 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
871 switch (adapter->hw.mac.type) {
873 snprintf(adapter->ptp_caps.name,
874 sizeof(adapter->ptp_caps.name),
876 adapter->ptp_caps.owner = THIS_MODULE;
877 adapter->ptp_caps.max_adj = 250000000;
878 adapter->ptp_caps.n_alarm = 0;
879 adapter->ptp_caps.n_ext_ts = 0;
880 adapter->ptp_caps.n_per_out = 0;
881 adapter->ptp_caps.pps = 1;
882 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
883 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
884 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
885 adapter->ptp_caps.settime = ixgbe_ptp_settime;
886 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
888 case ixgbe_mac_82599EB:
889 snprintf(adapter->ptp_caps.name,
890 sizeof(adapter->ptp_caps.name),
892 adapter->ptp_caps.owner = THIS_MODULE;
893 adapter->ptp_caps.max_adj = 250000000;
894 adapter->ptp_caps.n_alarm = 0;
895 adapter->ptp_caps.n_ext_ts = 0;
896 adapter->ptp_caps.n_per_out = 0;
897 adapter->ptp_caps.pps = 0;
898 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
899 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
900 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
901 adapter->ptp_caps.settime = ixgbe_ptp_settime;
902 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
905 adapter->ptp_clock = NULL;
909 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
910 &adapter->pdev->dev);
911 if (IS_ERR(adapter->ptp_clock)) {
912 err = PTR_ERR(adapter->ptp_clock);
913 adapter->ptp_clock = NULL;
914 e_dev_err("ptp_clock_register failed\n");
917 e_dev_info("registered PHC device on %s\n", netdev->name);
919 /* set default timestamp mode to disabled here. We do this in
920 * create_clock instead of init, because we don't want to override the
921 * previous settings during a resume cycle.
923 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
924 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
931 * @adapter: the ixgbe private adapter structure
933 * This function performs the required steps for enabling PTP
934 * support. If PTP support has already been loaded it simply calls the
935 * cyclecounter init routine and exits.
937 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
939 /* initialize the spin lock first since we can't control when a user
940 * will call the entry functions once we have initialized the clock
943 spin_lock_init(&adapter->tmreg_lock);
945 /* obtain a PTP device, or re-use an existing device */
946 if (ixgbe_ptp_create_clock(adapter))
949 /* we have a clock so we can initialize work now */
950 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
952 /* reset the PTP related hardware bits */
953 ixgbe_ptp_reset(adapter);
955 /* enter the IXGBE_PTP_RUNNING state */
956 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
962 * ixgbe_ptp_suspend - stop PTP work items
963 * @ adapter: pointer to adapter struct
965 * this function suspends PTP activity, and prevents more PTP work from being
966 * generated, but does not destroy the PTP clock device.
968 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
970 /* Leave the IXGBE_PTP_RUNNING state. */
971 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
974 /* since this might be called in suspend, we don't clear the state,
975 * but simply reset the auxiliary PPS signal control register
977 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TSAUXC, 0x0);
979 /* ensure that we cancel any pending PTP Tx work item in progress */
980 cancel_work_sync(&adapter->ptp_tx_work);
981 if (adapter->ptp_tx_skb) {
982 dev_kfree_skb_any(adapter->ptp_tx_skb);
983 adapter->ptp_tx_skb = NULL;
984 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
989 * ixgbe_ptp_stop - close the PTP device
990 * @adapter: pointer to adapter struct
992 * completely destroy the PTP device, should only be called when the device is
993 * being fully closed.
995 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
997 /* first, suspend PTP activity */
998 ixgbe_ptp_suspend(adapter);
1000 /* disable the PTP clock device */
1001 if (adapter->ptp_clock) {
1002 ptp_clock_unregister(adapter->ptp_clock);
1003 adapter->ptp_clock = NULL;
1004 e_dev_info("removed PHC on %s\n",
1005 adapter->netdev->name);