2 * Copyright (c) 2013 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * This file contains all of the code that is specific to the
37 * QLogic_IB 6120 PCIe chip.
40 #include <linux/interrupt.h>
41 #include <linux/pci.h>
42 #include <linux/delay.h>
43 #include <rdma/ib_verbs.h>
46 #include "qib_6120_regs.h"
48 static void qib_6120_setup_setextled(struct qib_pportdata *, u32);
49 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op);
50 static u8 qib_6120_phys_portstate(u64);
51 static u32 qib_6120_iblink_state(u64);
54 * This file contains all the chip-specific register information and
55 * access functions for the Intel Intel_IB PCI-Express chip.
59 /* KREG_IDX uses machine-generated #defines */
60 #define KREG_IDX(regname) (QIB_6120_##regname##_OFFS / sizeof(u64))
62 /* Use defines to tie machine-generated names to lower-case names */
63 #define kr_extctrl KREG_IDX(EXTCtrl)
64 #define kr_extstatus KREG_IDX(EXTStatus)
65 #define kr_gpio_clear KREG_IDX(GPIOClear)
66 #define kr_gpio_mask KREG_IDX(GPIOMask)
67 #define kr_gpio_out KREG_IDX(GPIOOut)
68 #define kr_gpio_status KREG_IDX(GPIOStatus)
69 #define kr_rcvctrl KREG_IDX(RcvCtrl)
70 #define kr_sendctrl KREG_IDX(SendCtrl)
71 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
72 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
73 #define kr_ibcstatus KREG_IDX(IBCStatus)
74 #define kr_ibcctrl KREG_IDX(IBCCtrl)
75 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
76 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
77 #define kr_counterregbase KREG_IDX(CntrRegBase)
78 #define kr_palign KREG_IDX(PageAlign)
79 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
80 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
81 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
82 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
83 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
84 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
85 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
86 #define kr_scratch KREG_IDX(Scratch)
87 #define kr_sendctrl KREG_IDX(SendCtrl)
88 #define kr_sendpioavailaddr KREG_IDX(SendPIOAvailAddr)
89 #define kr_sendpiobufbase KREG_IDX(SendPIOBufBase)
90 #define kr_sendpiobufcnt KREG_IDX(SendPIOBufCnt)
91 #define kr_sendpiosize KREG_IDX(SendPIOSize)
92 #define kr_sendregbase KREG_IDX(SendRegBase)
93 #define kr_userregbase KREG_IDX(UserRegBase)
94 #define kr_control KREG_IDX(Control)
95 #define kr_intclear KREG_IDX(IntClear)
96 #define kr_intmask KREG_IDX(IntMask)
97 #define kr_intstatus KREG_IDX(IntStatus)
98 #define kr_errclear KREG_IDX(ErrClear)
99 #define kr_errmask KREG_IDX(ErrMask)
100 #define kr_errstatus KREG_IDX(ErrStatus)
101 #define kr_hwerrclear KREG_IDX(HwErrClear)
102 #define kr_hwerrmask KREG_IDX(HwErrMask)
103 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
104 #define kr_revision KREG_IDX(Revision)
105 #define kr_portcnt KREG_IDX(PortCnt)
106 #define kr_serdes_cfg0 KREG_IDX(SerdesCfg0)
107 #define kr_serdes_cfg1 (kr_serdes_cfg0 + 1)
108 #define kr_serdes_stat KREG_IDX(SerdesStat)
109 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
111 /* These must only be written via qib_write_kreg_ctxt() */
112 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
113 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
115 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
116 QIB_6120_LBIntCnt_OFFS) / sizeof(u64))
118 #define cr_badformat CREG_IDX(RxBadFormatCnt)
119 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
120 #define cr_errlink CREG_IDX(RxLinkProblemCnt)
121 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
122 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
123 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlErrCnt)
124 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
125 #define cr_errslen CREG_IDX(TxLenErrCnt)
126 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
127 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
128 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
129 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
130 #define cr_lbint CREG_IDX(LBIntCnt)
131 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
132 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
133 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
134 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
135 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
136 #define cr_pktsend CREG_IDX(TxDataPktCnt)
137 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
138 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
139 #define cr_rcvebp CREG_IDX(RxEBPCnt)
140 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
141 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
142 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
143 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
144 #define cr_wordrcv CREG_IDX(RxDwordCnt)
145 #define cr_wordsend CREG_IDX(TxDwordCnt)
146 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
147 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
148 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
149 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
150 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
152 #define SYM_RMASK(regname, fldname) ((u64) \
153 QIB_6120_##regname##_##fldname##_RMASK)
154 #define SYM_MASK(regname, fldname) ((u64) \
155 QIB_6120_##regname##_##fldname##_RMASK << \
156 QIB_6120_##regname##_##fldname##_LSB)
157 #define SYM_LSB(regname, fldname) (QIB_6120_##regname##_##fldname##_LSB)
159 #define SYM_FIELD(value, regname, fldname) ((u64) \
160 (((value) >> SYM_LSB(regname, fldname)) & \
161 SYM_RMASK(regname, fldname)))
162 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
163 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
165 /* link training states, from IBC */
166 #define IB_6120_LT_STATE_DISABLED 0x00
167 #define IB_6120_LT_STATE_LINKUP 0x01
168 #define IB_6120_LT_STATE_POLLACTIVE 0x02
169 #define IB_6120_LT_STATE_POLLQUIET 0x03
170 #define IB_6120_LT_STATE_SLEEPDELAY 0x04
171 #define IB_6120_LT_STATE_SLEEPQUIET 0x05
172 #define IB_6120_LT_STATE_CFGDEBOUNCE 0x08
173 #define IB_6120_LT_STATE_CFGRCVFCFG 0x09
174 #define IB_6120_LT_STATE_CFGWAITRMT 0x0a
175 #define IB_6120_LT_STATE_CFGIDLE 0x0b
176 #define IB_6120_LT_STATE_RECOVERRETRAIN 0x0c
177 #define IB_6120_LT_STATE_RECOVERWAITRMT 0x0e
178 #define IB_6120_LT_STATE_RECOVERIDLE 0x0f
180 /* link state machine states from IBC */
181 #define IB_6120_L_STATE_DOWN 0x0
182 #define IB_6120_L_STATE_INIT 0x1
183 #define IB_6120_L_STATE_ARM 0x2
184 #define IB_6120_L_STATE_ACTIVE 0x3
185 #define IB_6120_L_STATE_ACT_DEFER 0x4
187 static const u8 qib_6120_physportstate[0x20] = {
188 [IB_6120_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
189 [IB_6120_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
190 [IB_6120_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
191 [IB_6120_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
192 [IB_6120_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
193 [IB_6120_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
194 [IB_6120_LT_STATE_CFGDEBOUNCE] =
195 IB_PHYSPORTSTATE_CFG_TRAIN,
196 [IB_6120_LT_STATE_CFGRCVFCFG] =
197 IB_PHYSPORTSTATE_CFG_TRAIN,
198 [IB_6120_LT_STATE_CFGWAITRMT] =
199 IB_PHYSPORTSTATE_CFG_TRAIN,
200 [IB_6120_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
201 [IB_6120_LT_STATE_RECOVERRETRAIN] =
202 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
203 [IB_6120_LT_STATE_RECOVERWAITRMT] =
204 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
205 [IB_6120_LT_STATE_RECOVERIDLE] =
206 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
207 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
208 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
209 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
210 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
211 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
212 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
213 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
214 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
218 struct qib_chip_specific {
219 u64 __iomem *cregbase;
222 void *dummy_hdrq; /* used after ctxt close */
223 dma_addr_t dummy_hdrq_phys;
224 spinlock_t kernel_tid_lock; /* no back to back kernel TID writes */
225 spinlock_t user_tid_lock; /* no back to back user TID writes */
226 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
227 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
230 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
231 u64 gpio_mask; /* shadow the gpio mask register */
232 u64 extctrl; /* shadow the gpio output enable, etc... */
234 * these 5 fields are used to establish deltas for IB symbol
235 * errors and linkrecovery errors. They can be reported on
236 * some chips during link negotiation prior to INIT, and with
237 * DDR when faking DDR negotiations with non-IBTA switches.
238 * The chip counters are adjusted at driver unload if there is
246 u64 ibcctrl; /* shadow for kr_ibcctrl */
247 u32 lastlinkrecov; /* link recovery issue */
253 /* used with gpio interrupts to implement IB counters */
254 u32 rxfc_unsupvl_errs;
255 u32 overrun_thresh_errs;
257 * these count only cases where _successive_ LocalLinkIntegrity
258 * errors were seen in the receive headers of IB standard packets
263 u64 sword; /* total dwords sent (sample result) */
264 u64 rword; /* total dwords received (sample result) */
265 u64 spkts; /* total packets sent (sample result) */
266 u64 rpkts; /* total packets received (sample result) */
267 u64 xmit_wait; /* # of ticks no data sent (sample result) */
268 struct timer_list pma_timer;
271 u8 pma_sample_status;
275 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
276 /* cycle through TS1/TS2 till OK */
277 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
278 /* wait for TS1, then go on */
279 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
280 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
282 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
283 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
284 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
285 #define QLOGIC_IB_IBCC_LINKCMD_SHIFT 18
288 * We could have a single register get/put routine, that takes a group type,
289 * but this is somewhat clearer and cleaner. It also gives us some error
290 * checking. 64 bit register reads should always work, but are inefficient
291 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
292 * so we use kreg32 wherever possible. User register and counter register
293 * reads are always 32 bit reads, so only one form of those routines.
297 * qib_read_ureg32 - read 32-bit virtualized per-context register
299 * @regno: register number
300 * @ctxt: context number
302 * Return the contents of a register that is virtualized to be per context.
303 * Returns -1 on errors (not distinguishable from valid contents at
304 * runtime; we may add a separate error variable at some point).
306 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
307 enum qib_ureg regno, int ctxt)
309 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
313 return readl(regno + (u64 __iomem *)
314 ((char __iomem *)dd->userbase +
315 dd->ureg_align * ctxt));
317 return readl(regno + (u64 __iomem *)
319 (char __iomem *)dd->kregbase +
320 dd->ureg_align * ctxt));
324 * qib_write_ureg - write 32-bit virtualized per-context register
326 * @regno: register number
330 * Write the contents of a register that is virtualized to be per context.
332 static inline void qib_write_ureg(const struct qib_devdata *dd,
333 enum qib_ureg regno, u64 value, int ctxt)
337 ubase = (u64 __iomem *)
338 ((char __iomem *) dd->userbase +
339 dd->ureg_align * ctxt);
341 ubase = (u64 __iomem *)
343 (char __iomem *) dd->kregbase +
344 dd->ureg_align * ctxt);
346 if (dd->kregbase && (dd->flags & QIB_PRESENT))
347 writeq(value, &ubase[regno]);
350 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
353 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
355 return readl((u32 __iomem *)&dd->kregbase[regno]);
358 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
361 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
364 return readq(&dd->kregbase[regno]);
367 static inline void qib_write_kreg(const struct qib_devdata *dd,
368 const u16 regno, u64 value)
370 if (dd->kregbase && (dd->flags & QIB_PRESENT))
371 writeq(value, &dd->kregbase[regno]);
375 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
376 * @dd: the qlogic_ib device
377 * @regno: the register number to write
378 * @ctxt: the context containing the register
379 * @value: the value to write
381 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
382 const u16 regno, unsigned ctxt,
385 qib_write_kreg(dd, regno + ctxt, value);
388 static inline void write_6120_creg(const struct qib_devdata *dd,
389 u16 regno, u64 value)
391 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
392 writeq(value, &dd->cspec->cregbase[regno]);
395 static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno)
397 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
399 return readq(&dd->cspec->cregbase[regno]);
402 static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno)
404 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
406 return readl(&dd->cspec->cregbase[regno]);
409 /* kr_control bits */
410 #define QLOGIC_IB_C_RESET 1U
412 /* kr_intstatus, kr_intclear, kr_intmask bits */
413 #define QLOGIC_IB_I_RCVURG_MASK ((1U << 5) - 1)
414 #define QLOGIC_IB_I_RCVURG_SHIFT 0
415 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1U << 5) - 1)
416 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 12
418 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
419 #define QLOGIC_IB_C_LINKENABLE 0x00000004
420 #define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
421 #define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
422 #define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
423 #define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
424 #define QLOGIC_IB_I_BITSEXTANT \
425 ((QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
426 (QLOGIC_IB_I_RCVAVAIL_MASK << \
427 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
428 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
429 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO)
431 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
432 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
433 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
434 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
435 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
436 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
437 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
438 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
439 #define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
440 #define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
441 #define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
442 #define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
443 #define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
446 /* kr_extstatus bits */
447 #define QLOGIC_IB_EXTS_FREQSEL 0x2
448 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
449 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
450 #define QLOGIC_IB_EXTS_MEMBIST_FOUND 0x0000000000008000
452 /* kr_xgxsconfig bits */
453 #define QLOGIC_IB_XGXS_RESET 0x5ULL
455 #define _QIB_GPIO_SDA_NUM 1
456 #define _QIB_GPIO_SCL_NUM 0
458 /* Bits in GPIO for the added IB link interrupts */
459 #define GPIO_RXUVL_BIT 3
460 #define GPIO_OVRUN_BIT 4
461 #define GPIO_LLI_BIT 5
462 #define GPIO_ERRINTR_MASK 0x38
465 #define QLOGIC_IB_RT_BUFSIZE_MASK 0xe0000000ULL
466 #define QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid) \
467 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
468 #define QLOGIC_IB_RT_BUFSIZE(tid) (1 << QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid))
469 #define QLOGIC_IB_RT_IS_VALID(tid) \
470 (((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) && \
471 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) != QLOGIC_IB_RT_BUFSIZE_MASK)))
472 #define QLOGIC_IB_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
473 #define QLOGIC_IB_RT_ADDR_SHIFT 10
475 #define QLOGIC_IB_R_INTRAVAIL_SHIFT 16
476 #define QLOGIC_IB_R_TAILUPD_SHIFT 31
477 #define IBA6120_R_PKEY_DIS_SHIFT 30
479 #define PBC_6120_VL15_SEND_CTRL (1ULL << 31) /* pbc; VL15; link_buf only */
481 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
482 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
484 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
485 ((1ULL << (SYM_LSB(regname, fldname) + (bit)))))
487 #define TXEMEMPARITYERR_PIOBUF \
488 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
489 #define TXEMEMPARITYERR_PIOPBC \
490 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
491 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
492 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
494 #define RXEMEMPARITYERR_RCVBUF \
495 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
496 #define RXEMEMPARITYERR_LOOKUPQ \
497 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
498 #define RXEMEMPARITYERR_EXPTID \
499 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
500 #define RXEMEMPARITYERR_EAGERTID \
501 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
502 #define RXEMEMPARITYERR_FLAGBUF \
503 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
504 #define RXEMEMPARITYERR_DATAINFO \
505 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
506 #define RXEMEMPARITYERR_HDRINFO \
507 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
509 /* 6120 specific hardware errors... */
510 static const struct qib_hwerror_msgs qib_6120_hwerror_msgs[] = {
511 /* generic hardware errors */
512 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
513 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
515 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
516 "TXE PIOBUF Memory Parity"),
517 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
518 "TXE PIOPBC Memory Parity"),
519 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
520 "TXE PIOLAUNCHFIFO Memory Parity"),
522 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
523 "RXE RCVBUF Memory Parity"),
524 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
525 "RXE LOOKUPQ Memory Parity"),
526 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
527 "RXE EAGERTID Memory Parity"),
528 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
529 "RXE EXPTID Memory Parity"),
530 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
531 "RXE FLAGBUF Memory Parity"),
532 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
533 "RXE DATAINFO Memory Parity"),
534 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
535 "RXE HDRINFO Memory Parity"),
537 /* chip-specific hardware errors */
538 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
539 "PCIe Poisoned TLP"),
540 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
541 "PCIe completion timeout"),
543 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
544 * parity or memory parity error failures, because most likely we
545 * won't be able to talk to the core of the chip. Nonetheless, we
546 * might see them, if they are in parts of the PCIe core that aren't
549 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
551 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
553 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
554 "PCIe XTLH core parity"),
555 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
556 "PCIe ADM TX core parity"),
557 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
558 "PCIe ADM RX core parity"),
559 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
563 #define TXE_PIO_PARITY (TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC)
564 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
565 QLOGIC_IB_HWE_COREPLL_RFSLIP)
567 /* variables for sanity checking interrupt and errors */
568 #define IB_HWE_BITSEXTANT \
569 (HWE_MASK(RXEMemParityErr) | \
570 HWE_MASK(TXEMemParityErr) | \
571 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
572 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
573 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
574 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
575 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
576 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
577 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
578 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
579 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
580 HWE_MASK(PowerOnBISTFailed) | \
581 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
582 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
583 QLOGIC_IB_HWE_SERDESPLLFAILED | \
584 HWE_MASK(IBCBusToSPCParityErr) | \
585 HWE_MASK(IBCBusFromSPCParityErr))
587 #define IB_E_BITSEXTANT \
588 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
589 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
590 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
591 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
592 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
593 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
594 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
595 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
596 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
597 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendMaxPktLenErr) | \
598 ERR_MASK(SendUnderRunErr) | ERR_MASK(SendPktLenErr) | \
599 ERR_MASK(SendDroppedSmpPktErr) | \
600 ERR_MASK(SendDroppedDataPktErr) | \
601 ERR_MASK(SendPioArmLaunchErr) | \
602 ERR_MASK(SendUnexpectedPktNumErr) | \
603 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(IBStatusChanged) | \
604 ERR_MASK(InvalidAddrErr) | ERR_MASK(ResetNegated) | \
605 ERR_MASK(HardwareErr))
607 #define QLOGIC_IB_E_PKTERRS ( \
608 ERR_MASK(SendPktLenErr) | \
609 ERR_MASK(SendDroppedDataPktErr) | \
610 ERR_MASK(RcvVCRCErr) | \
611 ERR_MASK(RcvICRCErr) | \
612 ERR_MASK(RcvShortPktLenErr) | \
615 /* These are all rcv-related errors which we want to count for stats */
616 #define E_SUM_PKTERRS \
617 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
618 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
619 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
620 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
621 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
622 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
624 /* These are all send-related errors which we want to count for stats */
626 (ERR_MASK(SendPioArmLaunchErr) | \
627 ERR_MASK(SendUnexpectedPktNumErr) | \
628 ERR_MASK(SendDroppedDataPktErr) | \
629 ERR_MASK(SendDroppedSmpPktErr) | \
630 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
631 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
632 ERR_MASK(InvalidAddrErr))
635 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
636 * errors not related to freeze and cancelling buffers. Can't ignore
637 * armlaunch because could get more while still cleaning up, and need
638 * to cancel those as they happen.
640 #define E_SPKT_ERRS_IGNORE \
641 (ERR_MASK(SendDroppedDataPktErr) | \
642 ERR_MASK(SendDroppedSmpPktErr) | \
643 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
644 ERR_MASK(SendPktLenErr))
647 * these are errors that can occur when the link changes state while
648 * a packet is being sent or received. This doesn't cover things
649 * like EBP or VCRC that can be the result of a sending having the
650 * link change state, so we receive a "known bad" packet.
652 #define E_SUM_LINK_PKTERRS \
653 (ERR_MASK(SendDroppedDataPktErr) | \
654 ERR_MASK(SendDroppedSmpPktErr) | \
655 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
656 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
657 ERR_MASK(RcvUnexpectedCharErr))
659 static void qib_6120_put_tid_2(struct qib_devdata *, u64 __iomem *,
663 * On platforms using this chip, and not having ordered WC stores, we
664 * can get TXE parity errors due to speculative reads to the PIO buffers,
665 * and this, due to a chip issue can result in (many) false parity error
666 * reports. So it's a debug print on those, and an info print on systems
667 * where the speculative reads don't occur.
669 static void qib_6120_txe_recover(struct qib_devdata *dd)
671 if (!qib_unordered_wc())
672 qib_devinfo(dd->pcidev,
673 "Recovering from TXE PIO parity error\n");
676 /* enable/disable chip from delivering interrupts */
677 static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable)
680 if (dd->flags & QIB_BADINTR)
682 qib_write_kreg(dd, kr_intmask, ~0ULL);
683 /* force re-interrupt of any pending interrupts. */
684 qib_write_kreg(dd, kr_intclear, 0ULL);
686 qib_write_kreg(dd, kr_intmask, 0ULL);
690 * Try to cleanup as much as possible for anything that might have gone
691 * wrong while in freeze mode, such as pio buffers being written by user
692 * processes (causing armlaunch), send errors due to going into freeze mode,
693 * etc., and try to avoid causing extra interrupts while doing so.
694 * Forcibly update the in-memory pioavail register copies after cleanup
695 * because the chip won't do it while in freeze mode (the register values
696 * themselves are kept correct).
697 * Make sure that we don't lose any important interrupts by using the chip
698 * feature that says that writing 0 to a bit in *clear that is set in
699 * *status will cause an interrupt to be generated again (if allowed by
701 * This is in chip-specific code because of all of the register accesses,
702 * even though the details are similar on most chips
704 static void qib_6120_clear_freeze(struct qib_devdata *dd)
706 /* disable error interrupts, to avoid confusion */
707 qib_write_kreg(dd, kr_errmask, 0ULL);
709 /* also disable interrupts; errormask is sometimes overwriten */
710 qib_6120_set_intr_state(dd, 0);
712 qib_cancel_sends(dd->pport);
714 /* clear the freeze, and be sure chip saw it */
715 qib_write_kreg(dd, kr_control, dd->control);
716 qib_read_kreg32(dd, kr_scratch);
718 /* force in-memory update now we are out of freeze */
719 qib_force_pio_avail_update(dd);
722 * force new interrupt if any hwerr, error or interrupt bits are
723 * still set, and clear "safe" send packet errors related to freeze
724 * and cancelling sends. Re-enable error interrupts before possible
725 * force of re-interrupt on pending interrupts.
727 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
728 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
729 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
730 qib_6120_set_intr_state(dd, 1);
734 * qib_handle_6120_hwerrors - display hardware errors.
735 * @dd: the qlogic_ib device
736 * @msg: the output buffer
737 * @msgl: the size of the output buffer
739 * Use same msg buffer as regular errors to avoid excessive stack
740 * use. Most hardware errors are catastrophic, but for right now,
741 * we'll print them and continue. Reuse the same message buffer as
742 * handle_6120_errors() to avoid excessive stack usage.
744 static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
753 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
756 if (hwerrs == ~0ULL) {
758 "Read of hardware error status failed (all bits set); ignoring\n");
761 qib_stats.sps_hwerrs++;
763 /* Always clear the error status register, except MEMBISTFAIL,
764 * regardless of whether we continue or stop using the chip.
765 * We want that set so we know it failed, even across driver reload.
766 * We'll still ignore it in the hwerrmask. We do this partly for
767 * diagnostics, but also for support */
768 qib_write_kreg(dd, kr_hwerrclear,
769 hwerrs & ~HWE_MASK(PowerOnBISTFailed));
771 hwerrs &= dd->cspec->hwerrmask;
773 /* We log some errors to EEPROM, check if we have any of those. */
774 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
775 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
776 qib_inc_eeprom_err(dd, log_idx, 1);
779 * Make sure we get this much out, unless told to be quiet,
780 * or it's occurred within the last 5 seconds.
782 if (hwerrs & ~(TXE_PIO_PARITY | RXEMEMPARITYERR_EAGERTID))
783 qib_devinfo(dd->pcidev,
784 "Hardware error: hwerr=0x%llx (cleared)\n",
785 (unsigned long long) hwerrs);
787 if (hwerrs & ~IB_HWE_BITSEXTANT)
789 "hwerror interrupt with unknown errors %llx set\n",
790 (unsigned long long)(hwerrs & ~IB_HWE_BITSEXTANT));
792 ctrl = qib_read_kreg32(dd, kr_control);
793 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
795 * Parity errors in send memory are recoverable,
796 * just cancel the send (if indicated in * sendbuffererror),
797 * count the occurrence, unfreeze (if no other handled
798 * hardware error bits are set), and continue. They can
799 * occur if a processor speculative read is done to the PIO
800 * buffer while we are sending a packet, for example.
802 if (hwerrs & TXE_PIO_PARITY) {
803 qib_6120_txe_recover(dd);
804 hwerrs &= ~TXE_PIO_PARITY;
808 static u32 freeze_cnt;
811 qib_6120_clear_freeze(dd);
818 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
821 "[Memory BIST test failed, InfiniPath hardware unusable]",
823 /* ignore from now on, so disable until driver reloaded */
824 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
825 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
828 qib_format_hwerrors(hwerrs, qib_6120_hwerror_msgs,
829 ARRAY_SIZE(qib_6120_hwerror_msgs), msg, msgl);
831 bitsmsg = dd->cspec->bitsmsgbuf;
832 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
833 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
834 bits = (u32) ((hwerrs >>
835 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
836 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
837 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
838 "[PCIe Mem Parity Errs %x] ", bits);
839 strlcat(msg, bitsmsg, msgl);
842 if (hwerrs & _QIB_PLL_FAIL) {
844 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
845 "[PLL failed (%llx), InfiniPath hardware unusable]",
846 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
847 strlcat(msg, bitsmsg, msgl);
848 /* ignore from now on, so disable until driver reloaded */
849 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
850 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
853 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
855 * If it occurs, it is left masked since the external
856 * interface is unused
858 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
859 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
864 * if any set that we aren't ignoring; only
865 * make the complaint once, in case it's stuck
866 * or recurring, and we get here multiple
869 qib_dev_err(dd, "%s hardware error\n", msg);
871 *msg = 0; /* recovered from all of them */
873 if (isfatal && !dd->diag_client) {
875 "Fatal Hardware Error, no longer usable, SN %.16s\n",
878 * for /sys status file and user programs to print; if no
879 * trailing brace is copied, we'll know it was truncated.
882 snprintf(dd->freezemsg, dd->freezelen,
884 qib_disable_after_error(dd);
889 * Decode the error status into strings, deciding whether to always
890 * print * it or not depending on "normal packet errors" vs everything
891 * else. Return 1 if "real" errors, otherwise 0 if only packet
892 * errors, so caller can decide what to print with the string.
894 static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen,
900 if (err & QLOGIC_IB_E_PKTERRS) {
901 if (!(err & ~QLOGIC_IB_E_PKTERRS))
903 if ((err & ERR_MASK(RcvICRCErr)) &&
904 !(err&(ERR_MASK(RcvVCRCErr)|ERR_MASK(RcvEBPErr))))
905 strlcat(buf, "CRC ", blen);
909 if (err & ERR_MASK(RcvHdrLenErr))
910 strlcat(buf, "rhdrlen ", blen);
911 if (err & ERR_MASK(RcvBadTidErr))
912 strlcat(buf, "rbadtid ", blen);
913 if (err & ERR_MASK(RcvBadVersionErr))
914 strlcat(buf, "rbadversion ", blen);
915 if (err & ERR_MASK(RcvHdrErr))
916 strlcat(buf, "rhdr ", blen);
917 if (err & ERR_MASK(RcvLongPktLenErr))
918 strlcat(buf, "rlongpktlen ", blen);
919 if (err & ERR_MASK(RcvMaxPktLenErr))
920 strlcat(buf, "rmaxpktlen ", blen);
921 if (err & ERR_MASK(RcvMinPktLenErr))
922 strlcat(buf, "rminpktlen ", blen);
923 if (err & ERR_MASK(SendMinPktLenErr))
924 strlcat(buf, "sminpktlen ", blen);
925 if (err & ERR_MASK(RcvFormatErr))
926 strlcat(buf, "rformaterr ", blen);
927 if (err & ERR_MASK(RcvUnsupportedVLErr))
928 strlcat(buf, "runsupvl ", blen);
929 if (err & ERR_MASK(RcvUnexpectedCharErr))
930 strlcat(buf, "runexpchar ", blen);
931 if (err & ERR_MASK(RcvIBFlowErr))
932 strlcat(buf, "ribflow ", blen);
933 if (err & ERR_MASK(SendUnderRunErr))
934 strlcat(buf, "sunderrun ", blen);
935 if (err & ERR_MASK(SendPioArmLaunchErr))
936 strlcat(buf, "spioarmlaunch ", blen);
937 if (err & ERR_MASK(SendUnexpectedPktNumErr))
938 strlcat(buf, "sunexperrpktnum ", blen);
939 if (err & ERR_MASK(SendDroppedSmpPktErr))
940 strlcat(buf, "sdroppedsmppkt ", blen);
941 if (err & ERR_MASK(SendMaxPktLenErr))
942 strlcat(buf, "smaxpktlen ", blen);
943 if (err & ERR_MASK(SendUnsupportedVLErr))
944 strlcat(buf, "sunsupVL ", blen);
945 if (err & ERR_MASK(InvalidAddrErr))
946 strlcat(buf, "invalidaddr ", blen);
947 if (err & ERR_MASK(RcvEgrFullErr))
948 strlcat(buf, "rcvegrfull ", blen);
949 if (err & ERR_MASK(RcvHdrFullErr))
950 strlcat(buf, "rcvhdrfull ", blen);
951 if (err & ERR_MASK(IBStatusChanged))
952 strlcat(buf, "ibcstatuschg ", blen);
953 if (err & ERR_MASK(RcvIBLostLinkErr))
954 strlcat(buf, "riblostlink ", blen);
955 if (err & ERR_MASK(HardwareErr))
956 strlcat(buf, "hardware ", blen);
957 if (err & ERR_MASK(ResetNegated))
958 strlcat(buf, "reset ", blen);
964 * Called when we might have an error that is specific to a particular
965 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
967 static void qib_disarm_6120_senderrbufs(struct qib_pportdata *ppd)
969 unsigned long sbuf[2];
970 struct qib_devdata *dd = ppd->dd;
973 * It's possible that sendbuffererror could have bits set; might
974 * have already done this as a result of hardware error handling.
976 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
977 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
979 if (sbuf[0] || sbuf[1])
980 qib_disarm_piobufs_set(dd, sbuf,
981 dd->piobcnt2k + dd->piobcnt4k);
984 static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs)
987 u32 ibstate = qib_6120_iblink_state(ibcs);
988 u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov);
990 if (linkrecov != dd->cspec->lastlinkrecov) {
991 /* and no more until active again */
992 dd->cspec->lastlinkrecov = 0;
993 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN);
996 if (ibstate == IB_PORT_ACTIVE)
997 dd->cspec->lastlinkrecov =
998 read_6120_creg32(dd, cr_iblinkerrrecov);
1002 static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
1005 u64 ignore_this_time = 0;
1008 struct qib_pportdata *ppd = dd->pport;
1011 /* don't report errors that are masked */
1012 errs &= dd->cspec->errormask;
1013 msg = dd->cspec->emsgbuf;
1015 /* do these first, they are most important */
1016 if (errs & ERR_MASK(HardwareErr))
1017 qib_handle_6120_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1019 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1020 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1021 qib_inc_eeprom_err(dd, log_idx, 1);
1023 if (errs & ~IB_E_BITSEXTANT)
1025 "error interrupt with unknown errors %llx set\n",
1026 (unsigned long long) (errs & ~IB_E_BITSEXTANT));
1028 if (errs & E_SUM_ERRS) {
1029 qib_disarm_6120_senderrbufs(ppd);
1030 if ((errs & E_SUM_LINK_PKTERRS) &&
1031 !(ppd->lflags & QIBL_LINKACTIVE)) {
1033 * This can happen when trying to bring the link
1034 * up, but the IB link changes state at the "wrong"
1035 * time. The IB logic then complains that the packet
1036 * isn't valid. We don't want to confuse people, so
1037 * we just don't print them, except at debug
1039 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1041 } else if ((errs & E_SUM_LINK_PKTERRS) &&
1042 !(ppd->lflags & QIBL_LINKACTIVE)) {
1044 * This can happen when SMA is trying to bring the link
1045 * up, but the IB link changes state at the "wrong" time.
1046 * The IB logic then complains that the packet isn't
1047 * valid. We don't want to confuse people, so we just
1048 * don't print them, except at debug
1050 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1053 qib_write_kreg(dd, kr_errclear, errs);
1055 errs &= ~ignore_this_time;
1060 * The ones we mask off are handled specially below
1063 mask = ERR_MASK(IBStatusChanged) | ERR_MASK(RcvEgrFullErr) |
1064 ERR_MASK(RcvHdrFullErr) | ERR_MASK(HardwareErr);
1065 qib_decode_6120_err(dd, msg, sizeof dd->cspec->emsgbuf, errs & ~mask);
1067 if (errs & E_SUM_PKTERRS)
1068 qib_stats.sps_rcverrs++;
1069 if (errs & E_SUM_ERRS)
1070 qib_stats.sps_txerrs++;
1072 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS);
1074 if (errs & ERR_MASK(IBStatusChanged)) {
1075 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1076 u32 ibstate = qib_6120_iblink_state(ibcs);
1079 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov)
1080 handle = chk_6120_linkrecovery(dd, ibcs);
1082 * Since going into a recovery state causes the link state
1083 * to go down and since recovery is transitory, it is better
1084 * if we "miss" ever seeing the link training state go into
1085 * recovery (i.e., ignore this transition for link state
1086 * special handling purposes) without updating lastibcstat.
1088 if (handle && qib_6120_phys_portstate(ibcs) ==
1089 IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1092 qib_handle_e_ibstatuschanged(ppd, ibcs);
1095 if (errs & ERR_MASK(ResetNegated)) {
1097 "Got reset, requires re-init (unload and reload driver)\n");
1098 dd->flags &= ~QIB_INITTED; /* needs re-init */
1099 /* mark as having had error */
1100 *dd->devstatusp |= QIB_STATUS_HWERROR;
1101 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1105 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1107 if (ppd->state_wanted & ppd->lflags)
1108 wake_up_interruptible(&ppd->state_wait);
1111 * If there were hdrq or egrfull errors, wake up any processes
1112 * waiting in poll. We used to try to check which contexts had
1113 * the overflow, but given the cost of that and the chip reads
1114 * to support it, it's better to just wake everybody up if we
1115 * get an overflow; waiters can poll again if it's not them.
1117 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1118 qib_handle_urcv(dd, ~0U);
1119 if (errs & ERR_MASK(RcvEgrFullErr))
1120 qib_stats.sps_buffull++;
1122 qib_stats.sps_hdrfull++;
1129 * qib_6120_init_hwerrors - enable hardware errors
1130 * @dd: the qlogic_ib device
1132 * now that we have finished initializing everything that might reasonably
1133 * cause a hardware error, and cleared those errors bits as they occur,
1134 * we can enable hardware errors in the mask (potentially enabling
1135 * freeze mode), and enable hardware errors as errors (along with
1136 * everything else) in errormask
1138 static void qib_6120_init_hwerrors(struct qib_devdata *dd)
1143 extsval = qib_read_kreg64(dd, kr_extstatus);
1145 if (!(extsval & QLOGIC_IB_EXTS_MEMBIST_ENDTEST))
1146 qib_dev_err(dd, "MemBIST did not complete!\n");
1148 /* init so all hwerrors interrupt, and enter freeze, ajdust below */
1150 if (dd->minrev < 2) {
1152 * Avoid problem with internal interface bus parity
1153 * checking. Fixed in Rev2.
1155 val &= ~QLOGIC_IB_HWE_PCIEBUSPARITYRADM;
1157 /* avoid some intel cpu's speculative read freeze mode issue */
1158 val &= ~TXEMEMPARITYERR_PIOBUF;
1160 dd->cspec->hwerrmask = val;
1162 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1163 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1166 qib_write_kreg(dd, kr_errclear, ~0ULL);
1167 /* enable errors that are masked, at least this first time. */
1168 qib_write_kreg(dd, kr_errmask, ~0ULL);
1169 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1170 /* clear any interrupts up to this point (ints still not enabled) */
1171 qib_write_kreg(dd, kr_intclear, ~0ULL);
1173 qib_write_kreg(dd, kr_rcvbthqp,
1174 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) |
1179 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
1180 * on chips that are count-based, rather than trigger-based. There is no
1181 * reference counting, but that's also fine, given the intended use.
1182 * Only chip-specific because it's all register accesses
1184 static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable)
1187 qib_write_kreg(dd, kr_errclear,
1188 ERR_MASK(SendPioArmLaunchErr));
1189 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1191 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1192 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1196 * Formerly took parameter <which> in pre-shifted,
1197 * pre-merged form with LinkCmd and LinkInitCmd
1198 * together, and assuming the zero was NOP.
1200 static void qib_set_ib_6120_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1204 struct qib_devdata *dd = ppd->dd;
1205 unsigned long flags;
1207 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1209 * If we are told to disable, note that so link-recovery
1210 * code does not attempt to bring us back up.
1212 spin_lock_irqsave(&ppd->lflags_lock, flags);
1213 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1214 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1215 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1217 * Any other linkinitcmd will lead to LINKDOWN and then
1218 * to INIT (if all is well), so clear flag to let
1219 * link-recovery code attempt to bring us back up.
1221 spin_lock_irqsave(&ppd->lflags_lock, flags);
1222 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1223 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1226 mod_wd = (linkcmd << QLOGIC_IB_IBCC_LINKCMD_SHIFT) |
1227 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1229 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd);
1230 /* write to chip to prevent back-to-back writes of control reg */
1231 qib_write_kreg(dd, kr_scratch, 0);
1235 * qib_6120_bringup_serdes - bring up the serdes
1236 * @dd: the qlogic_ib device
1238 static int qib_6120_bringup_serdes(struct qib_pportdata *ppd)
1240 struct qib_devdata *dd = ppd->dd;
1241 u64 val, config1, prev_val, hwstat, ibc;
1243 /* Put IBC in reset, sends disabled */
1244 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1245 qib_write_kreg(dd, kr_control, 0ULL);
1247 dd->cspec->ibdeltainprog = 1;
1248 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr);
1249 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov);
1251 /* flowcontrolwatermark is in units of KBytes */
1252 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1254 * How often flowctrl sent. More or less in usecs; balance against
1255 * watermark value, so that in theory senders always get a flow
1256 * control update in time to not let the IB link go idle.
1258 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1259 /* max error tolerance */
1260 dd->cspec->lli_thresh = 0xf;
1261 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold);
1262 /* use "real" buffer space for */
1263 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1264 /* IB credit flow control. */
1265 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1267 * set initial max size pkt IBC will send, including ICRC; it's the
1268 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1270 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1271 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1273 /* initially come up waiting for TS1, without sending anything. */
1274 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1275 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1276 qib_write_kreg(dd, kr_ibcctrl, val);
1278 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1279 config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1282 * Force reset on, also set rxdetect enable. Must do before reading
1283 * serdesstatus at least for simulation, or some of the bits in
1284 * serdes status will come back as undefined and cause simulation
1287 val |= SYM_MASK(SerdesCfg0, ResetPLL) |
1288 SYM_MASK(SerdesCfg0, RxDetEnX) |
1289 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1290 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1291 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1292 SYM_MASK(SerdesCfg0, L1PwrDnD));
1293 qib_write_kreg(dd, kr_serdes_cfg0, val);
1294 /* be sure chip saw it */
1295 qib_read_kreg64(dd, kr_scratch);
1296 udelay(5); /* need pll reset set at least for a bit */
1298 * after PLL is reset, set the per-lane Resets and TxIdle and
1299 * clear the PLL reset and rxdetect (to get falling edge).
1300 * Leave L1PWR bits set (permanently)
1302 val &= ~(SYM_MASK(SerdesCfg0, RxDetEnX) |
1303 SYM_MASK(SerdesCfg0, ResetPLL) |
1304 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1305 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1306 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1307 SYM_MASK(SerdesCfg0, L1PwrDnD)));
1308 val |= (SYM_MASK(SerdesCfg0, ResetA) |
1309 SYM_MASK(SerdesCfg0, ResetB) |
1310 SYM_MASK(SerdesCfg0, ResetC) |
1311 SYM_MASK(SerdesCfg0, ResetD)) |
1312 SYM_MASK(SerdesCfg0, TxIdeEnX);
1313 qib_write_kreg(dd, kr_serdes_cfg0, val);
1314 /* be sure chip saw it */
1315 (void) qib_read_kreg64(dd, kr_scratch);
1316 /* need PLL reset clear for at least 11 usec before lane
1317 * resets cleared; give it a few more to be sure */
1319 val &= ~((SYM_MASK(SerdesCfg0, ResetA) |
1320 SYM_MASK(SerdesCfg0, ResetB) |
1321 SYM_MASK(SerdesCfg0, ResetC) |
1322 SYM_MASK(SerdesCfg0, ResetD)) |
1323 SYM_MASK(SerdesCfg0, TxIdeEnX));
1325 qib_write_kreg(dd, kr_serdes_cfg0, val);
1326 /* be sure chip saw it */
1327 (void) qib_read_kreg64(dd, kr_scratch);
1329 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1331 if (val & QLOGIC_IB_XGXS_RESET)
1332 val &= ~QLOGIC_IB_XGXS_RESET;
1333 if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) {
1334 /* need to compensate for Tx inversion in partner */
1335 val &= ~SYM_MASK(XGXSCfg, polarity_inv);
1336 val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv);
1338 if (val != prev_val)
1339 qib_write_kreg(dd, kr_xgxs_cfg, val);
1341 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1343 /* clear current and de-emphasis bits */
1344 config1 &= ~0x0ffffffff00ULL;
1345 /* set current to 20ma */
1346 config1 |= 0x00000000000ULL;
1347 /* set de-emphasis to -5.68dB */
1348 config1 |= 0x0cccc000000ULL;
1349 qib_write_kreg(dd, kr_serdes_cfg1, config1);
1351 /* base and port guid same for single port */
1352 ppd->guid = dd->base_guid;
1355 * the process of setting and un-resetting the serdes normally
1356 * causes a serdes PLL error, so check for that and clear it
1357 * here. Also clearr hwerr bit in errstatus, but not others.
1359 hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1361 /* should just have PLL, clear all set, in an case */
1362 qib_write_kreg(dd, kr_hwerrclear, hwstat);
1363 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr));
1366 dd->control |= QLOGIC_IB_C_LINKENABLE;
1367 dd->control &= ~QLOGIC_IB_C_FREEZEMODE;
1368 qib_write_kreg(dd, kr_control, dd->control);
1374 * qib_6120_quiet_serdes - set serdes to txidle
1375 * @ppd: physical port of the qlogic_ib device
1376 * Called when driver is being unloaded
1378 static void qib_6120_quiet_serdes(struct qib_pportdata *ppd)
1380 struct qib_devdata *dd = ppd->dd;
1383 qib_set_ib_6120_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1386 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1387 qib_write_kreg(dd, kr_control,
1388 dd->control | QLOGIC_IB_C_FREEZEMODE);
1390 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta ||
1391 dd->cspec->ibdeltainprog) {
1394 /* enable counter writes */
1395 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1396 qib_write_kreg(dd, kr_hwdiagctrl,
1397 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1399 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) {
1400 val = read_6120_creg32(dd, cr_ibsymbolerr);
1401 if (dd->cspec->ibdeltainprog)
1402 val -= val - dd->cspec->ibsymsnap;
1403 val -= dd->cspec->ibsymdelta;
1404 write_6120_creg(dd, cr_ibsymbolerr, val);
1406 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) {
1407 val = read_6120_creg32(dd, cr_iblinkerrrecov);
1408 if (dd->cspec->ibdeltainprog)
1409 val -= val - dd->cspec->iblnkerrsnap;
1410 val -= dd->cspec->iblnkerrdelta;
1411 write_6120_creg(dd, cr_iblinkerrrecov, val);
1414 /* and disable counter writes */
1415 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1418 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1419 val |= SYM_MASK(SerdesCfg0, TxIdeEnX);
1420 qib_write_kreg(dd, kr_serdes_cfg0, val);
1424 * qib_6120_setup_setextled - set the state of the two external LEDs
1425 * @dd: the qlogic_ib device
1426 * @on: whether the link is up or not
1428 * The exact combo of LEDs if on is true is determined by looking
1431 * These LEDs indicate the physical and logical state of IB link.
1432 * For this chip (at least with recommended board pinouts), LED1
1433 * is Yellow (logical state) and LED2 is Green (physical state),
1435 * Note: We try to match the Mellanox HCA LED behavior as best
1436 * we can. Green indicates physical link state is OK (something is
1437 * plugged in, and we can train).
1438 * Amber indicates the link is logically up (ACTIVE).
1439 * Mellanox further blinks the amber LED to indicate data packet
1440 * activity, but we have no hardware support for that, so it would
1441 * require waking up every 10-20 msecs and checking the counters
1442 * on the chip, and then turning the LED off if appropriate. That's
1443 * visible overhead, so not something we will do.
1446 static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on)
1448 u64 extctl, val, lst, ltst;
1449 unsigned long flags;
1450 struct qib_devdata *dd = ppd->dd;
1453 * The diags use the LED to indicate diag info, so we leave
1454 * the external LED alone when the diags are running.
1456 if (dd->diag_client)
1459 /* Allow override of LED display for, e.g. Locating system in rack */
1460 if (ppd->led_override) {
1461 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1462 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1463 lst = (ppd->led_override & QIB_LED_LOG) ?
1464 IB_PORT_ACTIVE : IB_PORT_DOWN;
1466 val = qib_read_kreg64(dd, kr_ibcstatus);
1467 ltst = qib_6120_phys_portstate(val);
1468 lst = qib_6120_iblink_state(val);
1474 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1475 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1476 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1478 if (ltst == IB_PHYSPORTSTATE_LINKUP)
1479 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1480 if (lst == IB_PORT_ACTIVE)
1481 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1482 dd->cspec->extctrl = extctl;
1483 qib_write_kreg(dd, kr_extctrl, extctl);
1484 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1487 static void qib_6120_free_irq(struct qib_devdata *dd)
1489 if (dd->cspec->irq) {
1490 free_irq(dd->cspec->irq, dd);
1497 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
1498 * @dd: the qlogic_ib device
1500 * This is called during driver unload.
1502 static void qib_6120_setup_cleanup(struct qib_devdata *dd)
1504 qib_6120_free_irq(dd);
1505 kfree(dd->cspec->cntrs);
1506 kfree(dd->cspec->portcntrs);
1507 if (dd->cspec->dummy_hdrq) {
1508 dma_free_coherent(&dd->pcidev->dev,
1509 ALIGN(dd->rcvhdrcnt *
1511 sizeof(u32), PAGE_SIZE),
1512 dd->cspec->dummy_hdrq,
1513 dd->cspec->dummy_hdrq_phys);
1514 dd->cspec->dummy_hdrq = NULL;
1518 static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint)
1520 unsigned long flags;
1522 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1524 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail);
1526 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail);
1527 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1528 qib_write_kreg(dd, kr_scratch, 0ULL);
1529 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1533 * handle errors and unusual events first, separate function
1534 * to improve cache hits for fast path interrupt handling
1536 static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat)
1538 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1539 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n",
1540 istat & ~QLOGIC_IB_I_BITSEXTANT);
1542 if (istat & QLOGIC_IB_I_ERROR) {
1545 qib_stats.sps_errints++;
1546 estat = qib_read_kreg64(dd, kr_errstatus);
1548 qib_devinfo(dd->pcidev,
1549 "error interrupt (%Lx), but no error bits set!\n",
1551 handle_6120_errors(dd, estat);
1554 if (istat & QLOGIC_IB_I_GPIO) {
1559 * GPIO_3..5 on IBA6120 Rev2 chips indicate
1560 * errors that we need to count.
1562 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1563 /* First the error-counter case. */
1564 if (gpiostatus & GPIO_ERRINTR_MASK) {
1565 /* want to clear the bits we see asserted. */
1566 to_clear |= (gpiostatus & GPIO_ERRINTR_MASK);
1569 * Count appropriately, clear bits out of our copy,
1570 * as they have been "handled".
1572 if (gpiostatus & (1 << GPIO_RXUVL_BIT))
1573 dd->cspec->rxfc_unsupvl_errs++;
1574 if (gpiostatus & (1 << GPIO_OVRUN_BIT))
1575 dd->cspec->overrun_thresh_errs++;
1576 if (gpiostatus & (1 << GPIO_LLI_BIT))
1577 dd->cspec->lli_errs++;
1578 gpiostatus &= ~GPIO_ERRINTR_MASK;
1582 * Some unexpected bits remain. If they could have
1583 * caused the interrupt, complain and clear.
1584 * To avoid repetition of this condition, also clear
1585 * the mask. It is almost certainly due to error.
1587 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1590 * Also check that the chip reflects our shadow,
1591 * and report issues, If they caused the interrupt.
1592 * we will suppress by refreshing from the shadow.
1594 if (mask & gpiostatus) {
1595 to_clear |= (gpiostatus & mask);
1596 dd->cspec->gpio_mask &= ~(gpiostatus & mask);
1597 qib_write_kreg(dd, kr_gpio_mask,
1598 dd->cspec->gpio_mask);
1602 qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear);
1606 static irqreturn_t qib_6120intr(int irq, void *data)
1608 struct qib_devdata *dd = data;
1610 u32 istat, ctxtrbits, rmask, crcs = 0;
1613 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1615 * This return value is not great, but we do not want the
1616 * interrupt core code to remove our interrupt handler
1617 * because we don't appear to be handling an interrupt
1618 * during a chip reset.
1624 istat = qib_read_kreg32(dd, kr_intstatus);
1626 if (unlikely(!istat)) {
1627 ret = IRQ_NONE; /* not our interrupt, or already handled */
1630 if (unlikely(istat == -1)) {
1631 qib_bad_intrstatus(dd);
1632 /* don't know if it was our interrupt or not */
1637 this_cpu_inc(*dd->int_counter);
1639 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1640 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1641 unlikely_6120_intr(dd, istat);
1644 * Clear the interrupt bits we found set, relatively early, so we
1645 * "know" know the chip will have seen this by the time we process
1646 * the queue, and will re-interrupt if necessary. The processor
1647 * itself won't take the interrupt again until we return.
1649 qib_write_kreg(dd, kr_intclear, istat);
1652 * Handle kernel receive queues before checking for pio buffers
1653 * available since receives can overflow; piobuf waiters can afford
1654 * a few extra cycles, since they were waiting anyway.
1657 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1658 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1660 rmask = (1U << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1661 (1U << QLOGIC_IB_I_RCVURG_SHIFT);
1662 for (i = 0; i < dd->first_user_ctxt; i++) {
1663 if (ctxtrbits & rmask) {
1664 ctxtrbits &= ~rmask;
1665 crcs += qib_kreceive(dd->rcd[i],
1666 &dd->cspec->lli_counter,
1672 u32 cntr = dd->cspec->lli_counter;
1675 if (cntr > dd->cspec->lli_thresh) {
1676 dd->cspec->lli_counter = 0;
1677 dd->cspec->lli_errs++;
1679 dd->cspec->lli_counter += cntr;
1686 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1687 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
1688 qib_handle_urcv(dd, ctxtrbits);
1692 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
1693 qib_ib_piobufavail(dd);
1701 * Set up our chip-specific interrupt handler
1702 * The interrupt type has already been setup, so
1703 * we just need to do the registration and error checking.
1705 static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1708 * If the chip supports added error indication via GPIO pins,
1709 * enable interrupts on those bits so the interrupt routine
1710 * can count the events. Also set flag so interrupt routine
1711 * can know they are expected.
1713 if (SYM_FIELD(dd->revision, Revision_R,
1714 ChipRevMinor) > 1) {
1715 /* Rev2+ reports extra errors via internal GPIO pins */
1716 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK;
1717 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1720 if (!dd->cspec->irq)
1722 "irq is 0, BIOS error? Interrupts won't work\n");
1725 ret = request_irq(dd->cspec->irq, qib_6120intr, 0,
1729 "Couldn't setup interrupt (irq=%d): %d\n",
1730 dd->cspec->irq, ret);
1735 * pe_boardname - fill in the board name
1736 * @dd: the qlogic_ib device
1738 * info is based on the board revision register
1740 static void pe_boardname(struct qib_devdata *dd)
1743 u32 boardid, namelen;
1745 boardid = SYM_FIELD(dd->revision, Revision,
1750 n = "InfiniPath_QLE7140";
1753 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid);
1754 n = "Unknown_InfiniPath_6120";
1757 namelen = strlen(n) + 1;
1758 dd->boardname = kmalloc(namelen, GFP_KERNEL);
1760 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
1762 snprintf(dd->boardname, namelen, "%s", n);
1764 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2)
1766 "Unsupported InfiniPath hardware revision %u.%u!\n",
1767 dd->majrev, dd->minrev);
1769 snprintf(dd->boardversion, sizeof(dd->boardversion),
1770 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
1771 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
1772 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
1773 dd->majrev, dd->minrev,
1774 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
1779 * This routine sleeps, so it can only be called from user context, not
1780 * from interrupt context. If we need interrupt context, we can split
1781 * it into two routines.
1783 static int qib_6120_setup_reset(struct qib_devdata *dd)
1789 u8 int_line, clinesz;
1791 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
1793 /* Use ERROR so it shows up in logs, etc. */
1794 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
1796 /* no interrupts till re-initted */
1797 qib_6120_set_intr_state(dd, 0);
1799 dd->cspec->ibdeltainprog = 0;
1800 dd->cspec->ibsymdelta = 0;
1801 dd->cspec->iblnkerrdelta = 0;
1804 * Keep chip from being accessed until we are ready. Use
1805 * writeq() directly, to allow the write even though QIB_PRESENT
1808 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
1809 /* so we check interrupts work again */
1810 dd->z_int_counter = qib_int_counter(dd);
1811 val = dd->control | QLOGIC_IB_C_RESET;
1812 writeq(val, &dd->kregbase[kr_control]);
1813 mb(); /* prevent compiler re-ordering around actual reset */
1815 for (i = 1; i <= 5; i++) {
1817 * Allow MBIST, etc. to complete; longer on each retry.
1818 * We sometimes get machine checks from bus timeout if no
1819 * response, so for now, make it *really* long.
1821 msleep(1000 + (1 + i) * 2000);
1823 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
1826 * Use readq directly, so we don't need to mark it as PRESENT
1827 * until we get a successful indication that all is well.
1829 val = readq(&dd->kregbase[kr_revision]);
1830 if (val == dd->revision) {
1831 dd->flags |= QIB_PRESENT; /* it's back */
1832 ret = qib_reinit_intr(dd);
1836 ret = 0; /* failed */
1840 if (qib_pcie_params(dd, dd->lbus_width, NULL, NULL))
1842 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
1843 /* clear the reset error, init error/hwerror mask */
1844 qib_6120_init_hwerrors(dd);
1845 /* for Rev2 error interrupts; nop for rev 1 */
1846 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1847 /* clear the reset error, init error/hwerror mask */
1848 qib_6120_init_hwerrors(dd);
1854 * qib_6120_put_tid - write a TID in chip
1855 * @dd: the qlogic_ib device
1856 * @tidptr: pointer to the expected TID (in chip) to update
1857 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1859 * @pa: physical address of in memory buffer; tidinvalid if freeing
1861 * This exists as a separate routine to allow for special locking etc.
1862 * It's used for both the full cleanup on exit, as well as the normal
1863 * setup and teardown.
1865 static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
1866 u32 type, unsigned long pa)
1868 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1869 unsigned long flags;
1871 spinlock_t *tidlockp; /* select appropriate spinlock */
1876 if (pa != dd->tidinvalid) {
1877 if (pa & ((1U << 11) - 1)) {
1878 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1883 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1885 "Physical page address 0x%lx larger than supported\n",
1890 if (type == RCVHQ_RCV_TYPE_EAGER)
1891 pa |= dd->tidtemplate;
1892 else /* for now, always full 4KB page */
1897 * Avoid chip issue by writing the scratch register
1898 * before and after the TID, and with an io write barrier.
1899 * We use a spinlock around the writes, so they can't intermix
1900 * with other TID (eager or expected) writes (the chip problem
1901 * is triggered by back to back TID writes). Unfortunately, this
1902 * call can be done from interrupt level for the ctxt 0 eager TIDs,
1903 * so we have to use irqsave locks.
1906 * Assumes tidptr always > egrtidbase
1907 * if type == RCVHQ_RCV_TYPE_EAGER.
1909 tidx = tidptr - dd->egrtidbase;
1911 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt)
1912 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock;
1913 spin_lock_irqsave(tidlockp, flags);
1914 qib_write_kreg(dd, kr_scratch, 0xfeeddeaf);
1916 qib_write_kreg(dd, kr_scratch, 0xdeadbeef);
1918 spin_unlock_irqrestore(tidlockp, flags);
1922 * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher
1923 * @dd: the qlogic_ib device
1924 * @tidptr: pointer to the expected TID (in chip) to update
1925 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1927 * @pa: physical address of in memory buffer; tidinvalid if freeing
1929 * This exists as a separate routine to allow for selection of the
1930 * appropriate "flavor". The static calls in cleanup just use the
1931 * revision-agnostic form, as they are not performance critical.
1933 static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1934 u32 type, unsigned long pa)
1936 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1942 if (pa != dd->tidinvalid) {
1943 if (pa & ((1U << 11) - 1)) {
1944 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1949 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1951 "Physical page address 0x%lx larger than supported\n",
1956 if (type == RCVHQ_RCV_TYPE_EAGER)
1957 pa |= dd->tidtemplate;
1958 else /* for now, always full 4KB page */
1961 tidx = tidptr - dd->egrtidbase;
1968 * qib_6120_clear_tids - clear all TID entries for a context, expected and eager
1969 * @dd: the qlogic_ib device
1970 * @ctxt: the context
1972 * clear all TID entries for a context, expected and eager.
1973 * Used from qib_close(). On this chip, TIDs are only 32 bits,
1974 * not 64, but they are still on 64 bit boundaries, so tidbase
1975 * is declared as u64 * for the pointer math, even though we write 32 bits
1977 static void qib_6120_clear_tids(struct qib_devdata *dd,
1978 struct qib_ctxtdata *rcd)
1980 u64 __iomem *tidbase;
1981 unsigned long tidinv;
1985 if (!dd->kregbase || !rcd)
1990 tidinv = dd->tidinvalid;
1991 tidbase = (u64 __iomem *)
1992 ((char __iomem *)(dd->kregbase) +
1994 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
1996 for (i = 0; i < dd->rcvtidcnt; i++)
1997 /* use func pointer because could be one of two funcs */
1998 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
2001 tidbase = (u64 __iomem *)
2002 ((char __iomem *)(dd->kregbase) +
2004 rcd->rcvegr_tid_base * sizeof(*tidbase));
2006 for (i = 0; i < rcd->rcvegrcnt; i++)
2007 /* use func pointer because could be one of two funcs */
2008 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
2013 * qib_6120_tidtemplate - setup constants for TID updates
2014 * @dd: the qlogic_ib device
2016 * We setup stuff that we use a lot, to avoid calculating each time
2018 static void qib_6120_tidtemplate(struct qib_devdata *dd)
2020 u32 egrsize = dd->rcvegrbufsize;
2023 * For now, we always allocate 4KB buffers (at init) so we can
2024 * receive max size packets. We may want a module parameter to
2025 * specify 2KB or 4KB and/or make be per ctxt instead of per device
2026 * for those who want to reduce memory footprint. Note that the
2027 * rcvhdrentsize size must be large enough to hold the largest
2028 * IB header (currently 96 bytes) that we expect to handle (plus of
2029 * course the 2 dwords of RHF).
2031 if (egrsize == 2048)
2032 dd->tidtemplate = 1U << 29;
2033 else if (egrsize == 4096)
2034 dd->tidtemplate = 2U << 29;
2038 int __attribute__((weak)) qib_unordered_wc(void)
2044 * qib_6120_get_base_info - set chip-specific flags for user code
2045 * @rcd: the qlogic_ib ctxt
2046 * @kbase: qib_base_info pointer
2048 * We set the PCIE flag because the lower bandwidth on PCIe vs
2049 * HyperTransport can affect some user packet algorithms.
2051 static int qib_6120_get_base_info(struct qib_ctxtdata *rcd,
2052 struct qib_base_info *kinfo)
2054 if (qib_unordered_wc())
2055 kinfo->spi_runtime_flags |= QIB_RUNTIME_FORCE_WC_ORDER;
2057 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2058 QIB_RUNTIME_FORCE_PIOAVAIL | QIB_RUNTIME_PIO_REGSWAPPED;
2063 static struct qib_message_header *
2064 qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2066 return (struct qib_message_header *)
2067 &rhf_addr[sizeof(u64) / sizeof(u32)];
2070 static void qib_6120_config_ctxts(struct qib_devdata *dd)
2072 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt);
2073 if (qib_n_krcv_queues > 1) {
2074 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2075 if (dd->first_user_ctxt > dd->ctxtcnt)
2076 dd->first_user_ctxt = dd->ctxtcnt;
2077 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6;
2079 dd->first_user_ctxt = dd->num_pports;
2080 dd->n_krcv_queues = dd->first_user_ctxt;
2083 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2084 u32 updegr, u32 egrhd, u32 npkts)
2087 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2089 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2093 static u32 qib_6120_hdrqempty(struct qib_ctxtdata *rcd)
2097 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2098 if (rcd->rcvhdrtail_kvaddr)
2099 tail = qib_get_rcvhdrtail(rcd);
2101 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2102 return head == tail;
2106 * Used when we close any ctxt, for DMA already in flight
2107 * at close. Can't be done until we know hdrq size, so not
2108 * early in chip init.
2110 static void alloc_dummy_hdrq(struct qib_devdata *dd)
2112 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev,
2113 dd->rcd[0]->rcvhdrq_size,
2114 &dd->cspec->dummy_hdrq_phys,
2115 GFP_ATOMIC | __GFP_COMP);
2116 if (!dd->cspec->dummy_hdrq) {
2117 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n");
2118 /* fallback to just 0'ing */
2119 dd->cspec->dummy_hdrq_phys = 0UL;
2124 * Modify the RCVCTRL register in chip-specific way. This
2125 * is a function because bit positions and (future) register
2126 * location is chip-specific, but the needed operations are
2127 * generic. <op> is a bit-mask because we often want to
2128 * do multiple modifications.
2130 static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op,
2133 struct qib_devdata *dd = ppd->dd;
2135 unsigned long flags;
2137 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2139 if (op & QIB_RCVCTRL_TAILUPD_ENB)
2140 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2141 if (op & QIB_RCVCTRL_TAILUPD_DIS)
2142 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2143 if (op & QIB_RCVCTRL_PKEY_ENB)
2144 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2145 if (op & QIB_RCVCTRL_PKEY_DIS)
2146 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2148 mask = (1ULL << dd->ctxtcnt) - 1;
2150 mask = (1ULL << ctxt);
2151 if (op & QIB_RCVCTRL_CTXT_ENB) {
2152 /* always done for specific ctxt */
2153 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2154 if (!(dd->flags & QIB_NODMA_RTAIL))
2155 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT;
2156 /* Write these registers before the context is enabled. */
2157 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2158 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2159 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2160 dd->rcd[ctxt]->rcvhdrq_phys);
2162 if (ctxt == 0 && !dd->cspec->dummy_hdrq)
2163 alloc_dummy_hdrq(dd);
2165 if (op & QIB_RCVCTRL_CTXT_DIS)
2166 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2167 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2168 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2169 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2170 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2171 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2172 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2173 /* arm rcv interrupt */
2174 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2175 dd->rhdrhead_intr_off;
2176 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2178 if (op & QIB_RCVCTRL_CTXT_ENB) {
2180 * Init the context registers also; if we were
2181 * disabled, tail and head should both be zero
2182 * already from the enable, but since we don't
2183 * know, we have to do it explicitly.
2185 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2186 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2188 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2189 dd->rcd[ctxt]->head = val;
2190 /* If kctxt, interrupt on next receive. */
2191 if (ctxt < dd->first_user_ctxt)
2192 val |= dd->rhdrhead_intr_off;
2193 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2195 if (op & QIB_RCVCTRL_CTXT_DIS) {
2197 * Be paranoid, and never write 0's to these, just use an
2198 * unused page. Of course,
2199 * rcvhdraddr points to a large chunk of memory, so this
2200 * could still trash things, but at least it won't trash
2201 * page 0, and by disabling the ctxt, it should stop "soon",
2202 * even if a packet or two is in already in flight after we
2203 * disabled the ctxt. Only 6120 has this issue.
2206 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2207 dd->cspec->dummy_hdrq_phys);
2208 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2209 dd->cspec->dummy_hdrq_phys);
2213 for (i = 0; i < dd->cfgctxts; i++) {
2214 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2215 i, dd->cspec->dummy_hdrq_phys);
2216 qib_write_kreg_ctxt(dd, kr_rcvhdraddr,
2217 i, dd->cspec->dummy_hdrq_phys);
2221 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2225 * Modify the SENDCTRL register in chip-specific way. This
2226 * is a function there may be multiple such registers with
2227 * slightly different layouts. Only operations actually used
2228 * are implemented yet.
2229 * Chip requires no back-back sendctrl writes, so write
2230 * scratch register after writing sendctrl
2232 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op)
2234 struct qib_devdata *dd = ppd->dd;
2235 u64 tmp_dd_sendctrl;
2236 unsigned long flags;
2238 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2240 /* First the ones that are "sticky", saved in shadow */
2241 if (op & QIB_SENDCTRL_CLEAR)
2243 if (op & QIB_SENDCTRL_SEND_DIS)
2244 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable);
2245 else if (op & QIB_SENDCTRL_SEND_ENB)
2246 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable);
2247 if (op & QIB_SENDCTRL_AVAIL_DIS)
2248 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2249 else if (op & QIB_SENDCTRL_AVAIL_ENB)
2250 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd);
2252 if (op & QIB_SENDCTRL_DISARM_ALL) {
2255 tmp_dd_sendctrl = dd->sendctrl;
2257 * disarm any that are not yet launched, disabling sends
2258 * and updates until done.
2260 last = dd->piobcnt2k + dd->piobcnt4k;
2262 ~(SYM_MASK(SendCtrl, PIOEnable) |
2263 SYM_MASK(SendCtrl, PIOBufAvailUpd));
2264 for (i = 0; i < last; i++) {
2265 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl |
2266 SYM_MASK(SendCtrl, Disarm) | i);
2267 qib_write_kreg(dd, kr_scratch, 0);
2271 tmp_dd_sendctrl = dd->sendctrl;
2273 if (op & QIB_SENDCTRL_FLUSH)
2274 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2275 if (op & QIB_SENDCTRL_DISARM)
2276 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2277 ((op & QIB_6120_SendCtrl_DisarmPIOBuf_RMASK) <<
2278 SYM_LSB(SendCtrl, DisarmPIOBuf));
2279 if (op & QIB_SENDCTRL_AVAIL_BLIP)
2280 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2282 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2283 qib_write_kreg(dd, kr_scratch, 0);
2285 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2286 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2287 qib_write_kreg(dd, kr_scratch, 0);
2290 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2292 if (op & QIB_SENDCTRL_FLUSH) {
2295 * ensure writes have hit chip, then do a few
2296 * more reads, to allow DMA of pioavail registers
2297 * to occur, so in-memory copy is in sync with
2298 * the chip. Not always safe to sleep.
2300 v = qib_read_kreg32(dd, kr_scratch);
2301 qib_write_kreg(dd, kr_scratch, v);
2302 v = qib_read_kreg32(dd, kr_scratch);
2303 qib_write_kreg(dd, kr_scratch, v);
2304 qib_read_kreg32(dd, kr_scratch);
2309 * qib_portcntr_6120 - read a per-port counter
2310 * @dd: the qlogic_ib device
2311 * @creg: the counter to snapshot
2313 static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg)
2316 struct qib_devdata *dd = ppd->dd;
2318 /* 0xffff for unimplemented or synthesized counters */
2319 static const u16 xlator[] = {
2320 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2321 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2322 [QIBPORTCNTR_PSXMITDATA] = 0xffff,
2323 [QIBPORTCNTR_PSXMITPKTS] = 0xffff,
2324 [QIBPORTCNTR_PSXMITWAIT] = 0xffff,
2325 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2326 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2327 [QIBPORTCNTR_PSRCVDATA] = 0xffff,
2328 [QIBPORTCNTR_PSRCVPKTS] = 0xffff,
2329 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2330 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2331 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2332 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2333 [QIBPORTCNTR_RXLOCALPHYERR] = 0xffff,
2334 [QIBPORTCNTR_RXVLERR] = 0xffff,
2335 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2336 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2337 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2338 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2339 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2340 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2341 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2342 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2343 [QIBPORTCNTR_EXCESSBUFOVFL] = 0xffff,
2344 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2345 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2346 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2347 [QIBPORTCNTR_LLI] = 0xffff,
2348 [QIBPORTCNTR_PSINTERVAL] = 0xffff,
2349 [QIBPORTCNTR_PSSTART] = 0xffff,
2350 [QIBPORTCNTR_PSSTAT] = 0xffff,
2351 [QIBPORTCNTR_VL15PKTDROP] = 0xffff,
2352 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2353 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2356 if (reg >= ARRAY_SIZE(xlator)) {
2357 qib_devinfo(ppd->dd->pcidev,
2358 "Unimplemented portcounter %u\n", reg);
2363 /* handle counters requests not implemented as chip counters */
2364 if (reg == QIBPORTCNTR_LLI)
2365 ret = dd->cspec->lli_errs;
2366 else if (reg == QIBPORTCNTR_EXCESSBUFOVFL)
2367 ret = dd->cspec->overrun_thresh_errs;
2368 else if (reg == QIBPORTCNTR_KHDROVFL) {
2371 /* sum over all kernel contexts */
2372 for (i = 0; i < dd->first_user_ctxt; i++)
2373 ret += read_6120_creg32(dd, cr_portovfl + i);
2374 } else if (reg == QIBPORTCNTR_PSSTAT)
2375 ret = dd->cspec->pma_sample_status;
2380 * only fast incrementing counters are 64bit; use 32 bit reads to
2381 * avoid two independent reads when on opteron
2383 if (creg == cr_wordsend || creg == cr_wordrcv ||
2384 creg == cr_pktsend || creg == cr_pktrcv)
2385 ret = read_6120_creg(dd, creg);
2387 ret = read_6120_creg32(dd, creg);
2388 if (creg == cr_ibsymbolerr) {
2389 if (dd->cspec->ibdeltainprog)
2390 ret -= ret - dd->cspec->ibsymsnap;
2391 ret -= dd->cspec->ibsymdelta;
2392 } else if (creg == cr_iblinkerrrecov) {
2393 if (dd->cspec->ibdeltainprog)
2394 ret -= ret - dd->cspec->iblnkerrsnap;
2395 ret -= dd->cspec->iblnkerrdelta;
2397 if (reg == QIBPORTCNTR_RXDROPPKT) /* add special cased count */
2398 ret += dd->cspec->rxfc_unsupvl_errs;
2405 * Device counter names (not port-specific), one line per stat,
2406 * single string. Used by utilities like ipathstats to print the stats
2407 * in a way which works for different versions of drivers, without changing
2408 * the utility. Names need to be 12 chars or less (w/o newline), for proper
2409 * display by utility.
2410 * Non-error counters are first.
2411 * Start of "error" conters is indicated by a leading "E " on the first
2412 * "error" counter, and doesn't count in label length.
2413 * The EgrOvfl list needs to be last so we truncate them at the configured
2414 * context count for the device.
2415 * cntr6120indices contains the corresponding register indices.
2417 static const char cntr6120names[] =
2428 static const size_t cntr6120indices[] = {
2441 * same as cntr6120names and cntr6120indices, but for port-specific counters.
2442 * portcntr6120indices is somewhat complicated by some registers needing
2443 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
2445 static const char portcntr6120names[] =
2477 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
2478 static const size_t portcntr6120indices[] = {
2479 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
2481 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
2482 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
2484 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
2485 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
2487 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
2488 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
2489 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
2490 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
2491 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
2492 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
2493 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
2494 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
2495 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
2497 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
2498 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
2499 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
2500 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
2501 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
2502 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
2510 /* do all the setup to make the counter reads efficient later */
2511 static void init_6120_cntrnames(struct qib_devdata *dd)
2516 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts;
2518 /* we always have at least one counter before the egrovfl */
2519 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
2521 s = strchr(s + 1, '\n');
2525 dd->cspec->ncntrs = i;
2527 /* full list; size is without terminating null */
2528 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1;
2530 dd->cspec->cntrnamelen = 1 + s - cntr6120names;
2531 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
2532 * sizeof(u64), GFP_KERNEL);
2533 if (!dd->cspec->cntrs)
2534 qib_dev_err(dd, "Failed allocation for counters\n");
2536 for (i = 0, s = (char *)portcntr6120names; s; i++)
2537 s = strchr(s + 1, '\n');
2538 dd->cspec->nportcntrs = i - 1;
2539 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1;
2540 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
2541 * sizeof(u64), GFP_KERNEL);
2542 if (!dd->cspec->portcntrs)
2543 qib_dev_err(dd, "Failed allocation for portcounters\n");
2546 static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
2552 ret = dd->cspec->cntrnamelen;
2554 ret = 0; /* final read after getting everything */
2556 *namep = (char *)cntr6120names;
2558 u64 *cntr = dd->cspec->cntrs;
2561 ret = dd->cspec->ncntrs * sizeof(u64);
2562 if (!cntr || pos >= ret) {
2563 /* everything read, or couldn't get memory */
2568 ret = 0; /* final read after getting everything */
2572 for (i = 0; i < dd->cspec->ncntrs; i++)
2573 *cntr++ = read_6120_creg32(dd, cntr6120indices[i]);
2579 static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
2580 char **namep, u64 **cntrp)
2585 ret = dd->cspec->portcntrnamelen;
2587 ret = 0; /* final read after getting everything */
2589 *namep = (char *)portcntr6120names;
2591 u64 *cntr = dd->cspec->portcntrs;
2592 struct qib_pportdata *ppd = &dd->pport[port];
2595 ret = dd->cspec->nportcntrs * sizeof(u64);
2596 if (!cntr || pos >= ret) {
2597 /* everything read, or couldn't get memory */
2602 for (i = 0; i < dd->cspec->nportcntrs; i++) {
2603 if (portcntr6120indices[i] & _PORT_VIRT_FLAG)
2604 *cntr++ = qib_portcntr_6120(ppd,
2605 portcntr6120indices[i] &
2608 *cntr++ = read_6120_creg32(dd,
2609 portcntr6120indices[i]);
2616 static void qib_chk_6120_errormask(struct qib_devdata *dd)
2620 unsigned long errormask;
2621 unsigned long hwerrs;
2623 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED))
2626 errormask = qib_read_kreg64(dd, kr_errmask);
2628 if (errormask == dd->cspec->errormask)
2632 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2633 ctrl = qib_read_kreg32(dd, kr_control);
2635 qib_write_kreg(dd, kr_errmask,
2636 dd->cspec->errormask);
2638 if ((hwerrs & dd->cspec->hwerrmask) ||
2639 (ctrl & QLOGIC_IB_C_FREEZEMODE)) {
2640 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2641 qib_write_kreg(dd, kr_errclear, 0ULL);
2642 /* force re-interrupt of pending events, just in case */
2643 qib_write_kreg(dd, kr_intclear, 0ULL);
2644 qib_devinfo(dd->pcidev,
2645 "errormask fixed(%u) %lx->%lx, ctrl %x hwerr %lx\n",
2646 fixed, errormask, (unsigned long)dd->cspec->errormask,
2652 * qib_get_faststats - get word counters from chip before they overflow
2653 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
2655 * This needs more work; in particular, decision on whether we really
2656 * need traffic_wds done the way it is
2657 * called from add_timer
2659 static void qib_get_6120_faststats(unsigned long opaque)
2661 struct qib_devdata *dd = (struct qib_devdata *) opaque;
2662 struct qib_pportdata *ppd = dd->pport;
2663 unsigned long flags;
2667 * don't access the chip while running diags, or memory diags can
2670 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
2671 /* but re-arm the timer, for diags case; won't hurt other */
2675 * We now try to maintain an activity timer, based on traffic
2676 * exceeding a threshold, so we need to check the word-counts
2677 * even if they are 64-bit.
2679 traffic_wds = qib_portcntr_6120(ppd, cr_wordsend) +
2680 qib_portcntr_6120(ppd, cr_wordrcv);
2681 spin_lock_irqsave(&dd->eep_st_lock, flags);
2682 traffic_wds -= dd->traffic_wds;
2683 dd->traffic_wds += traffic_wds;
2684 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
2685 atomic_add(5, &dd->active_time); /* S/B #define */
2686 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
2688 qib_chk_6120_errormask(dd);
2690 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
2693 /* no interrupt fallback for these chips */
2694 static int qib_6120_nointr_fallback(struct qib_devdata *dd)
2700 * reset the XGXS (between serdes and IBC). Slightly less intrusive
2701 * than resetting the IBC or external link state, and useful in some
2702 * cases to cause some retraining. To do this right, we reset IBC
2705 static void qib_6120_xgxs_reset(struct qib_pportdata *ppd)
2708 struct qib_devdata *dd = ppd->dd;
2710 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
2711 val = prev_val | QLOGIC_IB_XGXS_RESET;
2712 prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
2713 qib_write_kreg(dd, kr_control,
2714 dd->control & ~QLOGIC_IB_C_LINKENABLE);
2715 qib_write_kreg(dd, kr_xgxs_cfg, val);
2716 qib_read_kreg32(dd, kr_scratch);
2717 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
2718 qib_write_kreg(dd, kr_control, dd->control);
2721 static int qib_6120_get_ib_cfg(struct qib_pportdata *ppd, int which)
2726 case QIB_IB_CFG_LWID:
2727 ret = ppd->link_width_active;
2730 case QIB_IB_CFG_SPD:
2731 ret = ppd->link_speed_active;
2734 case QIB_IB_CFG_LWID_ENB:
2735 ret = ppd->link_width_enabled;
2738 case QIB_IB_CFG_SPD_ENB:
2739 ret = ppd->link_speed_enabled;
2742 case QIB_IB_CFG_OP_VLS:
2743 ret = ppd->vls_operational;
2746 case QIB_IB_CFG_VL_HIGH_CAP:
2750 case QIB_IB_CFG_VL_LOW_CAP:
2754 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2755 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2759 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2760 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2764 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2765 /* will only take effect when the link state changes */
2766 ret = (ppd->dd->cspec->ibcctrl &
2767 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2768 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2771 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2772 ret = 0; /* no heartbeat on this chip */
2775 case QIB_IB_CFG_PMA_TICKS:
2776 ret = 250; /* 1 usec. */
2787 * We assume range checking is already done, if needed.
2789 static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2791 struct qib_devdata *dd = ppd->dd;
2797 case QIB_IB_CFG_LWID_ENB:
2798 ppd->link_width_enabled = val;
2801 case QIB_IB_CFG_SPD_ENB:
2802 ppd->link_speed_enabled = val;
2805 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2806 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2809 dd->cspec->ibcctrl &=
2810 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2811 dd->cspec->ibcctrl |= (u64) val <<
2812 SYM_LSB(IBCCtrl, OverrunThreshold);
2813 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2814 qib_write_kreg(dd, kr_scratch, 0);
2818 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2819 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2822 dd->cspec->ibcctrl &=
2823 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2824 dd->cspec->ibcctrl |= (u64) val <<
2825 SYM_LSB(IBCCtrl, PhyerrThreshold);
2826 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2827 qib_write_kreg(dd, kr_scratch, 0);
2831 case QIB_IB_CFG_PKEYS: /* update pkeys */
2832 val64 = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2833 ((u64) ppd->pkeys[2] << 32) |
2834 ((u64) ppd->pkeys[3] << 48);
2835 qib_write_kreg(dd, kr_partitionkey, val64);
2838 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2839 /* will only take effect when the link state changes */
2840 if (val == IB_LINKINITCMD_POLL)
2841 dd->cspec->ibcctrl &=
2842 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2844 dd->cspec->ibcctrl |=
2845 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2846 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2847 qib_write_kreg(dd, kr_scratch, 0);
2850 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2852 * Update our housekeeping variables, and set IBC max
2853 * size, same as init code; max IBC is max we allow in
2854 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2855 * Set even if it's unchanged, print debug message only
2858 val = (ppd->ibmaxlen >> 2) + 1;
2859 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2860 dd->cspec->ibcctrl |= (u64)val <<
2861 SYM_LSB(IBCCtrl, MaxPktLen);
2862 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2863 qib_write_kreg(dd, kr_scratch, 0);
2866 case QIB_IB_CFG_LSTATE: /* set the IB link state */
2867 switch (val & 0xffff0000) {
2868 case IB_LINKCMD_DOWN:
2869 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2870 if (!dd->cspec->ibdeltainprog) {
2871 dd->cspec->ibdeltainprog = 1;
2872 dd->cspec->ibsymsnap =
2873 read_6120_creg32(dd, cr_ibsymbolerr);
2874 dd->cspec->iblnkerrsnap =
2875 read_6120_creg32(dd, cr_iblinkerrrecov);
2879 case IB_LINKCMD_ARMED:
2880 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2883 case IB_LINKCMD_ACTIVE:
2884 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2889 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2892 switch (val & 0xffff) {
2893 case IB_LINKINITCMD_NOP:
2897 case IB_LINKINITCMD_POLL:
2898 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2901 case IB_LINKINITCMD_SLEEP:
2902 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2905 case IB_LINKINITCMD_DISABLE:
2906 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2911 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2915 qib_set_ib_6120_lstate(ppd, lcmd, licmd);
2918 case QIB_IB_CFG_HRTBT:
2929 static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what)
2932 if (!strncmp(what, "ibc", 3)) {
2933 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2934 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2935 ppd->dd->unit, ppd->port);
2936 } else if (!strncmp(what, "off", 3)) {
2937 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2938 qib_devinfo(ppd->dd->pcidev,
2939 "Disabling IB%u:%u IBC loopback (normal)\n",
2940 ppd->dd->unit, ppd->port);
2944 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl);
2945 qib_write_kreg(ppd->dd, kr_scratch, 0);
2950 static void pma_6120_timer(unsigned long data)
2952 struct qib_pportdata *ppd = (struct qib_pportdata *)data;
2953 struct qib_chip_specific *cs = ppd->dd->cspec;
2954 struct qib_ibport *ibp = &ppd->ibport_data;
2955 unsigned long flags;
2957 spin_lock_irqsave(&ibp->lock, flags);
2958 if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED) {
2959 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2960 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2961 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2962 mod_timer(&cs->pma_timer,
2963 jiffies + usecs_to_jiffies(ibp->pma_sample_interval));
2964 } else if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) {
2965 u64 ta, tb, tc, td, te;
2967 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2968 qib_snapshot_counters(ppd, &ta, &tb, &tc, &td, &te);
2970 cs->sword = ta - cs->sword;
2971 cs->rword = tb - cs->rword;
2972 cs->spkts = tc - cs->spkts;
2973 cs->rpkts = td - cs->rpkts;
2974 cs->xmit_wait = te - cs->xmit_wait;
2976 spin_unlock_irqrestore(&ibp->lock, flags);
2980 * Note that the caller has the ibp->lock held.
2982 static void qib_set_cntr_6120_sample(struct qib_pportdata *ppd, u32 intv,
2985 struct qib_chip_specific *cs = ppd->dd->cspec;
2987 if (start && intv) {
2988 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_STARTED;
2989 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(start));
2991 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2992 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2993 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2994 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(intv));
2996 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
3005 static u32 qib_6120_iblink_state(u64 ibcs)
3007 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
3010 case IB_6120_L_STATE_INIT:
3011 state = IB_PORT_INIT;
3013 case IB_6120_L_STATE_ARM:
3014 state = IB_PORT_ARMED;
3016 case IB_6120_L_STATE_ACTIVE:
3018 case IB_6120_L_STATE_ACT_DEFER:
3019 state = IB_PORT_ACTIVE;
3021 default: /* fall through */
3022 case IB_6120_L_STATE_DOWN:
3023 state = IB_PORT_DOWN;
3029 /* returns the IBTA port state, rather than the IBC link training state */
3030 static u8 qib_6120_phys_portstate(u64 ibcs)
3032 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
3033 return qib_6120_physportstate[state];
3036 static int qib_6120_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3038 unsigned long flags;
3040 spin_lock_irqsave(&ppd->lflags_lock, flags);
3041 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3042 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3045 if (ppd->dd->cspec->ibdeltainprog) {
3046 ppd->dd->cspec->ibdeltainprog = 0;
3047 ppd->dd->cspec->ibsymdelta +=
3048 read_6120_creg32(ppd->dd, cr_ibsymbolerr) -
3049 ppd->dd->cspec->ibsymsnap;
3050 ppd->dd->cspec->iblnkerrdelta +=
3051 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) -
3052 ppd->dd->cspec->iblnkerrsnap;
3056 ppd->dd->cspec->lli_counter = 0;
3057 if (!ppd->dd->cspec->ibdeltainprog) {
3058 ppd->dd->cspec->ibdeltainprog = 1;
3059 ppd->dd->cspec->ibsymsnap =
3060 read_6120_creg32(ppd->dd, cr_ibsymbolerr);
3061 ppd->dd->cspec->iblnkerrsnap =
3062 read_6120_creg32(ppd->dd, cr_iblinkerrrecov);
3067 qib_6120_setup_setextled(ppd, ibup);
3072 /* Does read/modify/write to appropriate registers to
3073 * set output and direction bits selected by mask.
3074 * these are in their canonical postions (e.g. lsb of
3075 * dir will end up in D48 of extctrl on existing chips).
3076 * returns contents of GP Inputs.
3078 static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3080 u64 read_val, new_out;
3081 unsigned long flags;
3084 /* some bits being written, lock access to GPIO */
3087 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3088 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3089 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3090 new_out = (dd->cspec->gpio_out & ~mask) | out;
3092 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3093 qib_write_kreg(dd, kr_gpio_out, new_out);
3094 dd->cspec->gpio_out = new_out;
3095 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3098 * It is unlikely that a read at this time would get valid
3099 * data on a pin whose direction line was set in the same
3100 * call to this function. We include the read here because
3101 * that allows us to potentially combine a change on one pin with
3102 * a read on another, and because the old code did something like
3105 read_val = qib_read_kreg64(dd, kr_extstatus);
3106 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3110 * Read fundamental info we need to use the chip. These are
3111 * the registers that describe chip capabilities, and are
3112 * saved in shadow registers.
3114 static void get_6120_chip_params(struct qib_devdata *dd)
3120 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3122 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3123 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3124 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3125 dd->palign = qib_read_kreg32(dd, kr_palign);
3126 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3127 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3129 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3131 val = qib_read_kreg64(dd, kr_sendpiosize);
3132 dd->piosize2k = val & ~0U;
3133 dd->piosize4k = val >> 32;
3135 mtu = ib_mtu_enum_to_int(qib_ibmtu);
3137 mtu = QIB_DEFAULT_MTU;
3138 dd->pport->ibmtu = (u32)mtu;
3140 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3141 dd->piobcnt2k = val & ~0U;
3142 dd->piobcnt4k = val >> 32;
3143 dd->last_pio = dd->piobcnt4k + dd->piobcnt2k - 1;
3144 /* these may be adjusted in init_chip_wc_pat() */
3145 dd->pio2kbase = (u32 __iomem *)
3146 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase);
3147 if (dd->piobcnt4k) {
3148 dd->pio4kbase = (u32 __iomem *)
3149 (((char __iomem *) dd->kregbase) +
3150 (dd->piobufbase >> 32));
3152 * 4K buffers take 2 pages; we use roundup just to be
3153 * paranoid; we calculate it once here, rather than on
3156 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3159 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3161 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3162 (sizeof(u64) * BITS_PER_BYTE / 2);
3166 * The chip base addresses in cspec and cpspec have to be set
3167 * after possible init_chip_wc_pat(), rather than in
3168 * get_6120_chip_params(), so split out as separate function
3170 static void set_6120_baseaddrs(struct qib_devdata *dd)
3173 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3174 dd->cspec->cregbase = (u64 __iomem *)
3175 ((char __iomem *) dd->kregbase + cregbase);
3177 dd->egrtidbase = (u64 __iomem *)
3178 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3182 * Write the final few registers that depend on some of the
3183 * init setup. Done late in init, just before bringing up
3186 static int qib_late_6120_initreg(struct qib_devdata *dd)
3191 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3192 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3193 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3194 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3195 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3196 if (val != dd->pioavailregs_phys) {
3198 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
3199 (unsigned long) dd->pioavailregs_phys,
3200 (unsigned long long) val);
3206 static int init_6120_variables(struct qib_devdata *dd)
3209 struct qib_pportdata *ppd;
3212 ppd = (struct qib_pportdata *)(dd + 1);
3216 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports);
3217 ppd->cpspec = NULL; /* not used in this chip */
3219 spin_lock_init(&dd->cspec->kernel_tid_lock);
3220 spin_lock_init(&dd->cspec->user_tid_lock);
3221 spin_lock_init(&dd->cspec->rcvmod_lock);
3222 spin_lock_init(&dd->cspec->gpio_lock);
3224 /* we haven't yet set QIB_PRESENT, so use read directly */
3225 dd->revision = readq(&dd->kregbase[kr_revision]);
3227 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
3229 "Revision register read failure, giving up initialization\n");
3233 dd->flags |= QIB_PRESENT; /* now register routines work */
3235 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3237 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3240 get_6120_chip_params(dd);
3241 pe_boardname(dd); /* fill in boardname */
3244 * GPIO bits for TWSI data and clock,
3245 * used for serial EEPROM.
3247 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
3248 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
3249 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV;
3251 if (qib_unordered_wc())
3252 dd->flags |= QIB_PIO_FLUSH_WC;
3255 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
3256 * 2 is Some Misc, 3 is reserved for future.
3258 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
3260 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
3261 if (qib_unordered_wc())
3262 dd->eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
3264 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
3266 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
3268 ret = qib_init_pportdata(ppd, dd, 0, 1);
3271 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
3272 ppd->link_speed_supported = QIB_IB_SDR;
3273 ppd->link_width_enabled = IB_WIDTH_4X;
3274 ppd->link_speed_enabled = ppd->link_speed_supported;
3275 /* these can't change for this chip, so set once */
3276 ppd->link_width_active = ppd->link_width_enabled;
3277 ppd->link_speed_active = ppd->link_speed_enabled;
3278 ppd->vls_supported = IB_VL_VL0;
3279 ppd->vls_operational = ppd->vls_supported;
3281 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
3282 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
3285 /* we always allocate at least 2048 bytes for eager buffers */
3286 ret = ib_mtu_enum_to_int(qib_ibmtu);
3287 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
3288 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
3289 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
3291 qib_6120_tidtemplate(dd);
3294 * We can request a receive interrupt for 1 or
3295 * more packets from current offset. For now, we set this
3296 * up for a single packet.
3298 dd->rhdrhead_intr_off = 1ULL << 32;
3300 /* setup the stats timer; the add_timer is done at end of init */
3301 init_timer(&dd->stats_timer);
3302 dd->stats_timer.function = qib_get_6120_faststats;
3303 dd->stats_timer.data = (unsigned long) dd;
3305 init_timer(&dd->cspec->pma_timer);
3306 dd->cspec->pma_timer.function = pma_6120_timer;
3307 dd->cspec->pma_timer.data = (unsigned long) ppd;
3309 dd->ureg_align = qib_read_kreg32(dd, kr_palign);
3311 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
3312 qib_6120_config_ctxts(dd);
3313 qib_set_ctxtcnt(dd);
3316 ret = init_chip_wc_pat(dd, 0);
3320 set_6120_baseaddrs(dd); /* set chip access pointers now */
3326 qib_num_cfg_vls = 1; /* if any 6120's, only one VL */
3328 ret = qib_create_ctxts(dd);
3329 init_6120_cntrnames(dd);
3331 /* use all of 4KB buffers for the kernel, otherwise 16 */
3332 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16;
3334 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs;
3335 dd->pbufsctxt = dd->lastctxt_piobuf /
3336 (dd->cfgctxts - dd->first_user_ctxt);
3345 * For this chip, we want to use the same buffer every time
3346 * when we are trying to bring the link up (they are always VL15
3347 * packets). At that link state the packet should always go out immediately
3348 * (or at least be discarded at the tx interface if the link is down).
3349 * If it doesn't, and the buffer isn't available, that means some other
3350 * sender has gotten ahead of us, and is preventing our packet from going
3351 * out. In that case, we flush all packets, and try again. If that still
3352 * fails, we fail the request, and hope things work the next time around.
3354 * We don't need very complicated heuristics on whether the packet had
3355 * time to go out or not, since even at SDR 1X, it goes out in very short
3356 * time periods, covered by the chip reads done here and as part of the
3359 static u32 __iomem *get_6120_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3362 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1;
3365 * always blip to get avail list updated, since it's almost
3366 * always needed, and is fairly cheap.
3368 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3369 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3370 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3374 sendctrl_6120_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
3375 QIB_SENDCTRL_AVAIL_BLIP);
3376 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */
3377 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3378 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3383 static u32 __iomem *qib_6120_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
3386 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
3387 struct qib_devdata *dd = ppd->dd;
3390 if (((pbc >> 32) & PBC_6120_VL15_SEND_CTRL) &&
3391 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
3392 buf = get_6120_link_buf(ppd, pbufnum);
3395 if ((plen + 1) > dd->piosize2kmax_dwords)
3396 first = dd->piobcnt2k;
3399 /* try 4k if all 2k busy, so same last for both sizes */
3400 last = dd->piobcnt2k + dd->piobcnt4k - 1;
3401 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
3406 static int init_sdma_6120_regs(struct qib_pportdata *ppd)
3411 static u16 qib_sdma_6120_gethead(struct qib_pportdata *ppd)
3416 static int qib_sdma_6120_busy(struct qib_pportdata *ppd)
3421 static void qib_sdma_update_6120_tail(struct qib_pportdata *ppd, u16 tail)
3425 static void qib_6120_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
3429 static void qib_sdma_set_6120_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
3434 * the pbc doesn't need a VL15 indicator, but we need it for link_buf.
3435 * The chip ignores the bit if set.
3437 static u32 qib_6120_setpbc_control(struct qib_pportdata *ppd, u32 plen,
3440 return vl == 15 ? PBC_6120_VL15_SEND_CTRL : 0;
3443 static void qib_6120_initvl15_bufs(struct qib_devdata *dd)
3447 static void qib_6120_init_ctxt(struct qib_ctxtdata *rcd)
3449 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt;
3450 rcd->rcvegr_tid_base = rcd->ctxt * rcd->rcvegrcnt;
3453 static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start,
3454 u32 len, u32 avail, struct qib_ctxtdata *rcd)
3458 static void writescratch(struct qib_devdata *dd, u32 val)
3460 (void) qib_write_kreg(dd, kr_scratch, val);
3463 static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum)
3468 #ifdef CONFIG_INFINIBAND_QIB_DCA
3469 static int qib_6120_notify_dca(struct qib_devdata *dd, unsigned long event)
3475 /* Dummy function, as 6120 boards never disable EEPROM Write */
3476 static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen)
3482 * qib_init_iba6120_funcs - set up the chip-specific function pointers
3483 * @pdev: pci_dev of the qlogic_ib device
3484 * @ent: pci_device_id matching this chip
3486 * This is global, and is called directly at init to set up the
3487 * chip-specific function pointers for later use.
3489 * It also allocates/partially-inits the qib_devdata struct for
3492 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev,
3493 const struct pci_device_id *ent)
3495 struct qib_devdata *dd;
3498 dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) +
3499 sizeof(struct qib_chip_specific));
3503 dd->f_bringup_serdes = qib_6120_bringup_serdes;
3504 dd->f_cleanup = qib_6120_setup_cleanup;
3505 dd->f_clear_tids = qib_6120_clear_tids;
3506 dd->f_free_irq = qib_6120_free_irq;
3507 dd->f_get_base_info = qib_6120_get_base_info;
3508 dd->f_get_msgheader = qib_6120_get_msgheader;
3509 dd->f_getsendbuf = qib_6120_getsendbuf;
3510 dd->f_gpio_mod = gpio_6120_mod;
3511 dd->f_eeprom_wen = qib_6120_eeprom_wen;
3512 dd->f_hdrqempty = qib_6120_hdrqempty;
3513 dd->f_ib_updown = qib_6120_ib_updown;
3514 dd->f_init_ctxt = qib_6120_init_ctxt;
3515 dd->f_initvl15_bufs = qib_6120_initvl15_bufs;
3516 dd->f_intr_fallback = qib_6120_nointr_fallback;
3517 dd->f_late_initreg = qib_late_6120_initreg;
3518 dd->f_setpbc_control = qib_6120_setpbc_control;
3519 dd->f_portcntr = qib_portcntr_6120;
3520 dd->f_put_tid = (dd->minrev >= 2) ?
3521 qib_6120_put_tid_2 :
3523 dd->f_quiet_serdes = qib_6120_quiet_serdes;
3524 dd->f_rcvctrl = rcvctrl_6120_mod;
3525 dd->f_read_cntrs = qib_read_6120cntrs;
3526 dd->f_read_portcntrs = qib_read_6120portcntrs;
3527 dd->f_reset = qib_6120_setup_reset;
3528 dd->f_init_sdma_regs = init_sdma_6120_regs;
3529 dd->f_sdma_busy = qib_sdma_6120_busy;
3530 dd->f_sdma_gethead = qib_sdma_6120_gethead;
3531 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl;
3532 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt;
3533 dd->f_sdma_update_tail = qib_sdma_update_6120_tail;
3534 dd->f_sendctrl = sendctrl_6120_mod;
3535 dd->f_set_armlaunch = qib_set_6120_armlaunch;
3536 dd->f_set_cntr_sample = qib_set_cntr_6120_sample;
3537 dd->f_iblink_state = qib_6120_iblink_state;
3538 dd->f_ibphys_portstate = qib_6120_phys_portstate;
3539 dd->f_get_ib_cfg = qib_6120_get_ib_cfg;
3540 dd->f_set_ib_cfg = qib_6120_set_ib_cfg;
3541 dd->f_set_ib_loopback = qib_6120_set_loopback;
3542 dd->f_set_intr_state = qib_6120_set_intr_state;
3543 dd->f_setextled = qib_6120_setup_setextled;
3544 dd->f_txchk_change = qib_6120_txchk_change;
3545 dd->f_update_usrhead = qib_update_6120_usrhead;
3546 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr;
3547 dd->f_xgxs_reset = qib_6120_xgxs_reset;
3548 dd->f_writescratch = writescratch;
3549 dd->f_tempsense_rd = qib_6120_tempsense_rd;
3550 #ifdef CONFIG_INFINIBAND_QIB_DCA
3551 dd->f_notify_dca = qib_6120_notify_dca;
3554 * Do remaining pcie setup and save pcie values in dd.
3555 * Any error printing is already done by the init code.
3556 * On return, we have the chip mapped and accessible,
3557 * but chip registers are not set up until start of
3558 * init_6120_variables.
3560 ret = qib_pcie_ddinit(dd, pdev, ent);
3564 /* initialize chip-specific variables */
3565 ret = init_6120_variables(dd);
3572 if (qib_pcie_params(dd, 8, NULL, NULL))
3574 "Failed to setup PCIe or interrupts; continuing anyway\n");
3575 dd->cspec->irq = pdev->irq; /* save IRQ */
3577 /* clear diagctrl register, in case diags were running and crashed */
3578 qib_write_kreg(dd, kr_hwdiagctrl, 0);
3580 if (qib_read_kreg64(dd, kr_hwerrstatus) &
3581 QLOGIC_IB_HWE_SERDESPLLFAILED)
3582 qib_write_kreg(dd, kr_hwerrclear,
3583 QLOGIC_IB_HWE_SERDESPLLFAILED);
3585 /* setup interrupt handler (interrupt type handled above) */
3586 qib_setup_6120_interrupt(dd);
3587 /* Note that qpn_mask is set by qib_6120_config_ctxts() first */
3588 qib_6120_init_hwerrors(dd);
3593 qib_pcie_ddcleanup(dd);
3595 qib_free_devdata(dd);