drivers/platform/x86/intel_pmc_core.c

   1 /*
   2  * Intel Core SoC Power Management Controller Driver
   3  *
   4  * Copyright (c) 2016, Intel Corporation.
   5  * All Rights Reserved.
   6  *
   7  * Authors: Rajneesh Bhardwaj <[email protected]>
   8  *          Vishwanath Somayaji <[email protected]>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  */
  20
  21 #include <linux/debugfs.h>
  22 #include <linux/delay.h>
  23 #include <linux/device.h>
  24 #include <linux/init.h>
  25 #include <linux/io.h>
  26 #include <linux/pci.h>
  27 #include <linux/uaccess.h>
  28
  29 #include <asm/cpu_device_id.h>
  30 #include <asm/intel-family.h>
  31 #include <asm/pmc_core.h>
  32
  33 #include "intel_pmc_core.h"
  34
  35 static struct pmc_dev pmc;
  36
  37 static const struct pmc_bit_map spt_pll_map[] = {
  38         {"MIPI PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE0},
  39         {"GEN2 USB2PCIE2 PLL",          SPT_PMC_BIT_MPHY_CMN_LANE1},
  40         {"DMIPCIE3 PLL",                SPT_PMC_BIT_MPHY_CMN_LANE2},
  41         {"SATA PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE3},
  42         {},
  43 };
  44
  45 static const struct pmc_bit_map spt_mphy_map[] = {
  46         {"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
  47         {"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
  48         {"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
  49         {"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
  50         {"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
  51         {"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
  52         {"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
  53         {"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
  54         {"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
  55         {"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
  56         {"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
  57         {"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
  58         {"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
  59         {"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
  60         {"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
  61         {"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
  62         {},
  63 };
  64
  65 static const struct pmc_bit_map spt_pfear_map[] = {
  66         {"PMC",                         SPT_PMC_BIT_PMC},
  67         {"OPI-DMI",                     SPT_PMC_BIT_OPI},
  68         {"SPI / eSPI",                  SPT_PMC_BIT_SPI},
  69         {"XHCI",                        SPT_PMC_BIT_XHCI},
  70         {"SPA",                         SPT_PMC_BIT_SPA},
  71         {"SPB",                         SPT_PMC_BIT_SPB},
  72         {"SPC",                         SPT_PMC_BIT_SPC},
  73         {"GBE",                         SPT_PMC_BIT_GBE},
  74         {"SATA",                        SPT_PMC_BIT_SATA},
  75         {"HDA-PGD0",                    SPT_PMC_BIT_HDA_PGD0},
  76         {"HDA-PGD1",                    SPT_PMC_BIT_HDA_PGD1},
  77         {"HDA-PGD2",                    SPT_PMC_BIT_HDA_PGD2},
  78         {"HDA-PGD3",                    SPT_PMC_BIT_HDA_PGD3},
  79         {"RSVD",                        SPT_PMC_BIT_RSVD_0B},
  80         {"LPSS",                        SPT_PMC_BIT_LPSS},
  81         {"LPC",                         SPT_PMC_BIT_LPC},
  82         {"SMB",                         SPT_PMC_BIT_SMB},
  83         {"ISH",                         SPT_PMC_BIT_ISH},
  84         {"P2SB",                        SPT_PMC_BIT_P2SB},
  85         {"DFX",                         SPT_PMC_BIT_DFX},
  86         {"SCC",                         SPT_PMC_BIT_SCC},
  87         {"RSVD",                        SPT_PMC_BIT_RSVD_0C},
  88         {"FUSE",                        SPT_PMC_BIT_FUSE},
  89         {"CAMERA",                      SPT_PMC_BIT_CAMREA},
  90         {"RSVD",                        SPT_PMC_BIT_RSVD_0D},
  91         {"USB3-OTG",                    SPT_PMC_BIT_USB3_OTG},
  92         {"EXI",                         SPT_PMC_BIT_EXI},
  93         {"CSE",                         SPT_PMC_BIT_CSE},
  94         {"CSME_KVM",                    SPT_PMC_BIT_CSME_KVM},
  95         {"CSME_PMT",                    SPT_PMC_BIT_CSME_PMT},
  96         {"CSME_CLINK",                  SPT_PMC_BIT_CSME_CLINK},
  97         {"CSME_PTIO",                   SPT_PMC_BIT_CSME_PTIO},
  98         {"CSME_USBR",                   SPT_PMC_BIT_CSME_USBR},
  99         {"CSME_SUSRAM",                 SPT_PMC_BIT_CSME_SUSRAM},
 100         {"CSME_SMT",                    SPT_PMC_BIT_CSME_SMT},
 101         {"RSVD",                        SPT_PMC_BIT_RSVD_1A},
 102         {"CSME_SMS2",                   SPT_PMC_BIT_CSME_SMS2},
 103         {"CSME_SMS1",                   SPT_PMC_BIT_CSME_SMS1},
 104         {"CSME_RTC",                    SPT_PMC_BIT_CSME_RTC},
 105         {"CSME_PSF",                    SPT_PMC_BIT_CSME_PSF},
 106         {},
 107 };
 108
 109 static const struct pmc_reg_map spt_reg_map = {
 110         .pfear_sts = spt_pfear_map,
 111         .mphy_sts = spt_mphy_map,
 112         .pll_sts = spt_pll_map,
 113         .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
 114         .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
 115         .regmap_length = SPT_PMC_MMIO_REG_LEN,
 116         .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
 117         .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
 118         .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
 119         .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
 120 };
 121
 122 static const struct pci_device_id pmc_pci_ids[] = {
 123         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID),
 124                                         (kernel_ulong_t)&spt_reg_map },
 125         { 0, },
 126 };
 127
 128 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 129 {
 130         return readb(pmcdev->regbase + offset);
 131 }
 132
 133 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
 134 {
 135         return readl(pmcdev->regbase + reg_offset);
 136 }
 137
 138 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
 139                                                         reg_offset, u32 val)
 140 {
 141         writel(val, pmcdev->regbase + reg_offset);
 142 }
 143
 144 static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
 145 {
 146         return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
 147 }
 148
 149 /**
 150  * intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
 151  * @data: Out param that contains current SLP_S0 count.
 152  *
 153  * This API currently supports Intel Skylake SoC and Sunrise
 154  * Point Platform Controller Hub. Future platform support
 155  * should be added for platforms that support low power modes
 156  * beyond Package C10 state.
 157  *
 158  * SLP_S0_RESIDENCY counter counts in 100 us granularity per
 159  * step hence function populates the multiplied value in out
 160  * parameter @data.
 161  *
 162  * Return: an error code or 0 on success.
 163  */
 164 int intel_pmc_slp_s0_counter_read(u32 *data)
 165 {
 166         struct pmc_dev *pmcdev = &pmc;
 167         const struct pmc_reg_map *map = pmcdev->map;
 168         u32 value;
 169
 170         if (!pmcdev->has_slp_s0_res)
 171                 return -EACCES;
 172
 173         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 174         *data = pmc_core_adjust_slp_s0_step(value);
 175
 176         return 0;
 177 }
 178 EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
 179
 180 static int pmc_core_dev_state_get(void *data, u64 *val)
 181 {
 182         struct pmc_dev *pmcdev = data;
 183         const struct pmc_reg_map *map = pmcdev->map;
 184         u32 value;
 185
 186         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 187         *val = pmc_core_adjust_slp_s0_step(value);
 188
 189         return 0;
 190 }
 191
 192 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 193
 194 static int pmc_core_check_read_lock_bit(void)
 195 {
 196         struct pmc_dev *pmcdev = &pmc;
 197         u32 value;
 198
 199         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
 200         return value & BIT(pmcdev->map->pm_read_disable_bit);
 201 }
 202
 203 #if IS_ENABLED(CONFIG_DEBUG_FS)
 204 static void pmc_core_display_map(struct seq_file *s, int index,
 205                                  u8 pf_reg, const struct pmc_bit_map *pf_map)
 206 {
 207         seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
 208                    index, pf_map[index].name,
 209                    pf_map[index].bit_mask & pf_reg ? "Off" : "On");
 210 }
 211
 212 static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
 213 {
 214         struct pmc_dev *pmcdev = s->private;
 215         const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
 216         u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 217         int index, iter;
 218
 219         iter = pmcdev->map->ppfear0_offset;
 220
 221         for (index = 0; index < pmcdev->map->ppfear_buckets &&
 222              index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 223                 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 224
 225         for (index = 0; map[index].name; index++)
 226                 pmc_core_display_map(s, index, pf_regs[index / 8], map);
 227
 228         return 0;
 229 }
 230
 231 static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
 232 {
 233         return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
 234 }
 235
 236 static const struct file_operations pmc_core_ppfear_ops = {
 237         .open           = pmc_core_ppfear_sts_open,
 238         .read           = seq_read,
 239         .llseek         = seq_lseek,
 240         .release        = single_release,
 241 };
 242
 243 /* This function should return link status, 0 means ready */
 244 static int pmc_core_mtpmc_link_status(void)
 245 {
 246         struct pmc_dev *pmcdev = &pmc;
 247         u32 value;
 248
 249         value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
 250         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 251 }
 252
 253 static int pmc_core_send_msg(u32 *addr_xram)
 254 {
 255         struct pmc_dev *pmcdev = &pmc;
 256         u32 dest;
 257         int timeout;
 258
 259         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 260                 if (pmc_core_mtpmc_link_status() == 0)
 261                         break;
 262                 msleep(5);
 263         }
 264
 265         if (timeout <= 0 && pmc_core_mtpmc_link_status())
 266                 return -EBUSY;
 267
 268         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 269         pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
 270         return 0;
 271 }
 272
 273 static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
 274 {
 275         struct pmc_dev *pmcdev = s->private;
 276         const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
 277         u32 mphy_core_reg_low, mphy_core_reg_high;
 278         u32 val_low, val_high;
 279         int index, err = 0;
 280
 281         if (pmcdev->pmc_xram_read_bit) {
 282                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 283                 return 0;
 284         }
 285
 286         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 287         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 288
 289         mutex_lock(&pmcdev->lock);
 290
 291         if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
 292                 err = -EBUSY;
 293                 goto out_unlock;
 294         }
 295
 296         msleep(10);
 297         val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 298
 299         if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
 300                 err = -EBUSY;
 301                 goto out_unlock;
 302         }
 303
 304         msleep(10);
 305         val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 306
 307         for (index = 0; map[index].name && index < 8; index++) {
 308                 seq_printf(s, "%-32s\tState: %s\n",
 309                            map[index].name,
 310                            map[index].bit_mask & val_low ? "Not power gated" :
 311                            "Power gated");
 312         }
 313
 314         for (index = 8; map[index].name; index++) {
 315                 seq_printf(s, "%-32s\tState: %s\n",
 316                            map[index].name,
 317                            map[index].bit_mask & val_high ? "Not power gated" :
 318                            "Power gated");
 319         }
 320
 321 out_unlock:
 322         mutex_unlock(&pmcdev->lock);
 323         return err;
 324 }
 325
 326 static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
 327 {
 328         return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
 329 }
 330
 331 static const struct file_operations pmc_core_mphy_pg_ops = {
 332         .open           = pmc_core_mphy_pg_sts_open,
 333         .read           = seq_read,
 334         .llseek         = seq_lseek,
 335         .release        = single_release,
 336 };
 337
 338 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 339 {
 340         struct pmc_dev *pmcdev = s->private;
 341         const struct pmc_bit_map *map = pmcdev->map->pll_sts;
 342         u32 mphy_common_reg, val;
 343         int index, err = 0;
 344
 345         if (pmcdev->pmc_xram_read_bit) {
 346                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 347                 return 0;
 348         }
 349
 350         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
 351         mutex_lock(&pmcdev->lock);
 352
 353         if (pmc_core_send_msg(&mphy_common_reg) != 0) {
 354                 err = -EBUSY;
 355                 goto out_unlock;
 356         }
 357
 358         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
 359         msleep(10);
 360         val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 361
 362         for (index = 0; map[index].name ; index++) {
 363                 seq_printf(s, "%-32s\tState: %s\n",
 364                            map[index].name,
 365                            map[index].bit_mask & val ? "Active" : "Idle");
 366         }
 367
 368 out_unlock:
 369         mutex_unlock(&pmcdev->lock);
 370         return err;
 371 }
 372
 373 static int pmc_core_pll_open(struct inode *inode, struct file *file)
 374 {
 375         return single_open(file, pmc_core_pll_show, inode->i_private);
 376 }
 377
 378 static const struct file_operations pmc_core_pll_ops = {
 379         .open           = pmc_core_pll_open,
 380         .read           = seq_read,
 381         .llseek         = seq_lseek,
 382         .release        = single_release,
 383 };
 384
 385 static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
 386 *userbuf, size_t count, loff_t *ppos)
 387 {
 388         struct pmc_dev *pmcdev = &pmc;
 389         const struct pmc_reg_map *map = pmcdev->map;
 390         u32 val, buf_size, fd;
 391         int err = 0;
 392
 393         buf_size = count < 64 ? count : 64;
 394         mutex_lock(&pmcdev->lock);
 395
 396         if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
 397                 err = -EFAULT;
 398                 goto out_unlock;
 399         }
 400
 401         if (val > NUM_IP_IGN_ALLOWED) {
 402                 err = -EINVAL;
 403                 goto out_unlock;
 404         }
 405
 406         fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
 407         fd |= (1U << val);
 408         pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
 409
 410 out_unlock:
 411         mutex_unlock(&pmcdev->lock);
 412         return err == 0 ? count : err;
 413 }
 414
 415 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
 416 {
 417         return 0;
 418 }
 419
 420 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
 421 {
 422         return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
 423 }
 424
 425 static const struct file_operations pmc_core_ltr_ignore_ops = {
 426         .open           = pmc_core_ltr_ignore_open,
 427         .read           = seq_read,
 428         .write          = pmc_core_ltr_ignore_write,
 429         .llseek         = seq_lseek,
 430         .release        = single_release,
 431 };
 432
 433 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 434 {
 435         debugfs_remove_recursive(pmcdev->dbgfs_dir);
 436 }
 437
 438 static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 439 {
 440         struct dentry *dir, *file;
 441
 442         dir = debugfs_create_dir("pmc_core", NULL);
 443         if (!dir)
 444                 return -ENOMEM;
 445
 446         pmcdev->dbgfs_dir = dir;
 447         file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
 448                                    dir, pmcdev, &pmc_core_dev_state);
 449         if (!file)
 450                 goto err;
 451
 452         file = debugfs_create_file("pch_ip_power_gating_status",
 453                                    S_IFREG | S_IRUGO, dir, pmcdev,
 454                                    &pmc_core_ppfear_ops);
 455         if (!file)
 456                 goto err;
 457
 458         file = debugfs_create_file("mphy_core_lanes_power_gating_status",
 459                                    S_IFREG | S_IRUGO, dir, pmcdev,
 460                                    &pmc_core_mphy_pg_ops);
 461         if (!file)
 462                 goto err;
 463
 464         file = debugfs_create_file("pll_status",
 465                                    S_IFREG | S_IRUGO, dir, pmcdev,
 466                                    &pmc_core_pll_ops);
 467         if (!file)
 468                 goto err;
 469
 470         file = debugfs_create_file("ltr_ignore",
 471                                    S_IFREG | S_IRUGO, dir, pmcdev,
 472                                    &pmc_core_ltr_ignore_ops);
 473
 474         if (!file)
 475                 goto err;
 476
 477         return 0;
 478 err:
 479         pmc_core_dbgfs_unregister(pmcdev);
 480         return -ENODEV;
 481 }
 482 #else
 483 static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 484 {
 485         return 0;
 486 }
 487
 488 static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 489 {
 490 }
 491 #endif /* CONFIG_DEBUG_FS */
 492
 493 static const struct x86_cpu_id intel_pmc_core_ids[] = {
 494         { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
 495                 (kernel_ulong_t)NULL},
 496         { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
 497                 (kernel_ulong_t)NULL},
 498         { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
 499                 (kernel_ulong_t)NULL},
 500         { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
 501                 (kernel_ulong_t)NULL},
 502         {}
 503 };
 504
 505 static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
 506 {
 507         struct device *ptr_dev = &dev->dev;
 508         struct pmc_dev *pmcdev = &pmc;
 509         const struct x86_cpu_id *cpu_id;
 510         const struct pmc_reg_map *map = (struct pmc_reg_map *)id->driver_data;
 511         int err;
 512
 513         cpu_id = x86_match_cpu(intel_pmc_core_ids);
 514         if (!cpu_id) {
 515                 dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
 516                 return -EINVAL;
 517         }
 518
 519         err = pcim_enable_device(dev);
 520         if (err < 0) {
 521                 dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
 522                 return err;
 523         }
 524
 525         err = pci_read_config_dword(dev,
 526                                     SPT_PMC_BASE_ADDR_OFFSET,
 527                                     &pmcdev->base_addr);
 528         if (err < 0) {
 529                 dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
 530                 return err;
 531         }
 532         pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
 533         dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
 534
 535         pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
 536                                               pmcdev->base_addr,
 537                                               SPT_PMC_MMIO_REG_LEN);
 538         if (!pmcdev->regbase) {
 539                 dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
 540                 return -ENOMEM;
 541         }
 542
 543         mutex_init(&pmcdev->lock);
 544         pmcdev->map = map;
 545         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
 546
 547         err = pmc_core_dbgfs_register(pmcdev);
 548         if (err < 0)
 549                 dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
 550
 551         pmc.has_slp_s0_res = true;
 552         return 0;
 553 }
 554
 555 static struct pci_driver intel_pmc_core_driver = {
 556         .name = "intel_pmc_core",
 557         .id_table = pmc_pci_ids,
 558         .probe = pmc_core_probe,
 559 };
 560
 561 builtin_pci_driver(intel_pmc_core_driver);