drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_psp.h"
  29 #include "amdgpu_ucode.h"
  30 #include "soc15_common.h"
  31 #include "psp_v10_0.h"
  32
  33 #include "mp/mp_10_0_offset.h"
  34 #include "gc/gc_9_1_offset.h"
  35 #include "sdma0/sdma0_4_1_offset.h"
  36
  37 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
  38 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
  39 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
  40
  41 static int
  42 psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
  43 {
  44         switch(ucode->ucode_id) {
  45         case AMDGPU_UCODE_ID_SDMA0:
  46                 *type = GFX_FW_TYPE_SDMA0;
  47                 break;
  48         case AMDGPU_UCODE_ID_SDMA1:
  49                 *type = GFX_FW_TYPE_SDMA1;
  50                 break;
  51         case AMDGPU_UCODE_ID_CP_CE:
  52                 *type = GFX_FW_TYPE_CP_CE;
  53                 break;
  54         case AMDGPU_UCODE_ID_CP_PFP:
  55                 *type = GFX_FW_TYPE_CP_PFP;
  56                 break;
  57         case AMDGPU_UCODE_ID_CP_ME:
  58                 *type = GFX_FW_TYPE_CP_ME;
  59                 break;
  60         case AMDGPU_UCODE_ID_CP_MEC1:
  61                 *type = GFX_FW_TYPE_CP_MEC;
  62                 break;
  63         case AMDGPU_UCODE_ID_CP_MEC1_JT:
  64                 *type = GFX_FW_TYPE_CP_MEC_ME1;
  65                 break;
  66         case AMDGPU_UCODE_ID_CP_MEC2:
  67                 *type = GFX_FW_TYPE_CP_MEC;
  68                 break;
  69         case AMDGPU_UCODE_ID_CP_MEC2_JT:
  70                 *type = GFX_FW_TYPE_CP_MEC_ME2;
  71                 break;
  72         case AMDGPU_UCODE_ID_RLC_G:
  73                 *type = GFX_FW_TYPE_RLC_G;
  74                 break;
  75         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
  76                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
  77                 break;
  78         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
  79                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
  80                 break;
  81         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
  82                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
  83                 break;
  84         case AMDGPU_UCODE_ID_SMC:
  85                 *type = GFX_FW_TYPE_SMU;
  86                 break;
  87         case AMDGPU_UCODE_ID_UVD:
  88                 *type = GFX_FW_TYPE_UVD;
  89                 break;
  90         case AMDGPU_UCODE_ID_VCE:
  91                 *type = GFX_FW_TYPE_VCE;
  92                 break;
  93         case AMDGPU_UCODE_ID_VCN:
  94                 *type = GFX_FW_TYPE_VCN;
  95                 break;
  96         case AMDGPU_UCODE_ID_DMCU_ERAM:
  97                 *type = GFX_FW_TYPE_DMCU_ERAM;
  98                 break;
  99         case AMDGPU_UCODE_ID_DMCU_INTV:
 100                 *type = GFX_FW_TYPE_DMCU_ISR;
 101                 break;
 102         case AMDGPU_UCODE_ID_MAXIMUM:
 103         default:
 104                 return -EINVAL;
 105         }
 106
 107         return 0;
 108 }
 109
 110 static int psp_v10_0_init_microcode(struct psp_context *psp)
 111 {
 112         struct amdgpu_device *adev = psp->adev;
 113         const char *chip_name;
 114         char fw_name[30];
 115         int err = 0;
 116         const struct psp_firmware_header_v1_0 *hdr;
 117
 118         DRM_DEBUG("\n");
 119
 120         switch (adev->asic_type) {
 121         case CHIP_RAVEN:
 122                 if (adev->rev_id >= 0x8)
 123                         chip_name = "raven2";
 124                 else if (adev->pdev->device == 0x15d8)
 125                         chip_name = "picasso";
 126                 else
 127                         chip_name = "raven";
 128                 break;
 129         default: BUG();
 130         }
 131
 132         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 133         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 134         if (err)
 135                 goto out;
 136
 137         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 138         if (err)
 139                 goto out;
 140
 141         hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 142         adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
 143         adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
 144         adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 145         adev->psp.asd_start_addr = (uint8_t *)hdr +
 146                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
 147
 148         return 0;
 149 out:
 150         if (err) {
 151                 dev_err(adev->dev,
 152                         "psp v10.0: Failed to load firmware \"%s\"\n",
 153                         fw_name);
 154                 release_firmware(adev->psp.asd_fw);
 155                 adev->psp.asd_fw = NULL;
 156         }
 157
 158         return err;
 159 }
 160
 161 static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
 162                                   struct psp_gfx_cmd_resp *cmd)
 163 {
 164         int ret;
 165         uint64_t fw_mem_mc_addr = ucode->mc_addr;
 166
 167         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 168
 169         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 170         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 171         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 172         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 173
 174         ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 175         if (ret)
 176                 DRM_ERROR("Unknown firmware type\n");
 177
 178         return ret;
 179 }
 180
 181 static int psp_v10_0_ring_init(struct psp_context *psp,
 182                                enum psp_ring_type ring_type)
 183 {
 184         int ret = 0;
 185         struct psp_ring *ring;
 186         struct amdgpu_device *adev = psp->adev;
 187
 188         ring = &psp->km_ring;
 189
 190         ring->ring_type = ring_type;
 191
 192         /* allocate 4k Page of Local Frame Buffer memory for ring */
 193         ring->ring_size = 0x1000;
 194         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 195                                       AMDGPU_GEM_DOMAIN_VRAM,
 196                                       &adev->firmware.rbuf,
 197                                       &ring->ring_mem_mc_addr,
 198                                       (void **)&ring->ring_mem);
 199         if (ret) {
 200                 ring->ring_size = 0;
 201                 return ret;
 202         }
 203
 204         return 0;
 205 }
 206
 207 static int psp_v10_0_ring_create(struct psp_context *psp,
 208                                  enum psp_ring_type ring_type)
 209 {
 210         int ret = 0;
 211         unsigned int psp_ring_reg = 0;
 212         struct psp_ring *ring = &psp->km_ring;
 213         struct amdgpu_device *adev = psp->adev;
 214
 215         /* Write low address of the ring to C2PMSG_69 */
 216         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 217         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 218         /* Write high address of the ring to C2PMSG_70 */
 219         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 220         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 221         /* Write size of ring to C2PMSG_71 */
 222         psp_ring_reg = ring->ring_size;
 223         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 224         /* Write the ring initialization command to C2PMSG_64 */
 225         psp_ring_reg = ring_type;
 226         psp_ring_reg = psp_ring_reg << 16;
 227         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 228
 229         /* There might be handshake issue with hardware which needs delay */
 230         mdelay(20);
 231
 232         /* Wait for response flag (bit 31) in C2PMSG_64 */
 233         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 234                            0x80000000, 0x8000FFFF, false);
 235
 236         return ret;
 237 }
 238
 239 static int psp_v10_0_ring_stop(struct psp_context *psp,
 240                                enum psp_ring_type ring_type)
 241 {
 242         int ret = 0;
 243         unsigned int psp_ring_reg = 0;
 244         struct amdgpu_device *adev = psp->adev;
 245
 246         /* Write the ring destroy command to C2PMSG_64 */
 247         psp_ring_reg = 3 << 16;
 248         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 249
 250         /* There might be handshake issue with hardware which needs delay */
 251         mdelay(20);
 252
 253         /* Wait for response flag (bit 31) in C2PMSG_64 */
 254         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 255                            0x80000000, 0x80000000, false);
 256
 257         return ret;
 258 }
 259
 260 static int psp_v10_0_ring_destroy(struct psp_context *psp,
 261                                   enum psp_ring_type ring_type)
 262 {
 263         int ret = 0;
 264         struct psp_ring *ring = &psp->km_ring;
 265         struct amdgpu_device *adev = psp->adev;
 266
 267         ret = psp_v10_0_ring_stop(psp, ring_type);
 268         if (ret)
 269                 DRM_ERROR("Fail to stop psp ring\n");
 270
 271         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 272                               &ring->ring_mem_mc_addr,
 273                               (void **)&ring->ring_mem);
 274
 275         return ret;
 276 }
 277
 278 static int psp_v10_0_cmd_submit(struct psp_context *psp,
 279                                 struct amdgpu_firmware_info *ucode,
 280                                 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 281                                 int index)
 282 {
 283         unsigned int psp_write_ptr_reg = 0;
 284         struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 285         struct psp_ring *ring = &psp->km_ring;
 286         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 287         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 288                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 289         struct amdgpu_device *adev = psp->adev;
 290         uint32_t ring_size_dw = ring->ring_size / 4;
 291         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 292
 293         /* KM (GPCOM) prepare write pointer */
 294         psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 295
 296         /* Update KM RB frame pointer to new frame */
 297         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 298                 write_frame = ring_buffer_start;
 299         else
 300                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 301         /* Check invalid write_frame ptr address */
 302         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 303                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 304                           ring_buffer_start, ring_buffer_end, write_frame);
 305                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 306                 return -EINVAL;
 307         }
 308
 309         /* Initialize KM RB frame */
 310         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 311
 312         /* Update KM RB frame */
 313         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 314         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 315         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 316         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 317         write_frame->fence_value = index;
 318
 319         /* Update the write Pointer in DWORDs */
 320         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 321         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 322
 323         return 0;
 324 }
 325
 326 static int
 327 psp_v10_0_sram_map(struct amdgpu_device *adev,
 328                    unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 329                    unsigned int *sram_data_reg_offset,
 330                    enum AMDGPU_UCODE_ID ucode_id)
 331 {
 332         int ret = 0;
 333
 334         switch(ucode_id) {
 335 /* TODO: needs to confirm */
 336 #if 0
 337         case AMDGPU_UCODE_ID_SMC:
 338                 *sram_offset = 0;
 339                 *sram_addr_reg_offset = 0;
 340                 *sram_data_reg_offset = 0;
 341                 break;
 342 #endif
 343
 344         case AMDGPU_UCODE_ID_CP_CE:
 345                 *sram_offset = 0x0;
 346                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 347                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 348                 break;
 349
 350         case AMDGPU_UCODE_ID_CP_PFP:
 351                 *sram_offset = 0x0;
 352                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 353                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 354                 break;
 355
 356         case AMDGPU_UCODE_ID_CP_ME:
 357                 *sram_offset = 0x0;
 358                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 359                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 360                 break;
 361
 362         case AMDGPU_UCODE_ID_CP_MEC1:
 363                 *sram_offset = 0x10000;
 364                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 365                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 366                 break;
 367
 368         case AMDGPU_UCODE_ID_CP_MEC2:
 369                 *sram_offset = 0x10000;
 370                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 371                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 372                 break;
 373
 374         case AMDGPU_UCODE_ID_RLC_G:
 375                 *sram_offset = 0x2000;
 376                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 377                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 378                 break;
 379
 380         case AMDGPU_UCODE_ID_SDMA0:
 381                 *sram_offset = 0x0;
 382                 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 383                 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 384                 break;
 385
 386 /* TODO: needs to confirm */
 387 #if 0
 388         case AMDGPU_UCODE_ID_SDMA1:
 389                 *sram_offset = ;
 390                 *sram_addr_reg_offset = ;
 391                 break;
 392
 393         case AMDGPU_UCODE_ID_UVD:
 394                 *sram_offset = ;
 395                 *sram_addr_reg_offset = ;
 396                 break;
 397
 398         case AMDGPU_UCODE_ID_VCE:
 399                 *sram_offset = ;
 400                 *sram_addr_reg_offset = ;
 401                 break;
 402 #endif
 403
 404         case AMDGPU_UCODE_ID_MAXIMUM:
 405         default:
 406                 ret = -EINVAL;
 407                 break;
 408         }
 409
 410         return ret;
 411 }
 412
 413 static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
 414                                         struct amdgpu_firmware_info *ucode,
 415                                         enum AMDGPU_UCODE_ID ucode_type)
 416 {
 417         int err = 0;
 418         unsigned int fw_sram_reg_val = 0;
 419         unsigned int fw_sram_addr_reg_offset = 0;
 420         unsigned int fw_sram_data_reg_offset = 0;
 421         unsigned int ucode_size;
 422         uint32_t *ucode_mem = NULL;
 423         struct amdgpu_device *adev = psp->adev;
 424
 425         err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 426                                 &fw_sram_data_reg_offset, ucode_type);
 427         if (err)
 428                 return false;
 429
 430         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 431
 432         ucode_size = ucode->ucode_size;
 433         ucode_mem = (uint32_t *)ucode->kaddr;
 434         while (!ucode_size) {
 435                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 436
 437                 if (*ucode_mem != fw_sram_reg_val)
 438                         return false;
 439
 440                 ucode_mem++;
 441                 /* 4 bytes */
 442                 ucode_size -= 4;
 443         }
 444
 445         return true;
 446 }
 447
 448
 449 static int psp_v10_0_mode1_reset(struct psp_context *psp)
 450 {
 451         DRM_INFO("psp mode 1 reset not supported now! \n");
 452         return -EINVAL;
 453 }
 454
 455 static const struct psp_funcs psp_v10_0_funcs = {
 456         .init_microcode = psp_v10_0_init_microcode,
 457         .prep_cmd_buf = psp_v10_0_prep_cmd_buf,
 458         .ring_init = psp_v10_0_ring_init,
 459         .ring_create = psp_v10_0_ring_create,
 460         .ring_stop = psp_v10_0_ring_stop,
 461         .ring_destroy = psp_v10_0_ring_destroy,
 462         .cmd_submit = psp_v10_0_cmd_submit,
 463         .compare_sram_data = psp_v10_0_compare_sram_data,
 464         .mode1_reset = psp_v10_0_mode1_reset,
 465 };
 466
 467 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
 468 {
 469         psp->funcs = &psp_v10_0_funcs;
 470 }