drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef POLARIS10_HWMGR_H
  25 #define POLARIS10_HWMGR_H
  26
  27 #include "hwmgr.h"
  28 #include "smu74.h"
  29 #include "smu74_discrete.h"
  30 #include "ppatomctrl.h"
  31 #include "polaris10_ppsmc.h"
  32 #include "polaris10_powertune.h"
  33 #include "polaris10_smumgr.h"
  34
  35 #define POLARIS10_MAX_HARDWARE_POWERLEVELS      2
  36
  37 #define POLARIS10_VOLTAGE_CONTROL_NONE                   0x0
  38 #define POLARIS10_VOLTAGE_CONTROL_BY_GPIO                0x1
  39 #define POLARIS10_VOLTAGE_CONTROL_BY_SVID2               0x2
  40 #define POLARIS10_VOLTAGE_CONTROL_MERGED                 0x3
  41
  42 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
  43 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
  44 #define DPMTABLE_UPDATE_SCLK        0x00000004
  45 #define DPMTABLE_UPDATE_MCLK        0x00000008
  46
  47 struct polaris10_performance_level {
  48         uint32_t  memory_clock;
  49         uint32_t  engine_clock;
  50         uint16_t  pcie_gen;
  51         uint16_t  pcie_lane;
  52 };
  53
  54 struct polaris10_uvd_clocks {
  55         uint32_t  vclk;
  56         uint32_t  dclk;
  57 };
  58
  59 struct polaris10_vce_clocks {
  60         uint32_t  evclk;
  61         uint32_t  ecclk;
  62 };
  63
  64 struct polaris10_power_state {
  65         uint32_t                  magic;
  66         struct polaris10_uvd_clocks    uvd_clks;
  67         struct polaris10_vce_clocks    vce_clks;
  68         uint32_t                  sam_clk;
  69         uint16_t                  performance_level_count;
  70         bool                      dc_compatible;
  71         uint32_t                  sclk_threshold;
  72         struct polaris10_performance_level  performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS];
  73 };
  74
  75 struct polaris10_dpm_level {
  76         bool    enabled;
  77         uint32_t        value;
  78         uint32_t        param1;
  79 };
  80
  81 #define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5
  82 #define MAX_REGULAR_DPM_NUMBER 8
  83 #define POLARIS10_MINIMUM_ENGINE_CLOCK 2500
  84
  85 struct polaris10_single_dpm_table {
  86         uint32_t                count;
  87         struct polaris10_dpm_level      dpm_levels[MAX_REGULAR_DPM_NUMBER];
  88 };
  89
  90 struct polaris10_dpm_table {
  91         struct polaris10_single_dpm_table  sclk_table;
  92         struct polaris10_single_dpm_table  mclk_table;
  93         struct polaris10_single_dpm_table  pcie_speed_table;
  94         struct polaris10_single_dpm_table  vddc_table;
  95         struct polaris10_single_dpm_table  vddci_table;
  96         struct polaris10_single_dpm_table  mvdd_table;
  97 };
  98
  99 struct polaris10_clock_registers {
 100         uint32_t  vCG_SPLL_FUNC_CNTL;
 101         uint32_t  vCG_SPLL_FUNC_CNTL_2;
 102         uint32_t  vCG_SPLL_FUNC_CNTL_3;
 103         uint32_t  vCG_SPLL_FUNC_CNTL_4;
 104         uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
 105         uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
 106         uint32_t  vDLL_CNTL;
 107         uint32_t  vMCLK_PWRMGT_CNTL;
 108         uint32_t  vMPLL_AD_FUNC_CNTL;
 109         uint32_t  vMPLL_DQ_FUNC_CNTL;
 110         uint32_t  vMPLL_FUNC_CNTL;
 111         uint32_t  vMPLL_FUNC_CNTL_1;
 112         uint32_t  vMPLL_FUNC_CNTL_2;
 113         uint32_t  vMPLL_SS1;
 114         uint32_t  vMPLL_SS2;
 115 };
 116
 117 #define DISABLE_MC_LOADMICROCODE   1
 118 #define DISABLE_MC_CFGPROGRAMMING  2
 119
 120 struct polaris10_voltage_smio_registers {
 121         uint32_t vS0_VID_LOWER_SMIO_CNTL;
 122 };
 123
 124 #define POLARIS10_MAX_LEAKAGE_COUNT  8
 125
 126 struct polaris10_leakage_voltage {
 127         uint16_t  count;
 128         uint16_t  leakage_id[POLARIS10_MAX_LEAKAGE_COUNT];
 129         uint16_t  actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT];
 130 };
 131
 132 struct polaris10_vbios_boot_state {
 133         uint16_t    mvdd_bootup_value;
 134         uint16_t    vddc_bootup_value;
 135         uint16_t    vddci_bootup_value;
 136         uint32_t    sclk_bootup_value;
 137         uint32_t    mclk_bootup_value;
 138         uint16_t    pcie_gen_bootup_value;
 139         uint16_t    pcie_lane_bootup_value;
 140 };
 141
 142 /* Ultra Low Voltage parameter structure */
 143 struct polaris10_ulv_parm {
 144         bool                           ulv_supported;
 145         uint32_t                       cg_ulv_parameter;
 146         uint32_t                       ulv_volt_change_delay;
 147         struct polaris10_performance_level  ulv_power_level;
 148 };
 149
 150 struct polaris10_display_timing {
 151         uint32_t  min_clock_in_sr;
 152         uint32_t  num_existing_displays;
 153 };
 154
 155 struct polaris10_dpmlevel_enable_mask {
 156         uint32_t  uvd_dpm_enable_mask;
 157         uint32_t  vce_dpm_enable_mask;
 158         uint32_t  acp_dpm_enable_mask;
 159         uint32_t  samu_dpm_enable_mask;
 160         uint32_t  sclk_dpm_enable_mask;
 161         uint32_t  mclk_dpm_enable_mask;
 162         uint32_t  pcie_dpm_enable_mask;
 163 };
 164
 165 struct polaris10_pcie_perf_range {
 166         uint16_t  max;
 167         uint16_t  min;
 168 };
 169
 170 struct polaris10_hwmgr {
 171         struct polaris10_dpm_table                      dpm_table;
 172         struct polaris10_dpm_table                      golden_dpm_table;
 173         SMU74_Discrete_DpmTable                         smc_state_table;
 174         struct SMU74_Discrete_Ulv            ulv_setting;
 175
 176         struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
 177         uint32_t                                                voting_rights_clients0;
 178         uint32_t                                                voting_rights_clients1;
 179         uint32_t                                                voting_rights_clients2;
 180         uint32_t                                                voting_rights_clients3;
 181         uint32_t                                                voting_rights_clients4;
 182         uint32_t                                                voting_rights_clients5;
 183         uint32_t                                                voting_rights_clients6;
 184         uint32_t                                                voting_rights_clients7;
 185         uint32_t                                                static_screen_threshold_unit;
 186         uint32_t                                                static_screen_threshold;
 187         uint32_t                                                voltage_control;
 188         uint32_t                                                vddc_vddci_delta;
 189
 190         uint32_t                                                active_auto_throttle_sources;
 191
 192         struct polaris10_clock_registers            clock_registers;
 193         struct polaris10_voltage_smio_registers      voltage_smio_registers;
 194
 195         bool                           is_memory_gddr5;
 196         uint16_t                       acpi_vddc;
 197         bool                           pspp_notify_required;
 198         uint16_t                       force_pcie_gen;
 199         uint16_t                       acpi_pcie_gen;
 200         uint32_t                       pcie_gen_cap;
 201         uint32_t                       pcie_lane_cap;
 202         uint32_t                       pcie_spc_cap;
 203         struct polaris10_leakage_voltage          vddc_leakage;
 204         struct polaris10_leakage_voltage          Vddci_leakage;
 205
 206         uint32_t                             mvdd_control;
 207         uint32_t                             vddc_mask_low;
 208         uint32_t                             mvdd_mask_low;
 209         uint16_t                            max_vddc_in_pptable;
 210         uint16_t                            min_vddc_in_pptable;
 211         uint16_t                            max_vddci_in_pptable;
 212         uint16_t                            min_vddci_in_pptable;
 213         uint32_t                             mclk_strobe_mode_threshold;
 214         uint32_t                             mclk_stutter_mode_threshold;
 215         uint32_t                             mclk_edc_enable_threshold;
 216         uint32_t                             mclk_edcwr_enable_threshold;
 217         bool                                is_uvd_enabled;
 218         struct polaris10_vbios_boot_state        vbios_boot_state;
 219
 220         bool                           pcie_performance_request;
 221         bool                           battery_state;
 222         bool                           is_tlu_enabled;
 223
 224         /* ---- SMC SRAM Address of firmware header tables ---- */
 225         uint32_t                             sram_end;
 226         uint32_t                             dpm_table_start;
 227         uint32_t                             soft_regs_start;
 228         uint32_t                             mc_reg_table_start;
 229         uint32_t                             fan_table_start;
 230         uint32_t                             arb_table_start;
 231
 232         /* ---- Stuff originally coming from Evergreen ---- */
 233         uint32_t                             vddci_control;
 234         struct pp_atomctrl_voltage_table     vddc_voltage_table;
 235         struct pp_atomctrl_voltage_table     vddci_voltage_table;
 236         struct pp_atomctrl_voltage_table     mvdd_voltage_table;
 237
 238         uint32_t                             mgcg_cgtt_local2;
 239         uint32_t                             mgcg_cgtt_local3;
 240         uint32_t                             gpio_debug;
 241         uint32_t                             mc_micro_code_feature;
 242         uint32_t                             highest_mclk;
 243         uint16_t                             acpi_vddci;
 244         uint8_t                              mvdd_high_index;
 245         uint8_t                              mvdd_low_index;
 246         bool                                 dll_default_on;
 247         bool                                 performance_request_registered;
 248
 249         /* ---- Low Power Features ---- */
 250         struct polaris10_ulv_parm                 ulv;
 251
 252         /* ---- CAC Stuff ---- */
 253         uint32_t                       cac_table_start;
 254         bool                           cac_configuration_required;
 255         bool                           driver_calculate_cac_leakage;
 256         bool                           cac_enabled;
 257
 258         /* ---- DPM2 Parameters ---- */
 259         uint32_t                       power_containment_features;
 260         bool                           enable_dte_feature;
 261         bool                           enable_tdc_limit_feature;
 262         bool                           enable_pkg_pwr_tracking_feature;
 263         bool                           disable_uvd_power_tune_feature;
 264         const struct polaris10_pt_defaults       *power_tune_defaults;
 265         struct SMU74_Discrete_PmFuses  power_tune_table;
 266         uint32_t                       dte_tj_offset;
 267         uint32_t                       fast_watermark_threshold;
 268
 269         /* ---- Phase Shedding ---- */
 270         bool                           vddc_phase_shed_control;
 271
 272         /* ---- DI/DT ---- */
 273         struct polaris10_display_timing        display_timing;
 274         uint32_t                      bif_sclk_table[SMU74_MAX_LEVELS_LINK];
 275
 276         /* ---- Thermal Temperature Setting ---- */
 277         struct polaris10_dpmlevel_enable_mask     dpm_level_enable_mask;
 278         uint32_t                                  need_update_smu7_dpm_table;
 279         uint32_t                                  sclk_dpm_key_disabled;
 280         uint32_t                                  mclk_dpm_key_disabled;
 281         uint32_t                                  pcie_dpm_key_disabled;
 282         uint32_t                                  min_engine_clocks;
 283         struct polaris10_pcie_perf_range          pcie_gen_performance;
 284         struct polaris10_pcie_perf_range          pcie_lane_performance;
 285         struct polaris10_pcie_perf_range          pcie_gen_power_saving;
 286         struct polaris10_pcie_perf_range          pcie_lane_power_saving;
 287         bool                                      use_pcie_performance_levels;
 288         bool                                      use_pcie_power_saving_levels;
 289         uint32_t                                  activity_target[SMU74_MAX_LEVELS_GRAPHICS];
 290         uint32_t                                  mclk_activity_target;
 291         uint32_t                                  mclk_dpm0_activity_target;
 292         uint32_t                                  low_sclk_interrupt_threshold;
 293         uint32_t                                  last_mclk_dpm_enable_mask;
 294         bool                                      uvd_enabled;
 295
 296         /* ---- Power Gating States ---- */
 297         bool                           uvd_power_gated;
 298         bool                           vce_power_gated;
 299         bool                           samu_power_gated;
 300         bool                           need_long_memory_training;
 301
 302         /* Application power optimization parameters */
 303         bool                               update_up_hyst;
 304         bool                               update_down_hyst;
 305         uint32_t                           down_hyst;
 306         uint32_t                           up_hyst;
 307         uint32_t disable_dpm_mask;
 308         bool apply_optimized_settings;
 309         uint32_t                              avfs_vdroop_override_setting;
 310         bool                                  apply_avfs_cks_off_voltage;
 311         uint32_t                              frame_time_x2;
 312 };
 313
 314 /* To convert to Q8.8 format for firmware */
 315 #define POLARIS10_Q88_FORMAT_CONVERSION_UNIT             256
 316
 317 enum Polaris10_I2CLineID {
 318         Polaris10_I2CLineID_DDC1 = 0x90,
 319         Polaris10_I2CLineID_DDC2 = 0x91,
 320         Polaris10_I2CLineID_DDC3 = 0x92,
 321         Polaris10_I2CLineID_DDC4 = 0x93,
 322         Polaris10_I2CLineID_DDC5 = 0x94,
 323         Polaris10_I2CLineID_DDC6 = 0x95,
 324         Polaris10_I2CLineID_SCLSDA = 0x96,
 325         Polaris10_I2CLineID_DDCVGA = 0x97
 326 };
 327
 328 #define POLARIS10_I2C_DDC1DATA          0
 329 #define POLARIS10_I2C_DDC1CLK           1
 330 #define POLARIS10_I2C_DDC2DATA          2
 331 #define POLARIS10_I2C_DDC2CLK           3
 332 #define POLARIS10_I2C_DDC3DATA          4
 333 #define POLARIS10_I2C_DDC3CLK           5
 334 #define POLARIS10_I2C_SDA               40
 335 #define POLARIS10_I2C_SCL               41
 336 #define POLARIS10_I2C_DDC4DATA          65
 337 #define POLARIS10_I2C_DDC4CLK           66
 338 #define POLARIS10_I2C_DDC5DATA          0x48
 339 #define POLARIS10_I2C_DDC5CLK           0x49
 340 #define POLARIS10_I2C_DDC6DATA          0x4a
 341 #define POLARIS10_I2C_DDC6CLK           0x4b
 342 #define POLARIS10_I2C_DDCVGADATA        0x4c
 343 #define POLARIS10_I2C_DDCVGACLK         0x4d
 344
 345 #define POLARIS10_UNUSED_GPIO_PIN       0x7F
 346
 347 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
 348
 349 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 350 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 351 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
 352 int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 353 #endif
 354