drivers/gpu/drm/amd/amdgpu/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_ucode.h"
  29 #include "cikd.h"
  30 #include "amdgpu_dpm.h"
  31 #include "ci_dpm.h"
  32 #include "gfx_v7_0.h"
  33 #include "atom.h"
  34 #include <linux/seq_file.h>
  35
  36 #include "smu/smu_7_0_1_d.h"
  37 #include "smu/smu_7_0_1_sh_mask.h"
  38
  39 #include "dce/dce_8_0_d.h"
  40 #include "dce/dce_8_0_sh_mask.h"
  41
  42 #include "bif/bif_4_1_d.h"
  43 #include "bif/bif_4_1_sh_mask.h"
  44
  45 #include "gca/gfx_7_2_d.h"
  46 #include "gca/gfx_7_2_sh_mask.h"
  47
  48 #include "gmc/gmc_7_1_d.h"
  49 #include "gmc/gmc_7_1_sh_mask.h"
  50
  51 MODULE_FIRMWARE("radeon/bonaire_smc.bin");
  52 MODULE_FIRMWARE("radeon/hawaii_smc.bin");
  53
  54 #define MC_CG_ARB_FREQ_F0           0x0a
  55 #define MC_CG_ARB_FREQ_F1           0x0b
  56 #define MC_CG_ARB_FREQ_F2           0x0c
  57 #define MC_CG_ARB_FREQ_F3           0x0d
  58
  59 #define SMC_RAM_END 0x40000
  60
  61 #define VOLTAGE_SCALE               4
  62 #define VOLTAGE_VID_OFFSET_SCALE1    625
  63 #define VOLTAGE_VID_OFFSET_SCALE2    100
  64
  65 static const struct ci_pt_defaults defaults_hawaii_xt =
  66 {
  67         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  68         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  69         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  70 };
  71
  72 static const struct ci_pt_defaults defaults_hawaii_pro =
  73 {
  74         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  75         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  76         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  77 };
  78
  79 static const struct ci_pt_defaults defaults_bonaire_xt =
  80 {
  81         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  82         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  83         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  84 };
  85
  86 static const struct ci_pt_defaults defaults_bonaire_pro =
  87 {
  88         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  89         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  90         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  91 };
  92
  93 static const struct ci_pt_defaults defaults_saturn_xt =
  94 {
  95         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  96         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  97         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  98 };
  99
 100 static const struct ci_pt_defaults defaults_saturn_pro =
 101 {
 102         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
 103         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
 104         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
 105 };
 106
 107 static const struct ci_pt_config_reg didt_config_ci[] =
 108 {
 109         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 162         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 163         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 164         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 165         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 166         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 167         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 168         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 169         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 170         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 171         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 172         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 173         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 174         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 175         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 176         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 177         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 178         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 179         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 180         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 181         { 0xFFFFFFFF }
 182 };
 183
 184 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
 185 {
 186         return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
 187 }
 188
 189 #define MC_CG_ARB_FREQ_F0           0x0a
 190 #define MC_CG_ARB_FREQ_F1           0x0b
 191 #define MC_CG_ARB_FREQ_F2           0x0c
 192 #define MC_CG_ARB_FREQ_F3           0x0d
 193
 194 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
 195                                        u32 arb_freq_src, u32 arb_freq_dest)
 196 {
 197         u32 mc_arb_dram_timing;
 198         u32 mc_arb_dram_timing2;
 199         u32 burst_time;
 200         u32 mc_cg_config;
 201
 202         switch (arb_freq_src) {
 203         case MC_CG_ARB_FREQ_F0:
 204                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
 205                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
 206                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
 207                          MC_ARB_BURST_TIME__STATE0__SHIFT;
 208                 break;
 209         case MC_CG_ARB_FREQ_F1:
 210                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING_1);
 211                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
 212                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
 213                          MC_ARB_BURST_TIME__STATE1__SHIFT;
 214                 break;
 215         default:
 216                 return -EINVAL;
 217         }
 218
 219         switch (arb_freq_dest) {
 220         case MC_CG_ARB_FREQ_F0:
 221                 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 222                 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 223                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
 224                         ~MC_ARB_BURST_TIME__STATE0_MASK);
 225                 break;
 226         case MC_CG_ARB_FREQ_F1:
 227                 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 228                 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 229                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
 230                         ~MC_ARB_BURST_TIME__STATE1_MASK);
 231                 break;
 232         default:
 233                 return -EINVAL;
 234         }
 235
 236         mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
 237         WREG32(mmMC_CG_CONFIG, mc_cg_config);
 238         WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
 239                 ~MC_ARB_CG__CG_ARB_REQ_MASK);
 240
 241         return 0;
 242 }
 243
 244 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
 245 {
 246         u8 mc_para_index;
 247
 248         if (memory_clock < 10000)
 249                 mc_para_index = 0;
 250         else if (memory_clock >= 80000)
 251                 mc_para_index = 0x0f;
 252         else
 253                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
 254         return mc_para_index;
 255 }
 256
 257 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
 258 {
 259         u8 mc_para_index;
 260
 261         if (strobe_mode) {
 262                 if (memory_clock < 12500)
 263                         mc_para_index = 0x00;
 264                 else if (memory_clock > 47500)
 265                         mc_para_index = 0x0f;
 266                 else
 267                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
 268         } else {
 269                 if (memory_clock < 65000)
 270                         mc_para_index = 0x00;
 271                 else if (memory_clock > 135000)
 272                         mc_para_index = 0x0f;
 273                 else
 274                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
 275         }
 276         return mc_para_index;
 277 }
 278
 279 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
 280                                                      u32 max_voltage_steps,
 281                                                      struct atom_voltage_table *voltage_table)
 282 {
 283         unsigned int i, diff;
 284
 285         if (voltage_table->count <= max_voltage_steps)
 286                 return;
 287
 288         diff = voltage_table->count - max_voltage_steps;
 289
 290         for (i = 0; i < max_voltage_steps; i++)
 291                 voltage_table->entries[i] = voltage_table->entries[i + diff];
 292
 293         voltage_table->count = max_voltage_steps;
 294 }
 295
 296 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
 297                                          struct atom_voltage_table_entry *voltage_table,
 298                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 299 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
 300 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
 301                                        u32 target_tdp);
 302 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
 303 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
 304 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
 305
 306 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
 307                                                              PPSMC_Msg msg, u32 parameter);
 308 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
 309 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
 310
 311 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
 312 {
 313         struct ci_power_info *pi = adev->pm.dpm.priv;
 314
 315         return pi;
 316 }
 317
 318 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
 319 {
 320         struct ci_ps *ps = rps->ps_priv;
 321
 322         return ps;
 323 }
 324
 325 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
 326 {
 327         struct ci_power_info *pi = ci_get_pi(adev);
 328
 329         switch (adev->pdev->device) {
 330         case 0x6649:
 331         case 0x6650:
 332         case 0x6651:
 333         case 0x6658:
 334         case 0x665C:
 335         case 0x665D:
 336         default:
 337                 pi->powertune_defaults = &defaults_bonaire_xt;
 338                 break;
 339         case 0x6640:
 340         case 0x6641:
 341         case 0x6646:
 342         case 0x6647:
 343                 pi->powertune_defaults = &defaults_saturn_xt;
 344                 break;
 345         case 0x67B8:
 346         case 0x67B0:
 347                 pi->powertune_defaults = &defaults_hawaii_xt;
 348                 break;
 349         case 0x67BA:
 350         case 0x67B1:
 351                 pi->powertune_defaults = &defaults_hawaii_pro;
 352                 break;
 353         case 0x67A0:
 354         case 0x67A1:
 355         case 0x67A2:
 356         case 0x67A8:
 357         case 0x67A9:
 358         case 0x67AA:
 359         case 0x67B9:
 360         case 0x67BE:
 361                 pi->powertune_defaults = &defaults_bonaire_xt;
 362                 break;
 363         }
 364
 365         pi->dte_tj_offset = 0;
 366
 367         pi->caps_power_containment = true;
 368         pi->caps_cac = false;
 369         pi->caps_sq_ramping = false;
 370         pi->caps_db_ramping = false;
 371         pi->caps_td_ramping = false;
 372         pi->caps_tcp_ramping = false;
 373
 374         if (pi->caps_power_containment) {
 375                 pi->caps_cac = true;
 376                 if (adev->asic_type == CHIP_HAWAII)
 377                         pi->enable_bapm_feature = false;
 378                 else
 379                         pi->enable_bapm_feature = true;
 380                 pi->enable_tdc_limit_feature = true;
 381                 pi->enable_pkg_pwr_tracking_feature = true;
 382         }
 383 }
 384
 385 static u8 ci_convert_to_vid(u16 vddc)
 386 {
 387         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 388 }
 389
 390 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
 391 {
 392         struct ci_power_info *pi = ci_get_pi(adev);
 393         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 394         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 395         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 396         u32 i;
 397
 398         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 399                 return -EINVAL;
 400         if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 401                 return -EINVAL;
 402         if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
 403             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 404                 return -EINVAL;
 405
 406         for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 407                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 408                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 409                         hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 410                         hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 411                 } else {
 412                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 413                         hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 414                 }
 415         }
 416         return 0;
 417 }
 418
 419 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
 420 {
 421         struct ci_power_info *pi = ci_get_pi(adev);
 422         u8 *vid = pi->smc_powertune_table.VddCVid;
 423         u32 i;
 424
 425         if (pi->vddc_voltage_table.count > 8)
 426                 return -EINVAL;
 427
 428         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 429                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 430
 431         return 0;
 432 }
 433
 434 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
 435 {
 436         struct ci_power_info *pi = ci_get_pi(adev);
 437         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 438
 439         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 440         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 441         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 442         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 443
 444         return 0;
 445 }
 446
 447 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
 448 {
 449         struct ci_power_info *pi = ci_get_pi(adev);
 450         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 451         u16 tdc_limit;
 452
 453         tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 454         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 455         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 456                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 457         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 458
 459         return 0;
 460 }
 461
 462 static int ci_populate_dw8(struct amdgpu_device *adev)
 463 {
 464         struct ci_power_info *pi = ci_get_pi(adev);
 465         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 466         int ret;
 467
 468         ret = amdgpu_ci_read_smc_sram_dword(adev,
 469                                      SMU7_FIRMWARE_HEADER_LOCATION +
 470                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 471                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 472                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 473                                      pi->sram_end);
 474         if (ret)
 475                 return -EINVAL;
 476         else
 477                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 478
 479         return 0;
 480 }
 481
 482 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
 483 {
 484         struct ci_power_info *pi = ci_get_pi(adev);
 485
 486         if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
 487             (adev->pm.dpm.fan.fan_output_sensitivity == 0))
 488                 adev->pm.dpm.fan.fan_output_sensitivity =
 489                         adev->pm.dpm.fan.default_fan_output_sensitivity;
 490
 491         pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
 492                 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
 493
 494         return 0;
 495 }
 496
 497 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
 498 {
 499         struct ci_power_info *pi = ci_get_pi(adev);
 500         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 501         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 502         int i, min, max;
 503
 504         min = max = hi_vid[0];
 505         for (i = 0; i < 8; i++) {
 506                 if (0 != hi_vid[i]) {
 507                         if (min > hi_vid[i])
 508                                 min = hi_vid[i];
 509                         if (max < hi_vid[i])
 510                                 max = hi_vid[i];
 511                 }
 512
 513                 if (0 != lo_vid[i]) {
 514                         if (min > lo_vid[i])
 515                                 min = lo_vid[i];
 516                         if (max < lo_vid[i])
 517                                 max = lo_vid[i];
 518                 }
 519         }
 520
 521         if ((min == 0) || (max == 0))
 522                 return -EINVAL;
 523         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 524         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 525
 526         return 0;
 527 }
 528
 529 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
 530 {
 531         struct ci_power_info *pi = ci_get_pi(adev);
 532         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 533         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 534         struct amdgpu_cac_tdp_table *cac_tdp_table =
 535                 adev->pm.dpm.dyn_state.cac_tdp_table;
 536
 537         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 538         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 539
 540         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 541         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 542
 543         return 0;
 544 }
 545
 546 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
 547 {
 548         struct ci_power_info *pi = ci_get_pi(adev);
 549         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 550         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 551         struct amdgpu_cac_tdp_table *cac_tdp_table =
 552                 adev->pm.dpm.dyn_state.cac_tdp_table;
 553         struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
 554         int i, j, k;
 555         const u16 *def1;
 556         const u16 *def2;
 557
 558         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 559         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 560
 561         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 562         dpm_table->GpuTjMax =
 563                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 564         dpm_table->GpuTjHyst = 8;
 565
 566         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 567
 568         if (ppm) {
 569                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 570                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 571         } else {
 572                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 573                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 574         }
 575
 576         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 577         def1 = pt_defaults->bapmti_r;
 578         def2 = pt_defaults->bapmti_rc;
 579
 580         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 581                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 582                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 583                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 584                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 585                                 def1++;
 586                                 def2++;
 587                         }
 588                 }
 589         }
 590
 591         return 0;
 592 }
 593
 594 static int ci_populate_pm_base(struct amdgpu_device *adev)
 595 {
 596         struct ci_power_info *pi = ci_get_pi(adev);
 597         u32 pm_fuse_table_offset;
 598         int ret;
 599
 600         if (pi->caps_power_containment) {
 601                 ret = amdgpu_ci_read_smc_sram_dword(adev,
 602                                              SMU7_FIRMWARE_HEADER_LOCATION +
 603                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 604                                              &pm_fuse_table_offset, pi->sram_end);
 605                 if (ret)
 606                         return ret;
 607                 ret = ci_populate_bapm_vddc_vid_sidd(adev);
 608                 if (ret)
 609                         return ret;
 610                 ret = ci_populate_vddc_vid(adev);
 611                 if (ret)
 612                         return ret;
 613                 ret = ci_populate_svi_load_line(adev);
 614                 if (ret)
 615                         return ret;
 616                 ret = ci_populate_tdc_limit(adev);
 617                 if (ret)
 618                         return ret;
 619                 ret = ci_populate_dw8(adev);
 620                 if (ret)
 621                         return ret;
 622                 ret = ci_populate_fuzzy_fan(adev);
 623                 if (ret)
 624                         return ret;
 625                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
 626                 if (ret)
 627                         return ret;
 628                 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
 629                 if (ret)
 630                         return ret;
 631                 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
 632                                            (u8 *)&pi->smc_powertune_table,
 633                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 634                 if (ret)
 635                         return ret;
 636         }
 637
 638         return 0;
 639 }
 640
 641 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
 642 {
 643         struct ci_power_info *pi = ci_get_pi(adev);
 644         u32 data;
 645
 646         if (pi->caps_sq_ramping) {
 647                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 648                 if (enable)
 649                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 650                 else
 651                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 652                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 653         }
 654
 655         if (pi->caps_db_ramping) {
 656                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 657                 if (enable)
 658                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 659                 else
 660                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 661                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 662         }
 663
 664         if (pi->caps_td_ramping) {
 665                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 666                 if (enable)
 667                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 668                 else
 669                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 670                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 671         }
 672
 673         if (pi->caps_tcp_ramping) {
 674                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 675                 if (enable)
 676                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 677                 else
 678                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 679                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 680         }
 681 }
 682
 683 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
 684                                           const struct ci_pt_config_reg *cac_config_regs)
 685 {
 686         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 687         u32 data;
 688         u32 cache = 0;
 689
 690         if (config_regs == NULL)
 691                 return -EINVAL;
 692
 693         while (config_regs->offset != 0xFFFFFFFF) {
 694                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 695                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 696                 } else {
 697                         switch (config_regs->type) {
 698                         case CISLANDS_CONFIGREG_SMC_IND:
 699                                 data = RREG32_SMC(config_regs->offset);
 700                                 break;
 701                         case CISLANDS_CONFIGREG_DIDT_IND:
 702                                 data = RREG32_DIDT(config_regs->offset);
 703                                 break;
 704                         default:
 705                                 data = RREG32(config_regs->offset);
 706                                 break;
 707                         }
 708
 709                         data &= ~config_regs->mask;
 710                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 711                         data |= cache;
 712
 713                         switch (config_regs->type) {
 714                         case CISLANDS_CONFIGREG_SMC_IND:
 715                                 WREG32_SMC(config_regs->offset, data);
 716                                 break;
 717                         case CISLANDS_CONFIGREG_DIDT_IND:
 718                                 WREG32_DIDT(config_regs->offset, data);
 719                                 break;
 720                         default:
 721                                 WREG32(config_regs->offset, data);
 722                                 break;
 723                         }
 724                         cache = 0;
 725                 }
 726                 config_regs++;
 727         }
 728         return 0;
 729 }
 730
 731 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
 732 {
 733         struct ci_power_info *pi = ci_get_pi(adev);
 734         int ret;
 735
 736         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 737             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 738                 gfx_v7_0_enter_rlc_safe_mode(adev);
 739
 740                 if (enable) {
 741                         ret = ci_program_pt_config_registers(adev, didt_config_ci);
 742                         if (ret) {
 743                                 gfx_v7_0_exit_rlc_safe_mode(adev);
 744                                 return ret;
 745                         }
 746                 }
 747
 748                 ci_do_enable_didt(adev, enable);
 749
 750                 gfx_v7_0_exit_rlc_safe_mode(adev);
 751         }
 752
 753         return 0;
 754 }
 755
 756 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
 757 {
 758         struct ci_power_info *pi = ci_get_pi(adev);
 759         PPSMC_Result smc_result;
 760         int ret = 0;
 761
 762         if (enable) {
 763                 pi->power_containment_features = 0;
 764                 if (pi->caps_power_containment) {
 765                         if (pi->enable_bapm_feature) {
 766                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
 767                                 if (smc_result != PPSMC_Result_OK)
 768                                         ret = -EINVAL;
 769                                 else
 770                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 771                         }
 772
 773                         if (pi->enable_tdc_limit_feature) {
 774                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
 775                                 if (smc_result != PPSMC_Result_OK)
 776                                         ret = -EINVAL;
 777                                 else
 778                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 779                         }
 780
 781                         if (pi->enable_pkg_pwr_tracking_feature) {
 782                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
 783                                 if (smc_result != PPSMC_Result_OK) {
 784                                         ret = -EINVAL;
 785                                 } else {
 786                                         struct amdgpu_cac_tdp_table *cac_tdp_table =
 787                                                 adev->pm.dpm.dyn_state.cac_tdp_table;
 788                                         u32 default_pwr_limit =
 789                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 790
 791                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 792
 793                                         ci_set_power_limit(adev, default_pwr_limit);
 794                                 }
 795                         }
 796                 }
 797         } else {
 798                 if (pi->caps_power_containment && pi->power_containment_features) {
 799                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 800                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
 801
 802                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 803                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
 804
 805                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 806                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
 807                         pi->power_containment_features = 0;
 808                 }
 809         }
 810
 811         return ret;
 812 }
 813
 814 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 815 {
 816         struct ci_power_info *pi = ci_get_pi(adev);
 817         PPSMC_Result smc_result;
 818         int ret = 0;
 819
 820         if (pi->caps_cac) {
 821                 if (enable) {
 822                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
 823                         if (smc_result != PPSMC_Result_OK) {
 824                                 ret = -EINVAL;
 825                                 pi->cac_enabled = false;
 826                         } else {
 827                                 pi->cac_enabled = true;
 828                         }
 829                 } else if (pi->cac_enabled) {
 830                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
 831                         pi->cac_enabled = false;
 832                 }
 833         }
 834
 835         return ret;
 836 }
 837
 838 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
 839                                             bool enable)
 840 {
 841         struct ci_power_info *pi = ci_get_pi(adev);
 842         PPSMC_Result smc_result = PPSMC_Result_OK;
 843
 844         if (pi->thermal_sclk_dpm_enabled) {
 845                 if (enable)
 846                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
 847                 else
 848                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
 849         }
 850
 851         if (smc_result == PPSMC_Result_OK)
 852                 return 0;
 853         else
 854                 return -EINVAL;
 855 }
 856
 857 static int ci_power_control_set_level(struct amdgpu_device *adev)
 858 {
 859         struct ci_power_info *pi = ci_get_pi(adev);
 860         struct amdgpu_cac_tdp_table *cac_tdp_table =
 861                 adev->pm.dpm.dyn_state.cac_tdp_table;
 862         s32 adjust_percent;
 863         s32 target_tdp;
 864         int ret = 0;
 865         bool adjust_polarity = false; /* ??? */
 866
 867         if (pi->caps_power_containment) {
 868                 adjust_percent = adjust_polarity ?
 869                         adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
 870                 target_tdp = ((100 + adjust_percent) *
 871                               (s32)cac_tdp_table->configurable_tdp) / 100;
 872
 873                 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
 874         }
 875
 876         return ret;
 877 }
 878
 879 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 880 {
 881         struct ci_power_info *pi = ci_get_pi(adev);
 882
 883         if (pi->uvd_power_gated == gate)
 884                 return;
 885
 886         pi->uvd_power_gated = gate;
 887
 888         ci_update_uvd_dpm(adev, gate);
 889 }
 890
 891 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
 892 {
 893         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
 894         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
 895
 896         if (vblank_time < switch_limit)
 897                 return true;
 898         else
 899                 return false;
 900
 901 }
 902
 903 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
 904                                         struct amdgpu_ps *rps)
 905 {
 906         struct ci_ps *ps = ci_get_ps(rps);
 907         struct ci_power_info *pi = ci_get_pi(adev);
 908         struct amdgpu_clock_and_voltage_limits *max_limits;
 909         bool disable_mclk_switching;
 910         u32 sclk, mclk;
 911         int i;
 912
 913         if (rps->vce_active) {
 914                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
 915                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
 916         } else {
 917                 rps->evclk = 0;
 918                 rps->ecclk = 0;
 919         }
 920
 921         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
 922             ci_dpm_vblank_too_short(adev))
 923                 disable_mclk_switching = true;
 924         else
 925                 disable_mclk_switching = false;
 926
 927         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 928                 pi->battery_state = true;
 929         else
 930                 pi->battery_state = false;
 931
 932         if (adev->pm.dpm.ac_power)
 933                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 934         else
 935                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 936
 937         if (adev->pm.dpm.ac_power == false) {
 938                 for (i = 0; i < ps->performance_level_count; i++) {
 939                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 940                                 ps->performance_levels[i].mclk = max_limits->mclk;
 941                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 942                                 ps->performance_levels[i].sclk = max_limits->sclk;
 943                 }
 944         }
 945
 946         /* XXX validate the min clocks required for display */
 947
 948         if (disable_mclk_switching) {
 949                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 950                 sclk = ps->performance_levels[0].sclk;
 951         } else {
 952                 mclk = ps->performance_levels[0].mclk;
 953                 sclk = ps->performance_levels[0].sclk;
 954         }
 955
 956         if (rps->vce_active) {
 957                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
 958                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
 959                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
 960                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
 961         }
 962
 963         ps->performance_levels[0].sclk = sclk;
 964         ps->performance_levels[0].mclk = mclk;
 965
 966         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 967                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 968
 969         if (disable_mclk_switching) {
 970                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 971                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 972         } else {
 973                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 974                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 975         }
 976 }
 977
 978 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
 979                                             int min_temp, int max_temp)
 980 {
 981         int low_temp = 0 * 1000;
 982         int high_temp = 255 * 1000;
 983         u32 tmp;
 984
 985         if (low_temp < min_temp)
 986                 low_temp = min_temp;
 987         if (high_temp > max_temp)
 988                 high_temp = max_temp;
 989         if (high_temp < low_temp) {
 990                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 991                 return -EINVAL;
 992         }
 993
 994         tmp = RREG32_SMC(ixCG_THERMAL_INT);
 995         tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
 996         tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
 997                 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
 998         WREG32_SMC(ixCG_THERMAL_INT, tmp);
 999
1000 #if 0
1001         /* XXX: need to figure out how to handle this properly */
1002         tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1003         tmp &= DIG_THERM_DPM_MASK;
1004         tmp |= DIG_THERM_DPM(high_temp / 1000);
1005         WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1006 #endif
1007
1008         adev->pm.dpm.thermal.min_temp = low_temp;
1009         adev->pm.dpm.thermal.max_temp = high_temp;
1010         return 0;
1011 }
1012
1013 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1014                                    bool enable)
1015 {
1016         u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1017         PPSMC_Result result;
1018
1019         if (enable) {
1020                 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1021                                  CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1022                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1023                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1024                 if (result != PPSMC_Result_OK) {
1025                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1026                         return -EINVAL;
1027                 }
1028         } else {
1029                 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1030                         CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1031                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1032                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1033                 if (result != PPSMC_Result_OK) {
1034                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1035                         return -EINVAL;
1036                 }
1037         }
1038
1039         return 0;
1040 }
1041
1042 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1043 {
1044         struct ci_power_info *pi = ci_get_pi(adev);
1045         u32 tmp;
1046
1047         if (pi->fan_ctrl_is_in_default_mode) {
1048                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1049                         >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1050                 pi->fan_ctrl_default_mode = tmp;
1051                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1052                         >> CG_FDO_CTRL2__TMIN__SHIFT;
1053                 pi->t_min = tmp;
1054                 pi->fan_ctrl_is_in_default_mode = false;
1055         }
1056
1057         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1058         tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1059         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1060
1061         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1062         tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1063         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1064 }
1065
1066 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1067 {
1068         struct ci_power_info *pi = ci_get_pi(adev);
1069         SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1070         u32 duty100;
1071         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1072         u16 fdo_min, slope1, slope2;
1073         u32 reference_clock, tmp;
1074         int ret;
1075         u64 tmp64;
1076
1077         if (!pi->fan_table_start) {
1078                 adev->pm.dpm.fan.ucode_fan_control = false;
1079                 return 0;
1080         }
1081
1082         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1083                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1084
1085         if (duty100 == 0) {
1086                 adev->pm.dpm.fan.ucode_fan_control = false;
1087                 return 0;
1088         }
1089
1090         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1091         do_div(tmp64, 10000);
1092         fdo_min = (u16)tmp64;
1093
1094         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1095         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1096
1097         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1098         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1099
1100         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1101         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1102
1103         fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1104         fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1105         fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1106
1107         fan_table.Slope1 = cpu_to_be16(slope1);
1108         fan_table.Slope2 = cpu_to_be16(slope2);
1109
1110         fan_table.FdoMin = cpu_to_be16(fdo_min);
1111
1112         fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1113
1114         fan_table.HystUp = cpu_to_be16(1);
1115
1116         fan_table.HystSlope = cpu_to_be16(1);
1117
1118         fan_table.TempRespLim = cpu_to_be16(5);
1119
1120         reference_clock = amdgpu_asic_get_xclk(adev);
1121
1122         fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1123                                                reference_clock) / 1600);
1124
1125         fan_table.FdoMax = cpu_to_be16((u16)duty100);
1126
1127         tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1128                 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1129         fan_table.TempSrc = (uint8_t)tmp;
1130
1131         ret = amdgpu_ci_copy_bytes_to_smc(adev,
1132                                           pi->fan_table_start,
1133                                           (u8 *)(&fan_table),
1134                                           sizeof(fan_table),
1135                                           pi->sram_end);
1136
1137         if (ret) {
1138                 DRM_ERROR("Failed to load fan table to the SMC.");
1139                 adev->pm.dpm.fan.ucode_fan_control = false;
1140         }
1141
1142         return 0;
1143 }
1144
1145 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1146 {
1147         struct ci_power_info *pi = ci_get_pi(adev);
1148         PPSMC_Result ret;
1149
1150         if (pi->caps_od_fuzzy_fan_control_support) {
1151                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1152                                                                PPSMC_StartFanControl,
1153                                                                FAN_CONTROL_FUZZY);
1154                 if (ret != PPSMC_Result_OK)
1155                         return -EINVAL;
1156                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1157                                                                PPSMC_MSG_SetFanPwmMax,
1158                                                                adev->pm.dpm.fan.default_max_fan_pwm);
1159                 if (ret != PPSMC_Result_OK)
1160                         return -EINVAL;
1161         } else {
1162                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1163                                                                PPSMC_StartFanControl,
1164                                                                FAN_CONTROL_TABLE);
1165                 if (ret != PPSMC_Result_OK)
1166                         return -EINVAL;
1167         }
1168
1169         pi->fan_is_controlled_by_smc = true;
1170         return 0;
1171 }
1172
1173
1174 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1175 {
1176         PPSMC_Result ret;
1177         struct ci_power_info *pi = ci_get_pi(adev);
1178
1179         ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1180         if (ret == PPSMC_Result_OK) {
1181                 pi->fan_is_controlled_by_smc = false;
1182                 return 0;
1183         } else {
1184                 return -EINVAL;
1185         }
1186 }
1187
1188 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1189                                         u32 *speed)
1190 {
1191         u32 duty, duty100;
1192         u64 tmp64;
1193
1194         if (adev->pm.no_fan)
1195                 return -ENOENT;
1196
1197         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1198                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1199         duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1200                 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1201
1202         if (duty100 == 0)
1203                 return -EINVAL;
1204
1205         tmp64 = (u64)duty * 100;
1206         do_div(tmp64, duty100);
1207         *speed = (u32)tmp64;
1208
1209         if (*speed > 100)
1210                 *speed = 100;
1211
1212         return 0;
1213 }
1214
1215 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1216                                         u32 speed)
1217 {
1218         u32 tmp;
1219         u32 duty, duty100;
1220         u64 tmp64;
1221         struct ci_power_info *pi = ci_get_pi(adev);
1222
1223         if (adev->pm.no_fan)
1224                 return -ENOENT;
1225
1226         if (pi->fan_is_controlled_by_smc)
1227                 return -EINVAL;
1228
1229         if (speed > 100)
1230                 return -EINVAL;
1231
1232         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1233                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1234
1235         if (duty100 == 0)
1236                 return -EINVAL;
1237
1238         tmp64 = (u64)speed * duty100;
1239         do_div(tmp64, 100);
1240         duty = (u32)tmp64;
1241
1242         tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1243         tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1244         WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1245
1246         return 0;
1247 }
1248
1249 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1250 {
1251         if (mode) {
1252                 /* stop auto-manage */
1253                 if (adev->pm.dpm.fan.ucode_fan_control)
1254                         ci_fan_ctrl_stop_smc_fan_control(adev);
1255                 ci_fan_ctrl_set_static_mode(adev, mode);
1256         } else {
1257                 /* restart auto-manage */
1258                 if (adev->pm.dpm.fan.ucode_fan_control)
1259                         ci_thermal_start_smc_fan_control(adev);
1260                 else
1261                         ci_fan_ctrl_set_default_mode(adev);
1262         }
1263 }
1264
1265 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1266 {
1267         struct ci_power_info *pi = ci_get_pi(adev);
1268         u32 tmp;
1269
1270         if (pi->fan_is_controlled_by_smc)
1271                 return 0;
1272
1273         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1274         return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
1275 }
1276
1277 #if 0
1278 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1279                                          u32 *speed)
1280 {
1281         u32 tach_period;
1282         u32 xclk = amdgpu_asic_get_xclk(adev);
1283
1284         if (adev->pm.no_fan)
1285                 return -ENOENT;
1286
1287         if (adev->pm.fan_pulses_per_revolution == 0)
1288                 return -ENOENT;
1289
1290         tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1291                 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1292         if (tach_period == 0)
1293                 return -ENOENT;
1294
1295         *speed = 60 * xclk * 10000 / tach_period;
1296
1297         return 0;
1298 }
1299
1300 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1301                                          u32 speed)
1302 {
1303         u32 tach_period, tmp;
1304         u32 xclk = amdgpu_asic_get_xclk(adev);
1305
1306         if (adev->pm.no_fan)
1307                 return -ENOENT;
1308
1309         if (adev->pm.fan_pulses_per_revolution == 0)
1310                 return -ENOENT;
1311
1312         if ((speed < adev->pm.fan_min_rpm) ||
1313             (speed > adev->pm.fan_max_rpm))
1314                 return -EINVAL;
1315
1316         if (adev->pm.dpm.fan.ucode_fan_control)
1317                 ci_fan_ctrl_stop_smc_fan_control(adev);
1318
1319         tach_period = 60 * xclk * 10000 / (8 * speed);
1320         tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1321         tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1322         WREG32_SMC(CG_TACH_CTRL, tmp);
1323
1324         ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1325
1326         return 0;
1327 }
1328 #endif
1329
1330 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1331 {
1332         struct ci_power_info *pi = ci_get_pi(adev);
1333         u32 tmp;
1334
1335         if (!pi->fan_ctrl_is_in_default_mode) {
1336                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1337                 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1338                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1339
1340                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1341                 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1342                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1343                 pi->fan_ctrl_is_in_default_mode = true;
1344         }
1345 }
1346
1347 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1348 {
1349         if (adev->pm.dpm.fan.ucode_fan_control) {
1350                 ci_fan_ctrl_start_smc_fan_control(adev);
1351                 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1352         }
1353 }
1354
1355 static void ci_thermal_initialize(struct amdgpu_device *adev)
1356 {
1357         u32 tmp;
1358
1359         if (adev->pm.fan_pulses_per_revolution) {
1360                 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1361                 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1362                         << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1363                 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1364         }
1365
1366         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1367         tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1368         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1369 }
1370
1371 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1372 {
1373         int ret;
1374
1375         ci_thermal_initialize(adev);
1376         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1377         if (ret)
1378                 return ret;
1379         ret = ci_thermal_enable_alert(adev, true);
1380         if (ret)
1381                 return ret;
1382         if (adev->pm.dpm.fan.ucode_fan_control) {
1383                 ret = ci_thermal_setup_fan_table(adev);
1384                 if (ret)
1385                         return ret;
1386                 ci_thermal_start_smc_fan_control(adev);
1387         }
1388
1389         return 0;
1390 }
1391
1392 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1393 {
1394         if (!adev->pm.no_fan)
1395                 ci_fan_ctrl_set_default_mode(adev);
1396 }
1397
1398 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1399                                      u16 reg_offset, u32 *value)
1400 {
1401         struct ci_power_info *pi = ci_get_pi(adev);
1402
1403         return amdgpu_ci_read_smc_sram_dword(adev,
1404                                       pi->soft_regs_start + reg_offset,
1405                                       value, pi->sram_end);
1406 }
1407
1408 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1409                                       u16 reg_offset, u32 value)
1410 {
1411         struct ci_power_info *pi = ci_get_pi(adev);
1412
1413         return amdgpu_ci_write_smc_sram_dword(adev,
1414                                        pi->soft_regs_start + reg_offset,
1415                                        value, pi->sram_end);
1416 }
1417
1418 static void ci_init_fps_limits(struct amdgpu_device *adev)
1419 {
1420         struct ci_power_info *pi = ci_get_pi(adev);
1421         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1422
1423         if (pi->caps_fps) {
1424                 u16 tmp;
1425
1426                 tmp = 45;
1427                 table->FpsHighT = cpu_to_be16(tmp);
1428
1429                 tmp = 30;
1430                 table->FpsLowT = cpu_to_be16(tmp);
1431         }
1432 }
1433
1434 static int ci_update_sclk_t(struct amdgpu_device *adev)
1435 {
1436         struct ci_power_info *pi = ci_get_pi(adev);
1437         int ret = 0;
1438         u32 low_sclk_interrupt_t = 0;
1439
1440         if (pi->caps_sclk_throttle_low_notification) {
1441                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1442
1443                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1444                                            pi->dpm_table_start +
1445                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1446                                            (u8 *)&low_sclk_interrupt_t,
1447                                            sizeof(u32), pi->sram_end);
1448
1449         }
1450
1451         return ret;
1452 }
1453
1454 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1455 {
1456         struct ci_power_info *pi = ci_get_pi(adev);
1457         u16 leakage_id, virtual_voltage_id;
1458         u16 vddc, vddci;
1459         int i;
1460
1461         pi->vddc_leakage.count = 0;
1462         pi->vddci_leakage.count = 0;
1463
1464         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1465                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1466                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1467                         if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1468                                 continue;
1469                         if (vddc != 0 && vddc != virtual_voltage_id) {
1470                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1471                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1472                                 pi->vddc_leakage.count++;
1473                         }
1474                 }
1475         } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1476                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1477                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1478                         if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1479                                                                                      virtual_voltage_id,
1480                                                                                      leakage_id) == 0) {
1481                                 if (vddc != 0 && vddc != virtual_voltage_id) {
1482                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1483                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1484                                         pi->vddc_leakage.count++;
1485                                 }
1486                                 if (vddci != 0 && vddci != virtual_voltage_id) {
1487                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1488                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1489                                         pi->vddci_leakage.count++;
1490                                 }
1491                         }
1492                 }
1493         }
1494 }
1495
1496 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1497 {
1498         struct ci_power_info *pi = ci_get_pi(adev);
1499         bool want_thermal_protection;
1500         enum amdgpu_dpm_event_src dpm_event_src;
1501         u32 tmp;
1502
1503         switch (sources) {
1504         case 0:
1505         default:
1506                 want_thermal_protection = false;
1507                 break;
1508         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1509                 want_thermal_protection = true;
1510                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1511                 break;
1512         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1513                 want_thermal_protection = true;
1514                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1515                 break;
1516         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1517               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1518                 want_thermal_protection = true;
1519                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1520                 break;
1521         }
1522
1523         if (want_thermal_protection) {
1524 #if 0
1525                 /* XXX: need to figure out how to handle this properly */
1526                 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1527                 tmp &= DPM_EVENT_SRC_MASK;
1528                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1529                 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1530 #endif
1531
1532                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1533                 if (pi->thermal_protection)
1534                         tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1535                 else
1536                         tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1537                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1538         } else {
1539                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1540                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1541                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1542         }
1543 }
1544
1545 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1546                                            enum amdgpu_dpm_auto_throttle_src source,
1547                                            bool enable)
1548 {
1549         struct ci_power_info *pi = ci_get_pi(adev);
1550
1551         if (enable) {
1552                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1553                         pi->active_auto_throttle_sources |= 1 << source;
1554                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1555                 }
1556         } else {
1557                 if (pi->active_auto_throttle_sources & (1 << source)) {
1558                         pi->active_auto_throttle_sources &= ~(1 << source);
1559                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1560                 }
1561         }
1562 }
1563
1564 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1565 {
1566         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1567                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1568 }
1569
1570 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1571 {
1572         struct ci_power_info *pi = ci_get_pi(adev);
1573         PPSMC_Result smc_result;
1574
1575         if (!pi->need_update_smu7_dpm_table)
1576                 return 0;
1577
1578         if ((!pi->sclk_dpm_key_disabled) &&
1579             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1580                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1581                 if (smc_result != PPSMC_Result_OK)
1582                         return -EINVAL;
1583         }
1584
1585         if ((!pi->mclk_dpm_key_disabled) &&
1586             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1587                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1588                 if (smc_result != PPSMC_Result_OK)
1589                         return -EINVAL;
1590         }
1591
1592         pi->need_update_smu7_dpm_table = 0;
1593         return 0;
1594 }
1595
1596 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1597 {
1598         struct ci_power_info *pi = ci_get_pi(adev);
1599         PPSMC_Result smc_result;
1600
1601         if (enable) {
1602                 if (!pi->sclk_dpm_key_disabled) {
1603                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1604                         if (smc_result != PPSMC_Result_OK)
1605                                 return -EINVAL;
1606                 }
1607
1608                 if (!pi->mclk_dpm_key_disabled) {
1609                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1610                         if (smc_result != PPSMC_Result_OK)
1611                                 return -EINVAL;
1612
1613                         WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1614                                         ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1615
1616                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1617                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1618                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1619
1620                         udelay(10);
1621
1622                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1623                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1624                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1625                 }
1626         } else {
1627                 if (!pi->sclk_dpm_key_disabled) {
1628                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1629                         if (smc_result != PPSMC_Result_OK)
1630                                 return -EINVAL;
1631                 }
1632
1633                 if (!pi->mclk_dpm_key_disabled) {
1634                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1635                         if (smc_result != PPSMC_Result_OK)
1636                                 return -EINVAL;
1637                 }
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int ci_start_dpm(struct amdgpu_device *adev)
1644 {
1645         struct ci_power_info *pi = ci_get_pi(adev);
1646         PPSMC_Result smc_result;
1647         int ret;
1648         u32 tmp;
1649
1650         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1651         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1652         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1653
1654         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1655         tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1656         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1657
1658         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1659
1660         WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1661
1662         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1663         if (smc_result != PPSMC_Result_OK)
1664                 return -EINVAL;
1665
1666         ret = ci_enable_sclk_mclk_dpm(adev, true);
1667         if (ret)
1668                 return ret;
1669
1670         if (!pi->pcie_dpm_key_disabled) {
1671                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1672                 if (smc_result != PPSMC_Result_OK)
1673                         return -EINVAL;
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1680 {
1681         struct ci_power_info *pi = ci_get_pi(adev);
1682         PPSMC_Result smc_result;
1683
1684         if (!pi->need_update_smu7_dpm_table)
1685                 return 0;
1686
1687         if ((!pi->sclk_dpm_key_disabled) &&
1688             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1689                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1690                 if (smc_result != PPSMC_Result_OK)
1691                         return -EINVAL;
1692         }
1693
1694         if ((!pi->mclk_dpm_key_disabled) &&
1695             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1696                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1697                 if (smc_result != PPSMC_Result_OK)
1698                         return -EINVAL;
1699         }
1700
1701         return 0;
1702 }
1703
1704 static int ci_stop_dpm(struct amdgpu_device *adev)
1705 {
1706         struct ci_power_info *pi = ci_get_pi(adev);
1707         PPSMC_Result smc_result;
1708         int ret;
1709         u32 tmp;
1710
1711         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1712         tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1713         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1714
1715         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1716         tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1717         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1718
1719         if (!pi->pcie_dpm_key_disabled) {
1720                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1721                 if (smc_result != PPSMC_Result_OK)
1722                         return -EINVAL;
1723         }
1724
1725         ret = ci_enable_sclk_mclk_dpm(adev, false);
1726         if (ret)
1727                 return ret;
1728
1729         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1730         if (smc_result != PPSMC_Result_OK)
1731                 return -EINVAL;
1732
1733         return 0;
1734 }
1735
1736 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1737 {
1738         u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1739
1740         if (enable)
1741                 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1742         else
1743                 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1744         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1745 }
1746
1747 #if 0
1748 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1749                                         bool ac_power)
1750 {
1751         struct ci_power_info *pi = ci_get_pi(adev);
1752         struct amdgpu_cac_tdp_table *cac_tdp_table =
1753                 adev->pm.dpm.dyn_state.cac_tdp_table;
1754         u32 power_limit;
1755
1756         if (ac_power)
1757                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1758         else
1759                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1760
1761         ci_set_power_limit(adev, power_limit);
1762
1763         if (pi->caps_automatic_dc_transition) {
1764                 if (ac_power)
1765                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1766                 else
1767                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1768         }
1769
1770         return 0;
1771 }
1772 #endif
1773
1774 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1775                                                       PPSMC_Msg msg, u32 parameter)
1776 {
1777         WREG32(mmSMC_MSG_ARG_0, parameter);
1778         return amdgpu_ci_send_msg_to_smc(adev, msg);
1779 }
1780
1781 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1782                                                         PPSMC_Msg msg, u32 *parameter)
1783 {
1784         PPSMC_Result smc_result;
1785
1786         smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1787
1788         if ((smc_result == PPSMC_Result_OK) && parameter)
1789                 *parameter = RREG32(mmSMC_MSG_ARG_0);
1790
1791         return smc_result;
1792 }
1793
1794 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1795 {
1796         struct ci_power_info *pi = ci_get_pi(adev);
1797
1798         if (!pi->sclk_dpm_key_disabled) {
1799                 PPSMC_Result smc_result =
1800                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1801                 if (smc_result != PPSMC_Result_OK)
1802                         return -EINVAL;
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1809 {
1810         struct ci_power_info *pi = ci_get_pi(adev);
1811
1812         if (!pi->mclk_dpm_key_disabled) {
1813                 PPSMC_Result smc_result =
1814                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1815                 if (smc_result != PPSMC_Result_OK)
1816                         return -EINVAL;
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1823 {
1824         struct ci_power_info *pi = ci_get_pi(adev);
1825
1826         if (!pi->pcie_dpm_key_disabled) {
1827                 PPSMC_Result smc_result =
1828                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1829                 if (smc_result != PPSMC_Result_OK)
1830                         return -EINVAL;
1831         }
1832
1833         return 0;
1834 }
1835
1836 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1837 {
1838         struct ci_power_info *pi = ci_get_pi(adev);
1839
1840         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1841                 PPSMC_Result smc_result =
1842                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1843                 if (smc_result != PPSMC_Result_OK)
1844                         return -EINVAL;
1845         }
1846
1847         return 0;
1848 }
1849
1850 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1851                                        u32 target_tdp)
1852 {
1853         PPSMC_Result smc_result =
1854                 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1855         if (smc_result != PPSMC_Result_OK)
1856                 return -EINVAL;
1857         return 0;
1858 }
1859
1860 #if 0
1861 static int ci_set_boot_state(struct amdgpu_device *adev)
1862 {
1863         return ci_enable_sclk_mclk_dpm(adev, false);
1864 }
1865 #endif
1866
1867 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1868 {
1869         u32 sclk_freq;
1870         PPSMC_Result smc_result =
1871                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1872                                                     PPSMC_MSG_API_GetSclkFrequency,
1873                                                     &sclk_freq);
1874         if (smc_result != PPSMC_Result_OK)
1875                 sclk_freq = 0;
1876
1877         return sclk_freq;
1878 }
1879
1880 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1881 {
1882         u32 mclk_freq;
1883         PPSMC_Result smc_result =
1884                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1885                                                     PPSMC_MSG_API_GetMclkFrequency,
1886                                                     &mclk_freq);
1887         if (smc_result != PPSMC_Result_OK)
1888                 mclk_freq = 0;
1889
1890         return mclk_freq;
1891 }
1892
1893 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1894 {
1895         int i;
1896
1897         amdgpu_ci_program_jump_on_start(adev);
1898         amdgpu_ci_start_smc_clock(adev);
1899         amdgpu_ci_start_smc(adev);
1900         for (i = 0; i < adev->usec_timeout; i++) {
1901                 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1902                         break;
1903         }
1904 }
1905
1906 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1907 {
1908         amdgpu_ci_reset_smc(adev);
1909         amdgpu_ci_stop_smc_clock(adev);
1910 }
1911
1912 static int ci_process_firmware_header(struct amdgpu_device *adev)
1913 {
1914         struct ci_power_info *pi = ci_get_pi(adev);
1915         u32 tmp;
1916         int ret;
1917
1918         ret = amdgpu_ci_read_smc_sram_dword(adev,
1919                                      SMU7_FIRMWARE_HEADER_LOCATION +
1920                                      offsetof(SMU7_Firmware_Header, DpmTable),
1921                                      &tmp, pi->sram_end);
1922         if (ret)
1923                 return ret;
1924
1925         pi->dpm_table_start = tmp;
1926
1927         ret = amdgpu_ci_read_smc_sram_dword(adev,
1928                                      SMU7_FIRMWARE_HEADER_LOCATION +
1929                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1930                                      &tmp, pi->sram_end);
1931         if (ret)
1932                 return ret;
1933
1934         pi->soft_regs_start = tmp;
1935
1936         ret = amdgpu_ci_read_smc_sram_dword(adev,
1937                                      SMU7_FIRMWARE_HEADER_LOCATION +
1938                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1939                                      &tmp, pi->sram_end);
1940         if (ret)
1941                 return ret;
1942
1943         pi->mc_reg_table_start = tmp;
1944
1945         ret = amdgpu_ci_read_smc_sram_dword(adev,
1946                                      SMU7_FIRMWARE_HEADER_LOCATION +
1947                                      offsetof(SMU7_Firmware_Header, FanTable),
1948                                      &tmp, pi->sram_end);
1949         if (ret)
1950                 return ret;
1951
1952         pi->fan_table_start = tmp;
1953
1954         ret = amdgpu_ci_read_smc_sram_dword(adev,
1955                                      SMU7_FIRMWARE_HEADER_LOCATION +
1956                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1957                                      &tmp, pi->sram_end);
1958         if (ret)
1959                 return ret;
1960
1961         pi->arb_table_start = tmp;
1962
1963         return 0;
1964 }
1965
1966 static void ci_read_clock_registers(struct amdgpu_device *adev)
1967 {
1968         struct ci_power_info *pi = ci_get_pi(adev);
1969
1970         pi->clock_registers.cg_spll_func_cntl =
1971                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1972         pi->clock_registers.cg_spll_func_cntl_2 =
1973                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1974         pi->clock_registers.cg_spll_func_cntl_3 =
1975                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
1976         pi->clock_registers.cg_spll_func_cntl_4 =
1977                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
1978         pi->clock_registers.cg_spll_spread_spectrum =
1979                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
1980         pi->clock_registers.cg_spll_spread_spectrum_2 =
1981                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
1982         pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
1983         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
1984         pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
1985         pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
1986         pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
1987         pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
1988         pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
1989         pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
1990         pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
1991 }
1992
1993 static void ci_init_sclk_t(struct amdgpu_device *adev)
1994 {
1995         struct ci_power_info *pi = ci_get_pi(adev);
1996
1997         pi->low_sclk_interrupt_t = 0;
1998 }
1999
2000 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2001                                          bool enable)
2002 {
2003         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2004
2005         if (enable)
2006                 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2007         else
2008                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2009         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2010 }
2011
2012 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2013 {
2014         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2015
2016         tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2017
2018         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2019 }
2020
2021 #if 0
2022 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2023 {
2024
2025         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2026
2027         udelay(25000);
2028
2029         return 0;
2030 }
2031
2032 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2033 {
2034         int i;
2035
2036         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2037
2038         udelay(7000);
2039
2040         for (i = 0; i < adev->usec_timeout; i++) {
2041                 if (RREG32(mmSMC_RESP_0) == 1)
2042                         break;
2043                 udelay(1000);
2044         }
2045
2046         return 0;
2047 }
2048 #endif
2049
2050 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2051                                         bool has_display)
2052 {
2053         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2054
2055         return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
2056 }
2057
2058 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2059                                       bool enable)
2060 {
2061         struct ci_power_info *pi = ci_get_pi(adev);
2062
2063         if (enable) {
2064                 if (pi->caps_sclk_ds) {
2065                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2066                                 return -EINVAL;
2067                 } else {
2068                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2069                                 return -EINVAL;
2070                 }
2071         } else {
2072                 if (pi->caps_sclk_ds) {
2073                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2074                                 return -EINVAL;
2075                 }
2076         }
2077
2078         return 0;
2079 }
2080
2081 static void ci_program_display_gap(struct amdgpu_device *adev)
2082 {
2083         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2084         u32 pre_vbi_time_in_us;
2085         u32 frame_time_in_us;
2086         u32 ref_clock = adev->clock.spll.reference_freq;
2087         u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2088         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2089
2090         tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2091         if (adev->pm.dpm.new_active_crtc_count > 0)
2092                 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2093         else
2094                 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2095         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2096
2097         if (refresh_rate == 0)
2098                 refresh_rate = 60;
2099         if (vblank_time == 0xffffffff)
2100                 vblank_time = 500;
2101         frame_time_in_us = 1000000 / refresh_rate;
2102         pre_vbi_time_in_us =
2103                 frame_time_in_us - 200 - vblank_time;
2104         tmp = pre_vbi_time_in_us * (ref_clock / 100);
2105
2106         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2107         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2108         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2109
2110
2111         ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2112
2113 }
2114
2115 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2116 {
2117         struct ci_power_info *pi = ci_get_pi(adev);
2118         u32 tmp;
2119
2120         if (enable) {
2121                 if (pi->caps_sclk_ss_support) {
2122                         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2123                         tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2124                         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2125                 }
2126         } else {
2127                 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2128                 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2129                 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2130
2131                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2132                 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2133                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2134         }
2135 }
2136
2137 static void ci_program_sstp(struct amdgpu_device *adev)
2138 {
2139         WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2140         ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2141          (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2142 }
2143
2144 static void ci_enable_display_gap(struct amdgpu_device *adev)
2145 {
2146         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2147
2148         tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2149                         CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2150         tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2151                 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2152
2153         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2154 }
2155
2156 static void ci_program_vc(struct amdgpu_device *adev)
2157 {
2158         u32 tmp;
2159
2160         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2161         tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2162         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2163
2164         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2165         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2166         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2167         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2168         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2169         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2170         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2171         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2172 }
2173
2174 static void ci_clear_vc(struct amdgpu_device *adev)
2175 {
2176         u32 tmp;
2177
2178         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2179         tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2180         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2181
2182         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2183         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2184         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2185         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2186         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2187         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2188         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2189         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2190 }
2191
2192 static int ci_upload_firmware(struct amdgpu_device *adev)
2193 {
2194         struct ci_power_info *pi = ci_get_pi(adev);
2195         int i, ret;
2196
2197         for (i = 0; i < adev->usec_timeout; i++) {
2198                 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2199                         break;
2200         }
2201         WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2202
2203         amdgpu_ci_stop_smc_clock(adev);
2204         amdgpu_ci_reset_smc(adev);
2205
2206         ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end);
2207
2208         return ret;
2209
2210 }
2211
2212 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2213                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2214                                      struct atom_voltage_table *voltage_table)
2215 {
2216         u32 i;
2217
2218         if (voltage_dependency_table == NULL)
2219                 return -EINVAL;
2220
2221         voltage_table->mask_low = 0;
2222         voltage_table->phase_delay = 0;
2223
2224         voltage_table->count = voltage_dependency_table->count;
2225         for (i = 0; i < voltage_table->count; i++) {
2226                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2227                 voltage_table->entries[i].smio_low = 0;
2228         }
2229
2230         return 0;
2231 }
2232
2233 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2234 {
2235         struct ci_power_info *pi = ci_get_pi(adev);
2236         int ret;
2237
2238         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2239                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2240                                                         VOLTAGE_OBJ_GPIO_LUT,
2241                                                         &pi->vddc_voltage_table);
2242                 if (ret)
2243                         return ret;
2244         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2245                 ret = ci_get_svi2_voltage_table(adev,
2246                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2247                                                 &pi->vddc_voltage_table);
2248                 if (ret)
2249                         return ret;
2250         }
2251
2252         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2253                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2254                                                          &pi->vddc_voltage_table);
2255
2256         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2257                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2258                                                         VOLTAGE_OBJ_GPIO_LUT,
2259                                                         &pi->vddci_voltage_table);
2260                 if (ret)
2261                         return ret;
2262         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2263                 ret = ci_get_svi2_voltage_table(adev,
2264                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2265                                                 &pi->vddci_voltage_table);
2266                 if (ret)
2267                         return ret;
2268         }
2269
2270         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2271                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2272                                                          &pi->vddci_voltage_table);
2273
2274         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2275                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2276                                                         VOLTAGE_OBJ_GPIO_LUT,
2277                                                         &pi->mvdd_voltage_table);
2278                 if (ret)
2279                         return ret;
2280         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2281                 ret = ci_get_svi2_voltage_table(adev,
2282                                                 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2283                                                 &pi->mvdd_voltage_table);
2284                 if (ret)
2285                         return ret;
2286         }
2287
2288         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2289                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2290                                                          &pi->mvdd_voltage_table);
2291
2292         return 0;
2293 }
2294
2295 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2296                                           struct atom_voltage_table_entry *voltage_table,
2297                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
2298 {
2299         int ret;
2300
2301         ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2302                                             &smc_voltage_table->StdVoltageHiSidd,
2303                                             &smc_voltage_table->StdVoltageLoSidd);
2304
2305         if (ret) {
2306                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2307                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2308         }
2309
2310         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2311         smc_voltage_table->StdVoltageHiSidd =
2312                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2313         smc_voltage_table->StdVoltageLoSidd =
2314                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2315 }
2316
2317 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2318                                       SMU7_Discrete_DpmTable *table)
2319 {
2320         struct ci_power_info *pi = ci_get_pi(adev);
2321         unsigned int count;
2322
2323         table->VddcLevelCount = pi->vddc_voltage_table.count;
2324         for (count = 0; count < table->VddcLevelCount; count++) {
2325                 ci_populate_smc_voltage_table(adev,
2326                                               &pi->vddc_voltage_table.entries[count],
2327                                               &table->VddcLevel[count]);
2328
2329                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2330                         table->VddcLevel[count].Smio |=
2331                                 pi->vddc_voltage_table.entries[count].smio_low;
2332                 else
2333                         table->VddcLevel[count].Smio = 0;
2334         }
2335         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2336
2337         return 0;
2338 }
2339
2340 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2341                                        SMU7_Discrete_DpmTable *table)
2342 {
2343         unsigned int count;
2344         struct ci_power_info *pi = ci_get_pi(adev);
2345
2346         table->VddciLevelCount = pi->vddci_voltage_table.count;
2347         for (count = 0; count < table->VddciLevelCount; count++) {
2348                 ci_populate_smc_voltage_table(adev,
2349                                               &pi->vddci_voltage_table.entries[count],
2350                                               &table->VddciLevel[count]);
2351
2352                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2353                         table->VddciLevel[count].Smio |=
2354                                 pi->vddci_voltage_table.entries[count].smio_low;
2355                 else
2356                         table->VddciLevel[count].Smio = 0;
2357         }
2358         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2359
2360         return 0;
2361 }
2362
2363 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2364                                       SMU7_Discrete_DpmTable *table)
2365 {
2366         struct ci_power_info *pi = ci_get_pi(adev);
2367         unsigned int count;
2368
2369         table->MvddLevelCount = pi->mvdd_voltage_table.count;
2370         for (count = 0; count < table->MvddLevelCount; count++) {
2371                 ci_populate_smc_voltage_table(adev,
2372                                               &pi->mvdd_voltage_table.entries[count],
2373                                               &table->MvddLevel[count]);
2374
2375                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2376                         table->MvddLevel[count].Smio |=
2377                                 pi->mvdd_voltage_table.entries[count].smio_low;
2378                 else
2379                         table->MvddLevel[count].Smio = 0;
2380         }
2381         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2382
2383         return 0;
2384 }
2385
2386 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2387                                           SMU7_Discrete_DpmTable *table)
2388 {
2389         int ret;
2390
2391         ret = ci_populate_smc_vddc_table(adev, table);
2392         if (ret)
2393                 return ret;
2394
2395         ret = ci_populate_smc_vddci_table(adev, table);
2396         if (ret)
2397                 return ret;
2398
2399         ret = ci_populate_smc_mvdd_table(adev, table);
2400         if (ret)
2401                 return ret;
2402
2403         return 0;
2404 }
2405
2406 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2407                                   SMU7_Discrete_VoltageLevel *voltage)
2408 {
2409         struct ci_power_info *pi = ci_get_pi(adev);
2410         u32 i = 0;
2411
2412         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2413                 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2414                         if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2415                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2416                                 break;
2417                         }
2418                 }
2419
2420                 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2421                         return -EINVAL;
2422         }
2423
2424         return -EINVAL;
2425 }
2426
2427 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2428                                          struct atom_voltage_table_entry *voltage_table,
2429                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2430 {
2431         u16 v_index, idx;
2432         bool voltage_found = false;
2433         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2434         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2435
2436         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2437                 return -EINVAL;
2438
2439         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2440                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2441                         if (voltage_table->value ==
2442                             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2443                                 voltage_found = true;
2444                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2445                                         idx = v_index;
2446                                 else
2447                                         idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2448                                 *std_voltage_lo_sidd =
2449                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2450                                 *std_voltage_hi_sidd =
2451                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2452                                 break;
2453                         }
2454                 }
2455
2456                 if (!voltage_found) {
2457                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2458                                 if (voltage_table->value <=
2459                                     adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2460                                         voltage_found = true;
2461                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2462                                                 idx = v_index;
2463                                         else
2464                                                 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2465                                         *std_voltage_lo_sidd =
2466                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2467                                         *std_voltage_hi_sidd =
2468                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2469                                         break;
2470                                 }
2471                         }
2472                 }
2473         }
2474
2475         return 0;
2476 }
2477
2478 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2479                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2480                                                   u32 sclk,
2481                                                   u32 *phase_shedding)
2482 {
2483         unsigned int i;
2484
2485         *phase_shedding = 1;
2486
2487         for (i = 0; i < limits->count; i++) {
2488                 if (sclk < limits->entries[i].sclk) {
2489                         *phase_shedding = i;
2490                         break;
2491                 }
2492         }
2493 }
2494
2495 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2496                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2497                                                   u32 mclk,
2498                                                   u32 *phase_shedding)
2499 {
2500         unsigned int i;
2501
2502         *phase_shedding = 1;
2503
2504         for (i = 0; i < limits->count; i++) {
2505                 if (mclk < limits->entries[i].mclk) {
2506                         *phase_shedding = i;
2507                         break;
2508                 }
2509         }
2510 }
2511
2512 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2513 {
2514         struct ci_power_info *pi = ci_get_pi(adev);
2515         u32 tmp;
2516         int ret;
2517
2518         ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2519                                      &tmp, pi->sram_end);
2520         if (ret)
2521                 return ret;
2522
2523         tmp &= 0x00FFFFFF;
2524         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2525
2526         return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2527                                        tmp, pi->sram_end);
2528 }
2529
2530 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2531                                          struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2532                                          u32 clock, u32 *voltage)
2533 {
2534         u32 i = 0;
2535
2536         if (allowed_clock_voltage_table->count == 0)
2537                 return -EINVAL;
2538
2539         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2540                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2541                         *voltage = allowed_clock_voltage_table->entries[i].v;
2542                         return 0;
2543                 }
2544         }
2545
2546         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2547
2548         return 0;
2549 }
2550
2551 static u8 ci_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2552                                              u32 sclk, u32 min_sclk_in_sr)
2553 {
2554         u32 i;
2555         u32 tmp;
2556         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2557                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2558
2559         if (sclk < min)
2560                 return 0;
2561
2562         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2563                 tmp = sclk / (1 << i);
2564                 if (tmp >= min || i == 0)
2565                         break;
2566         }
2567
2568         return (u8)i;
2569 }
2570
2571 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2572 {
2573         return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2574 }
2575
2576 static int ci_reset_to_default(struct amdgpu_device *adev)
2577 {
2578         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2579                 0 : -EINVAL;
2580 }
2581
2582 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2583 {
2584         u32 tmp;
2585
2586         tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2587
2588         if (tmp == MC_CG_ARB_FREQ_F0)
2589                 return 0;
2590
2591         return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2592 }
2593
2594 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2595                                         const u32 engine_clock,
2596                                         const u32 memory_clock,
2597                                         u32 *dram_timimg2)
2598 {
2599         bool patch;
2600         u32 tmp, tmp2;
2601
2602         tmp = RREG32(mmMC_SEQ_MISC0);
2603         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2604
2605         if (patch &&
2606             ((adev->pdev->device == 0x67B0) ||
2607              (adev->pdev->device == 0x67B1))) {
2608                 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2609                         tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2610                         *dram_timimg2 &= ~0x00ff0000;
2611                         *dram_timimg2 |= tmp2 << 16;
2612                 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2613                         tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2614                         *dram_timimg2 &= ~0x00ff0000;
2615                         *dram_timimg2 |= tmp2 << 16;
2616                 }
2617         }
2618 }
2619
2620 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2621                                                 u32 sclk,
2622                                                 u32 mclk,
2623                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2624 {
2625         u32 dram_timing;
2626         u32 dram_timing2;
2627         u32 burst_time;
2628
2629         amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2630
2631         dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
2632         dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2633         burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2634
2635         ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2636
2637         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2638         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2639         arb_regs->McArbBurstTime = (u8)burst_time;
2640
2641         return 0;
2642 }
2643
2644 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2645 {
2646         struct ci_power_info *pi = ci_get_pi(adev);
2647         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2648         u32 i, j;
2649         int ret =  0;
2650
2651         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2652
2653         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2654                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2655                         ret = ci_populate_memory_timing_parameters(adev,
2656                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2657                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2658                                                                    &arb_regs.entries[i][j]);
2659                         if (ret)
2660                                 break;
2661                 }
2662         }
2663
2664         if (ret == 0)
2665                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2666                                            pi->arb_table_start,
2667                                            (u8 *)&arb_regs,
2668                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2669                                            pi->sram_end);
2670
2671         return ret;
2672 }
2673
2674 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2675 {
2676         struct ci_power_info *pi = ci_get_pi(adev);
2677
2678         if (pi->need_update_smu7_dpm_table == 0)
2679                 return 0;
2680
2681         return ci_do_program_memory_timing_parameters(adev);
2682 }
2683
2684 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2685                                           struct amdgpu_ps *amdgpu_boot_state)
2686 {
2687         struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2688         struct ci_power_info *pi = ci_get_pi(adev);
2689         u32 level = 0;
2690
2691         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2692                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2693                     boot_state->performance_levels[0].sclk) {
2694                         pi->smc_state_table.GraphicsBootLevel = level;
2695                         break;
2696                 }
2697         }
2698
2699         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2700                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2701                     boot_state->performance_levels[0].mclk) {
2702                         pi->smc_state_table.MemoryBootLevel = level;
2703                         break;
2704                 }
2705         }
2706 }
2707
2708 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2709 {
2710         u32 i;
2711         u32 mask_value = 0;
2712
2713         for (i = dpm_table->count; i > 0; i--) {
2714                 mask_value = mask_value << 1;
2715                 if (dpm_table->dpm_levels[i-1].enabled)
2716                         mask_value |= 0x1;
2717                 else
2718                         mask_value &= 0xFFFFFFFE;
2719         }
2720
2721         return mask_value;
2722 }
2723
2724 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2725                                        SMU7_Discrete_DpmTable *table)
2726 {
2727         struct ci_power_info *pi = ci_get_pi(adev);
2728         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2729         u32 i;
2730
2731         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2732                 table->LinkLevel[i].PcieGenSpeed =
2733                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2734                 table->LinkLevel[i].PcieLaneCount =
2735                         amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2736                 table->LinkLevel[i].EnabledForActivity = 1;
2737                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2738                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2739         }
2740
2741         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2742         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2743                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2744 }
2745
2746 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2747                                      SMU7_Discrete_DpmTable *table)
2748 {
2749         u32 count;
2750         struct atom_clock_dividers dividers;
2751         int ret = -EINVAL;
2752
2753         table->UvdLevelCount =
2754                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2755
2756         for (count = 0; count < table->UvdLevelCount; count++) {
2757                 table->UvdLevel[count].VclkFrequency =
2758                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2759                 table->UvdLevel[count].DclkFrequency =
2760                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2761                 table->UvdLevel[count].MinVddc =
2762                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2763                 table->UvdLevel[count].MinVddcPhases = 1;
2764
2765                 ret = amdgpu_atombios_get_clock_dividers(adev,
2766                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2767                                                          table->UvdLevel[count].VclkFrequency, false, &dividers);
2768                 if (ret)
2769                         return ret;
2770
2771                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2772
2773                 ret = amdgpu_atombios_get_clock_dividers(adev,
2774                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2775                                                          table->UvdLevel[count].DclkFrequency, false, &dividers);
2776                 if (ret)
2777                         return ret;
2778
2779                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2780
2781                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2782                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2783                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2784         }
2785
2786         return ret;
2787 }
2788
2789 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2790                                      SMU7_Discrete_DpmTable *table)
2791 {
2792         u32 count;
2793         struct atom_clock_dividers dividers;
2794         int ret = -EINVAL;
2795
2796         table->VceLevelCount =
2797                 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2798
2799         for (count = 0; count < table->VceLevelCount; count++) {
2800                 table->VceLevel[count].Frequency =
2801                         adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2802                 table->VceLevel[count].MinVoltage =
2803                         (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2804                 table->VceLevel[count].MinPhases = 1;
2805
2806                 ret = amdgpu_atombios_get_clock_dividers(adev,
2807                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2808                                                          table->VceLevel[count].Frequency, false, &dividers);
2809                 if (ret)
2810                         return ret;
2811
2812                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2813
2814                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2815                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2816         }
2817
2818         return ret;
2819
2820 }
2821
2822 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2823                                      SMU7_Discrete_DpmTable *table)
2824 {
2825         u32 count;
2826         struct atom_clock_dividers dividers;
2827         int ret = -EINVAL;
2828
2829         table->AcpLevelCount = (u8)
2830                 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2831
2832         for (count = 0; count < table->AcpLevelCount; count++) {
2833                 table->AcpLevel[count].Frequency =
2834                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2835                 table->AcpLevel[count].MinVoltage =
2836                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2837                 table->AcpLevel[count].MinPhases = 1;
2838
2839                 ret = amdgpu_atombios_get_clock_dividers(adev,
2840                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2841                                                          table->AcpLevel[count].Frequency, false, &dividers);
2842                 if (ret)
2843                         return ret;
2844
2845                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2846
2847                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2848                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2849         }
2850
2851         return ret;
2852 }
2853
2854 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2855                                       SMU7_Discrete_DpmTable *table)
2856 {
2857         u32 count;
2858         struct atom_clock_dividers dividers;
2859         int ret = -EINVAL;
2860
2861         table->SamuLevelCount =
2862                 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2863
2864         for (count = 0; count < table->SamuLevelCount; count++) {
2865                 table->SamuLevel[count].Frequency =
2866                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2867                 table->SamuLevel[count].MinVoltage =
2868                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2869                 table->SamuLevel[count].MinPhases = 1;
2870
2871                 ret = amdgpu_atombios_get_clock_dividers(adev,
2872                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2873                                                          table->SamuLevel[count].Frequency, false, &dividers);
2874                 if (ret)
2875                         return ret;
2876
2877                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2878
2879                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2880                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2881         }
2882
2883         return ret;
2884 }
2885
2886 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2887                                     u32 memory_clock,
2888                                     SMU7_Discrete_MemoryLevel *mclk,
2889                                     bool strobe_mode,
2890                                     bool dll_state_on)
2891 {
2892         struct ci_power_info *pi = ci_get_pi(adev);
2893         u32  dll_cntl = pi->clock_registers.dll_cntl;
2894         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2895         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2896         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2897         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2898         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2899         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2900         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2901         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2902         struct atom_mpll_param mpll_param;
2903         int ret;
2904
2905         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2906         if (ret)
2907                 return ret;
2908
2909         mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2910         mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2911
2912         mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2913                         MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2914         mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2915                 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2916                 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2917
2918         mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2919         mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2920
2921         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2922                 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2923                                 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2924                 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2925                                 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2926         }
2927
2928         if (pi->caps_mclk_ss_support) {
2929                 struct amdgpu_atom_ss ss;
2930                 u32 freq_nom;
2931                 u32 tmp;
2932                 u32 reference_clock = adev->clock.mpll.reference_freq;
2933
2934                 if (mpll_param.qdr == 1)
2935                         freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2936                 else
2937                         freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2938
2939                 tmp = (freq_nom / reference_clock);
2940                 tmp = tmp * tmp;
2941                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2942                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2943                         u32 clks = reference_clock * 5 / ss.rate;
2944                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2945
2946                         mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2947                         mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2948
2949                         mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2950                         mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2951                 }
2952         }
2953
2954         mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2955         mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2956
2957         if (dll_state_on)
2958                 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2959                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2960         else
2961                 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2962                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2963
2964         mclk->MclkFrequency = memory_clock;
2965         mclk->MpllFuncCntl = mpll_func_cntl;
2966         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2967         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2968         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2969         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2970         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2971         mclk->DllCntl = dll_cntl;
2972         mclk->MpllSs1 = mpll_ss1;
2973         mclk->MpllSs2 = mpll_ss2;
2974
2975         return 0;
2976 }
2977
2978 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
2979                                            u32 memory_clock,
2980                                            SMU7_Discrete_MemoryLevel *memory_level)
2981 {
2982         struct ci_power_info *pi = ci_get_pi(adev);
2983         int ret;
2984         bool dll_state_on;
2985
2986         if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2987                 ret = ci_get_dependency_volt_by_clk(adev,
2988                                                     &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2989                                                     memory_clock, &memory_level->MinVddc);
2990                 if (ret)
2991                         return ret;
2992         }
2993
2994         if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2995                 ret = ci_get_dependency_volt_by_clk(adev,
2996                                                     &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2997                                                     memory_clock, &memory_level->MinVddci);
2998                 if (ret)
2999                         return ret;
3000         }
3001
3002         if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3003                 ret = ci_get_dependency_volt_by_clk(adev,
3004                                                     &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3005                                                     memory_clock, &memory_level->MinMvdd);
3006                 if (ret)
3007                         return ret;
3008         }
3009
3010         memory_level->MinVddcPhases = 1;
3011
3012         if (pi->vddc_phase_shed_control)
3013                 ci_populate_phase_value_based_on_mclk(adev,
3014                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3015                                                       memory_clock,
3016                                                       &memory_level->MinVddcPhases);
3017
3018         memory_level->EnabledForThrottle = 1;
3019         memory_level->UpH = 0;
3020         memory_level->DownH = 100;
3021         memory_level->VoltageDownH = 0;
3022         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3023
3024         memory_level->StutterEnable = false;
3025         memory_level->StrobeEnable = false;
3026         memory_level->EdcReadEnable = false;
3027         memory_level->EdcWriteEnable = false;
3028         memory_level->RttEnable = false;
3029
3030         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3031
3032         if (pi->mclk_stutter_mode_threshold &&
3033             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3034             (pi->uvd_enabled == false) &&
3035             (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3036             (adev->pm.dpm.new_active_crtc_count <= 2))
3037                 memory_level->StutterEnable = true;
3038
3039         if (pi->mclk_strobe_mode_threshold &&
3040             (memory_clock <= pi->mclk_strobe_mode_threshold))
3041                 memory_level->StrobeEnable = 1;
3042
3043         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3044                 memory_level->StrobeRatio =
3045                         ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3046                 if (pi->mclk_edc_enable_threshold &&
3047                     (memory_clock > pi->mclk_edc_enable_threshold))
3048                         memory_level->EdcReadEnable = true;
3049
3050                 if (pi->mclk_edc_wr_enable_threshold &&
3051                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
3052                         memory_level->EdcWriteEnable = true;
3053
3054                 if (memory_level->StrobeEnable) {
3055                         if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3056                             ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3057                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3058                         else
3059                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3060                 } else {
3061                         dll_state_on = pi->dll_default_on;
3062                 }
3063         } else {
3064                 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3065                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3066         }
3067
3068         ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3069         if (ret)
3070                 return ret;
3071
3072         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3073         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3074         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3075         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3076
3077         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3078         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3079         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3080         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3081         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3082         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3083         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3084         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3085         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3086         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3087         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3088
3089         return 0;
3090 }
3091
3092 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3093                                       SMU7_Discrete_DpmTable *table)
3094 {
3095         struct ci_power_info *pi = ci_get_pi(adev);
3096         struct atom_clock_dividers dividers;
3097         SMU7_Discrete_VoltageLevel voltage_level;
3098         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3099         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3100         u32 dll_cntl = pi->clock_registers.dll_cntl;
3101         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3102         int ret;
3103
3104         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3105
3106         if (pi->acpi_vddc)
3107                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3108         else
3109                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3110
3111         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3112
3113         table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3114
3115         ret = amdgpu_atombios_get_clock_dividers(adev,
3116                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3117                                                  table->ACPILevel.SclkFrequency, false, &dividers);
3118         if (ret)
3119                 return ret;
3120
3121         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3122         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3123         table->ACPILevel.DeepSleepDivId = 0;
3124
3125         spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3126         spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3127
3128         spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3129         spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3130
3131         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3132         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3133         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3134         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3135         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3136         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3137         table->ACPILevel.CcPwrDynRm = 0;
3138         table->ACPILevel.CcPwrDynRm1 = 0;
3139
3140         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3141         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3142         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3143         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3144         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3145         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3146         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3147         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3148         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3149         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3150         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3151
3152         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3153         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3154
3155         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3156                 if (pi->acpi_vddci)
3157                         table->MemoryACPILevel.MinVddci =
3158                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3159                 else
3160                         table->MemoryACPILevel.MinVddci =
3161                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3162         }
3163
3164         if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3165                 table->MemoryACPILevel.MinMvdd = 0;
3166         else
3167                 table->MemoryACPILevel.MinMvdd =
3168                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3169
3170         mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3171                 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3172         mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3173                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3174
3175         dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3176
3177         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3178         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3179         table->MemoryACPILevel.MpllAdFuncCntl =
3180                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3181         table->MemoryACPILevel.MpllDqFuncCntl =
3182                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3183         table->MemoryACPILevel.MpllFuncCntl =
3184                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3185         table->MemoryACPILevel.MpllFuncCntl_1 =
3186                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3187         table->MemoryACPILevel.MpllFuncCntl_2 =
3188                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3189         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3190         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3191
3192         table->MemoryACPILevel.EnabledForThrottle = 0;
3193         table->MemoryACPILevel.EnabledForActivity = 0;
3194         table->MemoryACPILevel.UpH = 0;
3195         table->MemoryACPILevel.DownH = 100;
3196         table->MemoryACPILevel.VoltageDownH = 0;
3197         table->MemoryACPILevel.ActivityLevel =
3198                 cpu_to_be16((u16)pi->mclk_activity_target);
3199
3200         table->MemoryACPILevel.StutterEnable = false;
3201         table->MemoryACPILevel.StrobeEnable = false;
3202         table->MemoryACPILevel.EdcReadEnable = false;
3203         table->MemoryACPILevel.EdcWriteEnable = false;
3204         table->MemoryACPILevel.RttEnable = false;
3205
3206         return 0;
3207 }
3208
3209
3210 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3211 {
3212         struct ci_power_info *pi = ci_get_pi(adev);
3213         struct ci_ulv_parm *ulv = &pi->ulv;
3214
3215         if (ulv->supported) {
3216                 if (enable)
3217                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3218                                 0 : -EINVAL;
3219                 else
3220                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3221                                 0 : -EINVAL;
3222         }
3223
3224         return 0;
3225 }
3226
3227 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3228                                  SMU7_Discrete_Ulv *state)
3229 {
3230         struct ci_power_info *pi = ci_get_pi(adev);
3231         u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3232
3233         state->CcPwrDynRm = 0;
3234         state->CcPwrDynRm1 = 0;
3235
3236         if (ulv_voltage == 0) {
3237                 pi->ulv.supported = false;
3238                 return 0;
3239         }
3240
3241         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3242                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3243                         state->VddcOffset = 0;
3244                 else
3245                         state->VddcOffset =
3246                                 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3247         } else {
3248                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3249                         state->VddcOffsetVid = 0;
3250                 else
3251                         state->VddcOffsetVid = (u8)
3252                                 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3253                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3254         }
3255         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3256
3257         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3258         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3259         state->VddcOffset = cpu_to_be16(state->VddcOffset);
3260
3261         return 0;
3262 }
3263
3264 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3265                                     u32 engine_clock,
3266                                     SMU7_Discrete_GraphicsLevel *sclk)
3267 {
3268         struct ci_power_info *pi = ci_get_pi(adev);
3269         struct atom_clock_dividers dividers;
3270         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3271         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3272         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3273         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3274         u32 reference_clock = adev->clock.spll.reference_freq;
3275         u32 reference_divider;
3276         u32 fbdiv;
3277         int ret;
3278
3279         ret = amdgpu_atombios_get_clock_dividers(adev,
3280                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3281                                                  engine_clock, false, &dividers);
3282         if (ret)
3283                 return ret;
3284
3285         reference_divider = 1 + dividers.ref_div;
3286         fbdiv = dividers.fb_div & 0x3FFFFFF;
3287
3288         spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3289         spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3290         spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3291
3292         if (pi->caps_sclk_ss_support) {
3293                 struct amdgpu_atom_ss ss;
3294                 u32 vco_freq = engine_clock * dividers.post_div;
3295
3296                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3297                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3298                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3299                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3300
3301                         cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3302                         cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3303                         cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3304
3305                         cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3306                         cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3307                 }
3308         }
3309
3310         sclk->SclkFrequency = engine_clock;
3311         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3312         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3313         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3314         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
3315         sclk->SclkDid = (u8)dividers.post_divider;
3316
3317         return 0;
3318 }
3319
3320 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3321                                             u32 engine_clock,
3322                                             u16 sclk_activity_level_t,
3323                                             SMU7_Discrete_GraphicsLevel *graphic_level)
3324 {
3325         struct ci_power_info *pi = ci_get_pi(adev);
3326         int ret;
3327
3328         ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3329         if (ret)
3330                 return ret;
3331
3332         ret = ci_get_dependency_volt_by_clk(adev,
3333                                             &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3334                                             engine_clock, &graphic_level->MinVddc);
3335         if (ret)
3336                 return ret;
3337
3338         graphic_level->SclkFrequency = engine_clock;
3339
3340         graphic_level->Flags =  0;
3341         graphic_level->MinVddcPhases = 1;
3342
3343         if (pi->vddc_phase_shed_control)
3344                 ci_populate_phase_value_based_on_sclk(adev,
3345                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3346                                                       engine_clock,
3347                                                       &graphic_level->MinVddcPhases);
3348
3349         graphic_level->ActivityLevel = sclk_activity_level_t;
3350
3351         graphic_level->CcPwrDynRm = 0;
3352         graphic_level->CcPwrDynRm1 = 0;
3353         graphic_level->EnabledForThrottle = 1;
3354         graphic_level->UpH = 0;
3355         graphic_level->DownH = 0;
3356         graphic_level->VoltageDownH = 0;
3357         graphic_level->PowerThrottle = 0;
3358
3359         if (pi->caps_sclk_ds)
3360                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(adev,
3361                                                                                    engine_clock,
3362                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
3363
3364         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3365
3366         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3367         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3368         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3369         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3370         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3371         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3372         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3373         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3374         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3375         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3376         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3377
3378         return 0;
3379 }
3380
3381 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3382 {
3383         struct ci_power_info *pi = ci_get_pi(adev);
3384         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3385         u32 level_array_address = pi->dpm_table_start +
3386                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3387         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3388                 SMU7_MAX_LEVELS_GRAPHICS;
3389         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3390         u32 i, ret;
3391
3392         memset(levels, 0, level_array_size);
3393
3394         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3395                 ret = ci_populate_single_graphic_level(adev,
3396                                                        dpm_table->sclk_table.dpm_levels[i].value,
3397                                                        (u16)pi->activity_target[i],
3398                                                        &pi->smc_state_table.GraphicsLevel[i]);
3399                 if (ret)
3400                         return ret;
3401                 if (i > 1)
3402                         pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3403                 if (i == (dpm_table->sclk_table.count - 1))
3404                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3405                                 PPSMC_DISPLAY_WATERMARK_HIGH;
3406         }
3407         pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3408
3409         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3410         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3411                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3412
3413         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3414                                    (u8 *)levels, level_array_size,
3415                                    pi->sram_end);
3416         if (ret)
3417                 return ret;
3418
3419         return 0;
3420 }
3421
3422 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3423                                  SMU7_Discrete_Ulv *ulv_level)
3424 {
3425         return ci_populate_ulv_level(adev, ulv_level);
3426 }
3427
3428 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3429 {
3430         struct ci_power_info *pi = ci_get_pi(adev);
3431         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3432         u32 level_array_address = pi->dpm_table_start +
3433                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3434         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3435                 SMU7_MAX_LEVELS_MEMORY;
3436         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3437         u32 i, ret;
3438
3439         memset(levels, 0, level_array_size);
3440
3441         for (i = 0; i < dpm_table->mclk_table.count; i++) {
3442                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3443                         return -EINVAL;
3444                 ret = ci_populate_single_memory_level(adev,
3445                                                       dpm_table->mclk_table.dpm_levels[i].value,
3446                                                       &pi->smc_state_table.MemoryLevel[i]);
3447                 if (ret)
3448                         return ret;
3449         }
3450
3451         pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3452
3453         if ((dpm_table->mclk_table.count >= 2) &&
3454             ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3455                 pi->smc_state_table.MemoryLevel[1].MinVddc =
3456                         pi->smc_state_table.MemoryLevel[0].MinVddc;
3457                 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3458                         pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3459         }
3460
3461         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3462
3463         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3464         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3465                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3466
3467         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3468                 PPSMC_DISPLAY_WATERMARK_HIGH;
3469
3470         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3471                                    (u8 *)levels, level_array_size,
3472                                    pi->sram_end);
3473         if (ret)
3474                 return ret;
3475
3476         return 0;
3477 }
3478
3479 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3480                                       struct ci_single_dpm_table* dpm_table,
3481                                       u32 count)
3482 {
3483         u32 i;
3484
3485         dpm_table->count = count;
3486         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3487                 dpm_table->dpm_levels[i].enabled = false;
3488 }
3489
3490 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3491                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
3492 {
3493         dpm_table->dpm_levels[index].value = pcie_gen;
3494         dpm_table->dpm_levels[index].param1 = pcie_lanes;
3495         dpm_table->dpm_levels[index].enabled = true;
3496 }
3497
3498 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3499 {
3500         struct ci_power_info *pi = ci_get_pi(adev);
3501
3502         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3503                 return -EINVAL;
3504
3505         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3506                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3507                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3508         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3509                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3510                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3511         }
3512
3513         ci_reset_single_dpm_table(adev,
3514                                   &pi->dpm_table.pcie_speed_table,
3515                                   SMU7_MAX_LEVELS_LINK);
3516
3517         if (adev->asic_type == CHIP_BONAIRE)
3518                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3519                                           pi->pcie_gen_powersaving.min,
3520                                           pi->pcie_lane_powersaving.max);
3521         else
3522                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3523                                           pi->pcie_gen_powersaving.min,
3524                                           pi->pcie_lane_powersaving.min);
3525         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3526                                   pi->pcie_gen_performance.min,
3527                                   pi->pcie_lane_performance.min);
3528         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3529                                   pi->pcie_gen_powersaving.min,
3530                                   pi->pcie_lane_powersaving.max);
3531         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3532                                   pi->pcie_gen_performance.min,
3533                                   pi->pcie_lane_performance.max);
3534         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3535                                   pi->pcie_gen_powersaving.max,
3536                                   pi->pcie_lane_powersaving.max);
3537         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3538                                   pi->pcie_gen_performance.max,
3539                                   pi->pcie_lane_performance.max);
3540
3541         pi->dpm_table.pcie_speed_table.count = 6;
3542
3543         return 0;
3544 }
3545
3546 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3547 {
3548         struct ci_power_info *pi = ci_get_pi(adev);
3549         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3550                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3551         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3552                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3553         struct amdgpu_cac_leakage_table *std_voltage_table =
3554                 &adev->pm.dpm.dyn_state.cac_leakage_table;
3555         u32 i;
3556
3557         if (allowed_sclk_vddc_table == NULL)
3558                 return -EINVAL;
3559         if (allowed_sclk_vddc_table->count < 1)
3560                 return -EINVAL;
3561         if (allowed_mclk_table == NULL)
3562                 return -EINVAL;
3563         if (allowed_mclk_table->count < 1)
3564                 return -EINVAL;
3565
3566         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3567
3568         ci_reset_single_dpm_table(adev,
3569                                   &pi->dpm_table.sclk_table,
3570                                   SMU7_MAX_LEVELS_GRAPHICS);
3571         ci_reset_single_dpm_table(adev,
3572                                   &pi->dpm_table.mclk_table,
3573                                   SMU7_MAX_LEVELS_MEMORY);
3574         ci_reset_single_dpm_table(adev,
3575                                   &pi->dpm_table.vddc_table,
3576                                   SMU7_MAX_LEVELS_VDDC);
3577         ci_reset_single_dpm_table(adev,
3578                                   &pi->dpm_table.vddci_table,
3579                                   SMU7_MAX_LEVELS_VDDCI);
3580         ci_reset_single_dpm_table(adev,
3581                                   &pi->dpm_table.mvdd_table,
3582                                   SMU7_MAX_LEVELS_MVDD);
3583
3584         pi->dpm_table.sclk_table.count = 0;
3585         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3586                 if ((i == 0) ||
3587                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3588                      allowed_sclk_vddc_table->entries[i].clk)) {
3589                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3590                                 allowed_sclk_vddc_table->entries[i].clk;
3591                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3592                                 (i == 0) ? true : false;
3593                         pi->dpm_table.sclk_table.count++;
3594                 }
3595         }
3596
3597         pi->dpm_table.mclk_table.count = 0;
3598         for (i = 0; i < allowed_mclk_table->count; i++) {
3599                 if ((i == 0) ||
3600                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3601                      allowed_mclk_table->entries[i].clk)) {
3602                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3603                                 allowed_mclk_table->entries[i].clk;
3604                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3605                                 (i == 0) ? true : false;
3606                         pi->dpm_table.mclk_table.count++;
3607                 }
3608         }
3609
3610         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3611                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3612                         allowed_sclk_vddc_table->entries[i].v;
3613                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3614                         std_voltage_table->entries[i].leakage;
3615                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3616         }
3617         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3618
3619         allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3620         if (allowed_mclk_table) {
3621                 for (i = 0; i < allowed_mclk_table->count; i++) {
3622                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3623                                 allowed_mclk_table->entries[i].v;
3624                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3625                 }
3626                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3627         }
3628
3629         allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3630         if (allowed_mclk_table) {
3631                 for (i = 0; i < allowed_mclk_table->count; i++) {
3632                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3633                                 allowed_mclk_table->entries[i].v;
3634                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3635                 }
3636                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3637         }
3638
3639         ci_setup_default_pcie_tables(adev);
3640
3641         return 0;
3642 }
3643
3644 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3645                               u32 value, u32 *boot_level)
3646 {
3647         u32 i;
3648         int ret = -EINVAL;
3649
3650         for(i = 0; i < table->count; i++) {
3651                 if (value == table->dpm_levels[i].value) {
3652                         *boot_level = i;
3653                         ret = 0;
3654                 }
3655         }
3656
3657         return ret;
3658 }
3659
3660 static int ci_init_smc_table(struct amdgpu_device *adev)
3661 {
3662         struct ci_power_info *pi = ci_get_pi(adev);
3663         struct ci_ulv_parm *ulv = &pi->ulv;
3664         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3665         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3666         int ret;
3667
3668         ret = ci_setup_default_dpm_tables(adev);
3669         if (ret)
3670                 return ret;
3671
3672         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3673                 ci_populate_smc_voltage_tables(adev, table);
3674
3675         ci_init_fps_limits(adev);
3676
3677         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3678                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3679
3680         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3681                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3682
3683         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3684                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3685
3686         if (ulv->supported) {
3687                 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3688                 if (ret)
3689                         return ret;
3690                 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3691         }
3692
3693         ret = ci_populate_all_graphic_levels(adev);
3694         if (ret)
3695                 return ret;
3696
3697         ret = ci_populate_all_memory_levels(adev);
3698         if (ret)
3699                 return ret;
3700
3701         ci_populate_smc_link_level(adev, table);
3702
3703         ret = ci_populate_smc_acpi_level(adev, table);
3704         if (ret)
3705                 return ret;
3706
3707         ret = ci_populate_smc_vce_level(adev, table);
3708         if (ret)
3709                 return ret;
3710
3711         ret = ci_populate_smc_acp_level(adev, table);
3712         if (ret)
3713                 return ret;
3714
3715         ret = ci_populate_smc_samu_level(adev, table);
3716         if (ret)
3717                 return ret;
3718
3719         ret = ci_do_program_memory_timing_parameters(adev);
3720         if (ret)
3721                 return ret;
3722
3723         ret = ci_populate_smc_uvd_level(adev, table);
3724         if (ret)
3725                 return ret;
3726
3727         table->UvdBootLevel  = 0;
3728         table->VceBootLevel  = 0;
3729         table->AcpBootLevel  = 0;
3730         table->SamuBootLevel  = 0;
3731         table->GraphicsBootLevel  = 0;
3732         table->MemoryBootLevel  = 0;
3733
3734         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3735                                  pi->vbios_boot_state.sclk_bootup_value,
3736                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3737
3738         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3739                                  pi->vbios_boot_state.mclk_bootup_value,
3740                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3741
3742         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3743         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3744         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3745
3746         ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3747
3748         ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3749         if (ret)
3750                 return ret;
3751
3752         table->UVDInterval = 1;
3753         table->VCEInterval = 1;
3754         table->ACPInterval = 1;
3755         table->SAMUInterval = 1;
3756         table->GraphicsVoltageChangeEnable = 1;
3757         table->GraphicsThermThrottleEnable = 1;
3758         table->GraphicsInterval = 1;
3759         table->VoltageInterval = 1;
3760         table->ThermalInterval = 1;
3761         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3762                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3763         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3764                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3765         table->MemoryVoltageChangeEnable = 1;
3766         table->MemoryInterval = 1;
3767         table->VoltageResponseTime = 0;
3768         table->VddcVddciDelta = 4000;
3769         table->PhaseResponseTime = 0;
3770         table->MemoryThermThrottleEnable = 1;
3771         table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3772         table->PCIeGenInterval = 1;
3773         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3774                 table->SVI2Enable  = 1;
3775         else
3776                 table->SVI2Enable  = 0;
3777
3778         table->ThermGpio = 17;
3779         table->SclkStepSize = 0x4000;
3780
3781         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3782         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3783         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3784         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3785         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3786         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3787         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3788         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3789         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3790         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3791         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3792         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3793         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3794         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3795
3796         ret = amdgpu_ci_copy_bytes_to_smc(adev,
3797                                    pi->dpm_table_start +
3798                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3799                                    (u8 *)&table->SystemFlags,
3800                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3801                                    pi->sram_end);
3802         if (ret)
3803                 return ret;
3804
3805         return 0;
3806 }
3807
3808 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3809                                       struct ci_single_dpm_table *dpm_table,
3810                                       u32 low_limit, u32 high_limit)
3811 {
3812         u32 i;
3813
3814         for (i = 0; i < dpm_table->count; i++) {
3815                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3816                     (dpm_table->dpm_levels[i].value > high_limit))
3817                         dpm_table->dpm_levels[i].enabled = false;
3818                 else
3819                         dpm_table->dpm_levels[i].enabled = true;
3820         }
3821 }
3822
3823 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3824                                     u32 speed_low, u32 lanes_low,
3825                                     u32 speed_high, u32 lanes_high)
3826 {
3827         struct ci_power_info *pi = ci_get_pi(adev);
3828         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3829         u32 i, j;
3830
3831         for (i = 0; i < pcie_table->count; i++) {
3832                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3833                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3834                     (pcie_table->dpm_levels[i].value > speed_high) ||
3835                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3836                         pcie_table->dpm_levels[i].enabled = false;
3837                 else
3838                         pcie_table->dpm_levels[i].enabled = true;
3839         }
3840
3841         for (i = 0; i < pcie_table->count; i++) {
3842                 if (pcie_table->dpm_levels[i].enabled) {
3843                         for (j = i + 1; j < pcie_table->count; j++) {
3844                                 if (pcie_table->dpm_levels[j].enabled) {
3845                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3846                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3847                                                 pcie_table->dpm_levels[j].enabled = false;
3848                                 }
3849                         }
3850                 }
3851         }
3852 }
3853
3854 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3855                               struct amdgpu_ps *amdgpu_state)
3856 {
3857         struct ci_ps *state = ci_get_ps(amdgpu_state);
3858         struct ci_power_info *pi = ci_get_pi(adev);
3859         u32 high_limit_count;
3860
3861         if (state->performance_level_count < 1)
3862                 return -EINVAL;
3863
3864         if (state->performance_level_count == 1)
3865                 high_limit_count = 0;
3866         else
3867                 high_limit_count = 1;
3868
3869         ci_trim_single_dpm_states(adev,
3870                                   &pi->dpm_table.sclk_table,
3871                                   state->performance_levels[0].sclk,
3872                                   state->performance_levels[high_limit_count].sclk);
3873
3874         ci_trim_single_dpm_states(adev,
3875                                   &pi->dpm_table.mclk_table,
3876                                   state->performance_levels[0].mclk,
3877                                   state->performance_levels[high_limit_count].mclk);
3878
3879         ci_trim_pcie_dpm_states(adev,
3880                                 state->performance_levels[0].pcie_gen,
3881                                 state->performance_levels[0].pcie_lane,
3882                                 state->performance_levels[high_limit_count].pcie_gen,
3883                                 state->performance_levels[high_limit_count].pcie_lane);
3884
3885         return 0;
3886 }
3887
3888 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3889 {
3890         struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3891                 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3892         struct amdgpu_clock_voltage_dependency_table *vddc_table =
3893                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3894         u32 requested_voltage = 0;
3895         u32 i;
3896
3897         if (disp_voltage_table == NULL)
3898                 return -EINVAL;
3899         if (!disp_voltage_table->count)
3900                 return -EINVAL;
3901
3902         for (i = 0; i < disp_voltage_table->count; i++) {
3903                 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3904                         requested_voltage = disp_voltage_table->entries[i].v;
3905         }
3906
3907         for (i = 0; i < vddc_table->count; i++) {
3908                 if (requested_voltage <= vddc_table->entries[i].v) {
3909                         requested_voltage = vddc_table->entries[i].v;
3910                         return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3911                                                                   PPSMC_MSG_VddC_Request,
3912                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3913                                 0 : -EINVAL;
3914                 }
3915         }
3916
3917         return -EINVAL;
3918 }
3919
3920 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3921 {
3922         struct ci_power_info *pi = ci_get_pi(adev);
3923         PPSMC_Result result;
3924
3925         ci_apply_disp_minimum_voltage_request(adev);
3926
3927         if (!pi->sclk_dpm_key_disabled) {
3928                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3929                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3930                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3931                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3932                         if (result != PPSMC_Result_OK)
3933                                 return -EINVAL;
3934                 }
3935         }
3936
3937         if (!pi->mclk_dpm_key_disabled) {
3938                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3939                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3940                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3941                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3942                         if (result != PPSMC_Result_OK)
3943                                 return -EINVAL;
3944                 }
3945         }
3946
3947 #if 0
3948         if (!pi->pcie_dpm_key_disabled) {
3949                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3950                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3951                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3952                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3953                         if (result != PPSMC_Result_OK)
3954                                 return -EINVAL;
3955                 }
3956         }
3957 #endif
3958
3959         return 0;
3960 }
3961
3962 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
3963                                                    struct amdgpu_ps *amdgpu_state)
3964 {
3965         struct ci_power_info *pi = ci_get_pi(adev);
3966         struct ci_ps *state = ci_get_ps(amdgpu_state);
3967         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3968         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3969         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3970         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3971         u32 i;
3972
3973         pi->need_update_smu7_dpm_table = 0;
3974
3975         for (i = 0; i < sclk_table->count; i++) {
3976                 if (sclk == sclk_table->dpm_levels[i].value)
3977                         break;
3978         }
3979
3980         if (i >= sclk_table->count) {
3981                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3982         } else {
3983                 /* XXX check display min clock requirements */
3984                 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3985                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3986         }
3987
3988         for (i = 0; i < mclk_table->count; i++) {
3989                 if (mclk == mclk_table->dpm_levels[i].value)
3990                         break;
3991         }
3992
3993         if (i >= mclk_table->count)
3994                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3995
3996         if (adev->pm.dpm.current_active_crtc_count !=
3997             adev->pm.dpm.new_active_crtc_count)
3998                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3999 }
4000
4001 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4002                                                        struct amdgpu_ps *amdgpu_state)
4003 {
4004         struct ci_power_info *pi = ci_get_pi(adev);
4005         struct ci_ps *state = ci_get_ps(amdgpu_state);
4006         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4007         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4008         struct ci_dpm_table *dpm_table = &pi->dpm_table;
4009         int ret;
4010
4011         if (!pi->need_update_smu7_dpm_table)
4012                 return 0;
4013
4014         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4015                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4016
4017         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4018                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4019
4020         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4021                 ret = ci_populate_all_graphic_levels(adev);
4022                 if (ret)
4023                         return ret;
4024         }
4025
4026         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4027                 ret = ci_populate_all_memory_levels(adev);
4028                 if (ret)
4029                         return ret;
4030         }
4031
4032         return 0;
4033 }
4034
4035 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4036 {
4037         struct ci_power_info *pi = ci_get_pi(adev);
4038         const struct amdgpu_clock_and_voltage_limits *max_limits;
4039         int i;
4040
4041         if (adev->pm.dpm.ac_power)
4042                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4043         else
4044                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4045
4046         if (enable) {
4047                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4048
4049                 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4050                         if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4051                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4052
4053                                 if (!pi->caps_uvd_dpm)
4054                                         break;
4055                         }
4056                 }
4057
4058                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4059                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
4060                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4061
4062                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4063                         pi->uvd_enabled = true;
4064                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4065                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4066                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4067                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4068                 }
4069         } else {
4070                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4071                         pi->uvd_enabled = false;
4072                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4073                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4074                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4075                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4076                 }
4077         }
4078
4079         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4080                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4081                 0 : -EINVAL;
4082 }
4083
4084 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4085 {
4086         struct ci_power_info *pi = ci_get_pi(adev);
4087         const struct amdgpu_clock_and_voltage_limits *max_limits;
4088         int i;
4089
4090         if (adev->pm.dpm.ac_power)
4091                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4092         else
4093                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4094
4095         if (enable) {
4096                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4097                 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4098                         if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4099                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4100
4101                                 if (!pi->caps_vce_dpm)
4102                                         break;
4103                         }
4104                 }
4105
4106                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4107                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
4108                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4109         }
4110
4111         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4112                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4113                 0 : -EINVAL;
4114 }
4115
4116 #if 0
4117 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4118 {
4119         struct ci_power_info *pi = ci_get_pi(adev);
4120         const struct amdgpu_clock_and_voltage_limits *max_limits;
4121         int i;
4122
4123         if (adev->pm.dpm.ac_power)
4124                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4125         else
4126                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4127
4128         if (enable) {
4129                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4130                 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4131                         if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4132                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4133
4134                                 if (!pi->caps_samu_dpm)
4135                                         break;
4136                         }
4137                 }
4138
4139                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4140                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
4141                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4142         }
4143         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4144                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4145                 0 : -EINVAL;
4146 }
4147
4148 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4149 {
4150         struct ci_power_info *pi = ci_get_pi(adev);
4151         const struct amdgpu_clock_and_voltage_limits *max_limits;
4152         int i;
4153
4154         if (adev->pm.dpm.ac_power)
4155                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4156         else
4157                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4158
4159         if (enable) {
4160                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4161                 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4162                         if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4163                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4164
4165                                 if (!pi->caps_acp_dpm)
4166                                         break;
4167                         }
4168                 }
4169
4170                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4171                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
4172                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4173         }
4174
4175         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4176                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4177                 0 : -EINVAL;
4178 }
4179 #endif
4180
4181 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4182 {
4183         struct ci_power_info *pi = ci_get_pi(adev);
4184         u32 tmp;
4185
4186         if (!gate) {
4187                 if (pi->caps_uvd_dpm ||
4188                     (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4189                         pi->smc_state_table.UvdBootLevel = 0;
4190                 else
4191                         pi->smc_state_table.UvdBootLevel =
4192                                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4193
4194                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4195                 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4196                 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4197                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4198         }
4199
4200         return ci_enable_uvd_dpm(adev, !gate);
4201 }
4202
4203 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4204 {
4205         u8 i;
4206         u32 min_evclk = 30000; /* ??? */
4207         struct amdgpu_vce_clock_voltage_dependency_table *table =
4208                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4209
4210         for (i = 0; i < table->count; i++) {
4211                 if (table->entries[i].evclk >= min_evclk)
4212                         return i;
4213         }
4214
4215         return table->count - 1;
4216 }
4217
4218 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4219                              struct amdgpu_ps *amdgpu_new_state,
4220                              struct amdgpu_ps *amdgpu_current_state)
4221 {
4222         struct ci_power_info *pi = ci_get_pi(adev);
4223         int ret = 0;
4224         u32 tmp;
4225
4226         if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4227                 if (amdgpu_new_state->evclk) {
4228                         /* turn the clocks on when encoding */
4229                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4230                                                             AMD_CG_STATE_UNGATE);
4231                         if (ret)
4232                                 return ret;
4233
4234                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4235                         tmp = RREG32_SMC(ixDPM_TABLE_475);
4236                         tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4237                         tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4238                         WREG32_SMC(ixDPM_TABLE_475, tmp);
4239
4240                         ret = ci_enable_vce_dpm(adev, true);
4241                 } else {
4242                         /* turn the clocks off when not encoding */
4243                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4244                                                             AMD_CG_STATE_GATE);
4245                         if (ret)
4246                                 return ret;
4247
4248                         ret = ci_enable_vce_dpm(adev, false);
4249                 }
4250         }
4251         return ret;
4252 }
4253
4254 #if 0
4255 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4256 {
4257         return ci_enable_samu_dpm(adev, gate);
4258 }
4259
4260 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4261 {
4262         struct ci_power_info *pi = ci_get_pi(adev);
4263         u32 tmp;
4264
4265         if (!gate) {
4266                 pi->smc_state_table.AcpBootLevel = 0;
4267
4268                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4269                 tmp &= ~AcpBootLevel_MASK;
4270                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4271                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4272         }
4273
4274         return ci_enable_acp_dpm(adev, !gate);
4275 }
4276 #endif
4277
4278 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4279                                              struct amdgpu_ps *amdgpu_state)
4280 {
4281         struct ci_power_info *pi = ci_get_pi(adev);
4282         int ret;
4283
4284         ret = ci_trim_dpm_states(adev, amdgpu_state);
4285         if (ret)
4286                 return ret;
4287
4288         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4289                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4290         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4291                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4292         pi->last_mclk_dpm_enable_mask =
4293                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4294         if (pi->uvd_enabled) {
4295                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4296                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4297         }
4298         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4299                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4300
4301         return 0;
4302 }
4303
4304 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4305                                        u32 level_mask)
4306 {
4307         u32 level = 0;
4308
4309         while ((level_mask & (1 << level)) == 0)
4310                 level++;
4311
4312         return level;
4313 }
4314
4315
4316 static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4317                                           enum amdgpu_dpm_forced_level level)
4318 {
4319         struct ci_power_info *pi = ci_get_pi(adev);
4320         u32 tmp, levels, i;
4321         int ret;
4322
4323         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
4324                 if ((!pi->pcie_dpm_key_disabled) &&
4325                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4326                         levels = 0;
4327                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4328                         while (tmp >>= 1)
4329                                 levels++;
4330                         if (levels) {
4331                                 ret = ci_dpm_force_state_pcie(adev, level);
4332                                 if (ret)
4333                                         return ret;
4334                                 for (i = 0; i < adev->usec_timeout; i++) {
4335                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4336                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4337                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4338                                         if (tmp == levels)
4339                                                 break;
4340                                         udelay(1);
4341                                 }
4342                         }
4343                 }
4344                 if ((!pi->sclk_dpm_key_disabled) &&
4345                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4346                         levels = 0;
4347                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4348                         while (tmp >>= 1)
4349                                 levels++;
4350                         if (levels) {
4351                                 ret = ci_dpm_force_state_sclk(adev, levels);
4352                                 if (ret)
4353                                         return ret;
4354                                 for (i = 0; i < adev->usec_timeout; i++) {
4355                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4356                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4357                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4358                                         if (tmp == levels)
4359                                                 break;
4360                                         udelay(1);
4361                                 }
4362                         }
4363                 }
4364                 if ((!pi->mclk_dpm_key_disabled) &&
4365                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4366                         levels = 0;
4367                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4368                         while (tmp >>= 1)
4369                                 levels++;
4370                         if (levels) {
4371                                 ret = ci_dpm_force_state_mclk(adev, levels);
4372                                 if (ret)
4373                                         return ret;
4374                                 for (i = 0; i < adev->usec_timeout; i++) {
4375                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4376                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4377                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4378                                         if (tmp == levels)
4379                                                 break;
4380                                         udelay(1);
4381                                 }
4382                         }
4383                 }
4384         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
4385                 if ((!pi->sclk_dpm_key_disabled) &&
4386                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4387                         levels = ci_get_lowest_enabled_level(adev,
4388                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4389                         ret = ci_dpm_force_state_sclk(adev, levels);
4390                         if (ret)
4391                                 return ret;
4392                         for (i = 0; i < adev->usec_timeout; i++) {
4393                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4394                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4395                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4396                                 if (tmp == levels)
4397                                         break;
4398                                 udelay(1);
4399                         }
4400                 }
4401                 if ((!pi->mclk_dpm_key_disabled) &&
4402                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4403                         levels = ci_get_lowest_enabled_level(adev,
4404                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4405                         ret = ci_dpm_force_state_mclk(adev, levels);
4406                         if (ret)
4407                                 return ret;
4408                         for (i = 0; i < adev->usec_timeout; i++) {
4409                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4410                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4411                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4412                                 if (tmp == levels)
4413                                         break;
4414                                 udelay(1);
4415                         }
4416                 }
4417                 if ((!pi->pcie_dpm_key_disabled) &&
4418                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4419                         levels = ci_get_lowest_enabled_level(adev,
4420                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4421                         ret = ci_dpm_force_state_pcie(adev, levels);
4422                         if (ret)
4423                                 return ret;
4424                         for (i = 0; i < adev->usec_timeout; i++) {
4425                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4426                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4427                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4428                                 if (tmp == levels)
4429                                         break;
4430                                 udelay(1);
4431                         }
4432                 }
4433         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
4434                 if (!pi->pcie_dpm_key_disabled) {
4435                         PPSMC_Result smc_result;
4436
4437                         smc_result = amdgpu_ci_send_msg_to_smc(adev,
4438                                                                PPSMC_MSG_PCIeDPM_UnForceLevel);
4439                         if (smc_result != PPSMC_Result_OK)
4440                                 return -EINVAL;
4441                 }
4442                 ret = ci_upload_dpm_level_enable_mask(adev);
4443                 if (ret)
4444                         return ret;
4445         }
4446
4447         adev->pm.dpm.forced_level = level;
4448
4449         return 0;
4450 }
4451
4452 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4453                                        struct ci_mc_reg_table *table)
4454 {
4455         u8 i, j, k;
4456         u32 temp_reg;
4457
4458         for (i = 0, j = table->last; i < table->last; i++) {
4459                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4460                         return -EINVAL;
4461                 switch(table->mc_reg_address[i].s1) {
4462                 case mmMC_SEQ_MISC1:
4463                         temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4464                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4465                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4466                         for (k = 0; k < table->num_entries; k++) {
4467                                 table->mc_reg_table_entry[k].mc_data[j] =
4468                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4469                         }
4470                         j++;
4471                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4472                                 return -EINVAL;
4473
4474                         temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4475                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4476                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4477                         for (k = 0; k < table->num_entries; k++) {
4478                                 table->mc_reg_table_entry[k].mc_data[j] =
4479                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4480                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4481                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4482                         }
4483                         j++;
4484                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4485                                 return -EINVAL;
4486
4487                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4488                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4489                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4490                                 for (k = 0; k < table->num_entries; k++) {
4491                                         table->mc_reg_table_entry[k].mc_data[j] =
4492                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4493                                 }
4494                                 j++;
4495                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4496                                         return -EINVAL;
4497                         }
4498                         break;
4499                 case mmMC_SEQ_RESERVE_M:
4500                         temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4501                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4502                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4503                         for (k = 0; k < table->num_entries; k++) {
4504                                 table->mc_reg_table_entry[k].mc_data[j] =
4505                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4506                         }
4507                         j++;
4508                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4509                                 return -EINVAL;
4510                         break;
4511                 default:
4512                         break;
4513                 }
4514
4515         }
4516
4517         table->last = j;
4518
4519         return 0;
4520 }
4521
4522 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4523 {
4524         bool result = true;
4525
4526         switch(in_reg) {
4527         case mmMC_SEQ_RAS_TIMING:
4528                 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4529                 break;
4530         case mmMC_SEQ_DLL_STBY:
4531                 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4532                 break;
4533         case mmMC_SEQ_G5PDX_CMD0:
4534                 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4535                 break;
4536         case mmMC_SEQ_G5PDX_CMD1:
4537                 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4538                 break;
4539         case mmMC_SEQ_G5PDX_CTRL:
4540                 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4541                 break;
4542         case mmMC_SEQ_CAS_TIMING:
4543                 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4544             break;
4545         case mmMC_SEQ_MISC_TIMING:
4546                 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4547                 break;
4548         case mmMC_SEQ_MISC_TIMING2:
4549                 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4550                 break;
4551         case mmMC_SEQ_PMG_DVS_CMD:
4552                 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4553                 break;
4554         case mmMC_SEQ_PMG_DVS_CTL:
4555                 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4556                 break;
4557         case mmMC_SEQ_RD_CTL_D0:
4558                 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4559                 break;
4560         case mmMC_SEQ_RD_CTL_D1:
4561                 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4562                 break;
4563         case mmMC_SEQ_WR_CTL_D0:
4564                 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4565                 break;
4566         case mmMC_SEQ_WR_CTL_D1:
4567                 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4568                 break;
4569         case mmMC_PMG_CMD_EMRS:
4570                 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4571                 break;
4572         case mmMC_PMG_CMD_MRS:
4573                 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4574                 break;
4575         case mmMC_PMG_CMD_MRS1:
4576                 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4577                 break;
4578         case mmMC_SEQ_PMG_TIMING:
4579                 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4580                 break;
4581         case mmMC_PMG_CMD_MRS2:
4582                 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4583                 break;
4584         case mmMC_SEQ_WR_CTL_2:
4585                 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4586                 break;
4587         default:
4588                 result = false;
4589                 break;
4590         }
4591
4592         return result;
4593 }
4594
4595 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4596 {
4597         u8 i, j;
4598
4599         for (i = 0; i < table->last; i++) {
4600                 for (j = 1; j < table->num_entries; j++) {
4601                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4602                             table->mc_reg_table_entry[j].mc_data[i]) {
4603                                 table->valid_flag |= 1 << i;
4604                                 break;
4605                         }
4606                 }
4607         }
4608 }
4609
4610 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4611 {
4612         u32 i;
4613         u16 address;
4614
4615         for (i = 0; i < table->last; i++) {
4616                 table->mc_reg_address[i].s0 =
4617                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4618                         address : table->mc_reg_address[i].s1;
4619         }
4620 }
4621
4622 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4623                                       struct ci_mc_reg_table *ci_table)
4624 {
4625         u8 i, j;
4626
4627         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4628                 return -EINVAL;
4629         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4630                 return -EINVAL;
4631
4632         for (i = 0; i < table->last; i++)
4633                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4634
4635         ci_table->last = table->last;
4636
4637         for (i = 0; i < table->num_entries; i++) {
4638                 ci_table->mc_reg_table_entry[i].mclk_max =
4639                         table->mc_reg_table_entry[i].mclk_max;
4640                 for (j = 0; j < table->last; j++)
4641                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4642                                 table->mc_reg_table_entry[i].mc_data[j];
4643         }
4644         ci_table->num_entries = table->num_entries;
4645
4646         return 0;
4647 }
4648
4649 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4650                                        struct ci_mc_reg_table *table)
4651 {
4652         u8 i, k;
4653         u32 tmp;
4654         bool patch;
4655
4656         tmp = RREG32(mmMC_SEQ_MISC0);
4657         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4658
4659         if (patch &&
4660             ((adev->pdev->device == 0x67B0) ||
4661              (adev->pdev->device == 0x67B1))) {
4662                 for (i = 0; i < table->last; i++) {
4663                         if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4664                                 return -EINVAL;
4665                         switch (table->mc_reg_address[i].s1) {
4666                         case mmMC_SEQ_MISC1:
4667                                 for (k = 0; k < table->num_entries; k++) {
4668                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4669                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4670                                                 table->mc_reg_table_entry[k].mc_data[i] =
4671                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4672                                                         0x00000007;
4673                                 }
4674                                 break;
4675                         case mmMC_SEQ_WR_CTL_D0:
4676                                 for (k = 0; k < table->num_entries; k++) {
4677                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4678                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4679                                                 table->mc_reg_table_entry[k].mc_data[i] =
4680                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4681                                                         0x0000D0DD;
4682                                 }
4683                                 break;
4684                         case mmMC_SEQ_WR_CTL_D1:
4685                                 for (k = 0; k < table->num_entries; k++) {
4686                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4687                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4688                                                 table->mc_reg_table_entry[k].mc_data[i] =
4689                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4690                                                         0x0000D0DD;
4691                                 }
4692                                 break;
4693                         case mmMC_SEQ_WR_CTL_2:
4694                                 for (k = 0; k < table->num_entries; k++) {
4695                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4696                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4697                                                 table->mc_reg_table_entry[k].mc_data[i] = 0;
4698                                 }
4699                                 break;
4700                         case mmMC_SEQ_CAS_TIMING:
4701                                 for (k = 0; k < table->num_entries; k++) {
4702                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4703                                                 table->mc_reg_table_entry[k].mc_data[i] =
4704                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4705                                                         0x000C0140;
4706                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4707                                                 table->mc_reg_table_entry[k].mc_data[i] =
4708                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4709                                                         0x000C0150;
4710                                 }
4711                                 break;
4712                         case mmMC_SEQ_MISC_TIMING:
4713                                 for (k = 0; k < table->num_entries; k++) {
4714                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4715                                                 table->mc_reg_table_entry[k].mc_data[i] =
4716                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4717                                                         0x00000030;
4718                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4719                                                 table->mc_reg_table_entry[k].mc_data[i] =
4720                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4721                                                         0x00000035;
4722                                 }
4723                                 break;
4724                         default:
4725                                 break;
4726                         }
4727                 }
4728
4729                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4730                 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4731                 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4732                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4733                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4734         }
4735
4736         return 0;
4737 }
4738
4739 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4740 {
4741         struct ci_power_info *pi = ci_get_pi(adev);
4742         struct atom_mc_reg_table *table;
4743         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4744         u8 module_index = ci_get_memory_module_index(adev);
4745         int ret;
4746
4747         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4748         if (!table)
4749                 return -ENOMEM;
4750
4751         WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4752         WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4753         WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4754         WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4755         WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4756         WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4757         WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4758         WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4759         WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4760         WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4761         WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4762         WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4763         WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4764         WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4765         WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4766         WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4767         WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4768         WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4769         WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4770         WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4771
4772         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4773         if (ret)
4774                 goto init_mc_done;
4775
4776         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4777         if (ret)
4778                 goto init_mc_done;
4779
4780         ci_set_s0_mc_reg_index(ci_table);
4781
4782         ret = ci_register_patching_mc_seq(adev, ci_table);
4783         if (ret)
4784                 goto init_mc_done;
4785
4786         ret = ci_set_mc_special_registers(adev, ci_table);
4787         if (ret)
4788                 goto init_mc_done;
4789
4790         ci_set_valid_flag(ci_table);
4791
4792 init_mc_done:
4793         kfree(table);
4794
4795         return ret;
4796 }
4797
4798 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4799                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4800 {
4801         struct ci_power_info *pi = ci_get_pi(adev);
4802         u32 i, j;
4803
4804         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4805                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4806                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4807                                 return -EINVAL;
4808                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4809                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4810                         i++;
4811                 }
4812         }
4813
4814         mc_reg_table->last = (u8)i;
4815
4816         return 0;
4817 }
4818
4819 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4820                                     SMU7_Discrete_MCRegisterSet *data,
4821                                     u32 num_entries, u32 valid_flag)
4822 {
4823         u32 i, j;
4824
4825         for (i = 0, j = 0; j < num_entries; j++) {
4826                 if (valid_flag & (1 << j)) {
4827                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4828                         i++;
4829                 }
4830         }
4831 }
4832
4833 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4834                                                  const u32 memory_clock,
4835                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4836 {
4837         struct ci_power_info *pi = ci_get_pi(adev);
4838         u32 i = 0;
4839
4840         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4841                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4842                         break;
4843         }
4844
4845         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4846                 --i;
4847
4848         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4849                                 mc_reg_table_data, pi->mc_reg_table.last,
4850                                 pi->mc_reg_table.valid_flag);
4851 }
4852
4853 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4854                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4855 {
4856         struct ci_power_info *pi = ci_get_pi(adev);
4857         u32 i;
4858
4859         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4860                 ci_convert_mc_reg_table_entry_to_smc(adev,
4861                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4862                                                      &mc_reg_table->data[i]);
4863 }
4864
4865 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4866 {
4867         struct ci_power_info *pi = ci_get_pi(adev);
4868         int ret;
4869
4870         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4871
4872         ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4873         if (ret)
4874                 return ret;
4875         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4876
4877         return amdgpu_ci_copy_bytes_to_smc(adev,
4878                                     pi->mc_reg_table_start,
4879                                     (u8 *)&pi->smc_mc_reg_table,
4880                                     sizeof(SMU7_Discrete_MCRegisters),
4881                                     pi->sram_end);
4882 }
4883
4884 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4885 {
4886         struct ci_power_info *pi = ci_get_pi(adev);
4887
4888         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4889                 return 0;
4890
4891         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4892
4893         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4894
4895         return amdgpu_ci_copy_bytes_to_smc(adev,
4896                                     pi->mc_reg_table_start +
4897                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4898                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4899                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4900                                     pi->dpm_table.mclk_table.count,
4901                                     pi->sram_end);
4902 }
4903
4904 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4905 {
4906         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4907
4908         tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4909         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4910 }
4911
4912 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4913                                                       struct amdgpu_ps *amdgpu_state)
4914 {
4915         struct ci_ps *state = ci_get_ps(amdgpu_state);
4916         int i;
4917         u16 pcie_speed, max_speed = 0;
4918
4919         for (i = 0; i < state->performance_level_count; i++) {
4920                 pcie_speed = state->performance_levels[i].pcie_gen;
4921                 if (max_speed < pcie_speed)
4922                         max_speed = pcie_speed;
4923         }
4924
4925         return max_speed;
4926 }
4927
4928 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4929 {
4930         u32 speed_cntl = 0;
4931
4932         speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4933                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4934         speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4935
4936         return (u16)speed_cntl;
4937 }
4938
4939 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
4940 {
4941         u32 link_width = 0;
4942
4943         link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
4944                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
4945         link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4946
4947         switch (link_width) {
4948         case 1:
4949                 return 1;
4950         case 2:
4951                 return 2;
4952         case 3:
4953                 return 4;
4954         case 4:
4955                 return 8;
4956         case 0:
4957         case 6:
4958         default:
4959                 return 16;
4960         }
4961 }
4962
4963 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
4964                                                              struct amdgpu_ps *amdgpu_new_state,
4965                                                              struct amdgpu_ps *amdgpu_current_state)
4966 {
4967         struct ci_power_info *pi = ci_get_pi(adev);
4968         enum amdgpu_pcie_gen target_link_speed =
4969                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
4970         enum amdgpu_pcie_gen current_link_speed;
4971
4972         if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
4973                 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
4974         else
4975                 current_link_speed = pi->force_pcie_gen;
4976
4977         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
4978         pi->pspp_notify_required = false;
4979         if (target_link_speed > current_link_speed) {
4980                 switch (target_link_speed) {
4981 #ifdef CONFIG_ACPI
4982                 case AMDGPU_PCIE_GEN3:
4983                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4984                                 break;
4985                         pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
4986                         if (current_link_speed == AMDGPU_PCIE_GEN2)
4987                                 break;
4988                 case AMDGPU_PCIE_GEN2:
4989                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4990                                 break;
4991 #endif
4992                 default:
4993                         pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
4994                         break;
4995                 }
4996         } else {
4997                 if (target_link_speed < current_link_speed)
4998                         pi->pspp_notify_required = true;
4999         }
5000 }
5001
5002 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5003                                                            struct amdgpu_ps *amdgpu_new_state,
5004                                                            struct amdgpu_ps *amdgpu_current_state)
5005 {
5006         struct ci_power_info *pi = ci_get_pi(adev);
5007         enum amdgpu_pcie_gen target_link_speed =
5008                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5009         u8 request;
5010
5011         if (pi->pspp_notify_required) {
5012                 if (target_link_speed == AMDGPU_PCIE_GEN3)
5013                         request = PCIE_PERF_REQ_PECI_GEN3;
5014                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5015                         request = PCIE_PERF_REQ_PECI_GEN2;
5016                 else
5017                         request = PCIE_PERF_REQ_PECI_GEN1;
5018
5019                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5020                     (ci_get_current_pcie_speed(adev) > 0))
5021                         return;
5022
5023 #ifdef CONFIG_ACPI
5024                 amdgpu_acpi_pcie_performance_request(adev, request, false);
5025 #endif
5026         }
5027 }
5028
5029 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5030 {
5031         struct ci_power_info *pi = ci_get_pi(adev);
5032         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5033                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5034         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5035                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5036         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5037                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5038
5039         if (allowed_sclk_vddc_table == NULL)
5040                 return -EINVAL;
5041         if (allowed_sclk_vddc_table->count < 1)
5042                 return -EINVAL;
5043         if (allowed_mclk_vddc_table == NULL)
5044                 return -EINVAL;
5045         if (allowed_mclk_vddc_table->count < 1)
5046                 return -EINVAL;
5047         if (allowed_mclk_vddci_table == NULL)
5048                 return -EINVAL;
5049         if (allowed_mclk_vddci_table->count < 1)
5050                 return -EINVAL;
5051
5052         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5053         pi->max_vddc_in_pp_table =
5054                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5055
5056         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5057         pi->max_vddci_in_pp_table =
5058                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5059
5060         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5061                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5062         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5063                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5064         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5065                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5066         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5067                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5068
5069         return 0;
5070 }
5071
5072 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5073 {
5074         struct ci_power_info *pi = ci_get_pi(adev);
5075         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5076         u32 leakage_index;
5077
5078         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5079                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5080                         *vddc = leakage_table->actual_voltage[leakage_index];
5081                         break;
5082                 }
5083         }
5084 }
5085
5086 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5087 {
5088         struct ci_power_info *pi = ci_get_pi(adev);
5089         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5090         u32 leakage_index;
5091
5092         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5093                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5094                         *vddci = leakage_table->actual_voltage[leakage_index];
5095                         break;
5096                 }
5097         }
5098 }
5099
5100 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5101                                                                       struct amdgpu_clock_voltage_dependency_table *table)
5102 {
5103         u32 i;
5104
5105         if (table) {
5106                 for (i = 0; i < table->count; i++)
5107                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5108         }
5109 }
5110
5111 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5112                                                                        struct amdgpu_clock_voltage_dependency_table *table)
5113 {
5114         u32 i;
5115
5116         if (table) {
5117                 for (i = 0; i < table->count; i++)
5118                         ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5119         }
5120 }
5121
5122 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5123                                                                           struct amdgpu_vce_clock_voltage_dependency_table *table)
5124 {
5125         u32 i;
5126
5127         if (table) {
5128                 for (i = 0; i < table->count; i++)
5129                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5130         }
5131 }
5132
5133 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5134                                                                           struct amdgpu_uvd_clock_voltage_dependency_table *table)
5135 {
5136         u32 i;
5137
5138         if (table) {
5139                 for (i = 0; i < table->count; i++)
5140                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5141         }
5142 }
5143
5144 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5145                                                                    struct amdgpu_phase_shedding_limits_table *table)
5146 {
5147         u32 i;
5148
5149         if (table) {
5150                 for (i = 0; i < table->count; i++)
5151                         ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5152         }
5153 }
5154
5155 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5156                                                             struct amdgpu_clock_and_voltage_limits *table)
5157 {
5158         if (table) {
5159                 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5160                 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5161         }
5162 }
5163
5164 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5165                                                          struct amdgpu_cac_leakage_table *table)
5166 {
5167         u32 i;
5168
5169         if (table) {
5170                 for (i = 0; i < table->count; i++)
5171                         ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5172         }
5173 }
5174
5175 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5176 {
5177
5178         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5179                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5180         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5181                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5182         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5183                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5184         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5185                                                                    &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5186         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5187                                                                       &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5188         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5189                                                                       &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5190         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5191                                                                   &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5192         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5193                                                                   &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5194         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5195                                                                &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5196         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5197                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5198         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5199                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5200         ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5201                                                      &adev->pm.dpm.dyn_state.cac_leakage_table);
5202
5203 }
5204
5205 static void ci_update_current_ps(struct amdgpu_device *adev,
5206                                  struct amdgpu_ps *rps)
5207 {
5208         struct ci_ps *new_ps = ci_get_ps(rps);
5209         struct ci_power_info *pi = ci_get_pi(adev);
5210
5211         pi->current_rps = *rps;
5212         pi->current_ps = *new_ps;
5213         pi->current_rps.ps_priv = &pi->current_ps;
5214 }
5215
5216 static void ci_update_requested_ps(struct amdgpu_device *adev,
5217                                    struct amdgpu_ps *rps)
5218 {
5219         struct ci_ps *new_ps = ci_get_ps(rps);
5220         struct ci_power_info *pi = ci_get_pi(adev);
5221
5222         pi->requested_rps = *rps;
5223         pi->requested_ps = *new_ps;
5224         pi->requested_rps.ps_priv = &pi->requested_ps;
5225 }
5226
5227 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5228 {
5229         struct ci_power_info *pi = ci_get_pi(adev);
5230         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5231         struct amdgpu_ps *new_ps = &requested_ps;
5232
5233         ci_update_requested_ps(adev, new_ps);
5234
5235         ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5236
5237         return 0;
5238 }
5239
5240 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5241 {
5242         struct ci_power_info *pi = ci_get_pi(adev);
5243         struct amdgpu_ps *new_ps = &pi->requested_rps;
5244
5245         ci_update_current_ps(adev, new_ps);
5246 }
5247
5248
5249 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5250 {
5251         ci_read_clock_registers(adev);
5252         ci_enable_acpi_power_management(adev);
5253         ci_init_sclk_t(adev);
5254 }
5255
5256 static int ci_dpm_enable(struct amdgpu_device *adev)
5257 {
5258         struct ci_power_info *pi = ci_get_pi(adev);
5259         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5260         int ret;
5261
5262         if (amdgpu_ci_is_smc_running(adev))
5263                 return -EINVAL;
5264         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5265                 ci_enable_voltage_control(adev);
5266                 ret = ci_construct_voltage_tables(adev);
5267                 if (ret) {
5268                         DRM_ERROR("ci_construct_voltage_tables failed\n");
5269                         return ret;
5270                 }
5271         }
5272         if (pi->caps_dynamic_ac_timing) {
5273                 ret = ci_initialize_mc_reg_table(adev);
5274                 if (ret)
5275                         pi->caps_dynamic_ac_timing = false;
5276         }
5277         if (pi->dynamic_ss)
5278                 ci_enable_spread_spectrum(adev, true);
5279         if (pi->thermal_protection)
5280                 ci_enable_thermal_protection(adev, true);
5281         ci_program_sstp(adev);
5282         ci_enable_display_gap(adev);
5283         ci_program_vc(adev);
5284         ret = ci_upload_firmware(adev);
5285         if (ret) {
5286                 DRM_ERROR("ci_upload_firmware failed\n");
5287                 return ret;
5288         }
5289         ret = ci_process_firmware_header(adev);
5290         if (ret) {
5291                 DRM_ERROR("ci_process_firmware_header failed\n");
5292                 return ret;
5293         }
5294         ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5295         if (ret) {
5296                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5297                 return ret;
5298         }
5299         ret = ci_init_smc_table(adev);
5300         if (ret) {
5301                 DRM_ERROR("ci_init_smc_table failed\n");
5302                 return ret;
5303         }
5304         ret = ci_init_arb_table_index(adev);
5305         if (ret) {
5306                 DRM_ERROR("ci_init_arb_table_index failed\n");
5307                 return ret;
5308         }
5309         if (pi->caps_dynamic_ac_timing) {
5310                 ret = ci_populate_initial_mc_reg_table(adev);
5311                 if (ret) {
5312                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5313                         return ret;
5314                 }
5315         }
5316         ret = ci_populate_pm_base(adev);
5317         if (ret) {
5318                 DRM_ERROR("ci_populate_pm_base failed\n");
5319                 return ret;
5320         }
5321         ci_dpm_start_smc(adev);
5322         ci_enable_vr_hot_gpio_interrupt(adev);
5323         ret = ci_notify_smc_display_change(adev, false);
5324         if (ret) {
5325                 DRM_ERROR("ci_notify_smc_display_change failed\n");
5326                 return ret;
5327         }
5328         ci_enable_sclk_control(adev, true);
5329         ret = ci_enable_ulv(adev, true);
5330         if (ret) {
5331                 DRM_ERROR("ci_enable_ulv failed\n");
5332                 return ret;
5333         }
5334         ret = ci_enable_ds_master_switch(adev, true);
5335         if (ret) {
5336                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5337                 return ret;
5338         }
5339         ret = ci_start_dpm(adev);
5340         if (ret) {
5341                 DRM_ERROR("ci_start_dpm failed\n");
5342                 return ret;
5343         }
5344         ret = ci_enable_didt(adev, true);
5345         if (ret) {
5346                 DRM_ERROR("ci_enable_didt failed\n");
5347                 return ret;
5348         }
5349         ret = ci_enable_smc_cac(adev, true);
5350         if (ret) {
5351                 DRM_ERROR("ci_enable_smc_cac failed\n");
5352                 return ret;
5353         }
5354         ret = ci_enable_power_containment(adev, true);
5355         if (ret) {
5356                 DRM_ERROR("ci_enable_power_containment failed\n");
5357                 return ret;
5358         }
5359
5360         ret = ci_power_control_set_level(adev);
5361         if (ret) {
5362                 DRM_ERROR("ci_power_control_set_level failed\n");
5363                 return ret;
5364         }
5365
5366         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5367
5368         ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5369         if (ret) {
5370                 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5371                 return ret;
5372         }
5373
5374         ci_thermal_start_thermal_controller(adev);
5375
5376         ci_update_current_ps(adev, boot_ps);
5377
5378         return 0;
5379 }
5380
5381 static void ci_dpm_disable(struct amdgpu_device *adev)
5382 {
5383         struct ci_power_info *pi = ci_get_pi(adev);
5384         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5385
5386         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5387                        AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5388         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5389                        AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5390
5391         ci_dpm_powergate_uvd(adev, false);
5392
5393         if (!amdgpu_ci_is_smc_running(adev))
5394                 return;
5395
5396         ci_thermal_stop_thermal_controller(adev);
5397
5398         if (pi->thermal_protection)
5399                 ci_enable_thermal_protection(adev, false);
5400         ci_enable_power_containment(adev, false);
5401         ci_enable_smc_cac(adev, false);
5402         ci_enable_didt(adev, false);
5403         ci_enable_spread_spectrum(adev, false);
5404         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5405         ci_stop_dpm(adev);
5406         ci_enable_ds_master_switch(adev, false);
5407         ci_enable_ulv(adev, false);
5408         ci_clear_vc(adev);
5409         ci_reset_to_default(adev);
5410         ci_dpm_stop_smc(adev);
5411         ci_force_switch_to_arb_f0(adev);
5412         ci_enable_thermal_based_sclk_dpm(adev, false);
5413
5414         ci_update_current_ps(adev, boot_ps);
5415 }
5416
5417 static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5418 {
5419         struct ci_power_info *pi = ci_get_pi(adev);
5420         struct amdgpu_ps *new_ps = &pi->requested_rps;
5421         struct amdgpu_ps *old_ps = &pi->current_rps;
5422         int ret;
5423
5424         ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5425         if (pi->pcie_performance_request)
5426                 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5427         ret = ci_freeze_sclk_mclk_dpm(adev);
5428         if (ret) {
5429                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5430                 return ret;
5431         }
5432         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5433         if (ret) {
5434                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5435                 return ret;
5436         }
5437         ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5438         if (ret) {
5439                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5440                 return ret;
5441         }
5442
5443         ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5444         if (ret) {
5445                 DRM_ERROR("ci_update_vce_dpm failed\n");
5446                 return ret;
5447         }
5448
5449         ret = ci_update_sclk_t(adev);
5450         if (ret) {
5451                 DRM_ERROR("ci_update_sclk_t failed\n");
5452                 return ret;
5453         }
5454         if (pi->caps_dynamic_ac_timing) {
5455                 ret = ci_update_and_upload_mc_reg_table(adev);
5456                 if (ret) {
5457                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5458                         return ret;
5459                 }
5460         }
5461         ret = ci_program_memory_timing_parameters(adev);
5462         if (ret) {
5463                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5464                 return ret;
5465         }
5466         ret = ci_unfreeze_sclk_mclk_dpm(adev);
5467         if (ret) {
5468                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5469                 return ret;
5470         }
5471         ret = ci_upload_dpm_level_enable_mask(adev);
5472         if (ret) {
5473                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5474                 return ret;
5475         }
5476         if (pi->pcie_performance_request)
5477                 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5478
5479         return 0;
5480 }
5481
5482 #if 0
5483 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5484 {
5485         ci_set_boot_state(adev);
5486 }
5487 #endif
5488
5489 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5490 {
5491         ci_program_display_gap(adev);
5492 }
5493
5494 union power_info {
5495         struct _ATOM_POWERPLAY_INFO info;
5496         struct _ATOM_POWERPLAY_INFO_V2 info_2;
5497         struct _ATOM_POWERPLAY_INFO_V3 info_3;
5498         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5499         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5500         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5501 };
5502
5503 union pplib_clock_info {
5504         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5505         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5506         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5507         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5508         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5509         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5510 };
5511
5512 union pplib_power_state {
5513         struct _ATOM_PPLIB_STATE v1;
5514         struct _ATOM_PPLIB_STATE_V2 v2;
5515 };
5516
5517 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5518                                           struct amdgpu_ps *rps,
5519                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5520                                           u8 table_rev)
5521 {
5522         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5523         rps->class = le16_to_cpu(non_clock_info->usClassification);
5524         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5525
5526         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5527                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5528                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5529         } else {
5530                 rps->vclk = 0;
5531                 rps->dclk = 0;
5532         }
5533
5534         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5535                 adev->pm.dpm.boot_ps = rps;
5536         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5537                 adev->pm.dpm.uvd_ps = rps;
5538 }
5539
5540 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5541                                       struct amdgpu_ps *rps, int index,
5542                                       union pplib_clock_info *clock_info)
5543 {
5544         struct ci_power_info *pi = ci_get_pi(adev);
5545         struct ci_ps *ps = ci_get_ps(rps);
5546         struct ci_pl *pl = &ps->performance_levels[index];
5547
5548         ps->performance_level_count = index + 1;
5549
5550         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5551         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5552         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5553         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5554
5555         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5556                                                    pi->sys_pcie_mask,
5557                                                    pi->vbios_boot_state.pcie_gen_bootup_value,
5558                                                    clock_info->ci.ucPCIEGen);
5559         pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5560                                                      pi->vbios_boot_state.pcie_lane_bootup_value,
5561                                                      le16_to_cpu(clock_info->ci.usPCIELane));
5562
5563         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5564                 pi->acpi_pcie_gen = pl->pcie_gen;
5565         }
5566
5567         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5568                 pi->ulv.supported = true;
5569                 pi->ulv.pl = *pl;
5570                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5571         }
5572
5573         /* patch up boot state */
5574         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5575                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5576                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5577                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5578                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5579         }
5580
5581         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5582         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5583                 pi->use_pcie_powersaving_levels = true;
5584                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5585                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
5586                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5587                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
5588                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5589                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
5590                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5591                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
5592                 break;
5593         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5594                 pi->use_pcie_performance_levels = true;
5595                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5596                         pi->pcie_gen_performance.max = pl->pcie_gen;
5597                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5598                         pi->pcie_gen_performance.min = pl->pcie_gen;
5599                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5600                         pi->pcie_lane_performance.max = pl->pcie_lane;
5601                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5602                         pi->pcie_lane_performance.min = pl->pcie_lane;
5603                 break;
5604         default:
5605                 break;
5606         }
5607 }
5608
5609 static int ci_parse_power_table(struct amdgpu_device *adev)
5610 {
5611         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5612         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5613         union pplib_power_state *power_state;
5614         int i, j, k, non_clock_array_index, clock_array_index;
5615         union pplib_clock_info *clock_info;
5616         struct _StateArray *state_array;
5617         struct _ClockInfoArray *clock_info_array;
5618         struct _NonClockInfoArray *non_clock_info_array;
5619         union power_info *power_info;
5620         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5621         u16 data_offset;
5622         u8 frev, crev;
5623         u8 *power_state_offset;
5624         struct ci_ps *ps;
5625
5626         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5627                                    &frev, &crev, &data_offset))
5628                 return -EINVAL;
5629         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5630
5631         amdgpu_add_thermal_controller(adev);
5632
5633         state_array = (struct _StateArray *)
5634                 (mode_info->atom_context->bios + data_offset +
5635                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
5636         clock_info_array = (struct _ClockInfoArray *)
5637                 (mode_info->atom_context->bios + data_offset +
5638                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5639         non_clock_info_array = (struct _NonClockInfoArray *)
5640                 (mode_info->atom_context->bios + data_offset +
5641                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5642
5643         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5644                                   state_array->ucNumEntries, GFP_KERNEL);
5645         if (!adev->pm.dpm.ps)
5646                 return -ENOMEM;
5647         power_state_offset = (u8 *)state_array->states;
5648         for (i = 0; i < state_array->ucNumEntries; i++) {
5649                 u8 *idx;
5650                 power_state = (union pplib_power_state *)power_state_offset;
5651                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5652                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5653                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5654                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5655                 if (ps == NULL) {
5656                         kfree(adev->pm.dpm.ps);
5657                         return -ENOMEM;
5658                 }
5659                 adev->pm.dpm.ps[i].ps_priv = ps;
5660                 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5661                                               non_clock_info,
5662                                               non_clock_info_array->ucEntrySize);
5663                 k = 0;
5664                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5665                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5666                         clock_array_index = idx[j];
5667                         if (clock_array_index >= clock_info_array->ucNumEntries)
5668                                 continue;
5669                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5670                                 break;
5671                         clock_info = (union pplib_clock_info *)
5672                                 ((u8 *)&clock_info_array->clockInfo[0] +
5673                                  (clock_array_index * clock_info_array->ucEntrySize));
5674                         ci_parse_pplib_clock_info(adev,
5675                                                   &adev->pm.dpm.ps[i], k,
5676                                                   clock_info);
5677                         k++;
5678                 }
5679                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5680         }
5681         adev->pm.dpm.num_ps = state_array->ucNumEntries;
5682
5683         /* fill in the vce power states */
5684         for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
5685                 u32 sclk, mclk;
5686                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5687                 clock_info = (union pplib_clock_info *)
5688                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5689                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5690                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5691                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5692                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5693                 adev->pm.dpm.vce_states[i].sclk = sclk;
5694                 adev->pm.dpm.vce_states[i].mclk = mclk;
5695         }
5696
5697         return 0;
5698 }
5699
5700 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5701                                     struct ci_vbios_boot_state *boot_state)
5702 {
5703         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5704         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5705         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5706         u8 frev, crev;
5707         u16 data_offset;
5708
5709         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5710                                    &frev, &crev, &data_offset)) {
5711                 firmware_info =
5712                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5713                                                     data_offset);
5714                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5715                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5716                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5717                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5718                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5719                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5720                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5721
5722                 return 0;
5723         }
5724         return -EINVAL;
5725 }
5726
5727 static void ci_dpm_fini(struct amdgpu_device *adev)
5728 {
5729         int i;
5730
5731         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5732                 kfree(adev->pm.dpm.ps[i].ps_priv);
5733         }
5734         kfree(adev->pm.dpm.ps);
5735         kfree(adev->pm.dpm.priv);
5736         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5737         amdgpu_free_extended_power_table(adev);
5738 }
5739
5740 /**
5741  * ci_dpm_init_microcode - load ucode images from disk
5742  *
5743  * @adev: amdgpu_device pointer
5744  *
5745  * Use the firmware interface to load the ucode images into
5746  * the driver (not loaded into hw).
5747  * Returns 0 on success, error on failure.
5748  */
5749 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5750 {
5751         const char *chip_name;
5752         char fw_name[30];
5753         int err;
5754
5755         DRM_DEBUG("\n");
5756
5757         switch (adev->asic_type) {
5758         case CHIP_BONAIRE:
5759                 chip_name = "bonaire";
5760                 break;
5761         case CHIP_HAWAII:
5762                 chip_name = "hawaii";
5763                 break;
5764         case CHIP_KAVERI:
5765         case CHIP_KABINI:
5766         default: BUG();
5767         }
5768
5769         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
5770         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
5771         if (err)
5772                 goto out;
5773         err = amdgpu_ucode_validate(adev->pm.fw);
5774
5775 out:
5776         if (err) {
5777                 printk(KERN_ERR
5778                        "cik_smc: Failed to load firmware \"%s\"\n",
5779                        fw_name);
5780                 release_firmware(adev->pm.fw);
5781                 adev->pm.fw = NULL;
5782         }
5783         return err;
5784 }
5785
5786 static int ci_dpm_init(struct amdgpu_device *adev)
5787 {
5788         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5789         SMU7_Discrete_DpmTable *dpm_table;
5790         struct amdgpu_gpio_rec gpio;
5791         u16 data_offset, size;
5792         u8 frev, crev;
5793         struct ci_power_info *pi;
5794         int ret;
5795         u32 mask;
5796
5797         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5798         if (pi == NULL)
5799                 return -ENOMEM;
5800         adev->pm.dpm.priv = pi;
5801
5802         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
5803         if (ret)
5804                 pi->sys_pcie_mask = 0;
5805         else
5806                 pi->sys_pcie_mask = mask;
5807         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5808
5809         pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5810         pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5811         pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5812         pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5813
5814         pi->pcie_lane_performance.max = 0;
5815         pi->pcie_lane_performance.min = 16;
5816         pi->pcie_lane_powersaving.max = 0;
5817         pi->pcie_lane_powersaving.min = 16;
5818
5819         ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5820         if (ret) {
5821                 ci_dpm_fini(adev);
5822                 return ret;
5823         }
5824
5825         ret = amdgpu_get_platform_caps(adev);
5826         if (ret) {
5827                 ci_dpm_fini(adev);
5828                 return ret;
5829         }
5830
5831         ret = amdgpu_parse_extended_power_table(adev);
5832         if (ret) {
5833                 ci_dpm_fini(adev);
5834                 return ret;
5835         }
5836
5837         ret = ci_parse_power_table(adev);
5838         if (ret) {
5839                 ci_dpm_fini(adev);
5840                 return ret;
5841         }
5842
5843         pi->dll_default_on = false;
5844         pi->sram_end = SMC_RAM_END;
5845
5846         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5847         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5848         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5849         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5850         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5851         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5852         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5853         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5854
5855         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5856
5857         pi->sclk_dpm_key_disabled = 0;
5858         pi->mclk_dpm_key_disabled = 0;
5859         pi->pcie_dpm_key_disabled = 0;
5860         pi->thermal_sclk_dpm_enabled = 0;
5861
5862         pi->caps_sclk_ds = true;
5863
5864         pi->mclk_strobe_mode_threshold = 40000;
5865         pi->mclk_stutter_mode_threshold = 40000;
5866         pi->mclk_edc_enable_threshold = 40000;
5867         pi->mclk_edc_wr_enable_threshold = 40000;
5868
5869         ci_initialize_powertune_defaults(adev);
5870
5871         pi->caps_fps = false;
5872
5873         pi->caps_sclk_throttle_low_notification = false;
5874
5875         pi->caps_uvd_dpm = true;
5876         pi->caps_vce_dpm = true;
5877
5878         ci_get_leakage_voltages(adev);
5879         ci_patch_dependency_tables_with_leakage(adev);
5880         ci_set_private_data_variables_based_on_pptable(adev);
5881
5882         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5883                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5884         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5885                 ci_dpm_fini(adev);
5886                 return -ENOMEM;
5887         }
5888         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5889         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5890         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5891         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5892         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5893         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5894         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5895         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5896         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5897
5898         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5899         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5900         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5901
5902         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5903         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5904         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5905         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5906
5907         if (adev->asic_type == CHIP_HAWAII) {
5908                 pi->thermal_temp_setting.temperature_low = 94500;
5909                 pi->thermal_temp_setting.temperature_high = 95000;
5910                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5911         } else {
5912                 pi->thermal_temp_setting.temperature_low = 99500;
5913                 pi->thermal_temp_setting.temperature_high = 100000;
5914                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5915         }
5916
5917         pi->uvd_enabled = false;
5918
5919         dpm_table = &pi->smc_state_table;
5920
5921         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5922         if (gpio.valid) {
5923                 dpm_table->VRHotGpio = gpio.shift;
5924                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5925         } else {
5926                 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5927                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5928         }
5929
5930         gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
5931         if (gpio.valid) {
5932                 dpm_table->AcDcGpio = gpio.shift;
5933                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5934         } else {
5935                 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5936                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5937         }
5938
5939         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
5940         if (gpio.valid) {
5941                 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
5942
5943                 switch (gpio.shift) {
5944                 case 0:
5945                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5946                         tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5947                         break;
5948                 case 1:
5949                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5950                         tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5951                         break;
5952                 case 2:
5953                         tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
5954                         break;
5955                 case 3:
5956                         tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
5957                         break;
5958                 case 4:
5959                         tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
5960                         break;
5961                 default:
5962                         DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
5963                         break;
5964                 }
5965                 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
5966         }
5967
5968         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5969         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5970         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5971         if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5972                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5973         else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5974                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5975
5976         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5977                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5978                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5979                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5980                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5981                 else
5982                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5983         }
5984
5985         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5986                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5987                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5988                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5989                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5990                 else
5991                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5992         }
5993
5994         pi->vddc_phase_shed_control = true;
5995
5996 #if defined(CONFIG_ACPI)
5997         pi->pcie_performance_request =
5998                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
5999 #else
6000         pi->pcie_performance_request = false;
6001 #endif
6002
6003         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6004                                    &frev, &crev, &data_offset)) {
6005                 pi->caps_sclk_ss_support = true;
6006                 pi->caps_mclk_ss_support = true;
6007                 pi->dynamic_ss = true;
6008         } else {
6009                 pi->caps_sclk_ss_support = false;
6010                 pi->caps_mclk_ss_support = false;
6011                 pi->dynamic_ss = true;
6012         }
6013
6014         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6015                 pi->thermal_protection = true;
6016         else
6017                 pi->thermal_protection = false;
6018
6019         pi->caps_dynamic_ac_timing = true;
6020
6021         pi->uvd_power_gated = false;
6022
6023         /* make sure dc limits are valid */
6024         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6025             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6026                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6027                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6028
6029         pi->fan_ctrl_is_in_default_mode = true;
6030
6031         return 0;
6032 }
6033
6034 static void
6035 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6036                                                struct seq_file *m)
6037 {
6038         struct ci_power_info *pi = ci_get_pi(adev);
6039         struct amdgpu_ps *rps = &pi->current_rps;
6040         u32 sclk = ci_get_average_sclk_freq(adev);
6041         u32 mclk = ci_get_average_mclk_freq(adev);
6042         u32 activity_percent = 50;
6043         int ret;
6044
6045         ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6046                                         &activity_percent);
6047
6048         if (ret == 0) {
6049                 activity_percent += 0x80;
6050                 activity_percent >>= 8;
6051                 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6052         }
6053
6054         seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
6055         seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6056         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
6057                    sclk, mclk);
6058         seq_printf(m, "GPU load: %u %%\n", activity_percent);
6059 }
6060
6061 static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6062                                      struct amdgpu_ps *rps)
6063 {
6064         struct ci_ps *ps = ci_get_ps(rps);
6065         struct ci_pl *pl;
6066         int i;
6067
6068         amdgpu_dpm_print_class_info(rps->class, rps->class2);
6069         amdgpu_dpm_print_cap_info(rps->caps);
6070         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6071         for (i = 0; i < ps->performance_level_count; i++) {
6072                 pl = &ps->performance_levels[i];
6073                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6074                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6075         }
6076         amdgpu_dpm_print_ps_status(adev, rps);
6077 }
6078
6079 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6080 {
6081         struct ci_power_info *pi = ci_get_pi(adev);
6082         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6083
6084         if (low)
6085                 return requested_state->performance_levels[0].sclk;
6086         else
6087                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6088 }
6089
6090 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6091 {
6092         struct ci_power_info *pi = ci_get_pi(adev);
6093         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6094
6095         if (low)
6096                 return requested_state->performance_levels[0].mclk;
6097         else
6098                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6099 }
6100
6101 /* get temperature in millidegrees */
6102 static int ci_dpm_get_temp(struct amdgpu_device *adev)
6103 {
6104         u32 temp;
6105         int actual_temp = 0;
6106
6107         temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6108                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6109
6110         if (temp & 0x200)
6111                 actual_temp = 255;
6112         else
6113                 actual_temp = temp & 0x1ff;
6114
6115         actual_temp = actual_temp * 1000;
6116
6117         return actual_temp;
6118 }
6119
6120 static int ci_set_temperature_range(struct amdgpu_device *adev)
6121 {
6122         int ret;
6123
6124         ret = ci_thermal_enable_alert(adev, false);
6125         if (ret)
6126                 return ret;
6127         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6128                                                CISLANDS_TEMP_RANGE_MAX);
6129         if (ret)
6130                 return ret;
6131         ret = ci_thermal_enable_alert(adev, true);
6132         if (ret)
6133                 return ret;
6134         return ret;
6135 }
6136
6137 static int ci_dpm_early_init(void *handle)
6138 {
6139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6140
6141         ci_dpm_set_dpm_funcs(adev);
6142         ci_dpm_set_irq_funcs(adev);
6143
6144         return 0;
6145 }
6146
6147 static int ci_dpm_late_init(void *handle)
6148 {
6149         int ret;
6150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6151
6152         if (!amdgpu_dpm)
6153                 return 0;
6154
6155         /* init the sysfs and debugfs files late */
6156         ret = amdgpu_pm_sysfs_init(adev);
6157         if (ret)
6158                 return ret;
6159
6160         ret = ci_set_temperature_range(adev);
6161         if (ret)
6162                 return ret;
6163
6164         ci_dpm_powergate_uvd(adev, true);
6165
6166         return 0;
6167 }
6168
6169 static int ci_dpm_sw_init(void *handle)
6170 {
6171         int ret;
6172         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6173
6174         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
6175         if (ret)
6176                 return ret;
6177
6178         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
6179         if (ret)
6180                 return ret;
6181
6182         /* default to balanced state */
6183         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6184         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6185         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
6186         adev->pm.default_sclk = adev->clock.default_sclk;
6187         adev->pm.default_mclk = adev->clock.default_mclk;
6188         adev->pm.current_sclk = adev->clock.default_sclk;
6189         adev->pm.current_mclk = adev->clock.default_mclk;
6190         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6191
6192         if (amdgpu_dpm == 0)
6193                 return 0;
6194
6195         ret = ci_dpm_init_microcode(adev);
6196         if (ret)
6197                 return ret;
6198
6199         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6200         mutex_lock(&adev->pm.mutex);
6201         ret = ci_dpm_init(adev);
6202         if (ret)
6203                 goto dpm_failed;
6204         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6205         if (amdgpu_dpm == 1)
6206                 amdgpu_pm_print_power_states(adev);
6207         mutex_unlock(&adev->pm.mutex);
6208         DRM_INFO("amdgpu: dpm initialized\n");
6209
6210         return 0;
6211
6212 dpm_failed:
6213         ci_dpm_fini(adev);
6214         mutex_unlock(&adev->pm.mutex);
6215         DRM_ERROR("amdgpu: dpm initialization failed\n");
6216         return ret;
6217 }
6218
6219 static int ci_dpm_sw_fini(void *handle)
6220 {
6221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6222
6223         mutex_lock(&adev->pm.mutex);
6224         amdgpu_pm_sysfs_fini(adev);
6225         ci_dpm_fini(adev);
6226         mutex_unlock(&adev->pm.mutex);
6227
6228         return 0;
6229 }
6230
6231 static int ci_dpm_hw_init(void *handle)
6232 {
6233         int ret;
6234
6235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6236
6237         if (!amdgpu_dpm)
6238                 return 0;
6239
6240         mutex_lock(&adev->pm.mutex);
6241         ci_dpm_setup_asic(adev);
6242         ret = ci_dpm_enable(adev);
6243         if (ret)
6244                 adev->pm.dpm_enabled = false;
6245         else
6246                 adev->pm.dpm_enabled = true;
6247         mutex_unlock(&adev->pm.mutex);
6248
6249         return ret;
6250 }
6251
6252 static int ci_dpm_hw_fini(void *handle)
6253 {
6254         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6255
6256         if (adev->pm.dpm_enabled) {
6257                 mutex_lock(&adev->pm.mutex);
6258                 ci_dpm_disable(adev);
6259                 mutex_unlock(&adev->pm.mutex);
6260         }
6261
6262         return 0;
6263 }
6264
6265 static int ci_dpm_suspend(void *handle)
6266 {
6267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6268
6269         if (adev->pm.dpm_enabled) {
6270                 mutex_lock(&adev->pm.mutex);
6271                 /* disable dpm */
6272                 ci_dpm_disable(adev);
6273                 /* reset the power state */
6274                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6275                 mutex_unlock(&adev->pm.mutex);
6276         }
6277         return 0;
6278 }
6279
6280 static int ci_dpm_resume(void *handle)
6281 {
6282         int ret;
6283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6284
6285         if (adev->pm.dpm_enabled) {
6286                 /* asic init will reset to the boot state */
6287                 mutex_lock(&adev->pm.mutex);
6288                 ci_dpm_setup_asic(adev);
6289                 ret = ci_dpm_enable(adev);
6290                 if (ret)
6291                         adev->pm.dpm_enabled = false;
6292                 else
6293                         adev->pm.dpm_enabled = true;
6294                 mutex_unlock(&adev->pm.mutex);
6295                 if (adev->pm.dpm_enabled)
6296                         amdgpu_pm_compute_clocks(adev);
6297         }
6298         return 0;
6299 }
6300
6301 static bool ci_dpm_is_idle(void *handle)
6302 {
6303         /* XXX */
6304         return true;
6305 }
6306
6307 static int ci_dpm_wait_for_idle(void *handle)
6308 {
6309         /* XXX */
6310         return 0;
6311 }
6312
6313 static void ci_dpm_print_status(void *handle)
6314 {
6315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6316
6317         dev_info(adev->dev, "CIK DPM registers\n");
6318         dev_info(adev->dev, "  BIOS_SCRATCH_4=0x%08X\n",
6319                  RREG32(mmBIOS_SCRATCH_4));
6320         dev_info(adev->dev, "  MC_ARB_DRAM_TIMING=0x%08X\n",
6321                  RREG32(mmMC_ARB_DRAM_TIMING));
6322         dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2=0x%08X\n",
6323                  RREG32(mmMC_ARB_DRAM_TIMING2));
6324         dev_info(adev->dev, "  MC_ARB_BURST_TIME=0x%08X\n",
6325                  RREG32(mmMC_ARB_BURST_TIME));
6326         dev_info(adev->dev, "  MC_ARB_DRAM_TIMING_1=0x%08X\n",
6327                  RREG32(mmMC_ARB_DRAM_TIMING_1));
6328         dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2_1=0x%08X\n",
6329                  RREG32(mmMC_ARB_DRAM_TIMING2_1));
6330         dev_info(adev->dev, "  MC_CG_CONFIG=0x%08X\n",
6331                  RREG32(mmMC_CG_CONFIG));
6332         dev_info(adev->dev, "  MC_ARB_CG=0x%08X\n",
6333                  RREG32(mmMC_ARB_CG));
6334         dev_info(adev->dev, "  DIDT_SQ_CTRL0=0x%08X\n",
6335                  RREG32_DIDT(ixDIDT_SQ_CTRL0));
6336         dev_info(adev->dev, "  DIDT_DB_CTRL0=0x%08X\n",
6337                  RREG32_DIDT(ixDIDT_DB_CTRL0));
6338         dev_info(adev->dev, "  DIDT_TD_CTRL0=0x%08X\n",
6339                  RREG32_DIDT(ixDIDT_TD_CTRL0));
6340         dev_info(adev->dev, "  DIDT_TCP_CTRL0=0x%08X\n",
6341                  RREG32_DIDT(ixDIDT_TCP_CTRL0));
6342         dev_info(adev->dev, "  CG_THERMAL_INT=0x%08X\n",
6343                  RREG32_SMC(ixCG_THERMAL_INT));
6344         dev_info(adev->dev, "  CG_THERMAL_CTRL=0x%08X\n",
6345                  RREG32_SMC(ixCG_THERMAL_CTRL));
6346         dev_info(adev->dev, "  GENERAL_PWRMGT=0x%08X\n",
6347                  RREG32_SMC(ixGENERAL_PWRMGT));
6348         dev_info(adev->dev, "  MC_SEQ_CNTL_3=0x%08X\n",
6349                  RREG32(mmMC_SEQ_CNTL_3));
6350         dev_info(adev->dev, "  LCAC_MC0_CNTL=0x%08X\n",
6351                  RREG32_SMC(ixLCAC_MC0_CNTL));
6352         dev_info(adev->dev, "  LCAC_MC1_CNTL=0x%08X\n",
6353                  RREG32_SMC(ixLCAC_MC1_CNTL));
6354         dev_info(adev->dev, "  LCAC_CPL_CNTL=0x%08X\n",
6355                  RREG32_SMC(ixLCAC_CPL_CNTL));
6356         dev_info(adev->dev, "  SCLK_PWRMGT_CNTL=0x%08X\n",
6357                  RREG32_SMC(ixSCLK_PWRMGT_CNTL));
6358         dev_info(adev->dev, "  BIF_LNCNT_RESET=0x%08X\n",
6359                  RREG32(mmBIF_LNCNT_RESET));
6360         dev_info(adev->dev, "  FIRMWARE_FLAGS=0x%08X\n",
6361                  RREG32_SMC(ixFIRMWARE_FLAGS));
6362         dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL=0x%08X\n",
6363                  RREG32_SMC(ixCG_SPLL_FUNC_CNTL));
6364         dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_2=0x%08X\n",
6365                  RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));
6366         dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_3=0x%08X\n",
6367                  RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));
6368         dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_4=0x%08X\n",
6369                  RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));
6370         dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",
6371                  RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));
6372         dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",
6373                  RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));
6374         dev_info(adev->dev, "  DLL_CNTL=0x%08X\n",
6375                  RREG32(mmDLL_CNTL));
6376         dev_info(adev->dev, "  MCLK_PWRMGT_CNTL=0x%08X\n",
6377                  RREG32(mmMCLK_PWRMGT_CNTL));
6378         dev_info(adev->dev, "  MPLL_AD_FUNC_CNTL=0x%08X\n",
6379                  RREG32(mmMPLL_AD_FUNC_CNTL));
6380         dev_info(adev->dev, "  MPLL_DQ_FUNC_CNTL=0x%08X\n",
6381                  RREG32(mmMPLL_DQ_FUNC_CNTL));
6382         dev_info(adev->dev, "  MPLL_FUNC_CNTL=0x%08X\n",
6383                  RREG32(mmMPLL_FUNC_CNTL));
6384         dev_info(adev->dev, "  MPLL_FUNC_CNTL_1=0x%08X\n",
6385                  RREG32(mmMPLL_FUNC_CNTL_1));
6386         dev_info(adev->dev, "  MPLL_FUNC_CNTL_2=0x%08X\n",
6387                  RREG32(mmMPLL_FUNC_CNTL_2));
6388         dev_info(adev->dev, "  MPLL_SS1=0x%08X\n",
6389                  RREG32(mmMPLL_SS1));
6390         dev_info(adev->dev, "  MPLL_SS2=0x%08X\n",
6391                  RREG32(mmMPLL_SS2));
6392         dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL=0x%08X\n",
6393                  RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));
6394         dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL2=0x%08X\n",
6395                  RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));
6396         dev_info(adev->dev, "  CG_STATIC_SCREEN_PARAMETER=0x%08X\n",
6397                  RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));
6398         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_0=0x%08X\n",
6399                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
6400         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_1=0x%08X\n",
6401                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));
6402         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_2=0x%08X\n",
6403                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));
6404         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_3=0x%08X\n",
6405                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));
6406         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_4=0x%08X\n",
6407                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));
6408         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_5=0x%08X\n",
6409                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));
6410         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_6=0x%08X\n",
6411                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));
6412         dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_7=0x%08X\n",
6413                  RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));
6414         dev_info(adev->dev, "  RCU_UC_EVENTS=0x%08X\n",
6415                  RREG32_SMC(ixRCU_UC_EVENTS));
6416         dev_info(adev->dev, "  DPM_TABLE_475=0x%08X\n",
6417                  RREG32_SMC(ixDPM_TABLE_475));
6418         dev_info(adev->dev, "  MC_SEQ_RAS_TIMING_LP=0x%08X\n",
6419                  RREG32(mmMC_SEQ_RAS_TIMING_LP));
6420         dev_info(adev->dev, "  MC_SEQ_RAS_TIMING=0x%08X\n",
6421                  RREG32(mmMC_SEQ_RAS_TIMING));
6422         dev_info(adev->dev, "  MC_SEQ_CAS_TIMING_LP=0x%08X\n",
6423                  RREG32(mmMC_SEQ_CAS_TIMING_LP));
6424         dev_info(adev->dev, "  MC_SEQ_CAS_TIMING=0x%08X\n",
6425                  RREG32(mmMC_SEQ_CAS_TIMING));
6426         dev_info(adev->dev, "  MC_SEQ_DLL_STBY_LP=0x%08X\n",
6427                  RREG32(mmMC_SEQ_DLL_STBY_LP));
6428         dev_info(adev->dev, "  MC_SEQ_DLL_STBY=0x%08X\n",
6429                  RREG32(mmMC_SEQ_DLL_STBY));
6430         dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",
6431                  RREG32(mmMC_SEQ_G5PDX_CMD0_LP));
6432         dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0=0x%08X\n",
6433                  RREG32(mmMC_SEQ_G5PDX_CMD0));
6434         dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",
6435                  RREG32(mmMC_SEQ_G5PDX_CMD1_LP));
6436         dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1=0x%08X\n",
6437                  RREG32(mmMC_SEQ_G5PDX_CMD1));
6438         dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",
6439                  RREG32(mmMC_SEQ_G5PDX_CTRL_LP));
6440         dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL=0x%08X\n",
6441                  RREG32(mmMC_SEQ_G5PDX_CTRL));
6442         dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",
6443                  RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));
6444         dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD=0x%08X\n",
6445                  RREG32(mmMC_SEQ_PMG_DVS_CMD));
6446         dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",
6447                  RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));
6448         dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL=0x%08X\n",
6449                  RREG32(mmMC_SEQ_PMG_DVS_CTL));
6450         dev_info(adev->dev, "  MC_SEQ_MISC_TIMING_LP=0x%08X\n",
6451                  RREG32(mmMC_SEQ_MISC_TIMING_LP));
6452         dev_info(adev->dev, "  MC_SEQ_MISC_TIMING=0x%08X\n",
6453                  RREG32(mmMC_SEQ_MISC_TIMING));
6454         dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2_LP=0x%08X\n",
6455                  RREG32(mmMC_SEQ_MISC_TIMING2_LP));
6456         dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2=0x%08X\n",
6457                  RREG32(mmMC_SEQ_MISC_TIMING2));
6458         dev_info(adev->dev, "  MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",
6459                  RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));
6460         dev_info(adev->dev, "  MC_PMG_CMD_EMRS=0x%08X\n",
6461                  RREG32(mmMC_PMG_CMD_EMRS));
6462         dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",
6463                  RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));
6464         dev_info(adev->dev, "  MC_PMG_CMD_MRS=0x%08X\n",
6465                  RREG32(mmMC_PMG_CMD_MRS));
6466         dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",
6467                  RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));
6468         dev_info(adev->dev, "  MC_PMG_CMD_MRS1=0x%08X\n",
6469                  RREG32(mmMC_PMG_CMD_MRS1));
6470         dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0_LP=0x%08X\n",
6471                  RREG32(mmMC_SEQ_WR_CTL_D0_LP));
6472         dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0=0x%08X\n",
6473                  RREG32(mmMC_SEQ_WR_CTL_D0));
6474         dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1_LP=0x%08X\n",
6475                  RREG32(mmMC_SEQ_WR_CTL_D1_LP));
6476         dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1=0x%08X\n",
6477                  RREG32(mmMC_SEQ_WR_CTL_D1));
6478         dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0_LP=0x%08X\n",
6479                  RREG32(mmMC_SEQ_RD_CTL_D0_LP));
6480         dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0=0x%08X\n",
6481                  RREG32(mmMC_SEQ_RD_CTL_D0));
6482         dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1_LP=0x%08X\n",
6483                  RREG32(mmMC_SEQ_RD_CTL_D1_LP));
6484         dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1=0x%08X\n",
6485                  RREG32(mmMC_SEQ_RD_CTL_D1));
6486         dev_info(adev->dev, "  MC_SEQ_PMG_TIMING_LP=0x%08X\n",
6487                  RREG32(mmMC_SEQ_PMG_TIMING_LP));
6488         dev_info(adev->dev, "  MC_SEQ_PMG_TIMING=0x%08X\n",
6489                  RREG32(mmMC_SEQ_PMG_TIMING));
6490         dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",
6491                  RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));
6492         dev_info(adev->dev, "  MC_PMG_CMD_MRS2=0x%08X\n",
6493                  RREG32(mmMC_PMG_CMD_MRS2));
6494         dev_info(adev->dev, "  MC_SEQ_WR_CTL_2_LP=0x%08X\n",
6495                  RREG32(mmMC_SEQ_WR_CTL_2_LP));
6496         dev_info(adev->dev, "  MC_SEQ_WR_CTL_2=0x%08X\n",
6497                  RREG32(mmMC_SEQ_WR_CTL_2));
6498         dev_info(adev->dev, "  PCIE_LC_SPEED_CNTL=0x%08X\n",
6499                  RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));
6500         dev_info(adev->dev, "  PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",
6501                  RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));
6502         dev_info(adev->dev, "  SMC_IND_INDEX_0=0x%08X\n",
6503                  RREG32(mmSMC_IND_INDEX_0));
6504         dev_info(adev->dev, "  SMC_IND_DATA_0=0x%08X\n",
6505                  RREG32(mmSMC_IND_DATA_0));
6506         dev_info(adev->dev, "  SMC_IND_ACCESS_CNTL=0x%08X\n",
6507                  RREG32(mmSMC_IND_ACCESS_CNTL));
6508         dev_info(adev->dev, "  SMC_RESP_0=0x%08X\n",
6509                  RREG32(mmSMC_RESP_0));
6510         dev_info(adev->dev, "  SMC_MESSAGE_0=0x%08X\n",
6511                  RREG32(mmSMC_MESSAGE_0));
6512         dev_info(adev->dev, "  SMC_SYSCON_RESET_CNTL=0x%08X\n",
6513                  RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));
6514         dev_info(adev->dev, "  SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",
6515                  RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));
6516         dev_info(adev->dev, "  SMC_SYSCON_MISC_CNTL=0x%08X\n",
6517                  RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));
6518         dev_info(adev->dev, "  SMC_PC_C=0x%08X\n",
6519                  RREG32_SMC(ixSMC_PC_C));
6520 }
6521
6522 static int ci_dpm_soft_reset(void *handle)
6523 {
6524         return 0;
6525 }
6526
6527 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6528                                       struct amdgpu_irq_src *source,
6529                                       unsigned type,
6530                                       enum amdgpu_interrupt_state state)
6531 {
6532         u32 cg_thermal_int;
6533
6534         switch (type) {
6535         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6536                 switch (state) {
6537                 case AMDGPU_IRQ_STATE_DISABLE:
6538                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6539                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6540                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6541                         break;
6542                 case AMDGPU_IRQ_STATE_ENABLE:
6543                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6544                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6545                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6546                         break;
6547                 default:
6548                         break;
6549                 }
6550                 break;
6551
6552         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6553                 switch (state) {
6554                 case AMDGPU_IRQ_STATE_DISABLE:
6555                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6556                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6557                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6558                         break;
6559                 case AMDGPU_IRQ_STATE_ENABLE:
6560                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6561                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6562                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6563                         break;
6564                 default:
6565                         break;
6566                 }
6567                 break;
6568
6569         default:
6570                 break;
6571         }
6572         return 0;
6573 }
6574
6575 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6576                                     struct amdgpu_irq_src *source,
6577                                     struct amdgpu_iv_entry *entry)
6578 {
6579         bool queue_thermal = false;
6580
6581         if (entry == NULL)
6582                 return -EINVAL;
6583
6584         switch (entry->src_id) {
6585         case 230: /* thermal low to high */
6586                 DRM_DEBUG("IH: thermal low to high\n");
6587                 adev->pm.dpm.thermal.high_to_low = false;
6588                 queue_thermal = true;
6589                 break;
6590         case 231: /* thermal high to low */
6591                 DRM_DEBUG("IH: thermal high to low\n");
6592                 adev->pm.dpm.thermal.high_to_low = true;
6593                 queue_thermal = true;
6594                 break;
6595         default:
6596                 break;
6597         }
6598
6599         if (queue_thermal)
6600                 schedule_work(&adev->pm.dpm.thermal.work);
6601
6602         return 0;
6603 }
6604
6605 static int ci_dpm_set_clockgating_state(void *handle,
6606                                           enum amd_clockgating_state state)
6607 {
6608         return 0;
6609 }
6610
6611 static int ci_dpm_set_powergating_state(void *handle,
6612                                           enum amd_powergating_state state)
6613 {
6614         return 0;
6615 }
6616
6617 const struct amd_ip_funcs ci_dpm_ip_funcs = {
6618         .early_init = ci_dpm_early_init,
6619         .late_init = ci_dpm_late_init,
6620         .sw_init = ci_dpm_sw_init,
6621         .sw_fini = ci_dpm_sw_fini,
6622         .hw_init = ci_dpm_hw_init,
6623         .hw_fini = ci_dpm_hw_fini,
6624         .suspend = ci_dpm_suspend,
6625         .resume = ci_dpm_resume,
6626         .is_idle = ci_dpm_is_idle,
6627         .wait_for_idle = ci_dpm_wait_for_idle,
6628         .soft_reset = ci_dpm_soft_reset,
6629         .print_status = ci_dpm_print_status,
6630         .set_clockgating_state = ci_dpm_set_clockgating_state,
6631         .set_powergating_state = ci_dpm_set_powergating_state,
6632 };
6633
6634 static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
6635         .get_temperature = &ci_dpm_get_temp,
6636         .pre_set_power_state = &ci_dpm_pre_set_power_state,
6637         .set_power_state = &ci_dpm_set_power_state,
6638         .post_set_power_state = &ci_dpm_post_set_power_state,
6639         .display_configuration_changed = &ci_dpm_display_configuration_changed,
6640         .get_sclk = &ci_dpm_get_sclk,
6641         .get_mclk = &ci_dpm_get_mclk,
6642         .print_power_state = &ci_dpm_print_power_state,
6643         .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
6644         .force_performance_level = &ci_dpm_force_performance_level,
6645         .vblank_too_short = &ci_dpm_vblank_too_short,
6646         .powergate_uvd = &ci_dpm_powergate_uvd,
6647         .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
6648         .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
6649         .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
6650         .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
6651 };
6652
6653 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
6654 {
6655         if (adev->pm.funcs == NULL)
6656                 adev->pm.funcs = &ci_dpm_funcs;
6657 }
6658
6659 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
6660         .set = ci_dpm_set_interrupt_state,
6661         .process = ci_dpm_process_interrupt,
6662 };
6663
6664 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6665 {
6666         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6667         adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
6668 }