drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/ttm/ttm_debug.h>
  38 #include <drm/drmP.h>
  39 #include <drm/amdgpu_drm.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/slab.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include <linux/debugfs.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_trace.h"
  48 #include "bif/bif_4_1_d.h"
  49
  50 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  51
  52 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  53                              struct ttm_mem_reg *mem, unsigned num_pages,
  54                              uint64_t offset, unsigned window,
  55                              struct amdgpu_ring *ring,
  56                              uint64_t *addr);
  57
  58 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  59 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  60
  61 /*
  62  * Global memory.
  63  */
  64 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  65 {
  66         return ttm_mem_global_init(ref->object);
  67 }
  68
  69 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  70 {
  71         ttm_mem_global_release(ref->object);
  72 }
  73
  74 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  75 {
  76         struct drm_global_reference *global_ref;
  77         struct amdgpu_ring *ring;
  78         struct amd_sched_rq *rq;
  79         int r;
  80
  81         adev->mman.mem_global_referenced = false;
  82         global_ref = &adev->mman.mem_global_ref;
  83         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  84         global_ref->size = sizeof(struct ttm_mem_global);
  85         global_ref->init = &amdgpu_ttm_mem_global_init;
  86         global_ref->release = &amdgpu_ttm_mem_global_release;
  87         r = drm_global_item_ref(global_ref);
  88         if (r) {
  89                 DRM_ERROR("Failed setting up TTM memory accounting "
  90                           "subsystem.\n");
  91                 goto error_mem;
  92         }
  93
  94         adev->mman.bo_global_ref.mem_glob =
  95                 adev->mman.mem_global_ref.object;
  96         global_ref = &adev->mman.bo_global_ref.ref;
  97         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  98         global_ref->size = sizeof(struct ttm_bo_global);
  99         global_ref->init = &ttm_bo_global_init;
 100         global_ref->release = &ttm_bo_global_release;
 101         r = drm_global_item_ref(global_ref);
 102         if (r) {
 103                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 104                 goto error_bo;
 105         }
 106
 107         mutex_init(&adev->mman.gtt_window_lock);
 108
 109         ring = adev->mman.buffer_funcs_ring;
 110         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 111         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 112                                   rq, amdgpu_sched_jobs);
 113         if (r) {
 114                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 115                 goto error_entity;
 116         }
 117
 118         adev->mman.mem_global_referenced = true;
 119
 120         return 0;
 121
 122 error_entity:
 123         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 124 error_bo:
 125         drm_global_item_unref(&adev->mman.mem_global_ref);
 126 error_mem:
 127         return r;
 128 }
 129
 130 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 131 {
 132         if (adev->mman.mem_global_referenced) {
 133                 amd_sched_entity_fini(adev->mman.entity.sched,
 134                                       &adev->mman.entity);
 135                 mutex_destroy(&adev->mman.gtt_window_lock);
 136                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 137                 drm_global_item_unref(&adev->mman.mem_global_ref);
 138                 adev->mman.mem_global_referenced = false;
 139         }
 140 }
 141
 142 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 143 {
 144         return 0;
 145 }
 146
 147 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 148                                 struct ttm_mem_type_manager *man)
 149 {
 150         struct amdgpu_device *adev;
 151
 152         adev = amdgpu_ttm_adev(bdev);
 153
 154         switch (type) {
 155         case TTM_PL_SYSTEM:
 156                 /* System memory */
 157                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 158                 man->available_caching = TTM_PL_MASK_CACHING;
 159                 man->default_caching = TTM_PL_FLAG_CACHED;
 160                 break;
 161         case TTM_PL_TT:
 162                 man->func = &amdgpu_gtt_mgr_func;
 163                 man->gpu_offset = adev->mc.gart_start;
 164                 man->available_caching = TTM_PL_MASK_CACHING;
 165                 man->default_caching = TTM_PL_FLAG_CACHED;
 166                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 167                 break;
 168         case TTM_PL_VRAM:
 169                 /* "On-card" video ram */
 170                 man->func = &amdgpu_vram_mgr_func;
 171                 man->gpu_offset = adev->mc.vram_start;
 172                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 173                              TTM_MEMTYPE_FLAG_MAPPABLE;
 174                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 175                 man->default_caching = TTM_PL_FLAG_WC;
 176                 break;
 177         case AMDGPU_PL_GDS:
 178         case AMDGPU_PL_GWS:
 179         case AMDGPU_PL_OA:
 180                 /* On-chip GDS memory*/
 181                 man->func = &ttm_bo_manager_func;
 182                 man->gpu_offset = 0;
 183                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 184                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 185                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 186                 break;
 187         default:
 188                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 189                 return -EINVAL;
 190         }
 191         return 0;
 192 }
 193
 194 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 195                                 struct ttm_placement *placement)
 196 {
 197         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 198         struct amdgpu_bo *abo;
 199         static const struct ttm_place placements = {
 200                 .fpfn = 0,
 201                 .lpfn = 0,
 202                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 203         };
 204
 205         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 206                 placement->placement = &placements;
 207                 placement->busy_placement = &placements;
 208                 placement->num_placement = 1;
 209                 placement->num_busy_placement = 1;
 210                 return;
 211         }
 212         abo = container_of(bo, struct amdgpu_bo, tbo);
 213         switch (bo->mem.mem_type) {
 214         case TTM_PL_VRAM:
 215                 if (adev->mman.buffer_funcs &&
 216                     adev->mman.buffer_funcs_ring &&
 217                     adev->mman.buffer_funcs_ring->ready == false) {
 218                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 219                 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 220                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 221                         unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 222                         struct drm_mm_node *node = bo->mem.mm_node;
 223                         unsigned long pages_left;
 224
 225                         for (pages_left = bo->mem.num_pages;
 226                              pages_left;
 227                              pages_left -= node->size, node++) {
 228                                 if (node->start < fpfn)
 229                                         break;
 230                         }
 231
 232                         if (!pages_left)
 233                                 goto gtt;
 234
 235                         /* Try evicting to the CPU inaccessible part of VRAM
 236                          * first, but only set GTT as busy placement, so this
 237                          * BO will be evicted to GTT rather than causing other
 238                          * BOs to be evicted from VRAM
 239                          */
 240                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 241                                                          AMDGPU_GEM_DOMAIN_GTT);
 242                         abo->placements[0].fpfn = fpfn;
 243                         abo->placements[0].lpfn = 0;
 244                         abo->placement.busy_placement = &abo->placements[1];
 245                         abo->placement.num_busy_placement = 1;
 246                 } else {
 247 gtt:
 248                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 249                 }
 250                 break;
 251         case TTM_PL_TT:
 252         default:
 253                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 254         }
 255         *placement = abo->placement;
 256 }
 257
 258 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 259 {
 260         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 261
 262         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 263                 return -EPERM;
 264         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 265                                           filp->private_data);
 266 }
 267
 268 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 269                              struct ttm_mem_reg *new_mem)
 270 {
 271         struct ttm_mem_reg *old_mem = &bo->mem;
 272
 273         BUG_ON(old_mem->mm_node != NULL);
 274         *old_mem = *new_mem;
 275         new_mem->mm_node = NULL;
 276 }
 277
 278 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 279                                     struct drm_mm_node *mm_node,
 280                                     struct ttm_mem_reg *mem)
 281 {
 282         uint64_t addr = 0;
 283
 284         if (mem->mem_type != TTM_PL_TT ||
 285             amdgpu_gtt_mgr_is_allocated(mem)) {
 286                 addr = mm_node->start << PAGE_SHIFT;
 287                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 288         }
 289         return addr;
 290 }
 291
 292 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 293                             bool evict, bool no_wait_gpu,
 294                             struct ttm_mem_reg *new_mem,
 295                             struct ttm_mem_reg *old_mem)
 296 {
 297         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 298         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 299
 300         struct drm_mm_node *old_mm, *new_mm;
 301         uint64_t old_start, old_size, new_start, new_size;
 302         unsigned long num_pages;
 303         struct dma_fence *fence = NULL;
 304         int r;
 305
 306         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 307
 308         if (!ring->ready) {
 309                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 310                 return -EINVAL;
 311         }
 312
 313         old_mm = old_mem->mm_node;
 314         old_size = old_mm->size;
 315         old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
 316
 317         new_mm = new_mem->mm_node;
 318         new_size = new_mm->size;
 319         new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
 320
 321         num_pages = new_mem->num_pages;
 322         mutex_lock(&adev->mman.gtt_window_lock);
 323         while (num_pages) {
 324                 unsigned long cur_pages = min(min(old_size, new_size),
 325                                               (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
 326                 uint64_t from = old_start, to = new_start;
 327                 struct dma_fence *next;
 328
 329                 if (old_mem->mem_type == TTM_PL_TT &&
 330                     !amdgpu_gtt_mgr_is_allocated(old_mem)) {
 331                         r = amdgpu_map_buffer(bo, old_mem, cur_pages,
 332                                               old_start, 0, ring, &from);
 333                         if (r)
 334                                 goto error;
 335                 }
 336
 337                 if (new_mem->mem_type == TTM_PL_TT &&
 338                     !amdgpu_gtt_mgr_is_allocated(new_mem)) {
 339                         r = amdgpu_map_buffer(bo, new_mem, cur_pages,
 340                                               new_start, 1, ring, &to);
 341                         if (r)
 342                                 goto error;
 343                 }
 344
 345                 r = amdgpu_copy_buffer(ring, from, to,
 346                                        cur_pages * PAGE_SIZE,
 347                                        bo->resv, &next, false, true);
 348                 if (r)
 349                         goto error;
 350
 351                 dma_fence_put(fence);
 352                 fence = next;
 353
 354                 num_pages -= cur_pages;
 355                 if (!num_pages)
 356                         break;
 357
 358                 old_size -= cur_pages;
 359                 if (!old_size) {
 360                         old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
 361                         old_size = old_mm->size;
 362                 } else {
 363                         old_start += cur_pages * PAGE_SIZE;
 364                 }
 365
 366                 new_size -= cur_pages;
 367                 if (!new_size) {
 368                         new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
 369                         new_size = new_mm->size;
 370                 } else {
 371                         new_start += cur_pages * PAGE_SIZE;
 372                 }
 373         }
 374         mutex_unlock(&adev->mman.gtt_window_lock);
 375
 376         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 377         dma_fence_put(fence);
 378         return r;
 379
 380 error:
 381         mutex_unlock(&adev->mman.gtt_window_lock);
 382
 383         if (fence)
 384                 dma_fence_wait(fence, false);
 385         dma_fence_put(fence);
 386         return r;
 387 }
 388
 389 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 390                                 bool evict, bool interruptible,
 391                                 bool no_wait_gpu,
 392                                 struct ttm_mem_reg *new_mem)
 393 {
 394         struct amdgpu_device *adev;
 395         struct ttm_mem_reg *old_mem = &bo->mem;
 396         struct ttm_mem_reg tmp_mem;
 397         struct ttm_place placements;
 398         struct ttm_placement placement;
 399         int r;
 400
 401         adev = amdgpu_ttm_adev(bo->bdev);
 402         tmp_mem = *new_mem;
 403         tmp_mem.mm_node = NULL;
 404         placement.num_placement = 1;
 405         placement.placement = &placements;
 406         placement.num_busy_placement = 1;
 407         placement.busy_placement = &placements;
 408         placements.fpfn = 0;
 409         placements.lpfn = 0;
 410         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 411         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 412                              interruptible, no_wait_gpu);
 413         if (unlikely(r)) {
 414                 return r;
 415         }
 416
 417         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 418         if (unlikely(r)) {
 419                 goto out_cleanup;
 420         }
 421
 422         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 423         if (unlikely(r)) {
 424                 goto out_cleanup;
 425         }
 426         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 427         if (unlikely(r)) {
 428                 goto out_cleanup;
 429         }
 430         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 431 out_cleanup:
 432         ttm_bo_mem_put(bo, &tmp_mem);
 433         return r;
 434 }
 435
 436 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 437                                 bool evict, bool interruptible,
 438                                 bool no_wait_gpu,
 439                                 struct ttm_mem_reg *new_mem)
 440 {
 441         struct amdgpu_device *adev;
 442         struct ttm_mem_reg *old_mem = &bo->mem;
 443         struct ttm_mem_reg tmp_mem;
 444         struct ttm_placement placement;
 445         struct ttm_place placements;
 446         int r;
 447
 448         adev = amdgpu_ttm_adev(bo->bdev);
 449         tmp_mem = *new_mem;
 450         tmp_mem.mm_node = NULL;
 451         placement.num_placement = 1;
 452         placement.placement = &placements;
 453         placement.num_busy_placement = 1;
 454         placement.busy_placement = &placements;
 455         placements.fpfn = 0;
 456         placements.lpfn = 0;
 457         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 458         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 459                              interruptible, no_wait_gpu);
 460         if (unlikely(r)) {
 461                 return r;
 462         }
 463         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 464         if (unlikely(r)) {
 465                 goto out_cleanup;
 466         }
 467         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 468         if (unlikely(r)) {
 469                 goto out_cleanup;
 470         }
 471 out_cleanup:
 472         ttm_bo_mem_put(bo, &tmp_mem);
 473         return r;
 474 }
 475
 476 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 477                         bool evict, bool interruptible,
 478                         bool no_wait_gpu,
 479                         struct ttm_mem_reg *new_mem)
 480 {
 481         struct amdgpu_device *adev;
 482         struct amdgpu_bo *abo;
 483         struct ttm_mem_reg *old_mem = &bo->mem;
 484         int r;
 485
 486         /* Can't move a pinned BO */
 487         abo = container_of(bo, struct amdgpu_bo, tbo);
 488         if (WARN_ON_ONCE(abo->pin_count > 0))
 489                 return -EINVAL;
 490
 491         adev = amdgpu_ttm_adev(bo->bdev);
 492
 493         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 494                 amdgpu_move_null(bo, new_mem);
 495                 return 0;
 496         }
 497         if ((old_mem->mem_type == TTM_PL_TT &&
 498              new_mem->mem_type == TTM_PL_SYSTEM) ||
 499             (old_mem->mem_type == TTM_PL_SYSTEM &&
 500              new_mem->mem_type == TTM_PL_TT)) {
 501                 /* bind is enough */
 502                 amdgpu_move_null(bo, new_mem);
 503                 return 0;
 504         }
 505         if (adev->mman.buffer_funcs == NULL ||
 506             adev->mman.buffer_funcs_ring == NULL ||
 507             !adev->mman.buffer_funcs_ring->ready) {
 508                 /* use memcpy */
 509                 goto memcpy;
 510         }
 511
 512         if (old_mem->mem_type == TTM_PL_VRAM &&
 513             new_mem->mem_type == TTM_PL_SYSTEM) {
 514                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 515                                         no_wait_gpu, new_mem);
 516         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 517                    new_mem->mem_type == TTM_PL_VRAM) {
 518                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 519                                             no_wait_gpu, new_mem);
 520         } else {
 521                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 522         }
 523
 524         if (r) {
 525 memcpy:
 526                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 527                 if (r) {
 528                         return r;
 529                 }
 530         }
 531
 532         if (bo->type == ttm_bo_type_device &&
 533             new_mem->mem_type == TTM_PL_VRAM &&
 534             old_mem->mem_type != TTM_PL_VRAM) {
 535                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 536                  * accesses the BO after it's moved.
 537                  */
 538                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 539         }
 540
 541         /* update statistics */
 542         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 543         return 0;
 544 }
 545
 546 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 547 {
 548         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 549         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 550
 551         mem->bus.addr = NULL;
 552         mem->bus.offset = 0;
 553         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 554         mem->bus.base = 0;
 555         mem->bus.is_iomem = false;
 556         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 557                 return -EINVAL;
 558         switch (mem->mem_type) {
 559         case TTM_PL_SYSTEM:
 560                 /* system memory */
 561                 return 0;
 562         case TTM_PL_TT:
 563                 break;
 564         case TTM_PL_VRAM:
 565                 mem->bus.offset = mem->start << PAGE_SHIFT;
 566                 /* check if it's visible */
 567                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 568                         return -EINVAL;
 569                 mem->bus.base = adev->mc.aper_base;
 570                 mem->bus.is_iomem = true;
 571                 break;
 572         default:
 573                 return -EINVAL;
 574         }
 575         return 0;
 576 }
 577
 578 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 579 {
 580 }
 581
 582 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 583                                            unsigned long page_offset)
 584 {
 585         struct drm_mm_node *mm = bo->mem.mm_node;
 586         uint64_t size = mm->size;
 587         uint64_t offset = page_offset;
 588
 589         page_offset = do_div(offset, size);
 590         mm += offset;
 591         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
 592 }
 593
 594 /*
 595  * TTM backend functions.
 596  */
 597 struct amdgpu_ttm_gup_task_list {
 598         struct list_head        list;
 599         struct task_struct      *task;
 600 };
 601
 602 struct amdgpu_ttm_tt {
 603         struct ttm_dma_tt       ttm;
 604         struct amdgpu_device    *adev;
 605         u64                     offset;
 606         uint64_t                userptr;
 607         struct mm_struct        *usermm;
 608         uint32_t                userflags;
 609         spinlock_t              guptasklock;
 610         struct list_head        guptasks;
 611         atomic_t                mmu_invalidations;
 612         struct list_head        list;
 613 };
 614
 615 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 616 {
 617         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 618         unsigned int flags = 0;
 619         unsigned pinned = 0;
 620         int r;
 621
 622         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 623                 flags |= FOLL_WRITE;
 624
 625         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 626                 /* check that we only use anonymous memory
 627                    to prevent problems with writeback */
 628                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 629                 struct vm_area_struct *vma;
 630
 631                 vma = find_vma(gtt->usermm, gtt->userptr);
 632                 if (!vma || vma->vm_file || vma->vm_end < end)
 633                         return -EPERM;
 634         }
 635
 636         do {
 637                 unsigned num_pages = ttm->num_pages - pinned;
 638                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 639                 struct page **p = pages + pinned;
 640                 struct amdgpu_ttm_gup_task_list guptask;
 641
 642                 guptask.task = current;
 643                 spin_lock(&gtt->guptasklock);
 644                 list_add(&guptask.list, &gtt->guptasks);
 645                 spin_unlock(&gtt->guptasklock);
 646
 647                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 648
 649                 spin_lock(&gtt->guptasklock);
 650                 list_del(&guptask.list);
 651                 spin_unlock(&gtt->guptasklock);
 652
 653                 if (r < 0)
 654                         goto release_pages;
 655
 656                 pinned += r;
 657
 658         } while (pinned < ttm->num_pages);
 659
 660         return 0;
 661
 662 release_pages:
 663         release_pages(pages, pinned, 0);
 664         return r;
 665 }
 666
 667 static void amdgpu_trace_dma_map(struct ttm_tt *ttm)
 668 {
 669         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 670         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 671
 672         ttm_trace_dma_map(adev->dev, &gtt->ttm);
 673 }
 674
 675 static void amdgpu_trace_dma_unmap(struct ttm_tt *ttm)
 676 {
 677         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 678         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 679
 680         ttm_trace_dma_unmap(adev->dev, &gtt->ttm);
 681 }
 682
 683 /* prepare the sg table with the user pages */
 684 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 685 {
 686         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 687         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 688         unsigned nents;
 689         int r;
 690
 691         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 692         enum dma_data_direction direction = write ?
 693                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 694
 695         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 696                                       ttm->num_pages << PAGE_SHIFT,
 697                                       GFP_KERNEL);
 698         if (r)
 699                 goto release_sg;
 700
 701         r = -ENOMEM;
 702         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 703         if (nents != ttm->sg->nents)
 704                 goto release_sg;
 705
 706         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 707                                          gtt->ttm.dma_address, ttm->num_pages);
 708
 709         amdgpu_trace_dma_map(ttm);
 710
 711         return 0;
 712
 713 release_sg:
 714         kfree(ttm->sg);
 715         return r;
 716 }
 717
 718 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 719 {
 720         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 721         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 722         struct sg_page_iter sg_iter;
 723
 724         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 725         enum dma_data_direction direction = write ?
 726                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 727
 728         /* double check that we don't free the table twice */
 729         if (!ttm->sg->sgl)
 730                 return;
 731
 732         /* free the sg table and pages again */
 733         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 734
 735         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 736                 struct page *page = sg_page_iter_page(&sg_iter);
 737                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 738                         set_page_dirty(page);
 739
 740                 mark_page_accessed(page);
 741                 put_page(page);
 742         }
 743
 744         amdgpu_trace_dma_unmap(ttm);
 745
 746         sg_free_table(ttm->sg);
 747 }
 748
 749 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 750                                    struct ttm_mem_reg *bo_mem)
 751 {
 752         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 753         uint64_t flags;
 754         int r = 0;
 755
 756         if (gtt->userptr) {
 757                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 758                 if (r) {
 759                         DRM_ERROR("failed to pin userptr\n");
 760                         return r;
 761                 }
 762         }
 763         if (!ttm->num_pages) {
 764                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 765                      ttm->num_pages, bo_mem, ttm);
 766         }
 767
 768         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 769             bo_mem->mem_type == AMDGPU_PL_GWS ||
 770             bo_mem->mem_type == AMDGPU_PL_OA)
 771                 return -EINVAL;
 772
 773         if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
 774                 return 0;
 775
 776         spin_lock(&gtt->adev->gtt_list_lock);
 777         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 778         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 779         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 780                 ttm->pages, gtt->ttm.dma_address, flags);
 781
 782         if (r) {
 783                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 784                           ttm->num_pages, gtt->offset);
 785                 goto error_gart_bind;
 786         }
 787
 788         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 789 error_gart_bind:
 790         spin_unlock(&gtt->adev->gtt_list_lock);
 791         return r;
 792 }
 793
 794 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 795 {
 796         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 797
 798         return gtt && !list_empty(&gtt->list);
 799 }
 800
 801 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 802 {
 803         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 804         struct ttm_tt *ttm = bo->ttm;
 805         struct ttm_mem_reg tmp;
 806
 807         struct ttm_placement placement;
 808         struct ttm_place placements;
 809         int r;
 810
 811         if (!ttm || amdgpu_ttm_is_bound(ttm))
 812                 return 0;
 813
 814         tmp = bo->mem;
 815         tmp.mm_node = NULL;
 816         placement.num_placement = 1;
 817         placement.placement = &placements;
 818         placement.num_busy_placement = 1;
 819         placement.busy_placement = &placements;
 820         placements.fpfn = 0;
 821         placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
 822         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 823
 824         r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
 825         if (unlikely(r))
 826                 return r;
 827
 828         r = ttm_bo_move_ttm(bo, true, false, &tmp);
 829         if (unlikely(r))
 830                 ttm_bo_mem_put(bo, &tmp);
 831         else
 832                 bo->offset = (bo->mem.start << PAGE_SHIFT) +
 833                         bo->bdev->man[bo->mem.mem_type].gpu_offset;
 834
 835         return r;
 836 }
 837
 838 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 839 {
 840         struct amdgpu_ttm_tt *gtt, *tmp;
 841         struct ttm_mem_reg bo_mem;
 842         uint64_t flags;
 843         int r;
 844
 845         bo_mem.mem_type = TTM_PL_TT;
 846         spin_lock(&adev->gtt_list_lock);
 847         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 848                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 849                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 850                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 851                                      flags);
 852                 if (r) {
 853                         spin_unlock(&adev->gtt_list_lock);
 854                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 855                                   gtt->ttm.ttm.num_pages, gtt->offset);
 856                         return r;
 857                 }
 858         }
 859         spin_unlock(&adev->gtt_list_lock);
 860         return 0;
 861 }
 862
 863 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 864 {
 865         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 866         int r;
 867
 868         if (gtt->userptr)
 869                 amdgpu_ttm_tt_unpin_userptr(ttm);
 870
 871         if (!amdgpu_ttm_is_bound(ttm))
 872                 return 0;
 873
 874         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 875         spin_lock(&gtt->adev->gtt_list_lock);
 876         r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 877         if (r) {
 878                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 879                           gtt->ttm.ttm.num_pages, gtt->offset);
 880                 goto error_unbind;
 881         }
 882         list_del_init(&gtt->list);
 883 error_unbind:
 884         spin_unlock(&gtt->adev->gtt_list_lock);
 885         return r;
 886 }
 887
 888 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 889 {
 890         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 891
 892         ttm_dma_tt_fini(&gtt->ttm);
 893         kfree(gtt);
 894 }
 895
 896 static struct ttm_backend_func amdgpu_backend_func = {
 897         .bind = &amdgpu_ttm_backend_bind,
 898         .unbind = &amdgpu_ttm_backend_unbind,
 899         .destroy = &amdgpu_ttm_backend_destroy,
 900 };
 901
 902 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 903                                     unsigned long size, uint32_t page_flags,
 904                                     struct page *dummy_read_page)
 905 {
 906         struct amdgpu_device *adev;
 907         struct amdgpu_ttm_tt *gtt;
 908
 909         adev = amdgpu_ttm_adev(bdev);
 910
 911         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 912         if (gtt == NULL) {
 913                 return NULL;
 914         }
 915         gtt->ttm.ttm.func = &amdgpu_backend_func;
 916         gtt->adev = adev;
 917         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 918                 kfree(gtt);
 919                 return NULL;
 920         }
 921         INIT_LIST_HEAD(&gtt->list);
 922         return &gtt->ttm.ttm;
 923 }
 924
 925 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 926 {
 927         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 928         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 929         int r;
 930         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 931
 932         if (ttm->state != tt_unpopulated)
 933                 return 0;
 934
 935         if (gtt && gtt->userptr) {
 936                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 937                 if (!ttm->sg)
 938                         return -ENOMEM;
 939
 940                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 941                 ttm->state = tt_unbound;
 942                 return 0;
 943         }
 944
 945         if (slave && ttm->sg) {
 946                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 947                                                  gtt->ttm.dma_address, ttm->num_pages);
 948                 ttm->state = tt_unbound;
 949                 r = 0;
 950                 goto trace_mappings;
 951         }
 952
 953 #ifdef CONFIG_SWIOTLB
 954         if (swiotlb_nr_tbl()) {
 955                 r = ttm_dma_populate(&gtt->ttm, adev->dev);
 956                 goto trace_mappings;
 957         }
 958 #endif
 959
 960         r = ttm_populate_and_map_pages(adev->dev, &gtt->ttm);
 961 trace_mappings:
 962         if (likely(!r))
 963                 amdgpu_trace_dma_map(ttm);
 964         return r;
 965 }
 966
 967 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 968 {
 969         struct amdgpu_device *adev;
 970         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 971         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 972
 973         if (gtt && gtt->userptr) {
 974                 kfree(ttm->sg);
 975                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 976                 return;
 977         }
 978
 979         if (slave)
 980                 return;
 981
 982         adev = amdgpu_ttm_adev(ttm->bdev);
 983
 984         amdgpu_trace_dma_unmap(ttm);
 985
 986 #ifdef CONFIG_SWIOTLB
 987         if (swiotlb_nr_tbl()) {
 988                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 989                 return;
 990         }
 991 #endif
 992
 993         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
 994 }
 995
 996 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 997                               uint32_t flags)
 998 {
 999         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1000
1001         if (gtt == NULL)
1002                 return -EINVAL;
1003
1004         gtt->userptr = addr;
1005         gtt->usermm = current->mm;
1006         gtt->userflags = flags;
1007         spin_lock_init(&gtt->guptasklock);
1008         INIT_LIST_HEAD(&gtt->guptasks);
1009         atomic_set(&gtt->mmu_invalidations, 0);
1010
1011         return 0;
1012 }
1013
1014 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1015 {
1016         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1017
1018         if (gtt == NULL)
1019                 return NULL;
1020
1021         return gtt->usermm;
1022 }
1023
1024 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1025                                   unsigned long end)
1026 {
1027         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1028         struct amdgpu_ttm_gup_task_list *entry;
1029         unsigned long size;
1030
1031         if (gtt == NULL || !gtt->userptr)
1032                 return false;
1033
1034         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1035         if (gtt->userptr > end || gtt->userptr + size <= start)
1036                 return false;
1037
1038         spin_lock(&gtt->guptasklock);
1039         list_for_each_entry(entry, &gtt->guptasks, list) {
1040                 if (entry->task == current) {
1041                         spin_unlock(&gtt->guptasklock);
1042                         return false;
1043                 }
1044         }
1045         spin_unlock(&gtt->guptasklock);
1046
1047         atomic_inc(&gtt->mmu_invalidations);
1048
1049         return true;
1050 }
1051
1052 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1053                                        int *last_invalidated)
1054 {
1055         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1056         int prev_invalidated = *last_invalidated;
1057
1058         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1059         return prev_invalidated != *last_invalidated;
1060 }
1061
1062 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1063 {
1064         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1065
1066         if (gtt == NULL)
1067                 return false;
1068
1069         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1070 }
1071
1072 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1073                                  struct ttm_mem_reg *mem)
1074 {
1075         uint64_t flags = 0;
1076
1077         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1078                 flags |= AMDGPU_PTE_VALID;
1079
1080         if (mem && mem->mem_type == TTM_PL_TT) {
1081                 flags |= AMDGPU_PTE_SYSTEM;
1082
1083                 if (ttm->caching_state == tt_cached)
1084                         flags |= AMDGPU_PTE_SNOOPED;
1085         }
1086
1087         flags |= adev->gart.gart_pte_flags;
1088         flags |= AMDGPU_PTE_READABLE;
1089
1090         if (!amdgpu_ttm_tt_is_readonly(ttm))
1091                 flags |= AMDGPU_PTE_WRITEABLE;
1092
1093         return flags;
1094 }
1095
1096 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1097                                             const struct ttm_place *place)
1098 {
1099         unsigned long num_pages = bo->mem.num_pages;
1100         struct drm_mm_node *node = bo->mem.mm_node;
1101
1102         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1103                 return ttm_bo_eviction_valuable(bo, place);
1104
1105         switch (bo->mem.mem_type) {
1106         case TTM_PL_TT:
1107                 return true;
1108
1109         case TTM_PL_VRAM:
1110                 /* Check each drm MM node individually */
1111                 while (num_pages) {
1112                         if (place->fpfn < (node->start + node->size) &&
1113                             !(place->lpfn && place->lpfn <= node->start))
1114                                 return true;
1115
1116                         num_pages -= node->size;
1117                         ++node;
1118                 }
1119                 break;
1120
1121         default:
1122                 break;
1123         }
1124
1125         return ttm_bo_eviction_valuable(bo, place);
1126 }
1127
1128 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1129                                     unsigned long offset,
1130                                     void *buf, int len, int write)
1131 {
1132         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
1133         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1134         struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
1135         uint32_t value = 0;
1136         int ret = 0;
1137         uint64_t pos;
1138         unsigned long flags;
1139
1140         if (bo->mem.mem_type != TTM_PL_VRAM)
1141                 return -EIO;
1142
1143         while (offset >= (nodes->size << PAGE_SHIFT)) {
1144                 offset -= nodes->size << PAGE_SHIFT;
1145                 ++nodes;
1146         }
1147         pos = (nodes->start << PAGE_SHIFT) + offset;
1148
1149         while (len && pos < adev->mc.mc_vram_size) {
1150                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1151                 uint32_t bytes = 4 - (pos & 3);
1152                 uint32_t shift = (pos & 3) * 8;
1153                 uint32_t mask = 0xffffffff << shift;
1154
1155                 if (len < bytes) {
1156                         mask &= 0xffffffff >> (bytes - len) * 8;
1157                         bytes = len;
1158                 }
1159
1160                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1161                 WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1162                 WREG32(mmMM_INDEX_HI, aligned_pos >> 31);
1163                 if (!write || mask != 0xffffffff)
1164                         value = RREG32(mmMM_DATA);
1165                 if (write) {
1166                         value &= ~mask;
1167                         value |= (*(uint32_t *)buf << shift) & mask;
1168                         WREG32(mmMM_DATA, value);
1169                 }
1170                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1171                 if (!write) {
1172                         value = (value & mask) >> shift;
1173                         memcpy(buf, &value, bytes);
1174                 }
1175
1176                 ret += bytes;
1177                 buf = (uint8_t *)buf + bytes;
1178                 pos += bytes;
1179                 len -= bytes;
1180                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1181                         ++nodes;
1182                         pos = (nodes->start << PAGE_SHIFT);
1183                 }
1184         }
1185
1186         return ret;
1187 }
1188
1189 static struct ttm_bo_driver amdgpu_bo_driver = {
1190         .ttm_tt_create = &amdgpu_ttm_tt_create,
1191         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1192         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1193         .invalidate_caches = &amdgpu_invalidate_caches,
1194         .init_mem_type = &amdgpu_init_mem_type,
1195         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1196         .evict_flags = &amdgpu_evict_flags,
1197         .move = &amdgpu_bo_move,
1198         .verify_access = &amdgpu_verify_access,
1199         .move_notify = &amdgpu_bo_move_notify,
1200         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1201         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1202         .io_mem_free = &amdgpu_ttm_io_mem_free,
1203         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1204         .access_memory = &amdgpu_ttm_access_memory
1205 };
1206
1207 int amdgpu_ttm_init(struct amdgpu_device *adev)
1208 {
1209         uint64_t gtt_size;
1210         int r;
1211         u64 vis_vram_limit;
1212
1213         r = amdgpu_ttm_global_init(adev);
1214         if (r) {
1215                 return r;
1216         }
1217         /* No others user of address space so set it to 0 */
1218         r = ttm_bo_device_init(&adev->mman.bdev,
1219                                adev->mman.bo_global_ref.ref.object,
1220                                &amdgpu_bo_driver,
1221                                adev->ddev->anon_inode->i_mapping,
1222                                DRM_FILE_PAGE_OFFSET,
1223                                adev->need_dma32);
1224         if (r) {
1225                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1226                 return r;
1227         }
1228         adev->mman.initialized = true;
1229         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1230                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1231         if (r) {
1232                 DRM_ERROR("Failed initializing VRAM heap.\n");
1233                 return r;
1234         }
1235
1236         /* Reduce size of CPU-visible VRAM if requested */
1237         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1238         if (amdgpu_vis_vram_limit > 0 &&
1239             vis_vram_limit <= adev->mc.visible_vram_size)
1240                 adev->mc.visible_vram_size = vis_vram_limit;
1241
1242         /* Change the size here instead of the init above so only lpfn is affected */
1243         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1244
1245         r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
1246                                     AMDGPU_GEM_DOMAIN_VRAM,
1247                                     &adev->stolen_vga_memory,
1248                                     NULL, NULL);
1249         if (r)
1250                 return r;
1251         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1252                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1253
1254         if (amdgpu_gtt_size == -1)
1255                 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1256                                adev->mc.mc_vram_size);
1257         else
1258                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1259         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1260         if (r) {
1261                 DRM_ERROR("Failed initializing GTT heap.\n");
1262                 return r;
1263         }
1264         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1265                  (unsigned)(gtt_size / (1024 * 1024)));
1266
1267         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1268         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1269         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1270         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1271         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1272         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1273         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1274         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1275         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1276         /* GDS Memory */
1277         if (adev->gds.mem.total_size) {
1278                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1279                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1280                 if (r) {
1281                         DRM_ERROR("Failed initializing GDS heap.\n");
1282                         return r;
1283                 }
1284         }
1285
1286         /* GWS */
1287         if (adev->gds.gws.total_size) {
1288                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1289                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1290                 if (r) {
1291                         DRM_ERROR("Failed initializing gws heap.\n");
1292                         return r;
1293                 }
1294         }
1295
1296         /* OA */
1297         if (adev->gds.oa.total_size) {
1298                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1299                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1300                 if (r) {
1301                         DRM_ERROR("Failed initializing oa heap.\n");
1302                         return r;
1303                 }
1304         }
1305
1306         r = amdgpu_ttm_debugfs_init(adev);
1307         if (r) {
1308                 DRM_ERROR("Failed to init debugfs\n");
1309                 return r;
1310         }
1311         return 0;
1312 }
1313
1314 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1315 {
1316         int r;
1317
1318         if (!adev->mman.initialized)
1319                 return;
1320         amdgpu_ttm_debugfs_fini(adev);
1321         if (adev->stolen_vga_memory) {
1322                 r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
1323                 if (r == 0) {
1324                         amdgpu_bo_unpin(adev->stolen_vga_memory);
1325                         amdgpu_bo_unreserve(adev->stolen_vga_memory);
1326                 }
1327                 amdgpu_bo_unref(&adev->stolen_vga_memory);
1328         }
1329         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1330         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1331         if (adev->gds.mem.total_size)
1332                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1333         if (adev->gds.gws.total_size)
1334                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1335         if (adev->gds.oa.total_size)
1336                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1337         ttm_bo_device_release(&adev->mman.bdev);
1338         amdgpu_gart_fini(adev);
1339         amdgpu_ttm_global_fini(adev);
1340         adev->mman.initialized = false;
1341         DRM_INFO("amdgpu: ttm finalized\n");
1342 }
1343
1344 /* this should only be called at bootup or when userspace
1345  * isn't running */
1346 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1347 {
1348         struct ttm_mem_type_manager *man;
1349
1350         if (!adev->mman.initialized)
1351                 return;
1352
1353         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1354         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1355         man->size = size >> PAGE_SHIFT;
1356 }
1357
1358 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1359 {
1360         struct drm_file *file_priv;
1361         struct amdgpu_device *adev;
1362
1363         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1364                 return -EINVAL;
1365
1366         file_priv = filp->private_data;
1367         adev = file_priv->minor->dev->dev_private;
1368         if (adev == NULL)
1369                 return -EINVAL;
1370
1371         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1372 }
1373
1374 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1375                              struct ttm_mem_reg *mem, unsigned num_pages,
1376                              uint64_t offset, unsigned window,
1377                              struct amdgpu_ring *ring,
1378                              uint64_t *addr)
1379 {
1380         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1381         struct amdgpu_device *adev = ring->adev;
1382         struct ttm_tt *ttm = bo->ttm;
1383         struct amdgpu_job *job;
1384         unsigned num_dw, num_bytes;
1385         dma_addr_t *dma_address;
1386         struct dma_fence *fence;
1387         uint64_t src_addr, dst_addr;
1388         uint64_t flags;
1389         int r;
1390
1391         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1392                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1393
1394         *addr = adev->mc.gart_start;
1395         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1396                 AMDGPU_GPU_PAGE_SIZE;
1397
1398         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1399         while (num_dw & 0x7)
1400                 num_dw++;
1401
1402         num_bytes = num_pages * 8;
1403
1404         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1405         if (r)
1406                 return r;
1407
1408         src_addr = num_dw * 4;
1409         src_addr += job->ibs[0].gpu_addr;
1410
1411         dst_addr = adev->gart.table_addr;
1412         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1413         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1414                                 dst_addr, num_bytes);
1415
1416         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1417         WARN_ON(job->ibs[0].length_dw > num_dw);
1418
1419         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1420         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1421         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1422                             &job->ibs[0].ptr[num_dw]);
1423         if (r)
1424                 goto error_free;
1425
1426         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1427                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1428         if (r)
1429                 goto error_free;
1430
1431         dma_fence_put(fence);
1432
1433         return r;
1434
1435 error_free:
1436         amdgpu_job_free(job);
1437         return r;
1438 }
1439
1440 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1441                        uint64_t dst_offset, uint32_t byte_count,
1442                        struct reservation_object *resv,
1443                        struct dma_fence **fence, bool direct_submit,
1444                        bool vm_needs_flush)
1445 {
1446         struct amdgpu_device *adev = ring->adev;
1447         struct amdgpu_job *job;
1448
1449         uint32_t max_bytes;
1450         unsigned num_loops, num_dw;
1451         unsigned i;
1452         int r;
1453
1454         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1455         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1456         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1457
1458         /* for IB padding */
1459         while (num_dw & 0x7)
1460                 num_dw++;
1461
1462         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1463         if (r)
1464                 return r;
1465
1466         job->vm_needs_flush = vm_needs_flush;
1467         if (resv) {
1468                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1469                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1470                 if (r) {
1471                         DRM_ERROR("sync failed (%d).\n", r);
1472                         goto error_free;
1473                 }
1474         }
1475
1476         for (i = 0; i < num_loops; i++) {
1477                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1478
1479                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1480                                         dst_offset, cur_size_in_bytes);
1481
1482                 src_offset += cur_size_in_bytes;
1483                 dst_offset += cur_size_in_bytes;
1484                 byte_count -= cur_size_in_bytes;
1485         }
1486
1487         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1488         WARN_ON(job->ibs[0].length_dw > num_dw);
1489         if (direct_submit) {
1490                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1491                                        NULL, fence);
1492                 job->fence = dma_fence_get(*fence);
1493                 if (r)
1494                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1495                 amdgpu_job_free(job);
1496         } else {
1497                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1498                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1499                 if (r)
1500                         goto error_free;
1501         }
1502
1503         return r;
1504
1505 error_free:
1506         amdgpu_job_free(job);
1507         return r;
1508 }
1509
1510 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1511                        uint64_t src_data,
1512                        struct reservation_object *resv,
1513                        struct dma_fence **fence)
1514 {
1515         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1516         /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/
1517         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1518         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1519
1520         struct drm_mm_node *mm_node;
1521         unsigned long num_pages;
1522         unsigned int num_loops, num_dw;
1523
1524         struct amdgpu_job *job;
1525         int r;
1526
1527         if (!ring->ready) {
1528                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1529                 return -EINVAL;
1530         }
1531
1532         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1533                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1534                 if (r)
1535                         return r;
1536         }
1537
1538         num_pages = bo->tbo.num_pages;
1539         mm_node = bo->tbo.mem.mm_node;
1540         num_loops = 0;
1541         while (num_pages) {
1542                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1543
1544                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1545                 num_pages -= mm_node->size;
1546                 ++mm_node;
1547         }
1548
1549         /* 10 double words for each SDMA_OP_PTEPDE cmd */
1550         num_dw = num_loops * 10;
1551
1552         /* for IB padding */
1553         num_dw += 64;
1554
1555         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1556         if (r)
1557                 return r;
1558
1559         if (resv) {
1560                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1561                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1562                 if (r) {
1563                         DRM_ERROR("sync failed (%d).\n", r);
1564                         goto error_free;
1565                 }
1566         }
1567
1568         num_pages = bo->tbo.num_pages;
1569         mm_node = bo->tbo.mem.mm_node;
1570
1571         while (num_pages) {
1572                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1573                 uint64_t dst_addr;
1574
1575                 WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
1576
1577                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1578                 while (byte_count) {
1579                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1580
1581                         amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
1582                                         dst_addr, 0,
1583                                         cur_size_in_bytes >> 3, 0,
1584                                         src_data);
1585
1586                         dst_addr += cur_size_in_bytes;
1587                         byte_count -= cur_size_in_bytes;
1588                 }
1589
1590                 num_pages -= mm_node->size;
1591                 ++mm_node;
1592         }
1593
1594         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1595         WARN_ON(job->ibs[0].length_dw > num_dw);
1596         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1597                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1598         if (r)
1599                 goto error_free;
1600
1601         return 0;
1602
1603 error_free:
1604         amdgpu_job_free(job);
1605         return r;
1606 }
1607
1608 #if defined(CONFIG_DEBUG_FS)
1609
1610 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1611 {
1612         struct drm_info_node *node = (struct drm_info_node *)m->private;
1613         unsigned ttm_pl = *(int *)node->info_ent->data;
1614         struct drm_device *dev = node->minor->dev;
1615         struct amdgpu_device *adev = dev->dev_private;
1616         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1617         struct drm_printer p = drm_seq_file_printer(m);
1618
1619         man->func->debug(man, &p);
1620         return 0;
1621 }
1622
1623 static int ttm_pl_vram = TTM_PL_VRAM;
1624 static int ttm_pl_tt = TTM_PL_TT;
1625
1626 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1627         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1628         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1629         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1630 #ifdef CONFIG_SWIOTLB
1631         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1632 #endif
1633 };
1634
1635 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1636                                     size_t size, loff_t *pos)
1637 {
1638         struct amdgpu_device *adev = file_inode(f)->i_private;
1639         ssize_t result = 0;
1640         int r;
1641
1642         if (size & 0x3 || *pos & 0x3)
1643                 return -EINVAL;
1644
1645         if (*pos >= adev->mc.mc_vram_size)
1646                 return -ENXIO;
1647
1648         while (size) {
1649                 unsigned long flags;
1650                 uint32_t value;
1651
1652                 if (*pos >= adev->mc.mc_vram_size)
1653                         return result;
1654
1655                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1656                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1657                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1658                 value = RREG32(mmMM_DATA);
1659                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1660
1661                 r = put_user(value, (uint32_t *)buf);
1662                 if (r)
1663                         return r;
1664
1665                 result += 4;
1666                 buf += 4;
1667                 *pos += 4;
1668                 size -= 4;
1669         }
1670
1671         return result;
1672 }
1673
1674 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1675                                     size_t size, loff_t *pos)
1676 {
1677         struct amdgpu_device *adev = file_inode(f)->i_private;
1678         ssize_t result = 0;
1679         int r;
1680
1681         if (size & 0x3 || *pos & 0x3)
1682                 return -EINVAL;
1683
1684         if (*pos >= adev->mc.mc_vram_size)
1685                 return -ENXIO;
1686
1687         while (size) {
1688                 unsigned long flags;
1689                 uint32_t value;
1690
1691                 if (*pos >= adev->mc.mc_vram_size)
1692                         return result;
1693
1694                 r = get_user(value, (uint32_t *)buf);
1695                 if (r)
1696                         return r;
1697
1698                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1699                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1700                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1701                 WREG32(mmMM_DATA, value);
1702                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1703
1704                 result += 4;
1705                 buf += 4;
1706                 *pos += 4;
1707                 size -= 4;
1708         }
1709
1710         return result;
1711 }
1712
1713 static const struct file_operations amdgpu_ttm_vram_fops = {
1714         .owner = THIS_MODULE,
1715         .read = amdgpu_ttm_vram_read,
1716         .write = amdgpu_ttm_vram_write,
1717         .llseek = default_llseek,
1718 };
1719
1720 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1721
1722 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1723                                    size_t size, loff_t *pos)
1724 {
1725         struct amdgpu_device *adev = file_inode(f)->i_private;
1726         ssize_t result = 0;
1727         int r;
1728
1729         while (size) {
1730                 loff_t p = *pos / PAGE_SIZE;
1731                 unsigned off = *pos & ~PAGE_MASK;
1732                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1733                 struct page *page;
1734                 void *ptr;
1735
1736                 if (p >= adev->gart.num_cpu_pages)
1737                         return result;
1738
1739                 page = adev->gart.pages[p];
1740                 if (page) {
1741                         ptr = kmap(page);
1742                         ptr += off;
1743
1744                         r = copy_to_user(buf, ptr, cur_size);
1745                         kunmap(adev->gart.pages[p]);
1746                 } else
1747                         r = clear_user(buf, cur_size);
1748
1749                 if (r)
1750                         return -EFAULT;
1751
1752                 result += cur_size;
1753                 buf += cur_size;
1754                 *pos += cur_size;
1755                 size -= cur_size;
1756         }
1757
1758         return result;
1759 }
1760
1761 static const struct file_operations amdgpu_ttm_gtt_fops = {
1762         .owner = THIS_MODULE,
1763         .read = amdgpu_ttm_gtt_read,
1764         .llseek = default_llseek
1765 };
1766
1767 #endif
1768
1769 #endif
1770
1771 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1772 {
1773 #if defined(CONFIG_DEBUG_FS)
1774         unsigned count;
1775
1776         struct drm_minor *minor = adev->ddev->primary;
1777         struct dentry *ent, *root = minor->debugfs_root;
1778
1779         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1780                                   adev, &amdgpu_ttm_vram_fops);
1781         if (IS_ERR(ent))
1782                 return PTR_ERR(ent);
1783         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1784         adev->mman.vram = ent;
1785
1786 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1787         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1788                                   adev, &amdgpu_ttm_gtt_fops);
1789         if (IS_ERR(ent))
1790                 return PTR_ERR(ent);
1791         i_size_write(ent->d_inode, adev->mc.gart_size);
1792         adev->mman.gtt = ent;
1793
1794 #endif
1795         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1796
1797 #ifdef CONFIG_SWIOTLB
1798         if (!swiotlb_nr_tbl())
1799                 --count;
1800 #endif
1801
1802         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1803 #else
1804
1805         return 0;
1806 #endif
1807 }
1808
1809 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1810 {
1811 #if defined(CONFIG_DEBUG_FS)
1812
1813         debugfs_remove(adev->mman.vram);
1814         adev->mman.vram = NULL;
1815
1816 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1817         debugfs_remove(adev->mman.gtt);
1818         adev->mman.gtt = NULL;
1819 #endif
1820
1821 #endif
1822 }