drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  35 {
  36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  37
  38         if (robj) {
  39                 if (robj->gem_base.import_attach)
  40                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  41                 amdgpu_mn_unregister(robj);
  42                 amdgpu_bo_unref(&robj);
  43         }
  44 }
  45
  46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  47                                 int alignment, u32 initial_domain,
  48                                 u64 flags, bool kernel,
  49                                 struct drm_gem_object **obj)
  50 {
  51         struct amdgpu_bo *robj;
  52         int r;
  53
  54         *obj = NULL;
  55         /* At least align on page size */
  56         if (alignment < PAGE_SIZE) {
  57                 alignment = PAGE_SIZE;
  58         }
  59
  60 retry:
  61         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  62                              flags, NULL, NULL, 0, &robj);
  63         if (r) {
  64                 if (r != -ERESTARTSYS) {
  65                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  66                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  67                                 goto retry;
  68                         }
  69                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  70                                   size, initial_domain, alignment, r);
  71                 }
  72                 return r;
  73         }
  74         *obj = &robj->gem_base;
  75
  76         return 0;
  77 }
  78
  79 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  80 {
  81         struct drm_device *ddev = adev->ddev;
  82         struct drm_file *file;
  83
  84         mutex_lock(&ddev->filelist_mutex);
  85
  86         list_for_each_entry(file, &ddev->filelist, lhead) {
  87                 struct drm_gem_object *gobj;
  88                 int handle;
  89
  90                 WARN_ONCE(1, "Still active user space clients!\n");
  91                 spin_lock(&file->table_lock);
  92                 idr_for_each_entry(&file->object_idr, gobj, handle) {
  93                         WARN_ONCE(1, "And also active allocations!\n");
  94                         drm_gem_object_put_unlocked(gobj);
  95                 }
  96                 idr_destroy(&file->object_idr);
  97                 spin_unlock(&file->table_lock);
  98         }
  99
 100         mutex_unlock(&ddev->filelist_mutex);
 101 }
 102
 103 /*
 104  * Call from drm_gem_handle_create which appear in both new and open ioctl
 105  * case.
 106  */
 107 int amdgpu_gem_object_open(struct drm_gem_object *obj,
 108                            struct drm_file *file_priv)
 109 {
 110         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 111         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 112         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 113         struct amdgpu_vm *vm = &fpriv->vm;
 114         struct amdgpu_bo_va *bo_va;
 115         int r;
 116         r = amdgpu_bo_reserve(abo, false);
 117         if (r)
 118                 return r;
 119
 120         bo_va = amdgpu_vm_bo_find(vm, abo);
 121         if (!bo_va) {
 122                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 123         } else {
 124                 ++bo_va->ref_count;
 125         }
 126         amdgpu_bo_unreserve(abo);
 127         return 0;
 128 }
 129
 130 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 131                              struct drm_file *file_priv)
 132 {
 133         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 134         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 135         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 136         struct amdgpu_vm *vm = &fpriv->vm;
 137
 138         struct amdgpu_bo_list_entry vm_pd;
 139         struct list_head list;
 140         struct ttm_validate_buffer tv;
 141         struct ww_acquire_ctx ticket;
 142         struct amdgpu_bo_va *bo_va;
 143         int r;
 144
 145         INIT_LIST_HEAD(&list);
 146
 147         tv.bo = &bo->tbo;
 148         tv.shared = true;
 149         list_add(&tv.head, &list);
 150
 151         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 152
 153         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
 154         if (r) {
 155                 dev_err(adev->dev, "leaking bo va because "
 156                         "we fail to reserve bo (%d)\n", r);
 157                 return;
 158         }
 159         bo_va = amdgpu_vm_bo_find(vm, bo);
 160         if (bo_va && --bo_va->ref_count == 0) {
 161                 amdgpu_vm_bo_rmv(adev, bo_va);
 162
 163                 if (amdgpu_vm_ready(adev, vm)) {
 164                         struct dma_fence *fence = NULL;
 165
 166                         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 167                         if (unlikely(r)) {
 168                                 dev_err(adev->dev, "failed to clear page "
 169                                         "tables on GEM object close (%d)\n", r);
 170                         }
 171
 172                         if (fence) {
 173                                 amdgpu_bo_fence(bo, fence, true);
 174                                 dma_fence_put(fence);
 175                         }
 176                 }
 177         }
 178         ttm_eu_backoff_reservation(&ticket, &list);
 179 }
 180
 181 /*
 182  * GEM ioctls.
 183  */
 184 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 185                             struct drm_file *filp)
 186 {
 187         struct amdgpu_device *adev = dev->dev_private;
 188         union drm_amdgpu_gem_create *args = data;
 189         uint64_t flags = args->in.domain_flags;
 190         uint64_t size = args->in.bo_size;
 191         struct drm_gem_object *gobj;
 192         uint32_t handle;
 193         int r;
 194
 195         /* reject invalid gem flags */
 196         if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 197                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 198                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 199                       AMDGPU_GEM_CREATE_VRAM_CLEARED))
 200                 return -EINVAL;
 201
 202         /* reject invalid gem domains */
 203         if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
 204                                  AMDGPU_GEM_DOMAIN_GTT |
 205                                  AMDGPU_GEM_DOMAIN_VRAM |
 206                                  AMDGPU_GEM_DOMAIN_GDS |
 207                                  AMDGPU_GEM_DOMAIN_GWS |
 208                                  AMDGPU_GEM_DOMAIN_OA))
 209                 return -EINVAL;
 210
 211         /* create a gem object to contain this object in */
 212         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 213             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 214                 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 215                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 216                         size = size << AMDGPU_GDS_SHIFT;
 217                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 218                         size = size << AMDGPU_GWS_SHIFT;
 219                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 220                         size = size << AMDGPU_OA_SHIFT;
 221                 else
 222                         return -EINVAL;
 223         }
 224         size = roundup(size, PAGE_SIZE);
 225
 226         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 227                                      (u32)(0xffffffff & args->in.domains),
 228                                      flags, false, &gobj);
 229         if (r)
 230                 return r;
 231
 232         r = drm_gem_handle_create(filp, gobj, &handle);
 233         /* drop reference from allocate - handle holds it now */
 234         drm_gem_object_put_unlocked(gobj);
 235         if (r)
 236                 return r;
 237
 238         memset(args, 0, sizeof(*args));
 239         args->out.handle = handle;
 240         return 0;
 241 }
 242
 243 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 244                              struct drm_file *filp)
 245 {
 246         struct amdgpu_device *adev = dev->dev_private;
 247         struct drm_amdgpu_gem_userptr *args = data;
 248         struct drm_gem_object *gobj;
 249         struct amdgpu_bo *bo;
 250         uint32_t handle;
 251         int r;
 252
 253         if (offset_in_page(args->addr | args->size))
 254                 return -EINVAL;
 255
 256         /* reject unknown flag values */
 257         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 258             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 259             AMDGPU_GEM_USERPTR_REGISTER))
 260                 return -EINVAL;
 261
 262         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 263              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 264
 265                 /* if we want to write to it we must install a MMU notifier */
 266                 return -EACCES;
 267         }
 268
 269         /* create a gem object to contain this object in */
 270         r = amdgpu_gem_object_create(adev, args->size, 0,
 271                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 272                                      0, &gobj);
 273         if (r)
 274                 return r;
 275
 276         bo = gem_to_amdgpu_bo(gobj);
 277         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 278         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 279         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 280         if (r)
 281                 goto release_object;
 282
 283         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 284                 r = amdgpu_mn_register(bo, args->addr);
 285                 if (r)
 286                         goto release_object;
 287         }
 288
 289         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 290                 down_read(&current->mm->mmap_sem);
 291
 292                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 293                                                  bo->tbo.ttm->pages);
 294                 if (r)
 295                         goto unlock_mmap_sem;
 296
 297                 r = amdgpu_bo_reserve(bo, true);
 298                 if (r)
 299                         goto free_pages;
 300
 301                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 302                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 303                 amdgpu_bo_unreserve(bo);
 304                 if (r)
 305                         goto free_pages;
 306
 307                 up_read(&current->mm->mmap_sem);
 308         }
 309
 310         r = drm_gem_handle_create(filp, gobj, &handle);
 311         /* drop reference from allocate - handle holds it now */
 312         drm_gem_object_put_unlocked(gobj);
 313         if (r)
 314                 return r;
 315
 316         args->handle = handle;
 317         return 0;
 318
 319 free_pages:
 320         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
 321
 322 unlock_mmap_sem:
 323         up_read(&current->mm->mmap_sem);
 324
 325 release_object:
 326         drm_gem_object_put_unlocked(gobj);
 327
 328         return r;
 329 }
 330
 331 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 332                           struct drm_device *dev,
 333                           uint32_t handle, uint64_t *offset_p)
 334 {
 335         struct drm_gem_object *gobj;
 336         struct amdgpu_bo *robj;
 337
 338         gobj = drm_gem_object_lookup(filp, handle);
 339         if (gobj == NULL) {
 340                 return -ENOENT;
 341         }
 342         robj = gem_to_amdgpu_bo(gobj);
 343         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 344             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 345                 drm_gem_object_put_unlocked(gobj);
 346                 return -EPERM;
 347         }
 348         *offset_p = amdgpu_bo_mmap_offset(robj);
 349         drm_gem_object_put_unlocked(gobj);
 350         return 0;
 351 }
 352
 353 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 354                           struct drm_file *filp)
 355 {
 356         union drm_amdgpu_gem_mmap *args = data;
 357         uint32_t handle = args->in.handle;
 358         memset(args, 0, sizeof(*args));
 359         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 360 }
 361
 362 /**
 363  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 364  *
 365  * @timeout_ns: timeout in ns
 366  *
 367  * Calculate the timeout in jiffies from an absolute timeout in ns.
 368  */
 369 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 370 {
 371         unsigned long timeout_jiffies;
 372         ktime_t timeout;
 373
 374         /* clamp timeout if it's to large */
 375         if (((int64_t)timeout_ns) < 0)
 376                 return MAX_SCHEDULE_TIMEOUT;
 377
 378         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 379         if (ktime_to_ns(timeout) < 0)
 380                 return 0;
 381
 382         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 383         /*  clamp timeout to avoid unsigned-> signed overflow */
 384         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 385                 return MAX_SCHEDULE_TIMEOUT - 1;
 386
 387         return timeout_jiffies;
 388 }
 389
 390 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 391                               struct drm_file *filp)
 392 {
 393         union drm_amdgpu_gem_wait_idle *args = data;
 394         struct drm_gem_object *gobj;
 395         struct amdgpu_bo *robj;
 396         uint32_t handle = args->in.handle;
 397         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 398         int r = 0;
 399         long ret;
 400
 401         gobj = drm_gem_object_lookup(filp, handle);
 402         if (gobj == NULL) {
 403                 return -ENOENT;
 404         }
 405         robj = gem_to_amdgpu_bo(gobj);
 406         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
 407                                                   timeout);
 408
 409         /* ret == 0 means not signaled,
 410          * ret > 0 means signaled
 411          * ret < 0 means interrupted before timeout
 412          */
 413         if (ret >= 0) {
 414                 memset(args, 0, sizeof(*args));
 415                 args->out.status = (ret == 0);
 416         } else
 417                 r = ret;
 418
 419         drm_gem_object_put_unlocked(gobj);
 420         return r;
 421 }
 422
 423 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 424                                 struct drm_file *filp)
 425 {
 426         struct drm_amdgpu_gem_metadata *args = data;
 427         struct drm_gem_object *gobj;
 428         struct amdgpu_bo *robj;
 429         int r = -1;
 430
 431         DRM_DEBUG("%d \n", args->handle);
 432         gobj = drm_gem_object_lookup(filp, args->handle);
 433         if (gobj == NULL)
 434                 return -ENOENT;
 435         robj = gem_to_amdgpu_bo(gobj);
 436
 437         r = amdgpu_bo_reserve(robj, false);
 438         if (unlikely(r != 0))
 439                 goto out;
 440
 441         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 442                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 443                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 444                                            sizeof(args->data.data),
 445                                            &args->data.data_size_bytes,
 446                                            &args->data.flags);
 447         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 448                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 449                         r = -EINVAL;
 450                         goto unreserve;
 451                 }
 452                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 453                 if (!r)
 454                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 455                                                    args->data.data_size_bytes,
 456                                                    args->data.flags);
 457         }
 458
 459 unreserve:
 460         amdgpu_bo_unreserve(robj);
 461 out:
 462         drm_gem_object_put_unlocked(gobj);
 463         return r;
 464 }
 465
 466 /**
 467  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 468  *
 469  * @adev: amdgpu_device pointer
 470  * @vm: vm to update
 471  * @bo_va: bo_va to update
 472  * @list: validation list
 473  * @operation: map, unmap or clear
 474  *
 475  * Update the bo_va directly after setting its address. Errors are not
 476  * vital here, so they are not reported back to userspace.
 477  */
 478 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 479                                     struct amdgpu_vm *vm,
 480                                     struct amdgpu_bo_va *bo_va,
 481                                     struct list_head *list,
 482                                     uint32_t operation)
 483 {
 484         int r = -ERESTARTSYS;
 485
 486         if (!amdgpu_vm_ready(adev, vm))
 487                 goto error;
 488
 489         r = amdgpu_vm_update_directories(adev, vm);
 490         if (r)
 491                 goto error;
 492
 493         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 494         if (r)
 495                 goto error;
 496
 497         if (operation == AMDGPU_VA_OP_MAP ||
 498             operation == AMDGPU_VA_OP_REPLACE)
 499                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 500
 501 error:
 502         if (r && r != -ERESTARTSYS)
 503                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 504 }
 505
 506 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 507                           struct drm_file *filp)
 508 {
 509         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 510                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 511                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
 512         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 513                 AMDGPU_VM_PAGE_PRT;
 514
 515         struct drm_amdgpu_gem_va *args = data;
 516         struct drm_gem_object *gobj;
 517         struct amdgpu_device *adev = dev->dev_private;
 518         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 519         struct amdgpu_bo *abo;
 520         struct amdgpu_bo_va *bo_va;
 521         struct amdgpu_bo_list_entry vm_pd;
 522         struct ttm_validate_buffer tv;
 523         struct ww_acquire_ctx ticket;
 524         struct list_head list;
 525         uint64_t va_flags;
 526         int r = 0;
 527
 528         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 529                 dev_err(&dev->pdev->dev,
 530                         "va_address 0x%lX is in reserved area 0x%X\n",
 531                         (unsigned long)args->va_address,
 532                         AMDGPU_VA_RESERVED_SIZE);
 533                 return -EINVAL;
 534         }
 535
 536         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 537                 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
 538                         args->flags);
 539                 return -EINVAL;
 540         }
 541
 542         switch (args->operation) {
 543         case AMDGPU_VA_OP_MAP:
 544         case AMDGPU_VA_OP_UNMAP:
 545         case AMDGPU_VA_OP_CLEAR:
 546         case AMDGPU_VA_OP_REPLACE:
 547                 break;
 548         default:
 549                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 550                         args->operation);
 551                 return -EINVAL;
 552         }
 553         if ((args->operation == AMDGPU_VA_OP_MAP) ||
 554             (args->operation == AMDGPU_VA_OP_REPLACE)) {
 555                 if (amdgpu_kms_vram_lost(adev, fpriv))
 556                         return -ENODEV;
 557         }
 558
 559         INIT_LIST_HEAD(&list);
 560         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 561             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 562                 gobj = drm_gem_object_lookup(filp, args->handle);
 563                 if (gobj == NULL)
 564                         return -ENOENT;
 565                 abo = gem_to_amdgpu_bo(gobj);
 566                 tv.bo = &abo->tbo;
 567                 tv.shared = false;
 568                 list_add(&tv.head, &list);
 569         } else {
 570                 gobj = NULL;
 571                 abo = NULL;
 572         }
 573
 574         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 575
 576         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
 577         if (r)
 578                 goto error_unref;
 579
 580         if (abo) {
 581                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 582                 if (!bo_va) {
 583                         r = -ENOENT;
 584                         goto error_backoff;
 585                 }
 586         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 587                 bo_va = fpriv->prt_va;
 588         } else {
 589                 bo_va = NULL;
 590         }
 591
 592         switch (args->operation) {
 593         case AMDGPU_VA_OP_MAP:
 594                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 595                                         args->map_size);
 596                 if (r)
 597                         goto error_backoff;
 598
 599                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 600                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 601                                      args->offset_in_bo, args->map_size,
 602                                      va_flags);
 603                 break;
 604         case AMDGPU_VA_OP_UNMAP:
 605                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 606                 break;
 607
 608         case AMDGPU_VA_OP_CLEAR:
 609                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 610                                                 args->va_address,
 611                                                 args->map_size);
 612                 break;
 613         case AMDGPU_VA_OP_REPLACE:
 614                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 615                                         args->map_size);
 616                 if (r)
 617                         goto error_backoff;
 618
 619                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 620                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 621                                              args->offset_in_bo, args->map_size,
 622                                              va_flags);
 623                 break;
 624         default:
 625                 break;
 626         }
 627         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
 628                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
 629                                         args->operation);
 630
 631 error_backoff:
 632         ttm_eu_backoff_reservation(&ticket, &list);
 633
 634 error_unref:
 635         drm_gem_object_put_unlocked(gobj);
 636         return r;
 637 }
 638
 639 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 640                         struct drm_file *filp)
 641 {
 642         struct drm_amdgpu_gem_op *args = data;
 643         struct drm_gem_object *gobj;
 644         struct amdgpu_bo *robj;
 645         int r;
 646
 647         gobj = drm_gem_object_lookup(filp, args->handle);
 648         if (gobj == NULL) {
 649                 return -ENOENT;
 650         }
 651         robj = gem_to_amdgpu_bo(gobj);
 652
 653         r = amdgpu_bo_reserve(robj, false);
 654         if (unlikely(r))
 655                 goto out;
 656
 657         switch (args->op) {
 658         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 659                 struct drm_amdgpu_gem_create_in info;
 660                 void __user *out = u64_to_user_ptr(args->value);
 661
 662                 info.bo_size = robj->gem_base.size;
 663                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 664                 info.domains = robj->preferred_domains;
 665                 info.domain_flags = robj->flags;
 666                 amdgpu_bo_unreserve(robj);
 667                 if (copy_to_user(out, &info, sizeof(info)))
 668                         r = -EFAULT;
 669                 break;
 670         }
 671         case AMDGPU_GEM_OP_SET_PLACEMENT:
 672                 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
 673                         r = -EINVAL;
 674                         amdgpu_bo_unreserve(robj);
 675                         break;
 676                 }
 677                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 678                         r = -EPERM;
 679                         amdgpu_bo_unreserve(robj);
 680                         break;
 681                 }
 682                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 683                                                         AMDGPU_GEM_DOMAIN_GTT |
 684                                                         AMDGPU_GEM_DOMAIN_CPU);
 685                 robj->allowed_domains = robj->preferred_domains;
 686                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 687                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 688
 689                 amdgpu_bo_unreserve(robj);
 690                 break;
 691         default:
 692                 amdgpu_bo_unreserve(robj);
 693                 r = -EINVAL;
 694         }
 695
 696 out:
 697         drm_gem_object_put_unlocked(gobj);
 698         return r;
 699 }
 700
 701 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 702                             struct drm_device *dev,
 703                             struct drm_mode_create_dumb *args)
 704 {
 705         struct amdgpu_device *adev = dev->dev_private;
 706         struct drm_gem_object *gobj;
 707         uint32_t handle;
 708         int r;
 709
 710         args->pitch = amdgpu_align_pitch(adev, args->width,
 711                                          DIV_ROUND_UP(args->bpp, 8), 0);
 712         args->size = (u64)args->pitch * args->height;
 713         args->size = ALIGN(args->size, PAGE_SIZE);
 714
 715         r = amdgpu_gem_object_create(adev, args->size, 0,
 716                                      AMDGPU_GEM_DOMAIN_VRAM,
 717                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 718                                      ttm_bo_type_device,
 719                                      &gobj);
 720         if (r)
 721                 return -ENOMEM;
 722
 723         r = drm_gem_handle_create(file_priv, gobj, &handle);
 724         /* drop reference from allocate - handle holds it now */
 725         drm_gem_object_put_unlocked(gobj);
 726         if (r) {
 727                 return r;
 728         }
 729         args->handle = handle;
 730         return 0;
 731 }
 732
 733 #if defined(CONFIG_DEBUG_FS)
 734 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 735 {
 736         struct drm_gem_object *gobj = ptr;
 737         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 738         struct seq_file *m = data;
 739
 740         unsigned domain;
 741         const char *placement;
 742         unsigned pin_count;
 743         uint64_t offset;
 744
 745         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 746         switch (domain) {
 747         case AMDGPU_GEM_DOMAIN_VRAM:
 748                 placement = "VRAM";
 749                 break;
 750         case AMDGPU_GEM_DOMAIN_GTT:
 751                 placement = " GTT";
 752                 break;
 753         case AMDGPU_GEM_DOMAIN_CPU:
 754         default:
 755                 placement = " CPU";
 756                 break;
 757         }
 758         seq_printf(m, "\t0x%08x: %12ld byte %s",
 759                    id, amdgpu_bo_size(bo), placement);
 760
 761         offset = ACCESS_ONCE(bo->tbo.mem.start);
 762         if (offset != AMDGPU_BO_INVALID_OFFSET)
 763                 seq_printf(m, " @ 0x%010Lx", offset);
 764
 765         pin_count = ACCESS_ONCE(bo->pin_count);
 766         if (pin_count)
 767                 seq_printf(m, " pin count %d", pin_count);
 768         seq_printf(m, "\n");
 769
 770         return 0;
 771 }
 772
 773 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 774 {
 775         struct drm_info_node *node = (struct drm_info_node *)m->private;
 776         struct drm_device *dev = node->minor->dev;
 777         struct drm_file *file;
 778         int r;
 779
 780         r = mutex_lock_interruptible(&dev->filelist_mutex);
 781         if (r)
 782                 return r;
 783
 784         list_for_each_entry(file, &dev->filelist, lhead) {
 785                 struct task_struct *task;
 786
 787                 /*
 788                  * Although we have a valid reference on file->pid, that does
 789                  * not guarantee that the task_struct who called get_pid() is
 790                  * still alive (e.g. get_pid(current) => fork() => exit()).
 791                  * Therefore, we need to protect this ->comm access using RCU.
 792                  */
 793                 rcu_read_lock();
 794                 task = pid_task(file->pid, PIDTYPE_PID);
 795                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 796                            task ? task->comm : "<unknown>");
 797                 rcu_read_unlock();
 798
 799                 spin_lock(&file->table_lock);
 800                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 801                 spin_unlock(&file->table_lock);
 802         }
 803
 804         mutex_unlock(&dev->filelist_mutex);
 805         return 0;
 806 }
 807
 808 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 809         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 810 };
 811 #endif
 812
 813 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 814 {
 815 #if defined(CONFIG_DEBUG_FS)
 816         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 817 #endif
 818         return 0;
 819 }