drivers/infiniband/hw/mlx5/main.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /*
   3  * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
   4  */
   5
   6 #include <linux/debugfs.h>
   7 #include <linux/highmem.h>
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/errno.h>
  11 #include <linux/pci.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/slab.h>
  14 #include <linux/bitmap.h>
  15 #include <linux/sched.h>
  16 #include <linux/sched/mm.h>
  17 #include <linux/sched/task.h>
  18 #include <linux/delay.h>
  19 #include <rdma/ib_user_verbs.h>
  20 #include <rdma/ib_addr.h>
  21 #include <rdma/ib_cache.h>
  22 #include <linux/mlx5/port.h>
  23 #include <linux/mlx5/vport.h>
  24 #include <linux/mlx5/fs.h>
  25 #include <linux/mlx5/eswitch.h>
  26 #include <linux/list.h>
  27 #include <rdma/ib_smi.h>
  28 #include <rdma/ib_umem.h>
  29 #include <rdma/lag.h>
  30 #include <linux/in.h>
  31 #include <linux/etherdevice.h>
  32 #include "mlx5_ib.h"
  33 #include "ib_rep.h"
  34 #include "cmd.h"
  35 #include "devx.h"
  36 #include "fs.h"
  37 #include "srq.h"
  38 #include "qp.h"
  39 #include "wr.h"
  40 #include "restrack.h"
  41 #include "counters.h"
  42 #include <linux/mlx5/accel.h>
  43 #include <rdma/uverbs_std_types.h>
  44 #include <rdma/mlx5_user_ioctl_verbs.h>
  45 #include <rdma/mlx5_user_ioctl_cmds.h>
  46 #include <rdma/ib_umem_odp.h>
  47
  48 #define UVERBS_MODULE_NAME mlx5_ib
  49 #include <rdma/uverbs_named_ioctl.h>
  50
  51 MODULE_AUTHOR("Eli Cohen <[email protected]>");
  52 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
  53 MODULE_LICENSE("Dual BSD/GPL");
  54
  55 struct mlx5_ib_event_work {
  56         struct work_struct      work;
  57         union {
  58                 struct mlx5_ib_dev            *dev;
  59                 struct mlx5_ib_multiport_info *mpi;
  60         };
  61         bool                    is_slave;
  62         unsigned int            event;
  63         void                    *param;
  64 };
  65
  66 enum {
  67         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  68 };
  69
  70 static struct workqueue_struct *mlx5_ib_event_wq;
  71 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  72 static LIST_HEAD(mlx5_ib_dev_list);
  73 /*
  74  * This mutex should be held when accessing either of the above lists
  75  */
  76 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  77
  78 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  79 {
  80         struct mlx5_ib_dev *dev;
  81
  82         mutex_lock(&mlx5_ib_multiport_mutex);
  83         dev = mpi->ibdev;
  84         mutex_unlock(&mlx5_ib_multiport_mutex);
  85         return dev;
  86 }
  87
  88 static enum rdma_link_layer
  89 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  90 {
  91         switch (port_type_cap) {
  92         case MLX5_CAP_PORT_TYPE_IB:
  93                 return IB_LINK_LAYER_INFINIBAND;
  94         case MLX5_CAP_PORT_TYPE_ETH:
  95                 return IB_LINK_LAYER_ETHERNET;
  96         default:
  97                 return IB_LINK_LAYER_UNSPECIFIED;
  98         }
  99 }
 100
 101 static enum rdma_link_layer
 102 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 103 {
 104         struct mlx5_ib_dev *dev = to_mdev(device);
 105         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 106
 107         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 108 }
 109
 110 static int get_port_state(struct ib_device *ibdev,
 111                           u8 port_num,
 112                           enum ib_port_state *state)
 113 {
 114         struct ib_port_attr attr;
 115         int ret;
 116
 117         memset(&attr, 0, sizeof(attr));
 118         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 119         if (!ret)
 120                 *state = attr.state;
 121         return ret;
 122 }
 123
 124 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 125                                            struct net_device *ndev,
 126                                            u8 *port_num)
 127 {
 128         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
 129         struct net_device *rep_ndev;
 130         struct mlx5_ib_port *port;
 131         int i;
 132
 133         for (i = 0; i < dev->num_ports; i++) {
 134                 port  = &dev->port[i];
 135                 if (!port->rep)
 136                         continue;
 137
 138                 read_lock(&port->roce.netdev_lock);
 139                 rep_ndev = mlx5_ib_get_rep_netdev(esw,
 140                                                   port->rep->vport);
 141                 if (rep_ndev == ndev) {
 142                         read_unlock(&port->roce.netdev_lock);
 143                         *port_num = i + 1;
 144                         return &port->roce;
 145                 }
 146                 read_unlock(&port->roce.netdev_lock);
 147         }
 148
 149         return NULL;
 150 }
 151
 152 static int mlx5_netdev_event(struct notifier_block *this,
 153                              unsigned long event, void *ptr)
 154 {
 155         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 156         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 157         u8 port_num = roce->native_port_num;
 158         struct mlx5_core_dev *mdev;
 159         struct mlx5_ib_dev *ibdev;
 160
 161         ibdev = roce->dev;
 162         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 163         if (!mdev)
 164                 return NOTIFY_DONE;
 165
 166         switch (event) {
 167         case NETDEV_REGISTER:
 168                 /* Should already be registered during the load */
 169                 if (ibdev->is_rep)
 170                         break;
 171                 write_lock(&roce->netdev_lock);
 172                 if (ndev->dev.parent == mdev->device)
 173                         roce->netdev = ndev;
 174                 write_unlock(&roce->netdev_lock);
 175                 break;
 176
 177         case NETDEV_UNREGISTER:
 178                 /* In case of reps, ib device goes away before the netdevs */
 179                 write_lock(&roce->netdev_lock);
 180                 if (roce->netdev == ndev)
 181                         roce->netdev = NULL;
 182                 write_unlock(&roce->netdev_lock);
 183                 break;
 184
 185         case NETDEV_CHANGE:
 186         case NETDEV_UP:
 187         case NETDEV_DOWN: {
 188                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 189                 struct net_device *upper = NULL;
 190
 191                 if (lag_ndev) {
 192                         upper = netdev_master_upper_dev_get(lag_ndev);
 193                         dev_put(lag_ndev);
 194                 }
 195
 196                 if (ibdev->is_rep)
 197                         roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
 198                 if (!roce)
 199                         return NOTIFY_DONE;
 200                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 201                     && ibdev->ib_active) {
 202                         struct ib_event ibev = { };
 203                         enum ib_port_state port_state;
 204
 205                         if (get_port_state(&ibdev->ib_dev, port_num,
 206                                            &port_state))
 207                                 goto done;
 208
 209                         if (roce->last_port_state == port_state)
 210                                 goto done;
 211
 212                         roce->last_port_state = port_state;
 213                         ibev.device = &ibdev->ib_dev;
 214                         if (port_state == IB_PORT_DOWN)
 215                                 ibev.event = IB_EVENT_PORT_ERR;
 216                         else if (port_state == IB_PORT_ACTIVE)
 217                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 218                         else
 219                                 goto done;
 220
 221                         ibev.element.port_num = port_num;
 222                         ib_dispatch_event(&ibev);
 223                 }
 224                 break;
 225         }
 226
 227         default:
 228                 break;
 229         }
 230 done:
 231         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 232         return NOTIFY_DONE;
 233 }
 234
 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 236                                              u8 port_num)
 237 {
 238         struct mlx5_ib_dev *ibdev = to_mdev(device);
 239         struct net_device *ndev;
 240         struct mlx5_core_dev *mdev;
 241
 242         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 243         if (!mdev)
 244                 return NULL;
 245
 246         ndev = mlx5_lag_get_roce_netdev(mdev);
 247         if (ndev)
 248                 goto out;
 249
 250         /* Ensure ndev does not disappear before we invoke dev_hold()
 251          */
 252         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 253         ndev = ibdev->port[port_num - 1].roce.netdev;
 254         if (ndev)
 255                 dev_hold(ndev);
 256         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 257
 258 out:
 259         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 260         return ndev;
 261 }
 262
 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 264                                                    u8 ib_port_num,
 265                                                    u8 *native_port_num)
 266 {
 267         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 268                                                           ib_port_num);
 269         struct mlx5_core_dev *mdev = NULL;
 270         struct mlx5_ib_multiport_info *mpi;
 271         struct mlx5_ib_port *port;
 272
 273         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 274             ll != IB_LINK_LAYER_ETHERNET) {
 275                 if (native_port_num)
 276                         *native_port_num = ib_port_num;
 277                 return ibdev->mdev;
 278         }
 279
 280         if (native_port_num)
 281                 *native_port_num = 1;
 282
 283         port = &ibdev->port[ib_port_num - 1];
 284         spin_lock(&port->mp.mpi_lock);
 285         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 286         if (mpi && !mpi->unaffiliate) {
 287                 mdev = mpi->mdev;
 288                 /* If it's the master no need to refcount, it'll exist
 289                  * as long as the ib_dev exists.
 290                  */
 291                 if (!mpi->is_master)
 292                         mpi->mdev_refcnt++;
 293         }
 294         spin_unlock(&port->mp.mpi_lock);
 295
 296         return mdev;
 297 }
 298
 299 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 300 {
 301         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 302                                                           port_num);
 303         struct mlx5_ib_multiport_info *mpi;
 304         struct mlx5_ib_port *port;
 305
 306         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 307                 return;
 308
 309         port = &ibdev->port[port_num - 1];
 310
 311         spin_lock(&port->mp.mpi_lock);
 312         mpi = ibdev->port[port_num - 1].mp.mpi;
 313         if (mpi->is_master)
 314                 goto out;
 315
 316         mpi->mdev_refcnt--;
 317         if (mpi->unaffiliate)
 318                 complete(&mpi->unref_comp);
 319 out:
 320         spin_unlock(&port->mp.mpi_lock);
 321 }
 322
 323 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
 324                                            u16 *active_speed, u8 *active_width)
 325 {
 326         switch (eth_proto_oper) {
 327         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 328         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 329         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 330         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 331                 *active_width = IB_WIDTH_1X;
 332                 *active_speed = IB_SPEED_SDR;
 333                 break;
 334         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 335         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 336         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 337         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 338         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 339         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 340         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 341                 *active_width = IB_WIDTH_1X;
 342                 *active_speed = IB_SPEED_QDR;
 343                 break;
 344         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 345         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 346         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 347                 *active_width = IB_WIDTH_1X;
 348                 *active_speed = IB_SPEED_EDR;
 349                 break;
 350         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 351         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 352         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 353         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 354                 *active_width = IB_WIDTH_4X;
 355                 *active_speed = IB_SPEED_QDR;
 356                 break;
 357         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 358         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 359         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 360                 *active_width = IB_WIDTH_1X;
 361                 *active_speed = IB_SPEED_HDR;
 362                 break;
 363         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 364                 *active_width = IB_WIDTH_4X;
 365                 *active_speed = IB_SPEED_FDR;
 366                 break;
 367         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 368         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 369         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 370         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 371                 *active_width = IB_WIDTH_4X;
 372                 *active_speed = IB_SPEED_EDR;
 373                 break;
 374         default:
 375                 return -EINVAL;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 382                                         u8 *active_width)
 383 {
 384         switch (eth_proto_oper) {
 385         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 386         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 387                 *active_width = IB_WIDTH_1X;
 388                 *active_speed = IB_SPEED_SDR;
 389                 break;
 390         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 391                 *active_width = IB_WIDTH_1X;
 392                 *active_speed = IB_SPEED_DDR;
 393                 break;
 394         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 395                 *active_width = IB_WIDTH_1X;
 396                 *active_speed = IB_SPEED_QDR;
 397                 break;
 398         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 399                 *active_width = IB_WIDTH_4X;
 400                 *active_speed = IB_SPEED_QDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 403                 *active_width = IB_WIDTH_1X;
 404                 *active_speed = IB_SPEED_EDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 407                 *active_width = IB_WIDTH_2X;
 408                 *active_speed = IB_SPEED_EDR;
 409                 break;
 410         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 411                 *active_width = IB_WIDTH_1X;
 412                 *active_speed = IB_SPEED_HDR;
 413                 break;
 414         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 415                 *active_width = IB_WIDTH_4X;
 416                 *active_speed = IB_SPEED_EDR;
 417                 break;
 418         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 419                 *active_width = IB_WIDTH_2X;
 420                 *active_speed = IB_SPEED_HDR;
 421                 break;
 422         case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
 423                 *active_width = IB_WIDTH_1X;
 424                 *active_speed = IB_SPEED_NDR;
 425                 break;
 426         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 427                 *active_width = IB_WIDTH_4X;
 428                 *active_speed = IB_SPEED_HDR;
 429                 break;
 430         case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
 431                 *active_width = IB_WIDTH_2X;
 432                 *active_speed = IB_SPEED_NDR;
 433                 break;
 434         case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
 435                 *active_width = IB_WIDTH_4X;
 436                 *active_speed = IB_SPEED_NDR;
 437                 break;
 438         default:
 439                 return -EINVAL;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 446                                     u8 *active_width, bool ext)
 447 {
 448         return ext ?
 449                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 450                                              active_width) :
 451                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 452                                                 active_width);
 453 }
 454
 455 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 456                                 struct ib_port_attr *props)
 457 {
 458         struct mlx5_ib_dev *dev = to_mdev(device);
 459         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 460         struct mlx5_core_dev *mdev;
 461         struct net_device *ndev, *upper;
 462         enum ib_mtu ndev_ib_mtu;
 463         bool put_mdev = true;
 464         u16 qkey_viol_cntr;
 465         u32 eth_prot_oper;
 466         u8 mdev_port_num;
 467         bool ext;
 468         int err;
 469
 470         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 471         if (!mdev) {
 472                 /* This means the port isn't affiliated yet. Get the
 473                  * info for the master port instead.
 474                  */
 475                 put_mdev = false;
 476                 mdev = dev->mdev;
 477                 mdev_port_num = 1;
 478                 port_num = 1;
 479         }
 480
 481         /* Possible bad flows are checked before filling out props so in case
 482          * of an error it will still be zeroed out.
 483          * Use native port in case of reps
 484          */
 485         if (dev->is_rep)
 486                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 487                                            1);
 488         else
 489                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 490                                            mdev_port_num);
 491         if (err)
 492                 goto out;
 493         ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
 494         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 495
 496         props->active_width     = IB_WIDTH_4X;
 497         props->active_speed     = IB_SPEED_QDR;
 498
 499         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 500                                  &props->active_width, ext);
 501
 502         props->port_cap_flags |= IB_PORT_CM_SUP;
 503         props->ip_gids = true;
 504
 505         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 506                                                 roce_address_table_size);
 507         props->max_mtu          = IB_MTU_4096;
 508         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 509         props->pkey_tbl_len     = 1;
 510         props->state            = IB_PORT_DOWN;
 511         props->phys_state       = IB_PORT_PHYS_STATE_DISABLED;
 512
 513         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 514         props->qkey_viol_cntr = qkey_viol_cntr;
 515
 516         /* If this is a stub query for an unaffiliated port stop here */
 517         if (!put_mdev)
 518                 goto out;
 519
 520         ndev = mlx5_ib_get_netdev(device, port_num);
 521         if (!ndev)
 522                 goto out;
 523
 524         if (dev->lag_active) {
 525                 rcu_read_lock();
 526                 upper = netdev_master_upper_dev_get_rcu(ndev);
 527                 if (upper) {
 528                         dev_put(ndev);
 529                         ndev = upper;
 530                         dev_hold(ndev);
 531                 }
 532                 rcu_read_unlock();
 533         }
 534
 535         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 536                 props->state      = IB_PORT_ACTIVE;
 537                 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
 538         }
 539
 540         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 541
 542         dev_put(ndev);
 543
 544         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 545 out:
 546         if (put_mdev)
 547                 mlx5_ib_put_native_port_mdev(dev, port_num);
 548         return err;
 549 }
 550
 551 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 552                          unsigned int index, const union ib_gid *gid,
 553                          const struct ib_gid_attr *attr)
 554 {
 555         enum ib_gid_type gid_type = IB_GID_TYPE_ROCE;
 556         u16 vlan_id = 0xffff;
 557         u8 roce_version = 0;
 558         u8 roce_l3_type = 0;
 559         u8 mac[ETH_ALEN];
 560         int ret;
 561
 562         if (gid) {
 563                 gid_type = attr->gid_type;
 564                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 565                 if (ret)
 566                         return ret;
 567         }
 568
 569         switch (gid_type) {
 570         case IB_GID_TYPE_ROCE:
 571                 roce_version = MLX5_ROCE_VERSION_1;
 572                 break;
 573         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 574                 roce_version = MLX5_ROCE_VERSION_2;
 575                 if (ipv6_addr_v4mapped((void *)gid))
 576                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 577                 else
 578                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 579                 break;
 580
 581         default:
 582                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 583         }
 584
 585         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 586                                       roce_l3_type, gid->raw, mac,
 587                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 588                                       port_num);
 589 }
 590
 591 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 592                            __always_unused void **context)
 593 {
 594         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 595                              attr->index, &attr->gid, attr);
 596 }
 597
 598 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 599                            __always_unused void **context)
 600 {
 601         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 602                              attr->index, NULL, NULL);
 603 }
 604
 605 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
 606                                    const struct ib_gid_attr *attr)
 607 {
 608         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 609                 return 0;
 610
 611         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 612 }
 613
 614 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 615 {
 616         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 617                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 618         return 0;
 619 }
 620
 621 enum {
 622         MLX5_VPORT_ACCESS_METHOD_MAD,
 623         MLX5_VPORT_ACCESS_METHOD_HCA,
 624         MLX5_VPORT_ACCESS_METHOD_NIC,
 625 };
 626
 627 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 628 {
 629         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 630                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 631
 632         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 633             IB_LINK_LAYER_ETHERNET)
 634                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 635
 636         return MLX5_VPORT_ACCESS_METHOD_HCA;
 637 }
 638
 639 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 640                             u8 atomic_size_qp,
 641                             struct ib_device_attr *props)
 642 {
 643         u8 tmp;
 644         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 645         u8 atomic_req_8B_endianness_mode =
 646                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 647
 648         /* Check if HW supports 8 bytes standard atomic operations and capable
 649          * of host endianness respond
 650          */
 651         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 652         if (((atomic_operations & tmp) == tmp) &&
 653             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 654             (atomic_req_8B_endianness_mode)) {
 655                 props->atomic_cap = IB_ATOMIC_HCA;
 656         } else {
 657                 props->atomic_cap = IB_ATOMIC_NONE;
 658         }
 659 }
 660
 661 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 662                                struct ib_device_attr *props)
 663 {
 664         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 665
 666         get_atomic_caps(dev, atomic_size_qp, props);
 667 }
 668
 669 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 670                                         __be64 *sys_image_guid)
 671 {
 672         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 673         struct mlx5_core_dev *mdev = dev->mdev;
 674         u64 tmp;
 675         int err;
 676
 677         switch (mlx5_get_vport_access_method(ibdev)) {
 678         case MLX5_VPORT_ACCESS_METHOD_MAD:
 679                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 680                                                             sys_image_guid);
 681
 682         case MLX5_VPORT_ACCESS_METHOD_HCA:
 683                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 684                 break;
 685
 686         case MLX5_VPORT_ACCESS_METHOD_NIC:
 687                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 688                 break;
 689
 690         default:
 691                 return -EINVAL;
 692         }
 693
 694         if (!err)
 695                 *sys_image_guid = cpu_to_be64(tmp);
 696
 697         return err;
 698
 699 }
 700
 701 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 702                                 u16 *max_pkeys)
 703 {
 704         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 705         struct mlx5_core_dev *mdev = dev->mdev;
 706
 707         switch (mlx5_get_vport_access_method(ibdev)) {
 708         case MLX5_VPORT_ACCESS_METHOD_MAD:
 709                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 710
 711         case MLX5_VPORT_ACCESS_METHOD_HCA:
 712         case MLX5_VPORT_ACCESS_METHOD_NIC:
 713                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 714                                                 pkey_table_size));
 715                 return 0;
 716
 717         default:
 718                 return -EINVAL;
 719         }
 720 }
 721
 722 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 723                                 u32 *vendor_id)
 724 {
 725         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 726
 727         switch (mlx5_get_vport_access_method(ibdev)) {
 728         case MLX5_VPORT_ACCESS_METHOD_MAD:
 729                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 730
 731         case MLX5_VPORT_ACCESS_METHOD_HCA:
 732         case MLX5_VPORT_ACCESS_METHOD_NIC:
 733                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 734
 735         default:
 736                 return -EINVAL;
 737         }
 738 }
 739
 740 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 741                                 __be64 *node_guid)
 742 {
 743         u64 tmp;
 744         int err;
 745
 746         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 747         case MLX5_VPORT_ACCESS_METHOD_MAD:
 748                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 749
 750         case MLX5_VPORT_ACCESS_METHOD_HCA:
 751                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 752                 break;
 753
 754         case MLX5_VPORT_ACCESS_METHOD_NIC:
 755                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 756                 break;
 757
 758         default:
 759                 return -EINVAL;
 760         }
 761
 762         if (!err)
 763                 *node_guid = cpu_to_be64(tmp);
 764
 765         return err;
 766 }
 767
 768 struct mlx5_reg_node_desc {
 769         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 770 };
 771
 772 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 773 {
 774         struct mlx5_reg_node_desc in;
 775
 776         if (mlx5_use_mad_ifc(dev))
 777                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 778
 779         memset(&in, 0, sizeof(in));
 780
 781         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 782                                     sizeof(struct mlx5_reg_node_desc),
 783                                     MLX5_REG_NODE_DESC, 0, 0);
 784 }
 785
 786 static int mlx5_ib_query_device(struct ib_device *ibdev,
 787                                 struct ib_device_attr *props,
 788                                 struct ib_udata *uhw)
 789 {
 790         size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
 791         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 792         struct mlx5_core_dev *mdev = dev->mdev;
 793         int err = -ENOMEM;
 794         int max_sq_desc;
 795         int max_rq_sg;
 796         int max_sq_sg;
 797         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 798         bool raw_support = !mlx5_core_mp_enabled(mdev);
 799         struct mlx5_ib_query_device_resp resp = {};
 800         size_t resp_len;
 801         u64 max_tso;
 802
 803         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 804         if (uhw_outlen && uhw_outlen < resp_len)
 805                 return -EINVAL;
 806
 807         resp.response_length = resp_len;
 808
 809         if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 810                 return -EINVAL;
 811
 812         memset(props, 0, sizeof(*props));
 813         err = mlx5_query_system_image_guid(ibdev,
 814                                            &props->sys_image_guid);
 815         if (err)
 816                 return err;
 817
 818         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 819         if (err)
 820                 return err;
 821
 822         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 823         if (err)
 824                 return err;
 825
 826         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 827                 (fw_rev_min(dev->mdev) << 16) |
 828                 fw_rev_sub(dev->mdev);
 829         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 830                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 831                 IB_DEVICE_SYS_IMAGE_GUID                |
 832                 IB_DEVICE_RC_RNR_NAK_GEN;
 833
 834         if (MLX5_CAP_GEN(mdev, pkv))
 835                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 836         if (MLX5_CAP_GEN(mdev, qkv))
 837                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 838         if (MLX5_CAP_GEN(mdev, apm))
 839                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 840         if (MLX5_CAP_GEN(mdev, xrc))
 841                 props->device_cap_flags |= IB_DEVICE_XRC;
 842         if (MLX5_CAP_GEN(mdev, imaicl)) {
 843                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 844                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 845                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 846                 /* We support 'Gappy' memory registration too */
 847                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 848         }
 849         /* IB_WR_REG_MR always requires changing the entity size with UMR */
 850         if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
 851                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 852         if (MLX5_CAP_GEN(mdev, sho)) {
 853                 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
 854                 /* At this stage no support for signature handover */
 855                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 856                                       IB_PROT_T10DIF_TYPE_2 |
 857                                       IB_PROT_T10DIF_TYPE_3;
 858                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 859                                        IB_GUARD_T10DIF_CSUM;
 860         }
 861         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 862                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 863
 864         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 865                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 866                         /* Legacy bit to support old userspace libraries */
 867                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 868                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 869                 }
 870
 871                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 872                         props->raw_packet_caps |=
 873                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 874
 875                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
 876                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 877                         if (max_tso) {
 878                                 resp.tso_caps.max_tso = 1 << max_tso;
 879                                 resp.tso_caps.supported_qpts |=
 880                                         1 << IB_QPT_RAW_PACKET;
 881                                 resp.response_length += sizeof(resp.tso_caps);
 882                         }
 883                 }
 884
 885                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
 886                         resp.rss_caps.rx_hash_function =
 887                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 888                         resp.rss_caps.rx_hash_fields_mask =
 889                                                 MLX5_RX_HASH_SRC_IPV4 |
 890                                                 MLX5_RX_HASH_DST_IPV4 |
 891                                                 MLX5_RX_HASH_SRC_IPV6 |
 892                                                 MLX5_RX_HASH_DST_IPV6 |
 893                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 894                                                 MLX5_RX_HASH_DST_PORT_TCP |
 895                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 896                                                 MLX5_RX_HASH_DST_PORT_UDP |
 897                                                 MLX5_RX_HASH_INNER;
 898                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 899                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 900                                 resp.rss_caps.rx_hash_fields_mask |=
 901                                         MLX5_RX_HASH_IPSEC_SPI;
 902                         resp.response_length += sizeof(resp.rss_caps);
 903                 }
 904         } else {
 905                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
 906                         resp.response_length += sizeof(resp.tso_caps);
 907                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
 908                         resp.response_length += sizeof(resp.rss_caps);
 909         }
 910
 911         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 912                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 913                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 914         }
 915
 916         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 917             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 918             raw_support)
 919                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 920
 921         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 922             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 923                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 924
 925         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 926             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 927             raw_support) {
 928                 /* Legacy bit to support old userspace libraries */
 929                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 930                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 931         }
 932
 933         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 934                 props->max_dm_size =
 935                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 936         }
 937
 938         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 939                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 940
 941         if (MLX5_CAP_GEN(mdev, end_pad))
 942                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 943
 944         props->vendor_part_id      = mdev->pdev->device;
 945         props->hw_ver              = mdev->pdev->revision;
 946
 947         props->max_mr_size         = ~0ull;
 948         props->page_size_cap       = ~(min_page_size - 1);
 949         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 950         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 951         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 952                      sizeof(struct mlx5_wqe_data_seg);
 953         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 954         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 955                      sizeof(struct mlx5_wqe_raddr_seg)) /
 956                 sizeof(struct mlx5_wqe_data_seg);
 957         props->max_send_sge = max_sq_sg;
 958         props->max_recv_sge = max_rq_sg;
 959         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 960         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 961         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 962         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 963         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 964         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 965         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 966         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 967         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 968         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 969         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 970         props->max_srq_sge         = max_rq_sg - 1;
 971         props->max_fast_reg_page_list_len =
 972                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 973         props->max_pi_fast_reg_page_list_len =
 974                 props->max_fast_reg_page_list_len / 2;
 975         props->max_sgl_rd =
 976                 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
 977         get_atomic_caps_qp(dev, props);
 978         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 979         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 980         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 981         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 982                                            props->max_mcast_grp;
 983         props->max_ah = INT_MAX;
 984         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 985         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 986
 987         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
 988                 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
 989                         props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 990                 props->odp_caps = dev->odp_caps;
 991                 if (!uhw) {
 992                         /* ODP for kernel QPs is not implemented for receive
 993                          * WQEs and SRQ WQEs
 994                          */
 995                         props->odp_caps.per_transport_caps.rc_odp_caps &=
 996                                 ~(IB_ODP_SUPPORT_READ |
 997                                   IB_ODP_SUPPORT_SRQ_RECV);
 998                         props->odp_caps.per_transport_caps.uc_odp_caps &=
 999                                 ~(IB_ODP_SUPPORT_READ |
1000                                   IB_ODP_SUPPORT_SRQ_RECV);
1001                         props->odp_caps.per_transport_caps.ud_odp_caps &=
1002                                 ~(IB_ODP_SUPPORT_READ |
1003                                   IB_ODP_SUPPORT_SRQ_RECV);
1004                         props->odp_caps.per_transport_caps.xrc_odp_caps &=
1005                                 ~(IB_ODP_SUPPORT_READ |
1006                                   IB_ODP_SUPPORT_SRQ_RECV);
1007                 }
1008         }
1009
1010         if (MLX5_CAP_GEN(mdev, cd))
1011                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1012
1013         if (mlx5_core_is_vf(mdev))
1014                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1015
1016         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1017             IB_LINK_LAYER_ETHERNET && raw_support) {
1018                 props->rss_caps.max_rwq_indirection_tables =
1019                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1020                 props->rss_caps.max_rwq_indirection_table_size =
1021                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1022                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1023                 props->max_wq_type_rq =
1024                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1025         }
1026
1027         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1028                 props->tm_caps.max_num_tags =
1029                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1030                 props->tm_caps.max_ops =
1031                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1032                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1033         }
1034
1035         if (MLX5_CAP_GEN(mdev, tag_matching) &&
1036             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1037                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1038                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1039         }
1040
1041         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1042                 props->cq_caps.max_cq_moderation_count =
1043                                                 MLX5_MAX_CQ_COUNT;
1044                 props->cq_caps.max_cq_moderation_period =
1045                                                 MLX5_MAX_CQ_PERIOD;
1046         }
1047
1048         if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1049                 resp.response_length += sizeof(resp.cqe_comp_caps);
1050
1051                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1052                         resp.cqe_comp_caps.max_num =
1053                                 MLX5_CAP_GEN(dev->mdev,
1054                                              cqe_compression_max_num);
1055
1056                         resp.cqe_comp_caps.supported_format =
1057                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1058                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1059
1060                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1061                                 resp.cqe_comp_caps.supported_format |=
1062                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1063                 }
1064         }
1065
1066         if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1067             raw_support) {
1068                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1069                     MLX5_CAP_GEN(mdev, qos)) {
1070                         resp.packet_pacing_caps.qp_rate_limit_max =
1071                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1072                         resp.packet_pacing_caps.qp_rate_limit_min =
1073                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1074                         resp.packet_pacing_caps.supported_qpts |=
1075                                 1 << IB_QPT_RAW_PACKET;
1076                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1077                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1078                                 resp.packet_pacing_caps.cap_flags |=
1079                                         MLX5_IB_PP_SUPPORT_BURST;
1080                 }
1081                 resp.response_length += sizeof(resp.packet_pacing_caps);
1082         }
1083
1084         if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1085             uhw_outlen) {
1086                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1087                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1088                                 MLX5_IB_ALLOW_MPW;
1089
1090                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1091                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1092                                 MLX5_IB_SUPPORT_EMPW;
1093
1094                 resp.response_length +=
1095                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1096         }
1097
1098         if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1099                 resp.response_length += sizeof(resp.flags);
1100
1101                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1102                         resp.flags |=
1103                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1104
1105                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1106                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1107                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1108                         resp.flags |=
1109                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1110
1111                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1112         }
1113
1114         if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1115                 resp.response_length += sizeof(resp.sw_parsing_caps);
1116                 if (MLX5_CAP_ETH(mdev, swp)) {
1117                         resp.sw_parsing_caps.sw_parsing_offloads |=
1118                                 MLX5_IB_SW_PARSING;
1119
1120                         if (MLX5_CAP_ETH(mdev, swp_csum))
1121                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1122                                         MLX5_IB_SW_PARSING_CSUM;
1123
1124                         if (MLX5_CAP_ETH(mdev, swp_lso))
1125                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1126                                         MLX5_IB_SW_PARSING_LSO;
1127
1128                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1129                                 resp.sw_parsing_caps.supported_qpts =
1130                                         BIT(IB_QPT_RAW_PACKET);
1131                 }
1132         }
1133
1134         if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1135             raw_support) {
1136                 resp.response_length += sizeof(resp.striding_rq_caps);
1137                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1138                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1139                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1140                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1141                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1142                         if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1143                                 resp.striding_rq_caps
1144                                         .min_single_wqe_log_num_of_strides =
1145                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1146                         else
1147                                 resp.striding_rq_caps
1148                                         .min_single_wqe_log_num_of_strides =
1149                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1150                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1151                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1152                         resp.striding_rq_caps.supported_qpts =
1153                                 BIT(IB_QPT_RAW_PACKET);
1154                 }
1155         }
1156
1157         if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1158                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1159                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1160                         resp.tunnel_offloads_caps |=
1161                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1162                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1163                         resp.tunnel_offloads_caps |=
1164                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1165                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1166                         resp.tunnel_offloads_caps |=
1167                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1168                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1169                         resp.tunnel_offloads_caps |=
1170                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1171                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1172                         resp.tunnel_offloads_caps |=
1173                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1174         }
1175
1176         if (uhw_outlen) {
1177                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1178
1179                 if (err)
1180                         return err;
1181         }
1182
1183         return 0;
1184 }
1185
1186 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1187                                    u8 *ib_width)
1188 {
1189         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1190
1191         if (active_width & MLX5_PTYS_WIDTH_1X)
1192                 *ib_width = IB_WIDTH_1X;
1193         else if (active_width & MLX5_PTYS_WIDTH_2X)
1194                 *ib_width = IB_WIDTH_2X;
1195         else if (active_width & MLX5_PTYS_WIDTH_4X)
1196                 *ib_width = IB_WIDTH_4X;
1197         else if (active_width & MLX5_PTYS_WIDTH_8X)
1198                 *ib_width = IB_WIDTH_8X;
1199         else if (active_width & MLX5_PTYS_WIDTH_12X)
1200                 *ib_width = IB_WIDTH_12X;
1201         else {
1202                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1203                             active_width);
1204                 *ib_width = IB_WIDTH_4X;
1205         }
1206
1207         return;
1208 }
1209
1210 static int mlx5_mtu_to_ib_mtu(int mtu)
1211 {
1212         switch (mtu) {
1213         case 256: return 1;
1214         case 512: return 2;
1215         case 1024: return 3;
1216         case 2048: return 4;
1217         case 4096: return 5;
1218         default:
1219                 pr_warn("invalid mtu\n");
1220                 return -1;
1221         }
1222 }
1223
1224 enum ib_max_vl_num {
1225         __IB_MAX_VL_0           = 1,
1226         __IB_MAX_VL_0_1         = 2,
1227         __IB_MAX_VL_0_3         = 3,
1228         __IB_MAX_VL_0_7         = 4,
1229         __IB_MAX_VL_0_14        = 5,
1230 };
1231
1232 enum mlx5_vl_hw_cap {
1233         MLX5_VL_HW_0    = 1,
1234         MLX5_VL_HW_0_1  = 2,
1235         MLX5_VL_HW_0_2  = 3,
1236         MLX5_VL_HW_0_3  = 4,
1237         MLX5_VL_HW_0_4  = 5,
1238         MLX5_VL_HW_0_5  = 6,
1239         MLX5_VL_HW_0_6  = 7,
1240         MLX5_VL_HW_0_7  = 8,
1241         MLX5_VL_HW_0_14 = 15
1242 };
1243
1244 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1245                                 u8 *max_vl_num)
1246 {
1247         switch (vl_hw_cap) {
1248         case MLX5_VL_HW_0:
1249                 *max_vl_num = __IB_MAX_VL_0;
1250                 break;
1251         case MLX5_VL_HW_0_1:
1252                 *max_vl_num = __IB_MAX_VL_0_1;
1253                 break;
1254         case MLX5_VL_HW_0_3:
1255                 *max_vl_num = __IB_MAX_VL_0_3;
1256                 break;
1257         case MLX5_VL_HW_0_7:
1258                 *max_vl_num = __IB_MAX_VL_0_7;
1259                 break;
1260         case MLX5_VL_HW_0_14:
1261                 *max_vl_num = __IB_MAX_VL_0_14;
1262                 break;
1263
1264         default:
1265                 return -EINVAL;
1266         }
1267
1268         return 0;
1269 }
1270
1271 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1272                                struct ib_port_attr *props)
1273 {
1274         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1275         struct mlx5_core_dev *mdev = dev->mdev;
1276         struct mlx5_hca_vport_context *rep;
1277         u16 max_mtu;
1278         u16 oper_mtu;
1279         int err;
1280         u16 ib_link_width_oper;
1281         u8 vl_hw_cap;
1282
1283         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1284         if (!rep) {
1285                 err = -ENOMEM;
1286                 goto out;
1287         }
1288
1289         /* props being zeroed by the caller, avoid zeroing it here */
1290
1291         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1292         if (err)
1293                 goto out;
1294
1295         props->lid              = rep->lid;
1296         props->lmc              = rep->lmc;
1297         props->sm_lid           = rep->sm_lid;
1298         props->sm_sl            = rep->sm_sl;
1299         props->state            = rep->vport_state;
1300         props->phys_state       = rep->port_physical_state;
1301         props->port_cap_flags   = rep->cap_mask1;
1302         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1303         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1304         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1305         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1306         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1307         props->subnet_timeout   = rep->subnet_timeout;
1308         props->init_type_reply  = rep->init_type_reply;
1309
1310         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1311                 props->port_cap_flags2 = rep->cap_mask2;
1312
1313         err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1314                                       &props->active_speed, port);
1315         if (err)
1316                 goto out;
1317
1318         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1319
1320         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1321
1322         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1323
1324         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1325
1326         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1327
1328         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1329         if (err)
1330                 goto out;
1331
1332         err = translate_max_vl_num(ibdev, vl_hw_cap,
1333                                    &props->max_vl_num);
1334 out:
1335         kfree(rep);
1336         return err;
1337 }
1338
1339 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1340                        struct ib_port_attr *props)
1341 {
1342         unsigned int count;
1343         int ret;
1344
1345         switch (mlx5_get_vport_access_method(ibdev)) {
1346         case MLX5_VPORT_ACCESS_METHOD_MAD:
1347                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1348                 break;
1349
1350         case MLX5_VPORT_ACCESS_METHOD_HCA:
1351                 ret = mlx5_query_hca_port(ibdev, port, props);
1352                 break;
1353
1354         case MLX5_VPORT_ACCESS_METHOD_NIC:
1355                 ret = mlx5_query_port_roce(ibdev, port, props);
1356                 break;
1357
1358         default:
1359                 ret = -EINVAL;
1360         }
1361
1362         if (!ret && props) {
1363                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1364                 struct mlx5_core_dev *mdev;
1365                 bool put_mdev = true;
1366
1367                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1368                 if (!mdev) {
1369                         /* If the port isn't affiliated yet query the master.
1370                          * The master and slave will have the same values.
1371                          */
1372                         mdev = dev->mdev;
1373                         port = 1;
1374                         put_mdev = false;
1375                 }
1376                 count = mlx5_core_reserved_gids_count(mdev);
1377                 if (put_mdev)
1378                         mlx5_ib_put_native_port_mdev(dev, port);
1379                 props->gid_tbl_len -= count;
1380         }
1381         return ret;
1382 }
1383
1384 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1385                                   struct ib_port_attr *props)
1386 {
1387         int ret;
1388
1389         /* Only link layer == ethernet is valid for representors
1390          * and we always use port 1
1391          */
1392         ret = mlx5_query_port_roce(ibdev, port, props);
1393         if (ret || !props)
1394                 return ret;
1395
1396         /* We don't support GIDS */
1397         props->gid_tbl_len = 0;
1398
1399         return ret;
1400 }
1401
1402 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1403                              union ib_gid *gid)
1404 {
1405         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1406         struct mlx5_core_dev *mdev = dev->mdev;
1407
1408         switch (mlx5_get_vport_access_method(ibdev)) {
1409         case MLX5_VPORT_ACCESS_METHOD_MAD:
1410                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1411
1412         case MLX5_VPORT_ACCESS_METHOD_HCA:
1413                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1414
1415         default:
1416                 return -EINVAL;
1417         }
1418
1419 }
1420
1421 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1422                                    u16 index, u16 *pkey)
1423 {
1424         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1425         struct mlx5_core_dev *mdev;
1426         bool put_mdev = true;
1427         u8 mdev_port_num;
1428         int err;
1429
1430         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1431         if (!mdev) {
1432                 /* The port isn't affiliated yet, get the PKey from the master
1433                  * port. For RoCE the PKey tables will be the same.
1434                  */
1435                 put_mdev = false;
1436                 mdev = dev->mdev;
1437                 mdev_port_num = 1;
1438         }
1439
1440         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1441                                         index, pkey);
1442         if (put_mdev)
1443                 mlx5_ib_put_native_port_mdev(dev, port);
1444
1445         return err;
1446 }
1447
1448 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1449                               u16 *pkey)
1450 {
1451         switch (mlx5_get_vport_access_method(ibdev)) {
1452         case MLX5_VPORT_ACCESS_METHOD_MAD:
1453                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1454
1455         case MLX5_VPORT_ACCESS_METHOD_HCA:
1456         case MLX5_VPORT_ACCESS_METHOD_NIC:
1457                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1458         default:
1459                 return -EINVAL;
1460         }
1461 }
1462
1463 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1464                                  struct ib_device_modify *props)
1465 {
1466         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1467         struct mlx5_reg_node_desc in;
1468         struct mlx5_reg_node_desc out;
1469         int err;
1470
1471         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1472                 return -EOPNOTSUPP;
1473
1474         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1475                 return 0;
1476
1477         /*
1478          * If possible, pass node desc to FW, so it can generate
1479          * a 144 trap.  If cmd fails, just ignore.
1480          */
1481         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1482         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1483                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1484         if (err)
1485                 return err;
1486
1487         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1488
1489         return err;
1490 }
1491
1492 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1493                                 u32 value)
1494 {
1495         struct mlx5_hca_vport_context ctx = {};
1496         struct mlx5_core_dev *mdev;
1497         u8 mdev_port_num;
1498         int err;
1499
1500         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1501         if (!mdev)
1502                 return -ENODEV;
1503
1504         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1505         if (err)
1506                 goto out;
1507
1508         if (~ctx.cap_mask1_perm & mask) {
1509                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1510                              mask, ctx.cap_mask1_perm);
1511                 err = -EINVAL;
1512                 goto out;
1513         }
1514
1515         ctx.cap_mask1 = value;
1516         ctx.cap_mask1_perm = mask;
1517         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1518                                                  0, &ctx);
1519
1520 out:
1521         mlx5_ib_put_native_port_mdev(dev, port_num);
1522
1523         return err;
1524 }
1525
1526 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1527                                struct ib_port_modify *props)
1528 {
1529         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1530         struct ib_port_attr attr;
1531         u32 tmp;
1532         int err;
1533         u32 change_mask;
1534         u32 value;
1535         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1536                       IB_LINK_LAYER_INFINIBAND);
1537
1538         /* CM layer calls ib_modify_port() regardless of the link layer. For
1539          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1540          */
1541         if (!is_ib)
1542                 return 0;
1543
1544         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1545                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1546                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1547                 return set_port_caps_atomic(dev, port, change_mask, value);
1548         }
1549
1550         mutex_lock(&dev->cap_mask_mutex);
1551
1552         err = ib_query_port(ibdev, port, &attr);
1553         if (err)
1554                 goto out;
1555
1556         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1557                 ~props->clr_port_cap_mask;
1558
1559         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1560
1561 out:
1562         mutex_unlock(&dev->cap_mask_mutex);
1563         return err;
1564 }
1565
1566 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1567 {
1568         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1569                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1570 }
1571
1572 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1573 {
1574         /* Large page with non 4k uar support might limit the dynamic size */
1575         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1576                 return MLX5_MIN_DYN_BFREGS;
1577
1578         return MLX5_MAX_DYN_BFREGS;
1579 }
1580
1581 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1582                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1583                              struct mlx5_bfreg_info *bfregi)
1584 {
1585         int uars_per_sys_page;
1586         int bfregs_per_sys_page;
1587         int ref_bfregs = req->total_num_bfregs;
1588
1589         if (req->total_num_bfregs == 0)
1590                 return -EINVAL;
1591
1592         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1593         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1594
1595         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1596                 return -ENOMEM;
1597
1598         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1599         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1600         /* This holds the required static allocation asked by the user */
1601         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1602         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1603                 return -EINVAL;
1604
1605         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1606         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1607         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1608         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1609
1610         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1611                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1612                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1613                     req->total_num_bfregs, bfregi->total_num_bfregs,
1614                     bfregi->num_sys_pages);
1615
1616         return 0;
1617 }
1618
1619 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1620 {
1621         struct mlx5_bfreg_info *bfregi;
1622         int err;
1623         int i;
1624
1625         bfregi = &context->bfregi;
1626         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1627                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1628                 if (err)
1629                         goto error;
1630
1631                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1632         }
1633
1634         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1635                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1636
1637         return 0;
1638
1639 error:
1640         for (--i; i >= 0; i--)
1641                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1642                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1643
1644         return err;
1645 }
1646
1647 static void deallocate_uars(struct mlx5_ib_dev *dev,
1648                             struct mlx5_ib_ucontext *context)
1649 {
1650         struct mlx5_bfreg_info *bfregi;
1651         int i;
1652
1653         bfregi = &context->bfregi;
1654         for (i = 0; i < bfregi->num_sys_pages; i++)
1655                 if (i < bfregi->num_static_sys_pages ||
1656                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1657                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1658 }
1659
1660 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1661 {
1662         int err = 0;
1663
1664         mutex_lock(&dev->lb.mutex);
1665         if (td)
1666                 dev->lb.user_td++;
1667         if (qp)
1668                 dev->lb.qps++;
1669
1670         if (dev->lb.user_td == 2 ||
1671             dev->lb.qps == 1) {
1672                 if (!dev->lb.enabled) {
1673                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1674                         dev->lb.enabled = true;
1675                 }
1676         }
1677
1678         mutex_unlock(&dev->lb.mutex);
1679
1680         return err;
1681 }
1682
1683 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1684 {
1685         mutex_lock(&dev->lb.mutex);
1686         if (td)
1687                 dev->lb.user_td--;
1688         if (qp)
1689                 dev->lb.qps--;
1690
1691         if (dev->lb.user_td == 1 &&
1692             dev->lb.qps == 0) {
1693                 if (dev->lb.enabled) {
1694                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1695                         dev->lb.enabled = false;
1696                 }
1697         }
1698
1699         mutex_unlock(&dev->lb.mutex);
1700 }
1701
1702 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1703                                           u16 uid)
1704 {
1705         int err;
1706
1707         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1708                 return 0;
1709
1710         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1711         if (err)
1712                 return err;
1713
1714         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1715             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1716              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1717                 return err;
1718
1719         return mlx5_ib_enable_lb(dev, true, false);
1720 }
1721
1722 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1723                                              u16 uid)
1724 {
1725         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1726                 return;
1727
1728         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1729
1730         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1731             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1732              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1733                 return;
1734
1735         mlx5_ib_disable_lb(dev, true, false);
1736 }
1737
1738 static int set_ucontext_resp(struct ib_ucontext *uctx,
1739                              struct mlx5_ib_alloc_ucontext_resp *resp)
1740 {
1741         struct ib_device *ibdev = uctx->device;
1742         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1743         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1744         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1745         int err;
1746
1747         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1748                 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1749                                               &resp->dump_fill_mkey);
1750                 if (err)
1751                         return err;
1752                 resp->comp_mask |=
1753                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1754         }
1755
1756         resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1757         if (dev->wc_support)
1758                 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1759                                                       log_bf_reg_size);
1760         resp->cache_line_size = cache_line_size();
1761         resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1762         resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1763         resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1764         resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1765         resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1766         resp->cqe_version = context->cqe_version;
1767         resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1768                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1769         resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1770                                         MLX5_CAP_GEN(dev->mdev,
1771                                                      num_of_uars_per_page) : 1;
1772
1773         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1774                                 MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1775                 if (mlx5_get_flow_namespace(dev->mdev,
1776                                 MLX5_FLOW_NAMESPACE_EGRESS))
1777                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1778                 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1779                                 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1780                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1781                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1782                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1783                 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1784                                 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1785                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1786                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1787         }
1788
1789         resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1790                         bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1791         resp->num_ports = dev->num_ports;
1792         resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1793                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1794
1795         if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1796                 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1797                 resp->eth_min_inline++;
1798         }
1799
1800         if (dev->mdev->clock_info)
1801                 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1802
1803         /*
1804          * We don't want to expose information from the PCI bar that is located
1805          * after 4096 bytes, so if the arch only supports larger pages, let's
1806          * pretend we don't support reading the HCA's core clock. This is also
1807          * forced by mmap function.
1808          */
1809         if (PAGE_SIZE <= 4096) {
1810                 resp->comp_mask |=
1811                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1812                 resp->hca_core_clock_offset =
1813                         offsetof(struct mlx5_init_seg,
1814                                  internal_timer_h) % PAGE_SIZE;
1815         }
1816
1817         if (MLX5_CAP_GEN(dev->mdev, ece_support))
1818                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1819
1820         resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1821         return 0;
1822 }
1823
1824 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1825                                   struct ib_udata *udata)
1826 {
1827         struct ib_device *ibdev = uctx->device;
1828         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1829         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1830         struct mlx5_ib_alloc_ucontext_resp resp = {};
1831         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1832         struct mlx5_bfreg_info *bfregi;
1833         int ver;
1834         int err;
1835         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1836                                      max_cqe_version);
1837         bool lib_uar_4k;
1838         bool lib_uar_dyn;
1839
1840         if (!dev->ib_active)
1841                 return -EAGAIN;
1842
1843         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1844                 ver = 0;
1845         else if (udata->inlen >= min_req_v2)
1846                 ver = 2;
1847         else
1848                 return -EINVAL;
1849
1850         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1851         if (err)
1852                 return err;
1853
1854         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1855                 return -EOPNOTSUPP;
1856
1857         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1858                 return -EOPNOTSUPP;
1859
1860         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1861                                     MLX5_NON_FP_BFREGS_PER_UAR);
1862         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1863                 return -EINVAL;
1864
1865         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1866         lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1867         bfregi = &context->bfregi;
1868
1869         if (lib_uar_dyn) {
1870                 bfregi->lib_uar_dyn = lib_uar_dyn;
1871                 goto uar_done;
1872         }
1873
1874         /* updates req->total_num_bfregs */
1875         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1876         if (err)
1877                 goto out_ctx;
1878
1879         mutex_init(&bfregi->lock);
1880         bfregi->lib_uar_4k = lib_uar_4k;
1881         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1882                                 GFP_KERNEL);
1883         if (!bfregi->count) {
1884                 err = -ENOMEM;
1885                 goto out_ctx;
1886         }
1887
1888         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1889                                     sizeof(*bfregi->sys_pages),
1890                                     GFP_KERNEL);
1891         if (!bfregi->sys_pages) {
1892                 err = -ENOMEM;
1893                 goto out_count;
1894         }
1895
1896         err = allocate_uars(dev, context);
1897         if (err)
1898                 goto out_sys_pages;
1899
1900 uar_done:
1901         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1902                 err = mlx5_ib_devx_create(dev, true);
1903                 if (err < 0)
1904                         goto out_uars;
1905                 context->devx_uid = err;
1906         }
1907
1908         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1909                                              context->devx_uid);
1910         if (err)
1911                 goto out_devx;
1912
1913         INIT_LIST_HEAD(&context->db_page_list);
1914         mutex_init(&context->db_page_mutex);
1915
1916         context->cqe_version = min_t(__u8,
1917                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1918                                  req.max_cqe_version);
1919
1920         err = set_ucontext_resp(uctx, &resp);
1921         if (err)
1922                 goto out_mdev;
1923
1924         resp.response_length = min(udata->outlen, sizeof(resp));
1925         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1926         if (err)
1927                 goto out_mdev;
1928
1929         bfregi->ver = ver;
1930         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1931         context->lib_caps = req.lib_caps;
1932         print_lib_caps(dev, context->lib_caps);
1933
1934         if (mlx5_ib_lag_should_assign_affinity(dev)) {
1935                 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1936
1937                 atomic_set(&context->tx_port_affinity,
1938                            atomic_add_return(
1939                                    1, &dev->port[port].roce.tx_port_affinity));
1940         }
1941
1942         return 0;
1943
1944 out_mdev:
1945         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1946 out_devx:
1947         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1948                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1949
1950 out_uars:
1951         deallocate_uars(dev, context);
1952
1953 out_sys_pages:
1954         kfree(bfregi->sys_pages);
1955
1956 out_count:
1957         kfree(bfregi->count);
1958
1959 out_ctx:
1960         return err;
1961 }
1962
1963 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1964                                   struct uverbs_attr_bundle *attrs)
1965 {
1966         struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1967         int ret;
1968
1969         ret = set_ucontext_resp(ibcontext, &uctx_resp);
1970         if (ret)
1971                 return ret;
1972
1973         uctx_resp.response_length =
1974                 min_t(size_t,
1975                       uverbs_attr_get_len(attrs,
1976                                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1977                       sizeof(uctx_resp));
1978
1979         ret = uverbs_copy_to_struct_or_zero(attrs,
1980                                         MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
1981                                         &uctx_resp,
1982                                         sizeof(uctx_resp));
1983         return ret;
1984 }
1985
1986 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1987 {
1988         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1989         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1990         struct mlx5_bfreg_info *bfregi;
1991
1992         bfregi = &context->bfregi;
1993         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1994
1995         if (context->devx_uid)
1996                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1997
1998         deallocate_uars(dev, context);
1999         kfree(bfregi->sys_pages);
2000         kfree(bfregi->count);
2001 }
2002
2003 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2004                                  int uar_idx)
2005 {
2006         int fw_uars_per_page;
2007
2008         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2009
2010         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2011 }
2012
2013 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2014                                  int uar_idx)
2015 {
2016         unsigned int fw_uars_per_page;
2017
2018         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2019                                 MLX5_UARS_IN_PAGE : 1;
2020
2021         return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2022 }
2023
2024 static int get_command(unsigned long offset)
2025 {
2026         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2027 }
2028
2029 static int get_arg(unsigned long offset)
2030 {
2031         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2032 }
2033
2034 static int get_index(unsigned long offset)
2035 {
2036         return get_arg(offset);
2037 }
2038
2039 /* Index resides in an extra byte to enable larger values than 255 */
2040 static int get_extended_index(unsigned long offset)
2041 {
2042         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2043 }
2044
2045
2046 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2047 {
2048 }
2049
2050 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2051 {
2052         switch (cmd) {
2053         case MLX5_IB_MMAP_WC_PAGE:
2054                 return "WC";
2055         case MLX5_IB_MMAP_REGULAR_PAGE:
2056                 return "best effort WC";
2057         case MLX5_IB_MMAP_NC_PAGE:
2058                 return "NC";
2059         case MLX5_IB_MMAP_DEVICE_MEM:
2060                 return "Device Memory";
2061         default:
2062                 return NULL;
2063         }
2064 }
2065
2066 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2067                                         struct vm_area_struct *vma,
2068                                         struct mlx5_ib_ucontext *context)
2069 {
2070         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2071             !(vma->vm_flags & VM_SHARED))
2072                 return -EINVAL;
2073
2074         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2075                 return -EOPNOTSUPP;
2076
2077         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2078                 return -EPERM;
2079         vma->vm_flags &= ~VM_MAYWRITE;
2080
2081         if (!dev->mdev->clock_info)
2082                 return -EOPNOTSUPP;
2083
2084         return vm_insert_page(vma, vma->vm_start,
2085                               virt_to_page(dev->mdev->clock_info));
2086 }
2087
2088 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2089 {
2090         struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2091         struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2092         struct mlx5_var_table *var_table = &dev->var_table;
2093         struct mlx5_ib_dm *mdm;
2094
2095         switch (mentry->mmap_flag) {
2096         case MLX5_IB_MMAP_TYPE_MEMIC:
2097                 mdm = container_of(mentry, struct mlx5_ib_dm, mentry);
2098                 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr,
2099                                        mdm->size);
2100                 kfree(mdm);
2101                 break;
2102         case MLX5_IB_MMAP_TYPE_VAR:
2103                 mutex_lock(&var_table->bitmap_lock);
2104                 clear_bit(mentry->page_idx, var_table->bitmap);
2105                 mutex_unlock(&var_table->bitmap_lock);
2106                 kfree(mentry);
2107                 break;
2108         case MLX5_IB_MMAP_TYPE_UAR_WC:
2109         case MLX5_IB_MMAP_TYPE_UAR_NC:
2110                 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2111                 kfree(mentry);
2112                 break;
2113         default:
2114                 WARN_ON(true);
2115         }
2116 }
2117
2118 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2119                     struct vm_area_struct *vma,
2120                     struct mlx5_ib_ucontext *context)
2121 {
2122         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2123         int err;
2124         unsigned long idx;
2125         phys_addr_t pfn;
2126         pgprot_t prot;
2127         u32 bfreg_dyn_idx = 0;
2128         u32 uar_index;
2129         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2130         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2131                                 bfregi->num_static_sys_pages;
2132
2133         if (bfregi->lib_uar_dyn)
2134                 return -EINVAL;
2135
2136         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2137                 return -EINVAL;
2138
2139         if (dyn_uar)
2140                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2141         else
2142                 idx = get_index(vma->vm_pgoff);
2143
2144         if (idx >= max_valid_idx) {
2145                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2146                              idx, max_valid_idx);
2147                 return -EINVAL;
2148         }
2149
2150         switch (cmd) {
2151         case MLX5_IB_MMAP_WC_PAGE:
2152         case MLX5_IB_MMAP_ALLOC_WC:
2153         case MLX5_IB_MMAP_REGULAR_PAGE:
2154                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2155                 prot = pgprot_writecombine(vma->vm_page_prot);
2156                 break;
2157         case MLX5_IB_MMAP_NC_PAGE:
2158                 prot = pgprot_noncached(vma->vm_page_prot);
2159                 break;
2160         default:
2161                 return -EINVAL;
2162         }
2163
2164         if (dyn_uar) {
2165                 int uars_per_page;
2166
2167                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2168                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2169                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2170                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2171                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2172                         return -EINVAL;
2173                 }
2174
2175                 mutex_lock(&bfregi->lock);
2176                 /* Fail if uar already allocated, first bfreg index of each
2177                  * page holds its count.
2178                  */
2179                 if (bfregi->count[bfreg_dyn_idx]) {
2180                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2181                         mutex_unlock(&bfregi->lock);
2182                         return -EINVAL;
2183                 }
2184
2185                 bfregi->count[bfreg_dyn_idx]++;
2186                 mutex_unlock(&bfregi->lock);
2187
2188                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2189                 if (err) {
2190                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2191                         goto free_bfreg;
2192                 }
2193         } else {
2194                 uar_index = bfregi->sys_pages[idx];
2195         }
2196
2197         pfn = uar_index2pfn(dev, uar_index);
2198         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2199
2200         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2201                                 prot, NULL);
2202         if (err) {
2203                 mlx5_ib_err(dev,
2204                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2205                             err, mmap_cmd2str(cmd));
2206                 goto err;
2207         }
2208
2209         if (dyn_uar)
2210                 bfregi->sys_pages[idx] = uar_index;
2211         return 0;
2212
2213 err:
2214         if (!dyn_uar)
2215                 return err;
2216
2217         mlx5_cmd_free_uar(dev->mdev, idx);
2218
2219 free_bfreg:
2220         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2221
2222         return err;
2223 }
2224
2225 static int add_dm_mmap_entry(struct ib_ucontext *context,
2226                              struct mlx5_ib_dm *mdm,
2227                              u64 address)
2228 {
2229         mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC;
2230         mdm->mentry.address = address;
2231         return rdma_user_mmap_entry_insert_range(
2232                         context, &mdm->mentry.rdma_entry,
2233                         mdm->size,
2234                         MLX5_IB_MMAP_DEVICE_MEM << 16,
2235                         (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1);
2236 }
2237
2238 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2239 {
2240         unsigned long idx;
2241         u8 command;
2242
2243         command = get_command(vma->vm_pgoff);
2244         idx = get_extended_index(vma->vm_pgoff);
2245
2246         return (command << 16 | idx);
2247 }
2248
2249 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2250                                struct vm_area_struct *vma,
2251                                struct ib_ucontext *ucontext)
2252 {
2253         struct mlx5_user_mmap_entry *mentry;
2254         struct rdma_user_mmap_entry *entry;
2255         unsigned long pgoff;
2256         pgprot_t prot;
2257         phys_addr_t pfn;
2258         int ret;
2259
2260         pgoff = mlx5_vma_to_pgoff(vma);
2261         entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2262         if (!entry)
2263                 return -EINVAL;
2264
2265         mentry = to_mmmap(entry);
2266         pfn = (mentry->address >> PAGE_SHIFT);
2267         if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2268             mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2269                 prot = pgprot_noncached(vma->vm_page_prot);
2270         else
2271                 prot = pgprot_writecombine(vma->vm_page_prot);
2272         ret = rdma_user_mmap_io(ucontext, vma, pfn,
2273                                 entry->npages * PAGE_SIZE,
2274                                 prot,
2275                                 entry);
2276         rdma_user_mmap_entry_put(&mentry->rdma_entry);
2277         return ret;
2278 }
2279
2280 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2281 {
2282         u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2283         u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2284
2285         return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2286                 (index & 0xFF)) << PAGE_SHIFT;
2287 }
2288
2289 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2290 {
2291         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2292         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2293         unsigned long command;
2294         phys_addr_t pfn;
2295
2296         command = get_command(vma->vm_pgoff);
2297         switch (command) {
2298         case MLX5_IB_MMAP_WC_PAGE:
2299         case MLX5_IB_MMAP_ALLOC_WC:
2300                 if (!dev->wc_support)
2301                         return -EPERM;
2302                 fallthrough;
2303         case MLX5_IB_MMAP_NC_PAGE:
2304         case MLX5_IB_MMAP_REGULAR_PAGE:
2305                 return uar_mmap(dev, command, vma, context);
2306
2307         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2308                 return -ENOSYS;
2309
2310         case MLX5_IB_MMAP_CORE_CLOCK:
2311                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2312                         return -EINVAL;
2313
2314                 if (vma->vm_flags & VM_WRITE)
2315                         return -EPERM;
2316                 vma->vm_flags &= ~VM_MAYWRITE;
2317
2318                 /* Don't expose to user-space information it shouldn't have */
2319                 if (PAGE_SIZE > 4096)
2320                         return -EOPNOTSUPP;
2321
2322                 pfn = (dev->mdev->iseg_base +
2323                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2324                         PAGE_SHIFT;
2325                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2326                                          PAGE_SIZE,
2327                                          pgprot_noncached(vma->vm_page_prot),
2328                                          NULL);
2329         case MLX5_IB_MMAP_CLOCK_INFO:
2330                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2331
2332         default:
2333                 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2334         }
2335
2336         return 0;
2337 }
2338
2339 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2340                                         u32 type)
2341 {
2342         switch (type) {
2343         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2344                 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2345                         return -EOPNOTSUPP;
2346                 break;
2347         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2348         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2349                 if (!capable(CAP_SYS_RAWIO) ||
2350                     !capable(CAP_NET_RAW))
2351                         return -EPERM;
2352
2353                 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2354                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) ||
2355                       MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) ||
2356                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2)))
2357                         return -EOPNOTSUPP;
2358                 break;
2359         }
2360
2361         return 0;
2362 }
2363
2364 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2365                                  struct mlx5_ib_dm *dm,
2366                                  struct ib_dm_alloc_attr *attr,
2367                                  struct uverbs_attr_bundle *attrs)
2368 {
2369         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2370         u64 start_offset;
2371         u16 page_idx;
2372         int err;
2373         u64 address;
2374
2375         dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2376
2377         err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2378                                    dm->size, attr->alignment);
2379         if (err)
2380                 return err;
2381
2382         address = dm->dev_addr & PAGE_MASK;
2383         err = add_dm_mmap_entry(ctx, dm, address);
2384         if (err)
2385                 goto err_dealloc;
2386
2387         page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF;
2388         err = uverbs_copy_to(attrs,
2389                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2390                              &page_idx,
2391                              sizeof(page_idx));
2392         if (err)
2393                 goto err_copy;
2394
2395         start_offset = dm->dev_addr & ~PAGE_MASK;
2396         err = uverbs_copy_to(attrs,
2397                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2398                              &start_offset, sizeof(start_offset));
2399         if (err)
2400                 goto err_copy;
2401
2402         return 0;
2403
2404 err_copy:
2405         rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2406 err_dealloc:
2407         mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2408
2409         return err;
2410 }
2411
2412 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2413                                   struct mlx5_ib_dm *dm,
2414                                   struct ib_dm_alloc_attr *attr,
2415                                   struct uverbs_attr_bundle *attrs,
2416                                   int type)
2417 {
2418         struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
2419         u64 act_size;
2420         int err;
2421
2422         /* Allocation size must a multiple of the basic block size
2423          * and a power of 2.
2424          */
2425         act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
2426         act_size = roundup_pow_of_two(act_size);
2427
2428         dm->size = act_size;
2429         err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment,
2430                                    to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2431                                    &dm->icm_dm.obj_id);
2432         if (err)
2433                 return err;
2434
2435         err = uverbs_copy_to(attrs,
2436                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2437                              &dm->dev_addr, sizeof(dm->dev_addr));
2438         if (err)
2439                 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2440                                        to_mucontext(ctx)->devx_uid, dm->dev_addr,
2441                                        dm->icm_dm.obj_id);
2442
2443         return err;
2444 }
2445
2446 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2447                                struct ib_ucontext *context,
2448                                struct ib_dm_alloc_attr *attr,
2449                                struct uverbs_attr_bundle *attrs)
2450 {
2451         struct mlx5_ib_dm *dm;
2452         enum mlx5_ib_uapi_dm_type type;
2453         int err;
2454
2455         err = uverbs_get_const_default(&type, attrs,
2456                                        MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2457                                        MLX5_IB_UAPI_DM_TYPE_MEMIC);
2458         if (err)
2459                 return ERR_PTR(err);
2460
2461         mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2462                     type, attr->length, attr->alignment);
2463
2464         err = check_dm_type_support(to_mdev(ibdev), type);
2465         if (err)
2466                 return ERR_PTR(err);
2467
2468         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2469         if (!dm)
2470                 return ERR_PTR(-ENOMEM);
2471
2472         dm->type = type;
2473
2474         switch (type) {
2475         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2476                 err = handle_alloc_dm_memic(context, dm,
2477                                             attr,
2478                                             attrs);
2479                 break;
2480         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2481                 err = handle_alloc_dm_sw_icm(context, dm,
2482                                              attr, attrs,
2483                                              MLX5_SW_ICM_TYPE_STEERING);
2484                 break;
2485         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2486                 err = handle_alloc_dm_sw_icm(context, dm,
2487                                              attr, attrs,
2488                                              MLX5_SW_ICM_TYPE_HEADER_MODIFY);
2489                 break;
2490         default:
2491                 err = -EOPNOTSUPP;
2492         }
2493
2494         if (err)
2495                 goto err_free;
2496
2497         return &dm->ibdm;
2498
2499 err_free:
2500         kfree(dm);
2501         return ERR_PTR(err);
2502 }
2503
2504 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2505 {
2506         struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2507                 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2508         struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
2509         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2510         int ret;
2511
2512         switch (dm->type) {
2513         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2514                 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2515                 return 0;
2516         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2517                 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2518                                              dm->size, ctx->devx_uid, dm->dev_addr,
2519                                              dm->icm_dm.obj_id);
2520                 if (ret)
2521                         return ret;
2522                 break;
2523         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2524                 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2525                                              dm->size, ctx->devx_uid, dm->dev_addr,
2526                                              dm->icm_dm.obj_id);
2527                 if (ret)
2528                         return ret;
2529                 break;
2530         default:
2531                 return -EOPNOTSUPP;
2532         }
2533
2534         kfree(dm);
2535
2536         return 0;
2537 }
2538
2539 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2540 {
2541         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2542         struct ib_device *ibdev = ibpd->device;
2543         struct mlx5_ib_alloc_pd_resp resp;
2544         int err;
2545         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2546         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2547         u16 uid = 0;
2548         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2549                 udata, struct mlx5_ib_ucontext, ibucontext);
2550
2551         uid = context ? context->devx_uid : 0;
2552         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2553         MLX5_SET(alloc_pd_in, in, uid, uid);
2554         err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2555         if (err)
2556                 return err;
2557
2558         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2559         pd->uid = uid;
2560         if (udata) {
2561                 resp.pdn = pd->pdn;
2562                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2563                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2564                         return -EFAULT;
2565                 }
2566         }
2567
2568         return 0;
2569 }
2570
2571 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2572 {
2573         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2574         struct mlx5_ib_pd *mpd = to_mpd(pd);
2575
2576         return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2577 }
2578
2579 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2580 {
2581         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2582         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2583         int err;
2584         u16 uid;
2585
2586         uid = ibqp->pd ?
2587                 to_mpd(ibqp->pd)->uid : 0;
2588
2589         if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2590                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2591                 return -EOPNOTSUPP;
2592         }
2593
2594         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2595         if (err)
2596                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2597                              ibqp->qp_num, gid->raw);
2598
2599         return err;
2600 }
2601
2602 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2603 {
2604         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2605         int err;
2606         u16 uid;
2607
2608         uid = ibqp->pd ?
2609                 to_mpd(ibqp->pd)->uid : 0;
2610         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2611         if (err)
2612                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2613                              ibqp->qp_num, gid->raw);
2614
2615         return err;
2616 }
2617
2618 static int init_node_data(struct mlx5_ib_dev *dev)
2619 {
2620         int err;
2621
2622         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2623         if (err)
2624                 return err;
2625
2626         dev->mdev->rev_id = dev->mdev->pdev->revision;
2627
2628         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2629 }
2630
2631 static ssize_t fw_pages_show(struct device *device,
2632                              struct device_attribute *attr, char *buf)
2633 {
2634         struct mlx5_ib_dev *dev =
2635                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2636
2637         return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2638 }
2639 static DEVICE_ATTR_RO(fw_pages);
2640
2641 static ssize_t reg_pages_show(struct device *device,
2642                               struct device_attribute *attr, char *buf)
2643 {
2644         struct mlx5_ib_dev *dev =
2645                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2646
2647         return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2648 }
2649 static DEVICE_ATTR_RO(reg_pages);
2650
2651 static ssize_t hca_type_show(struct device *device,
2652                              struct device_attribute *attr, char *buf)
2653 {
2654         struct mlx5_ib_dev *dev =
2655                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2656
2657         return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2658 }
2659 static DEVICE_ATTR_RO(hca_type);
2660
2661 static ssize_t hw_rev_show(struct device *device,
2662                            struct device_attribute *attr, char *buf)
2663 {
2664         struct mlx5_ib_dev *dev =
2665                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2666
2667         return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2668 }
2669 static DEVICE_ATTR_RO(hw_rev);
2670
2671 static ssize_t board_id_show(struct device *device,
2672                              struct device_attribute *attr, char *buf)
2673 {
2674         struct mlx5_ib_dev *dev =
2675                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2676
2677         return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2678                           dev->mdev->board_id);
2679 }
2680 static DEVICE_ATTR_RO(board_id);
2681
2682 static struct attribute *mlx5_class_attributes[] = {
2683         &dev_attr_hw_rev.attr,
2684         &dev_attr_hca_type.attr,
2685         &dev_attr_board_id.attr,
2686         &dev_attr_fw_pages.attr,
2687         &dev_attr_reg_pages.attr,
2688         NULL,
2689 };
2690
2691 static const struct attribute_group mlx5_attr_group = {
2692         .attrs = mlx5_class_attributes,
2693 };
2694
2695 static void pkey_change_handler(struct work_struct *work)
2696 {
2697         struct mlx5_ib_port_resources *ports =
2698                 container_of(work, struct mlx5_ib_port_resources,
2699                              pkey_change_work);
2700
2701         mlx5_ib_gsi_pkey_change(ports->gsi);
2702 }
2703
2704 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2705 {
2706         struct mlx5_ib_qp *mqp;
2707         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2708         struct mlx5_core_cq *mcq;
2709         struct list_head cq_armed_list;
2710         unsigned long flags_qp;
2711         unsigned long flags_cq;
2712         unsigned long flags;
2713
2714         INIT_LIST_HEAD(&cq_armed_list);
2715
2716         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2717         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2718         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2719                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2720                 if (mqp->sq.tail != mqp->sq.head) {
2721                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2722                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2723                         if (send_mcq->mcq.comp &&
2724                             mqp->ibqp.send_cq->comp_handler) {
2725                                 if (!send_mcq->mcq.reset_notify_added) {
2726                                         send_mcq->mcq.reset_notify_added = 1;
2727                                         list_add_tail(&send_mcq->mcq.reset_notify,
2728                                                       &cq_armed_list);
2729                                 }
2730                         }
2731                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2732                 }
2733                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2734                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2735                 /* no handling is needed for SRQ */
2736                 if (!mqp->ibqp.srq) {
2737                         if (mqp->rq.tail != mqp->rq.head) {
2738                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2739                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2740                                 if (recv_mcq->mcq.comp &&
2741                                     mqp->ibqp.recv_cq->comp_handler) {
2742                                         if (!recv_mcq->mcq.reset_notify_added) {
2743                                                 recv_mcq->mcq.reset_notify_added = 1;
2744                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2745                                                               &cq_armed_list);
2746                                         }
2747                                 }
2748                                 spin_unlock_irqrestore(&recv_mcq->lock,
2749                                                        flags_cq);
2750                         }
2751                 }
2752                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2753         }
2754         /*At that point all inflight post send were put to be executed as of we
2755          * lock/unlock above locks Now need to arm all involved CQs.
2756          */
2757         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2758                 mcq->comp(mcq, NULL);
2759         }
2760         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2761 }
2762
2763 static void delay_drop_handler(struct work_struct *work)
2764 {
2765         int err;
2766         struct mlx5_ib_delay_drop *delay_drop =
2767                 container_of(work, struct mlx5_ib_delay_drop,
2768                              delay_drop_work);
2769
2770         atomic_inc(&delay_drop->events_cnt);
2771
2772         mutex_lock(&delay_drop->lock);
2773         err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2774         if (err) {
2775                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2776                              delay_drop->timeout);
2777                 delay_drop->activate = false;
2778         }
2779         mutex_unlock(&delay_drop->lock);
2780 }
2781
2782 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2783                                  struct ib_event *ibev)
2784 {
2785         u8 port = (eqe->data.port.port >> 4) & 0xf;
2786
2787         switch (eqe->sub_type) {
2788         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2789                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2790                                             IB_LINK_LAYER_ETHERNET)
2791                         schedule_work(&ibdev->delay_drop.delay_drop_work);
2792                 break;
2793         default: /* do nothing */
2794                 return;
2795         }
2796 }
2797
2798 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2799                               struct ib_event *ibev)
2800 {
2801         u8 port = (eqe->data.port.port >> 4) & 0xf;
2802
2803         ibev->element.port_num = port;
2804
2805         switch (eqe->sub_type) {
2806         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2807         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2808         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2809                 /* In RoCE, port up/down events are handled in
2810                  * mlx5_netdev_event().
2811                  */
2812                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2813                                             IB_LINK_LAYER_ETHERNET)
2814                         return -EINVAL;
2815
2816                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2817                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2818                 break;
2819
2820         case MLX5_PORT_CHANGE_SUBTYPE_LID:
2821                 ibev->event = IB_EVENT_LID_CHANGE;
2822                 break;
2823
2824         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2825                 ibev->event = IB_EVENT_PKEY_CHANGE;
2826                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2827                 break;
2828
2829         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2830                 ibev->event = IB_EVENT_GID_CHANGE;
2831                 break;
2832
2833         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2834                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2835                 break;
2836         default:
2837                 return -EINVAL;
2838         }
2839
2840         return 0;
2841 }
2842
2843 static void mlx5_ib_handle_event(struct work_struct *_work)
2844 {
2845         struct mlx5_ib_event_work *work =
2846                 container_of(_work, struct mlx5_ib_event_work, work);
2847         struct mlx5_ib_dev *ibdev;
2848         struct ib_event ibev;
2849         bool fatal = false;
2850
2851         if (work->is_slave) {
2852                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2853                 if (!ibdev)
2854                         goto out;
2855         } else {
2856                 ibdev = work->dev;
2857         }
2858
2859         switch (work->event) {
2860         case MLX5_DEV_EVENT_SYS_ERROR:
2861                 ibev.event = IB_EVENT_DEVICE_FATAL;
2862                 mlx5_ib_handle_internal_error(ibdev);
2863                 ibev.element.port_num  = (u8)(unsigned long)work->param;
2864                 fatal = true;
2865                 break;
2866         case MLX5_EVENT_TYPE_PORT_CHANGE:
2867                 if (handle_port_change(ibdev, work->param, &ibev))
2868                         goto out;
2869                 break;
2870         case MLX5_EVENT_TYPE_GENERAL_EVENT:
2871                 handle_general_event(ibdev, work->param, &ibev);
2872                 fallthrough;
2873         default:
2874                 goto out;
2875         }
2876
2877         ibev.device = &ibdev->ib_dev;
2878
2879         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2880                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
2881                 goto out;
2882         }
2883
2884         if (ibdev->ib_active)
2885                 ib_dispatch_event(&ibev);
2886
2887         if (fatal)
2888                 ibdev->ib_active = false;
2889 out:
2890         kfree(work);
2891 }
2892
2893 static int mlx5_ib_event(struct notifier_block *nb,
2894                          unsigned long event, void *param)
2895 {
2896         struct mlx5_ib_event_work *work;
2897
2898         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2899         if (!work)
2900                 return NOTIFY_DONE;
2901
2902         INIT_WORK(&work->work, mlx5_ib_handle_event);
2903         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2904         work->is_slave = false;
2905         work->param = param;
2906         work->event = event;
2907
2908         queue_work(mlx5_ib_event_wq, &work->work);
2909
2910         return NOTIFY_OK;
2911 }
2912
2913 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2914                                     unsigned long event, void *param)
2915 {
2916         struct mlx5_ib_event_work *work;
2917
2918         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2919         if (!work)
2920                 return NOTIFY_DONE;
2921
2922         INIT_WORK(&work->work, mlx5_ib_handle_event);
2923         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2924         work->is_slave = true;
2925         work->param = param;
2926         work->event = event;
2927         queue_work(mlx5_ib_event_wq, &work->work);
2928
2929         return NOTIFY_OK;
2930 }
2931
2932 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2933 {
2934         struct mlx5_hca_vport_context vport_ctx;
2935         int err;
2936         int port;
2937
2938         for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
2939                 dev->mdev->port_caps[port - 1].has_smi = false;
2940                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2941                     MLX5_CAP_PORT_TYPE_IB) {
2942                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2943                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2944                                                                    port, 0,
2945                                                                    &vport_ctx);
2946                                 if (err) {
2947                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2948                                                     port, err);
2949                                         return err;
2950                                 }
2951                                 dev->mdev->port_caps[port - 1].has_smi =
2952                                         vport_ctx.has_smi;
2953                         } else {
2954                                 dev->mdev->port_caps[port - 1].has_smi = true;
2955                         }
2956                 }
2957         }
2958         return 0;
2959 }
2960
2961 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2962 {
2963         int port;
2964
2965         for (port = 1; port <= dev->num_ports; port++)
2966                 mlx5_query_ext_port_caps(dev, port);
2967 }
2968
2969 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
2970 {
2971         struct ib_device_attr *dprops = NULL;
2972         struct ib_port_attr *pprops = NULL;
2973         int err = -ENOMEM;
2974
2975         pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
2976         if (!pprops)
2977                 goto out;
2978
2979         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2980         if (!dprops)
2981                 goto out;
2982
2983         err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL);
2984         if (err) {
2985                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2986                 goto out;
2987         }
2988
2989         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2990         if (err) {
2991                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2992                              port, err);
2993                 goto out;
2994         }
2995
2996         dev->mdev->port_caps[port - 1].pkey_table_len =
2997                                         dprops->max_pkeys;
2998         dev->mdev->port_caps[port - 1].gid_table_len =
2999                                         pprops->gid_tbl_len;
3000         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3001                     port, dprops->max_pkeys, pprops->gid_tbl_len);
3002
3003 out:
3004         kfree(pprops);
3005         kfree(dprops);
3006
3007         return err;
3008 }
3009
3010 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
3011 {
3012         /* For representors use port 1, is this is the only native
3013          * port
3014          */
3015         if (dev->is_rep)
3016                 return __get_port_caps(dev, 1);
3017         return __get_port_caps(dev, port);
3018 }
3019
3020 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3021 {
3022         switch (umr_fence_cap) {
3023         case MLX5_CAP_UMR_FENCE_NONE:
3024                 return MLX5_FENCE_MODE_NONE;
3025         case MLX5_CAP_UMR_FENCE_SMALL:
3026                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3027         default:
3028                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3029         }
3030 }
3031
3032 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
3033 {
3034         struct mlx5_ib_resources *devr = &dev->devr;
3035         struct ib_srq_init_attr attr;
3036         struct ib_device *ibdev;
3037         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3038         int port;
3039         int ret = 0;
3040
3041         ibdev = &dev->ib_dev;
3042
3043         if (!MLX5_CAP_GEN(dev->mdev, xrc))
3044                 return -EOPNOTSUPP;
3045
3046         mutex_init(&devr->mutex);
3047
3048         devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
3049         if (!devr->p0)
3050                 return -ENOMEM;
3051
3052         devr->p0->device  = ibdev;
3053         devr->p0->uobject = NULL;
3054         atomic_set(&devr->p0->usecnt, 0);
3055
3056         ret = mlx5_ib_alloc_pd(devr->p0, NULL);
3057         if (ret)
3058                 goto error0;
3059
3060         devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
3061         if (!devr->c0) {
3062                 ret = -ENOMEM;
3063                 goto error1;
3064         }
3065
3066         devr->c0->device = &dev->ib_dev;
3067         atomic_set(&devr->c0->usecnt, 0);
3068
3069         ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
3070         if (ret)
3071                 goto err_create_cq;
3072
3073         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
3074         if (ret)
3075                 goto error2;
3076
3077         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
3078         if (ret)
3079                 goto error3;
3080
3081         memset(&attr, 0, sizeof(attr));
3082         attr.attr.max_sge = 1;
3083         attr.attr.max_wr = 1;
3084         attr.srq_type = IB_SRQT_XRC;
3085         attr.ext.cq = devr->c0;
3086
3087         devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
3088         if (!devr->s0) {
3089                 ret = -ENOMEM;
3090                 goto error4;
3091         }
3092
3093         devr->s0->device        = &dev->ib_dev;
3094         devr->s0->pd            = devr->p0;
3095         devr->s0->srq_type      = IB_SRQT_XRC;
3096         devr->s0->ext.cq        = devr->c0;
3097         ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
3098         if (ret)
3099                 goto err_create;
3100
3101         atomic_inc(&devr->s0->ext.cq->usecnt);
3102         atomic_inc(&devr->p0->usecnt);
3103         atomic_set(&devr->s0->usecnt, 0);
3104
3105         memset(&attr, 0, sizeof(attr));
3106         attr.attr.max_sge = 1;
3107         attr.attr.max_wr = 1;
3108         attr.srq_type = IB_SRQT_BASIC;
3109         devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
3110         if (!devr->s1) {
3111                 ret = -ENOMEM;
3112                 goto error5;
3113         }
3114
3115         devr->s1->device        = &dev->ib_dev;
3116         devr->s1->pd            = devr->p0;
3117         devr->s1->srq_type      = IB_SRQT_BASIC;
3118         devr->s1->ext.cq        = devr->c0;
3119
3120         ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
3121         if (ret)
3122                 goto error6;
3123
3124         atomic_inc(&devr->p0->usecnt);
3125         atomic_set(&devr->s1->usecnt, 0);
3126
3127         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
3128                 INIT_WORK(&devr->ports[port].pkey_change_work,
3129                           pkey_change_handler);
3130
3131         return 0;
3132
3133 error6:
3134         kfree(devr->s1);
3135 error5:
3136         mlx5_ib_destroy_srq(devr->s0, NULL);
3137 err_create:
3138         kfree(devr->s0);
3139 error4:
3140         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3141 error3:
3142         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3143 error2:
3144         mlx5_ib_destroy_cq(devr->c0, NULL);
3145 err_create_cq:
3146         kfree(devr->c0);
3147 error1:
3148         mlx5_ib_dealloc_pd(devr->p0, NULL);
3149 error0:
3150         kfree(devr->p0);
3151         return ret;
3152 }
3153
3154 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
3155 {
3156         struct mlx5_ib_resources *devr = &dev->devr;
3157         int port;
3158
3159         mlx5_ib_destroy_srq(devr->s1, NULL);
3160         kfree(devr->s1);
3161         mlx5_ib_destroy_srq(devr->s0, NULL);
3162         kfree(devr->s0);
3163         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3164         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3165         mlx5_ib_destroy_cq(devr->c0, NULL);
3166         kfree(devr->c0);
3167         mlx5_ib_dealloc_pd(devr->p0, NULL);
3168         kfree(devr->p0);
3169
3170         /* Make sure no change P_Key work items are still executing */
3171         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
3172                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3173 }
3174
3175 static u32 get_core_cap_flags(struct ib_device *ibdev,
3176                               struct mlx5_hca_vport_context *rep)
3177 {
3178         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3179         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3180         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3181         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3182         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3183         u32 ret = 0;
3184
3185         if (rep->grh_required)
3186                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
3187
3188         if (ll == IB_LINK_LAYER_INFINIBAND)
3189                 return ret | RDMA_CORE_PORT_IBA_IB;
3190
3191         if (raw_support)
3192                 ret |= RDMA_CORE_PORT_RAW_PACKET;
3193
3194         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3195                 return ret;
3196
3197         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3198                 return ret;
3199
3200         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3201                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3202
3203         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3204                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3205
3206         return ret;
3207 }
3208
3209 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3210                                struct ib_port_immutable *immutable)
3211 {
3212         struct ib_port_attr attr;
3213         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3214         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3215         struct mlx5_hca_vport_context rep = {0};
3216         int err;
3217
3218         err = ib_query_port(ibdev, port_num, &attr);
3219         if (err)
3220                 return err;
3221
3222         if (ll == IB_LINK_LAYER_INFINIBAND) {
3223                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3224                                                    &rep);
3225                 if (err)
3226                         return err;
3227         }
3228
3229         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3230         immutable->gid_tbl_len = attr.gid_tbl_len;
3231         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
3232         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3233
3234         return 0;
3235 }
3236
3237 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
3238                                    struct ib_port_immutable *immutable)
3239 {
3240         struct ib_port_attr attr;
3241         int err;
3242
3243         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3244
3245         err = ib_query_port(ibdev, port_num, &attr);
3246         if (err)
3247                 return err;
3248
3249         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3250         immutable->gid_tbl_len = attr.gid_tbl_len;
3251         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3252
3253         return 0;
3254 }
3255
3256 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3257 {
3258         struct mlx5_ib_dev *dev =
3259                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3260         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3261                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3262                  fw_rev_sub(dev->mdev));
3263 }
3264
3265 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3266 {
3267         struct mlx5_core_dev *mdev = dev->mdev;
3268         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3269                                                                  MLX5_FLOW_NAMESPACE_LAG);
3270         struct mlx5_flow_table *ft;
3271         int err;
3272
3273         if (!ns || !mlx5_lag_is_roce(mdev))
3274                 return 0;
3275
3276         err = mlx5_cmd_create_vport_lag(mdev);
3277         if (err)
3278                 return err;
3279
3280         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3281         if (IS_ERR(ft)) {
3282                 err = PTR_ERR(ft);
3283                 goto err_destroy_vport_lag;
3284         }
3285
3286         dev->flow_db->lag_demux_ft = ft;
3287         dev->lag_active = true;
3288         return 0;
3289
3290 err_destroy_vport_lag:
3291         mlx5_cmd_destroy_vport_lag(mdev);
3292         return err;
3293 }
3294
3295 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3296 {
3297         struct mlx5_core_dev *mdev = dev->mdev;
3298
3299         if (dev->lag_active) {
3300                 dev->lag_active = false;
3301
3302                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3303                 dev->flow_db->lag_demux_ft = NULL;
3304
3305                 mlx5_cmd_destroy_vport_lag(mdev);
3306         }
3307 }
3308
3309 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3310 {
3311         int err;
3312
3313         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3314         err = register_netdevice_notifier_net(mlx5_core_net(dev->mdev),
3315                                               &dev->port[port_num].roce.nb);
3316         if (err) {
3317                 dev->port[port_num].roce.nb.notifier_call = NULL;
3318                 return err;
3319         }
3320
3321         return 0;
3322 }
3323
3324 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3325 {
3326         if (dev->port[port_num].roce.nb.notifier_call) {
3327                 unregister_netdevice_notifier_net(mlx5_core_net(dev->mdev),
3328                                                   &dev->port[port_num].roce.nb);
3329                 dev->port[port_num].roce.nb.notifier_call = NULL;
3330         }
3331 }
3332
3333 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3334 {
3335         int err;
3336
3337         err = mlx5_nic_vport_enable_roce(dev->mdev);
3338         if (err)
3339                 return err;
3340
3341         err = mlx5_eth_lag_init(dev);
3342         if (err)
3343                 goto err_disable_roce;
3344
3345         return 0;
3346
3347 err_disable_roce:
3348         mlx5_nic_vport_disable_roce(dev->mdev);
3349
3350         return err;
3351 }
3352
3353 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3354 {
3355         mlx5_eth_lag_cleanup(dev);
3356         mlx5_nic_vport_disable_roce(dev->mdev);
3357 }
3358
3359 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
3360                                  enum rdma_netdev_t type,
3361                                  struct rdma_netdev_alloc_params *params)
3362 {
3363         if (type != RDMA_NETDEV_IPOIB)
3364                 return -EOPNOTSUPP;
3365
3366         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3367 }
3368
3369 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3370                                        size_t count, loff_t *pos)
3371 {
3372         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3373         char lbuf[20];
3374         int len;
3375
3376         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3377         return simple_read_from_buffer(buf, count, pos, lbuf, len);
3378 }
3379
3380 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3381                                         size_t count, loff_t *pos)
3382 {
3383         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3384         u32 timeout;
3385         u32 var;
3386
3387         if (kstrtouint_from_user(buf, count, 0, &var))
3388                 return -EFAULT;
3389
3390         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3391                         1000);
3392         if (timeout != var)
3393                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3394                             timeout);
3395
3396         delay_drop->timeout = timeout;
3397
3398         return count;
3399 }
3400
3401 static const struct file_operations fops_delay_drop_timeout = {
3402         .owner  = THIS_MODULE,
3403         .open   = simple_open,
3404         .write  = delay_drop_timeout_write,
3405         .read   = delay_drop_timeout_read,
3406 };
3407
3408 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3409                                       struct mlx5_ib_multiport_info *mpi)
3410 {
3411         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3412         struct mlx5_ib_port *port = &ibdev->port[port_num];
3413         int comps;
3414         int err;
3415         int i;
3416
3417         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3418
3419         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3420
3421         spin_lock(&port->mp.mpi_lock);
3422         if (!mpi->ibdev) {
3423                 spin_unlock(&port->mp.mpi_lock);
3424                 return;
3425         }
3426
3427         mpi->ibdev = NULL;
3428
3429         spin_unlock(&port->mp.mpi_lock);
3430         if (mpi->mdev_events.notifier_call)
3431                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3432         mpi->mdev_events.notifier_call = NULL;
3433         mlx5_remove_netdev_notifier(ibdev, port_num);
3434         spin_lock(&port->mp.mpi_lock);
3435
3436         comps = mpi->mdev_refcnt;
3437         if (comps) {
3438                 mpi->unaffiliate = true;
3439                 init_completion(&mpi->unref_comp);
3440                 spin_unlock(&port->mp.mpi_lock);
3441
3442                 for (i = 0; i < comps; i++)
3443                         wait_for_completion(&mpi->unref_comp);
3444
3445                 spin_lock(&port->mp.mpi_lock);
3446                 mpi->unaffiliate = false;
3447         }
3448
3449         port->mp.mpi = NULL;
3450
3451         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
3452
3453         spin_unlock(&port->mp.mpi_lock);
3454
3455         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3456
3457         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
3458         /* Log an error, still needed to cleanup the pointers and add
3459          * it back to the list.
3460          */
3461         if (err)
3462                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3463                             port_num + 1);
3464
3465         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3466 }
3467
3468 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3469                                     struct mlx5_ib_multiport_info *mpi)
3470 {
3471         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3472         int err;
3473
3474         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3475
3476         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3477         if (ibdev->port[port_num].mp.mpi) {
3478                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
3479                             port_num + 1);
3480                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3481                 return false;
3482         }
3483
3484         ibdev->port[port_num].mp.mpi = mpi;
3485         mpi->ibdev = ibdev;
3486         mpi->mdev_events.notifier_call = NULL;
3487         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3488
3489         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3490         if (err)
3491                 goto unbind;
3492
3493         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
3494         if (err)
3495                 goto unbind;
3496
3497         err = mlx5_add_netdev_notifier(ibdev, port_num);
3498         if (err) {
3499                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3500                             port_num + 1);
3501                 goto unbind;
3502         }
3503
3504         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3505         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3506
3507         mlx5_ib_init_cong_debugfs(ibdev, port_num);
3508
3509         return true;
3510
3511 unbind:
3512         mlx5_ib_unbind_slave_port(ibdev, mpi);
3513         return false;
3514 }
3515
3516 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3517 {
3518         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3519         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3520                                                           port_num + 1);
3521         struct mlx5_ib_multiport_info *mpi;
3522         int err;
3523         int i;
3524
3525         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3526                 return 0;
3527
3528         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3529                                                      &dev->sys_image_guid);
3530         if (err)
3531                 return err;
3532
3533         err = mlx5_nic_vport_enable_roce(dev->mdev);
3534         if (err)
3535                 return err;
3536
3537         mutex_lock(&mlx5_ib_multiport_mutex);
3538         for (i = 0; i < dev->num_ports; i++) {
3539                 bool bound = false;
3540
3541                 /* build a stub multiport info struct for the native port. */
3542                 if (i == port_num) {
3543                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3544                         if (!mpi) {
3545                                 mutex_unlock(&mlx5_ib_multiport_mutex);
3546                                 mlx5_nic_vport_disable_roce(dev->mdev);
3547                                 return -ENOMEM;
3548                         }
3549
3550                         mpi->is_master = true;
3551                         mpi->mdev = dev->mdev;
3552                         mpi->sys_image_guid = dev->sys_image_guid;
3553                         dev->port[i].mp.mpi = mpi;
3554                         mpi->ibdev = dev;
3555                         mpi = NULL;
3556                         continue;
3557                 }
3558
3559                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3560                                     list) {
3561                         if (dev->sys_image_guid == mpi->sys_image_guid &&
3562                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3563                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
3564                         }
3565
3566                         if (bound) {
3567                                 dev_dbg(mpi->mdev->device,
3568                                         "removing port from unaffiliated list.\n");
3569                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3570                                 list_del(&mpi->list);
3571                                 break;
3572                         }
3573                 }
3574                 if (!bound) {
3575                         get_port_caps(dev, i + 1);
3576                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
3577                                     i + 1);
3578                 }
3579         }
3580
3581         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3582         mutex_unlock(&mlx5_ib_multiport_mutex);
3583         return err;
3584 }
3585
3586 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3587 {
3588         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3589         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3590                                                           port_num + 1);
3591         int i;
3592
3593         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3594                 return;
3595
3596         mutex_lock(&mlx5_ib_multiport_mutex);
3597         for (i = 0; i < dev->num_ports; i++) {
3598                 if (dev->port[i].mp.mpi) {
3599                         /* Destroy the native port stub */
3600                         if (i == port_num) {
3601                                 kfree(dev->port[i].mp.mpi);
3602                                 dev->port[i].mp.mpi = NULL;
3603                         } else {
3604                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
3605                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
3606                         }
3607                 }
3608         }
3609
3610         mlx5_ib_dbg(dev, "removing from devlist\n");
3611         list_del(&dev->ib_dev_list);
3612         mutex_unlock(&mlx5_ib_multiport_mutex);
3613
3614         mlx5_nic_vport_disable_roce(dev->mdev);
3615 }
3616
3617 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3618                             enum rdma_remove_reason why,
3619                             struct uverbs_attr_bundle *attrs)
3620 {
3621         struct mlx5_user_mmap_entry *obj = uobject->object;
3622
3623         rdma_user_mmap_entry_remove(&obj->rdma_entry);
3624         return 0;
3625 }
3626
3627 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3628                                             struct mlx5_user_mmap_entry *entry,
3629                                             size_t length)
3630 {
3631         return rdma_user_mmap_entry_insert_range(
3632                 &c->ibucontext, &entry->rdma_entry, length,
3633                 (MLX5_IB_MMAP_OFFSET_START << 16),
3634                 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3635 }
3636
3637 static struct mlx5_user_mmap_entry *
3638 alloc_var_entry(struct mlx5_ib_ucontext *c)
3639 {
3640         struct mlx5_user_mmap_entry *entry;
3641         struct mlx5_var_table *var_table;
3642         u32 page_idx;
3643         int err;
3644
3645         var_table = &to_mdev(c->ibucontext.device)->var_table;
3646         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3647         if (!entry)
3648                 return ERR_PTR(-ENOMEM);
3649
3650         mutex_lock(&var_table->bitmap_lock);
3651         page_idx = find_first_zero_bit(var_table->bitmap,
3652                                        var_table->num_var_hw_entries);
3653         if (page_idx >= var_table->num_var_hw_entries) {
3654                 err = -ENOSPC;
3655                 mutex_unlock(&var_table->bitmap_lock);
3656                 goto end;
3657         }
3658
3659         set_bit(page_idx, var_table->bitmap);
3660         mutex_unlock(&var_table->bitmap_lock);
3661
3662         entry->address = var_table->hw_start_addr +
3663                                 (page_idx * var_table->stride_size);
3664         entry->page_idx = page_idx;
3665         entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3666
3667         err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3668                                                var_table->stride_size);
3669         if (err)
3670                 goto err_insert;
3671
3672         return entry;
3673
3674 err_insert:
3675         mutex_lock(&var_table->bitmap_lock);
3676         clear_bit(page_idx, var_table->bitmap);
3677         mutex_unlock(&var_table->bitmap_lock);
3678 end:
3679         kfree(entry);
3680         return ERR_PTR(err);
3681 }
3682
3683 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3684         struct uverbs_attr_bundle *attrs)
3685 {
3686         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3687                 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3688         struct mlx5_ib_ucontext *c;
3689         struct mlx5_user_mmap_entry *entry;
3690         u64 mmap_offset;
3691         u32 length;
3692         int err;
3693
3694         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3695         if (IS_ERR(c))
3696                 return PTR_ERR(c);
3697
3698         entry = alloc_var_entry(c);
3699         if (IS_ERR(entry))
3700                 return PTR_ERR(entry);
3701
3702         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3703         length = entry->rdma_entry.npages * PAGE_SIZE;
3704         uobj->object = entry;
3705         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3706
3707         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3708                              &mmap_offset, sizeof(mmap_offset));
3709         if (err)
3710                 return err;
3711
3712         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3713                              &entry->page_idx, sizeof(entry->page_idx));
3714         if (err)
3715                 return err;
3716
3717         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3718                              &length, sizeof(length));
3719         return err;
3720 }
3721
3722 DECLARE_UVERBS_NAMED_METHOD(
3723         MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3724         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3725                         MLX5_IB_OBJECT_VAR,
3726                         UVERBS_ACCESS_NEW,
3727                         UA_MANDATORY),
3728         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3729                            UVERBS_ATTR_TYPE(u32),
3730                            UA_MANDATORY),
3731         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3732                            UVERBS_ATTR_TYPE(u32),
3733                            UA_MANDATORY),
3734         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3735                             UVERBS_ATTR_TYPE(u64),
3736                             UA_MANDATORY));
3737
3738 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3739         MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3740         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3741                         MLX5_IB_OBJECT_VAR,
3742                         UVERBS_ACCESS_DESTROY,
3743                         UA_MANDATORY));
3744
3745 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3746                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3747                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3748                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3749
3750 static bool var_is_supported(struct ib_device *device)
3751 {
3752         struct mlx5_ib_dev *dev = to_mdev(device);
3753
3754         return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3755                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3756 }
3757
3758 static struct mlx5_user_mmap_entry *
3759 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3760                 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3761 {
3762         struct mlx5_user_mmap_entry *entry;
3763         struct mlx5_ib_dev *dev;
3764         u32 uar_index;
3765         int err;
3766
3767         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3768         if (!entry)
3769                 return ERR_PTR(-ENOMEM);
3770
3771         dev = to_mdev(c->ibucontext.device);
3772         err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3773         if (err)
3774                 goto end;
3775
3776         entry->page_idx = uar_index;
3777         entry->address = uar_index2paddress(dev, uar_index);
3778         if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3779                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3780         else
3781                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3782
3783         err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3784         if (err)
3785                 goto err_insert;
3786
3787         return entry;
3788
3789 err_insert:
3790         mlx5_cmd_free_uar(dev->mdev, uar_index);
3791 end:
3792         kfree(entry);
3793         return ERR_PTR(err);
3794 }
3795
3796 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3797         struct uverbs_attr_bundle *attrs)
3798 {
3799         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3800                 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3801         enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3802         struct mlx5_ib_ucontext *c;
3803         struct mlx5_user_mmap_entry *entry;
3804         u64 mmap_offset;
3805         u32 length;
3806         int err;
3807
3808         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3809         if (IS_ERR(c))
3810                 return PTR_ERR(c);
3811
3812         err = uverbs_get_const(&alloc_type, attrs,
3813                                MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3814         if (err)
3815                 return err;
3816
3817         if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3818             alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3819                 return -EOPNOTSUPP;
3820
3821         if (!to_mdev(c->ibucontext.device)->wc_support &&
3822             alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3823                 return -EOPNOTSUPP;
3824
3825         entry = alloc_uar_entry(c, alloc_type);
3826         if (IS_ERR(entry))
3827                 return PTR_ERR(entry);
3828
3829         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3830         length = entry->rdma_entry.npages * PAGE_SIZE;
3831         uobj->object = entry;
3832         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3833
3834         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3835                              &mmap_offset, sizeof(mmap_offset));
3836         if (err)
3837                 return err;
3838
3839         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3840                              &entry->page_idx, sizeof(entry->page_idx));
3841         if (err)
3842                 return err;
3843
3844         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3845                              &length, sizeof(length));
3846         return err;
3847 }
3848
3849 DECLARE_UVERBS_NAMED_METHOD(
3850         MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3851         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3852                         MLX5_IB_OBJECT_UAR,
3853                         UVERBS_ACCESS_NEW,
3854                         UA_MANDATORY),
3855         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3856                              enum mlx5_ib_uapi_uar_alloc_type,
3857                              UA_MANDATORY),
3858         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3859                            UVERBS_ATTR_TYPE(u32),
3860                            UA_MANDATORY),
3861         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3862                            UVERBS_ATTR_TYPE(u32),
3863                            UA_MANDATORY),
3864         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3865                             UVERBS_ATTR_TYPE(u64),
3866                             UA_MANDATORY));
3867
3868 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3869         MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3870         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3871                         MLX5_IB_OBJECT_UAR,
3872                         UVERBS_ACCESS_DESTROY,
3873                         UA_MANDATORY));
3874
3875 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3876                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3877                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3878                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3879
3880 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3881         mlx5_ib_dm,
3882         UVERBS_OBJECT_DM,
3883         UVERBS_METHOD_DM_ALLOC,
3884         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
3885                             UVERBS_ATTR_TYPE(u64),
3886                             UA_MANDATORY),
3887         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
3888                             UVERBS_ATTR_TYPE(u16),
3889                             UA_OPTIONAL),
3890         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
3891                              enum mlx5_ib_uapi_dm_type,
3892                              UA_OPTIONAL));
3893
3894 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3895         mlx5_ib_flow_action,
3896         UVERBS_OBJECT_FLOW_ACTION,
3897         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
3898         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3899                              enum mlx5_ib_uapi_flow_action_flags));
3900
3901 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3902         mlx5_ib_query_context,
3903         UVERBS_OBJECT_DEVICE,
3904         UVERBS_METHOD_QUERY_CONTEXT,
3905         UVERBS_ATTR_PTR_OUT(
3906                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3907                 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3908                                    dump_fill_mkey),
3909                 UA_MANDATORY));
3910
3911 static const struct uapi_definition mlx5_ib_defs[] = {
3912         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3913         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3914         UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3915         UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3916
3917         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
3918                                 &mlx5_ib_flow_action),
3919         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
3920         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3921         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3922                                 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3923         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3924         {}
3925 };
3926
3927 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3928 {
3929         mlx5_ib_cleanup_multiport_master(dev);
3930         WARN_ON(!xa_empty(&dev->odp_mkeys));
3931         cleanup_srcu_struct(&dev->odp_srcu);
3932
3933         WARN_ON(!xa_empty(&dev->sig_mrs));
3934         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3935 }
3936
3937 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3938 {
3939         struct mlx5_core_dev *mdev = dev->mdev;
3940         int err;
3941         int i;
3942
3943         for (i = 0; i < dev->num_ports; i++) {
3944                 spin_lock_init(&dev->port[i].mp.mpi_lock);
3945                 rwlock_init(&dev->port[i].roce.netdev_lock);
3946                 dev->port[i].roce.dev = dev;
3947                 dev->port[i].roce.native_port_num = i + 1;
3948                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3949         }
3950
3951         mlx5_ib_internal_fill_odp_caps(dev);
3952
3953         err = mlx5_ib_init_multiport_master(dev);
3954         if (err)
3955                 return err;
3956
3957         err = set_has_smi_cap(dev);
3958         if (err)
3959                 return err;
3960
3961         if (!mlx5_core_mp_enabled(mdev)) {
3962                 for (i = 1; i <= dev->num_ports; i++) {
3963                         err = get_port_caps(dev, i);
3964                         if (err)
3965                                 break;
3966                 }
3967         } else {
3968                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
3969         }
3970         if (err)
3971                 goto err_mp;
3972
3973         if (mlx5_use_mad_ifc(dev))
3974                 get_ext_port_caps(dev);
3975
3976         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3977         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3978         dev->ib_dev.phys_port_cnt       = dev->num_ports;
3979         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
3980         dev->ib_dev.dev.parent          = mdev->device;
3981         dev->ib_dev.lag_flags           = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3982
3983         mutex_init(&dev->cap_mask_mutex);
3984         INIT_LIST_HEAD(&dev->qp_list);
3985         spin_lock_init(&dev->reset_flow_resource_lock);
3986         xa_init(&dev->odp_mkeys);
3987         xa_init(&dev->sig_mrs);
3988         atomic_set(&dev->mkey_var, 0);
3989
3990         spin_lock_init(&dev->dm.lock);
3991         dev->dm.dev = mdev;
3992
3993         err = init_srcu_struct(&dev->odp_srcu);
3994         if (err)
3995                 goto err_mp;
3996
3997         return 0;
3998
3999 err_mp:
4000         mlx5_ib_cleanup_multiport_master(dev);
4001
4002         return -ENOMEM;
4003 }
4004
4005 static int mlx5_ib_enable_driver(struct ib_device *dev)
4006 {
4007         struct mlx5_ib_dev *mdev = to_mdev(dev);
4008         int ret;
4009
4010         ret = mlx5_ib_test_wc(mdev);
4011         mlx5_ib_dbg(mdev, "Write-Combining %s",
4012                     mdev->wc_support ? "supported" : "not supported");
4013
4014         return ret;
4015 }
4016
4017 static const struct ib_device_ops mlx5_ib_dev_ops = {
4018         .owner = THIS_MODULE,
4019         .driver_id = RDMA_DRIVER_MLX5,
4020         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
4021
4022         .add_gid = mlx5_ib_add_gid,
4023         .alloc_mr = mlx5_ib_alloc_mr,
4024         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
4025         .alloc_pd = mlx5_ib_alloc_pd,
4026         .alloc_ucontext = mlx5_ib_alloc_ucontext,
4027         .attach_mcast = mlx5_ib_mcg_attach,
4028         .check_mr_status = mlx5_ib_check_mr_status,
4029         .create_ah = mlx5_ib_create_ah,
4030         .create_cq = mlx5_ib_create_cq,
4031         .create_qp = mlx5_ib_create_qp,
4032         .create_srq = mlx5_ib_create_srq,
4033         .create_user_ah = mlx5_ib_create_ah,
4034         .dealloc_pd = mlx5_ib_dealloc_pd,
4035         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
4036         .del_gid = mlx5_ib_del_gid,
4037         .dereg_mr = mlx5_ib_dereg_mr,
4038         .destroy_ah = mlx5_ib_destroy_ah,
4039         .destroy_cq = mlx5_ib_destroy_cq,
4040         .destroy_qp = mlx5_ib_destroy_qp,
4041         .destroy_srq = mlx5_ib_destroy_srq,
4042         .detach_mcast = mlx5_ib_mcg_detach,
4043         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
4044         .drain_rq = mlx5_ib_drain_rq,
4045         .drain_sq = mlx5_ib_drain_sq,
4046         .enable_driver = mlx5_ib_enable_driver,
4047         .get_dev_fw_str = get_dev_fw_str,
4048         .get_dma_mr = mlx5_ib_get_dma_mr,
4049         .get_link_layer = mlx5_ib_port_link_layer,
4050         .map_mr_sg = mlx5_ib_map_mr_sg,
4051         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
4052         .mmap = mlx5_ib_mmap,
4053         .mmap_free = mlx5_ib_mmap_free,
4054         .modify_cq = mlx5_ib_modify_cq,
4055         .modify_device = mlx5_ib_modify_device,
4056         .modify_port = mlx5_ib_modify_port,
4057         .modify_qp = mlx5_ib_modify_qp,
4058         .modify_srq = mlx5_ib_modify_srq,
4059         .poll_cq = mlx5_ib_poll_cq,
4060         .post_recv = mlx5_ib_post_recv_nodrain,
4061         .post_send = mlx5_ib_post_send_nodrain,
4062         .post_srq_recv = mlx5_ib_post_srq_recv,
4063         .process_mad = mlx5_ib_process_mad,
4064         .query_ah = mlx5_ib_query_ah,
4065         .query_device = mlx5_ib_query_device,
4066         .query_gid = mlx5_ib_query_gid,
4067         .query_pkey = mlx5_ib_query_pkey,
4068         .query_qp = mlx5_ib_query_qp,
4069         .query_srq = mlx5_ib_query_srq,
4070         .query_ucontext = mlx5_ib_query_ucontext,
4071         .reg_user_mr = mlx5_ib_reg_user_mr,
4072         .req_notify_cq = mlx5_ib_arm_cq,
4073         .rereg_user_mr = mlx5_ib_rereg_user_mr,
4074         .resize_cq = mlx5_ib_resize_cq,
4075
4076         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
4077         INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
4078         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
4079         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
4080         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
4081         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
4082 };
4083
4084 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
4085         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
4086 };
4087
4088 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
4089         .get_vf_config = mlx5_ib_get_vf_config,
4090         .get_vf_guid = mlx5_ib_get_vf_guid,
4091         .get_vf_stats = mlx5_ib_get_vf_stats,
4092         .set_vf_guid = mlx5_ib_set_vf_guid,
4093         .set_vf_link_state = mlx5_ib_set_vf_link_state,
4094 };
4095
4096 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
4097         .alloc_mw = mlx5_ib_alloc_mw,
4098         .dealloc_mw = mlx5_ib_dealloc_mw,
4099
4100         INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
4101 };
4102
4103 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
4104         .alloc_xrcd = mlx5_ib_alloc_xrcd,
4105         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
4106
4107         INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
4108 };
4109
4110 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
4111         .alloc_dm = mlx5_ib_alloc_dm,
4112         .dealloc_dm = mlx5_ib_dealloc_dm,
4113         .reg_dm_mr = mlx5_ib_reg_dm_mr,
4114 };
4115
4116 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
4117 {
4118         struct mlx5_core_dev *mdev = dev->mdev;
4119         struct mlx5_var_table *var_table = &dev->var_table;
4120         u8 log_doorbell_bar_size;
4121         u8 log_doorbell_stride;
4122         u64 bar_size;
4123
4124         log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4125                                         log_doorbell_bar_size);
4126         log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4127                                         log_doorbell_stride);
4128         var_table->hw_start_addr = dev->mdev->bar_addr +
4129                                 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
4130                                         doorbell_bar_offset);
4131         bar_size = (1ULL << log_doorbell_bar_size) * 4096;
4132         var_table->stride_size = 1ULL << log_doorbell_stride;
4133         var_table->num_var_hw_entries = div_u64(bar_size,
4134                                                 var_table->stride_size);
4135         mutex_init(&var_table->bitmap_lock);
4136         var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
4137                                           GFP_KERNEL);
4138         return (var_table->bitmap) ? 0 : -ENOMEM;
4139 }
4140
4141 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
4142 {
4143         bitmap_free(dev->var_table.bitmap);
4144 }
4145
4146 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4147 {
4148         struct mlx5_core_dev *mdev = dev->mdev;
4149         int err;
4150
4151         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
4152             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
4153                 ib_set_device_ops(&dev->ib_dev,
4154                                   &mlx5_ib_dev_ipoib_enhanced_ops);
4155
4156         if (mlx5_core_is_pf(mdev))
4157                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
4158
4159         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4160
4161         if (MLX5_CAP_GEN(mdev, imaicl))
4162                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
4163
4164         if (MLX5_CAP_GEN(mdev, xrc))
4165                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
4166
4167         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
4168             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4169             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
4170                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
4171
4172         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
4173
4174         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
4175                 dev->ib_dev.driver_def = mlx5_ib_defs;
4176
4177         err = init_node_data(dev);
4178         if (err)
4179                 return err;
4180
4181         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4182             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4183              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4184                 mutex_init(&dev->lb.mutex);
4185
4186         if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4187                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
4188                 err = mlx5_ib_init_var_table(dev);
4189                 if (err)
4190                         return err;
4191         }
4192
4193         dev->ib_dev.use_cq_dim = true;
4194
4195         return 0;
4196 }
4197
4198 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
4199         .get_port_immutable = mlx5_port_immutable,
4200         .query_port = mlx5_ib_query_port,
4201 };
4202
4203 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
4204 {
4205         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
4206         return 0;
4207 }
4208
4209 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
4210         .get_port_immutable = mlx5_port_rep_immutable,
4211         .query_port = mlx5_ib_rep_query_port,
4212 };
4213
4214 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
4215 {
4216         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
4217         return 0;
4218 }
4219
4220 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
4221         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
4222         .create_wq = mlx5_ib_create_wq,
4223         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
4224         .destroy_wq = mlx5_ib_destroy_wq,
4225         .get_netdev = mlx5_ib_get_netdev,
4226         .modify_wq = mlx5_ib_modify_wq,
4227
4228         INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
4229                            ib_rwq_ind_tbl),
4230 };
4231
4232 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
4233 {
4234         struct mlx5_core_dev *mdev = dev->mdev;
4235         enum rdma_link_layer ll;
4236         int port_type_cap;
4237         u8 port_num = 0;
4238         int err;
4239
4240         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4241         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4242
4243         if (ll == IB_LINK_LAYER_ETHERNET) {
4244                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
4245
4246                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4247
4248                 /* Register only for native ports */
4249                 err = mlx5_add_netdev_notifier(dev, port_num);
4250                 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev))
4251                         /*
4252                          * We don't enable ETH interface for
4253                          * 1. IB representors
4254                          * 2. User disabled ROCE through devlink interface
4255                          */
4256                         return err;
4257
4258                 err = mlx5_enable_eth(dev);
4259                 if (err)
4260                         goto cleanup;
4261         }
4262
4263         return 0;
4264 cleanup:
4265         mlx5_remove_netdev_notifier(dev, port_num);
4266         return err;
4267 }
4268
4269 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
4270 {
4271         struct mlx5_core_dev *mdev = dev->mdev;
4272         enum rdma_link_layer ll;
4273         int port_type_cap;
4274         u8 port_num;
4275
4276         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4277         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4278
4279         if (ll == IB_LINK_LAYER_ETHERNET) {
4280                 if (!dev->is_rep)
4281                         mlx5_disable_eth(dev);
4282
4283                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4284                 mlx5_remove_netdev_notifier(dev, port_num);
4285         }
4286 }
4287
4288 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4289 {
4290         mlx5_ib_init_cong_debugfs(dev,
4291                                   mlx5_core_native_port_num(dev->mdev) - 1);
4292         return 0;
4293 }
4294
4295 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4296 {
4297         mlx5_ib_cleanup_cong_debugfs(dev,
4298                                      mlx5_core_native_port_num(dev->mdev) - 1);
4299 }
4300
4301 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4302 {
4303         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4304         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4305 }
4306
4307 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4308 {
4309         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4310 }
4311
4312 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4313 {
4314         int err;
4315
4316         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4317         if (err)
4318                 return err;
4319
4320         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4321         if (err)
4322                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4323
4324         return err;
4325 }
4326
4327 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4328 {
4329         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4330         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4331 }
4332
4333 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4334 {
4335         const char *name;
4336
4337         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
4338         if (!mlx5_lag_is_roce(dev->mdev))
4339                 name = "mlx5_%d";
4340         else
4341                 name = "mlx5_bond_%d";
4342         return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4343 }
4344
4345 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4346 {
4347         int err;
4348
4349         err = mlx5_mr_cache_cleanup(dev);
4350         if (err)
4351                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4352
4353         if (dev->umrc.qp)
4354                 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4355         if (dev->umrc.cq)
4356                 ib_free_cq(dev->umrc.cq);
4357         if (dev->umrc.pd)
4358                 ib_dealloc_pd(dev->umrc.pd);
4359 }
4360
4361 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4362 {
4363         ib_unregister_device(&dev->ib_dev);
4364 }
4365
4366 enum {
4367         MAX_UMR_WR = 128,
4368 };
4369
4370 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4371 {
4372         struct ib_qp_init_attr *init_attr = NULL;
4373         struct ib_qp_attr *attr = NULL;
4374         struct ib_pd *pd;
4375         struct ib_cq *cq;
4376         struct ib_qp *qp;
4377         int ret;
4378
4379         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4380         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4381         if (!attr || !init_attr) {
4382                 ret = -ENOMEM;
4383                 goto error_0;
4384         }
4385
4386         pd = ib_alloc_pd(&dev->ib_dev, 0);
4387         if (IS_ERR(pd)) {
4388                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4389                 ret = PTR_ERR(pd);
4390                 goto error_0;
4391         }
4392
4393         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4394         if (IS_ERR(cq)) {
4395                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4396                 ret = PTR_ERR(cq);
4397                 goto error_2;
4398         }
4399
4400         init_attr->send_cq = cq;
4401         init_attr->recv_cq = cq;
4402         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4403         init_attr->cap.max_send_wr = MAX_UMR_WR;
4404         init_attr->cap.max_send_sge = 1;
4405         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4406         init_attr->port_num = 1;
4407         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4408         if (IS_ERR(qp)) {
4409                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4410                 ret = PTR_ERR(qp);
4411                 goto error_3;
4412         }
4413         qp->device     = &dev->ib_dev;
4414         qp->real_qp    = qp;
4415         qp->uobject    = NULL;
4416         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4417         qp->send_cq    = init_attr->send_cq;
4418         qp->recv_cq    = init_attr->recv_cq;
4419
4420         attr->qp_state = IB_QPS_INIT;
4421         attr->port_num = 1;
4422         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4423                                 IB_QP_PORT, NULL);
4424         if (ret) {
4425                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4426                 goto error_4;
4427         }
4428
4429         memset(attr, 0, sizeof(*attr));
4430         attr->qp_state = IB_QPS_RTR;
4431         attr->path_mtu = IB_MTU_256;
4432
4433         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4434         if (ret) {
4435                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4436                 goto error_4;
4437         }
4438
4439         memset(attr, 0, sizeof(*attr));
4440         attr->qp_state = IB_QPS_RTS;
4441         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4442         if (ret) {
4443                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4444                 goto error_4;
4445         }
4446
4447         dev->umrc.qp = qp;
4448         dev->umrc.cq = cq;
4449         dev->umrc.pd = pd;
4450
4451         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4452         ret = mlx5_mr_cache_init(dev);
4453         if (ret) {
4454                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4455                 goto error_4;
4456         }
4457
4458         kfree(attr);
4459         kfree(init_attr);
4460
4461         return 0;
4462
4463 error_4:
4464         mlx5_ib_destroy_qp(qp, NULL);
4465         dev->umrc.qp = NULL;
4466
4467 error_3:
4468         ib_free_cq(cq);
4469         dev->umrc.cq = NULL;
4470
4471 error_2:
4472         ib_dealloc_pd(pd);
4473         dev->umrc.pd = NULL;
4474
4475 error_0:
4476         kfree(attr);
4477         kfree(init_attr);
4478         return ret;
4479 }
4480
4481 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4482 {
4483         struct dentry *root;
4484
4485         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4486                 return 0;
4487
4488         mutex_init(&dev->delay_drop.lock);
4489         dev->delay_drop.dev = dev;
4490         dev->delay_drop.activate = false;
4491         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4492         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4493         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4494         atomic_set(&dev->delay_drop.events_cnt, 0);
4495
4496         if (!mlx5_debugfs_root)
4497                 return 0;
4498
4499         root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4500         dev->delay_drop.dir_debugfs = root;
4501
4502         debugfs_create_atomic_t("num_timeout_events", 0400, root,
4503                                 &dev->delay_drop.events_cnt);
4504         debugfs_create_atomic_t("num_rqs", 0400, root,
4505                                 &dev->delay_drop.rqs_cnt);
4506         debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4507                             &fops_delay_drop_timeout);
4508         return 0;
4509 }
4510
4511 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4512 {
4513         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4514                 return;
4515
4516         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4517         if (!dev->delay_drop.dir_debugfs)
4518                 return;
4519
4520         debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4521         dev->delay_drop.dir_debugfs = NULL;
4522 }
4523
4524 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4525 {
4526         dev->mdev_events.notifier_call = mlx5_ib_event;
4527         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4528         return 0;
4529 }
4530
4531 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4532 {
4533         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4534 }
4535
4536 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4537                       const struct mlx5_ib_profile *profile,
4538                       int stage)
4539 {
4540         dev->ib_active = false;
4541
4542         /* Number of stages to cleanup */
4543         while (stage) {
4544                 stage--;
4545                 if (profile->stage[stage].cleanup)
4546                         profile->stage[stage].cleanup(dev);
4547         }
4548
4549         kfree(dev->port);
4550         ib_dealloc_device(&dev->ib_dev);
4551 }
4552
4553 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4554                   const struct mlx5_ib_profile *profile)
4555 {
4556         int err;
4557         int i;
4558
4559         dev->profile = profile;
4560
4561         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4562                 if (profile->stage[i].init) {
4563                         err = profile->stage[i].init(dev);
4564                         if (err)
4565                                 goto err_out;
4566                 }
4567         }
4568
4569         dev->ib_active = true;
4570         return 0;
4571
4572 err_out:
4573         /* Clean up stages which were initialized */
4574         while (i) {
4575                 i--;
4576                 if (profile->stage[i].cleanup)
4577                         profile->stage[i].cleanup(dev);
4578         }
4579         return -ENOMEM;
4580 }
4581
4582 static const struct mlx5_ib_profile pf_profile = {
4583         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4584                      mlx5_ib_stage_init_init,
4585                      mlx5_ib_stage_init_cleanup),
4586         STAGE_CREATE(MLX5_IB_STAGE_FS,
4587                      mlx5_ib_fs_init,
4588                      mlx5_ib_fs_cleanup),
4589         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4590                      mlx5_ib_stage_caps_init,
4591                      mlx5_ib_stage_caps_cleanup),
4592         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4593                      mlx5_ib_stage_non_default_cb,
4594                      NULL),
4595         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4596                      mlx5_ib_roce_init,
4597                      mlx5_ib_roce_cleanup),
4598         STAGE_CREATE(MLX5_IB_STAGE_QP,
4599                      mlx5_init_qp_table,
4600                      mlx5_cleanup_qp_table),
4601         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4602                      mlx5_init_srq_table,
4603                      mlx5_cleanup_srq_table),
4604         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4605                      mlx5_ib_dev_res_init,
4606                      mlx5_ib_dev_res_cleanup),
4607         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4608                      mlx5_ib_stage_dev_notifier_init,
4609                      mlx5_ib_stage_dev_notifier_cleanup),
4610         STAGE_CREATE(MLX5_IB_STAGE_ODP,
4611                      mlx5_ib_odp_init_one,
4612                      mlx5_ib_odp_cleanup_one),
4613         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4614                      mlx5_ib_counters_init,
4615                      mlx5_ib_counters_cleanup),
4616         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4617                      mlx5_ib_stage_cong_debugfs_init,
4618                      mlx5_ib_stage_cong_debugfs_cleanup),
4619         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4620                      mlx5_ib_stage_uar_init,
4621                      mlx5_ib_stage_uar_cleanup),
4622         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4623                      mlx5_ib_stage_bfrag_init,
4624                      mlx5_ib_stage_bfrag_cleanup),
4625         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4626                      NULL,
4627                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4628         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4629                      mlx5_ib_devx_init,
4630                      mlx5_ib_devx_cleanup),
4631         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4632                      mlx5_ib_stage_ib_reg_init,
4633                      mlx5_ib_stage_ib_reg_cleanup),
4634         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4635                      mlx5_ib_stage_post_ib_reg_umr_init,
4636                      NULL),
4637         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4638                      mlx5_ib_stage_delay_drop_init,
4639                      mlx5_ib_stage_delay_drop_cleanup),
4640         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4641                      mlx5_ib_restrack_init,
4642                      NULL),
4643 };
4644
4645 const struct mlx5_ib_profile raw_eth_profile = {
4646         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4647                      mlx5_ib_stage_init_init,
4648                      mlx5_ib_stage_init_cleanup),
4649         STAGE_CREATE(MLX5_IB_STAGE_FS,
4650                      mlx5_ib_fs_init,
4651                      mlx5_ib_fs_cleanup),
4652         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4653                      mlx5_ib_stage_caps_init,
4654                      mlx5_ib_stage_caps_cleanup),
4655         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4656                      mlx5_ib_stage_raw_eth_non_default_cb,
4657                      NULL),
4658         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4659                      mlx5_ib_roce_init,
4660                      mlx5_ib_roce_cleanup),
4661         STAGE_CREATE(MLX5_IB_STAGE_QP,
4662                      mlx5_init_qp_table,
4663                      mlx5_cleanup_qp_table),
4664         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4665                      mlx5_init_srq_table,
4666                      mlx5_cleanup_srq_table),
4667         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4668                      mlx5_ib_dev_res_init,
4669                      mlx5_ib_dev_res_cleanup),
4670         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4671                      mlx5_ib_stage_dev_notifier_init,
4672                      mlx5_ib_stage_dev_notifier_cleanup),
4673         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4674                      mlx5_ib_counters_init,
4675                      mlx5_ib_counters_cleanup),
4676         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4677                      mlx5_ib_stage_cong_debugfs_init,
4678                      mlx5_ib_stage_cong_debugfs_cleanup),
4679         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4680                      mlx5_ib_stage_uar_init,
4681                      mlx5_ib_stage_uar_cleanup),
4682         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4683                      mlx5_ib_stage_bfrag_init,
4684                      mlx5_ib_stage_bfrag_cleanup),
4685         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4686                      NULL,
4687                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4688         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4689                      mlx5_ib_devx_init,
4690                      mlx5_ib_devx_cleanup),
4691         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4692                      mlx5_ib_stage_ib_reg_init,
4693                      mlx5_ib_stage_ib_reg_cleanup),
4694         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4695                      mlx5_ib_stage_post_ib_reg_umr_init,
4696                      NULL),
4697         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4698                      mlx5_ib_restrack_init,
4699                      NULL),
4700 };
4701
4702 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4703                           const struct auxiliary_device_id *id)
4704 {
4705         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4706         struct mlx5_core_dev *mdev = idev->mdev;
4707         struct mlx5_ib_multiport_info *mpi;
4708         struct mlx5_ib_dev *dev;
4709         bool bound = false;
4710         int err;
4711
4712         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4713         if (!mpi)
4714                 return -ENOMEM;
4715
4716         mpi->mdev = mdev;
4717         err = mlx5_query_nic_vport_system_image_guid(mdev,
4718                                                      &mpi->sys_image_guid);
4719         if (err) {
4720                 kfree(mpi);
4721                 return err;
4722         }
4723
4724         mutex_lock(&mlx5_ib_multiport_mutex);
4725         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4726                 if (dev->sys_image_guid == mpi->sys_image_guid)
4727                         bound = mlx5_ib_bind_slave_port(dev, mpi);
4728
4729                 if (bound) {
4730                         rdma_roce_rescan_device(&dev->ib_dev);
4731                         break;
4732                 }
4733         }
4734
4735         if (!bound) {
4736                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4737                 dev_dbg(mdev->device,
4738                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
4739         }
4740         mutex_unlock(&mlx5_ib_multiport_mutex);
4741
4742         dev_set_drvdata(&adev->dev, mpi);
4743         return 0;
4744 }
4745
4746 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4747 {
4748         struct mlx5_ib_multiport_info *mpi;
4749
4750         mpi = dev_get_drvdata(&adev->dev);
4751         mutex_lock(&mlx5_ib_multiport_mutex);
4752         if (mpi->ibdev)
4753                 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4754         list_del(&mpi->list);
4755         mutex_unlock(&mlx5_ib_multiport_mutex);
4756         kfree(mpi);
4757 }
4758
4759 static int mlx5r_probe(struct auxiliary_device *adev,
4760                        const struct auxiliary_device_id *id)
4761 {
4762         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4763         struct mlx5_core_dev *mdev = idev->mdev;
4764         const struct mlx5_ib_profile *profile;
4765         int port_type_cap, num_ports, ret;
4766         enum rdma_link_layer ll;
4767         struct mlx5_ib_dev *dev;
4768
4769         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4770         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4771
4772         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4773                         MLX5_CAP_GEN(mdev, num_vhca_ports));
4774         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4775         if (!dev)
4776                 return -ENOMEM;
4777         dev->port = kcalloc(num_ports, sizeof(*dev->port),
4778                              GFP_KERNEL);
4779         if (!dev->port) {
4780                 ib_dealloc_device(&dev->ib_dev);
4781                 return -ENOMEM;
4782         }
4783
4784         dev->mdev = mdev;
4785         dev->num_ports = num_ports;
4786
4787         if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev))
4788                 profile = &raw_eth_profile;
4789         else
4790                 profile = &pf_profile;
4791
4792         ret = __mlx5_ib_add(dev, profile);
4793         if (ret) {
4794                 kfree(dev->port);
4795                 ib_dealloc_device(&dev->ib_dev);
4796                 return ret;
4797         }
4798
4799         dev_set_drvdata(&adev->dev, dev);
4800         return 0;
4801 }
4802
4803 static void mlx5r_remove(struct auxiliary_device *adev)
4804 {
4805         struct mlx5_ib_dev *dev;
4806
4807         dev = dev_get_drvdata(&adev->dev);
4808         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4809 }
4810
4811 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4812         { .name = MLX5_ADEV_NAME ".multiport", },
4813         {},
4814 };
4815
4816 static const struct auxiliary_device_id mlx5r_id_table[] = {
4817         { .name = MLX5_ADEV_NAME ".rdma", },
4818         {},
4819 };
4820
4821 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4822 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4823
4824 static struct auxiliary_driver mlx5r_mp_driver = {
4825         .name = "multiport",
4826         .probe = mlx5r_mp_probe,
4827         .remove = mlx5r_mp_remove,
4828         .id_table = mlx5r_mp_id_table,
4829 };
4830
4831 static struct auxiliary_driver mlx5r_driver = {
4832         .name = "rdma",
4833         .probe = mlx5r_probe,
4834         .remove = mlx5r_remove,
4835         .id_table = mlx5r_id_table,
4836 };
4837
4838 static int __init mlx5_ib_init(void)
4839 {
4840         int ret;
4841
4842         xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4843         if (!xlt_emergency_page)
4844                 return -ENOMEM;
4845
4846         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4847         if (!mlx5_ib_event_wq) {
4848                 free_page((unsigned long)xlt_emergency_page);
4849                 return -ENOMEM;
4850         }
4851
4852         mlx5_ib_odp_init();
4853         ret = mlx5r_rep_init();
4854         if (ret)
4855                 goto rep_err;
4856         ret = auxiliary_driver_register(&mlx5r_mp_driver);
4857         if (ret)
4858                 goto mp_err;
4859         ret = auxiliary_driver_register(&mlx5r_driver);
4860         if (ret)
4861                 goto drv_err;
4862         return 0;
4863
4864 drv_err:
4865         auxiliary_driver_unregister(&mlx5r_mp_driver);
4866 mp_err:
4867         mlx5r_rep_cleanup();
4868 rep_err:
4869         destroy_workqueue(mlx5_ib_event_wq);
4870         free_page((unsigned long)xlt_emergency_page);
4871         return ret;
4872 }
4873
4874 static void __exit mlx5_ib_cleanup(void)
4875 {
4876         auxiliary_driver_unregister(&mlx5r_driver);
4877         auxiliary_driver_unregister(&mlx5r_mp_driver);
4878         mlx5r_rep_cleanup();
4879
4880         destroy_workqueue(mlx5_ib_event_wq);
4881         free_page((unsigned long)xlt_emergency_page);
4882 }
4883
4884 module_init(mlx5_ib_init);
4885 module_exit(mlx5_ib_cleanup);