drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v3_0_2.h"
  26
  27 #include "mmhub/mmhub_3_0_2_offset.h"
  28 #include "mmhub/mmhub_3_0_2_sh_mask.h"
  29 #include "navi10_enum.h"
  30
  31 #include "soc15_common.h"
  32
  33 #define regMMVM_L2_CNTL3_DEFAULT                                0x80100007
  34 #define regMMVM_L2_CNTL4_DEFAULT                                0x000000c1
  35 #define regMMVM_L2_CNTL5_DEFAULT                                0x00003fe0
  36
  37 static const char *mmhub_client_ids_v3_0_2[][2] = {
  38         [0][0] = "VMC",
  39         [4][0] = "DCEDMC",
  40         [5][0] = "DCEVGA",
  41         [6][0] = "MP0",
  42         [7][0] = "MP1",
  43         [8][0] = "MPIO",
  44         [16][0] = "HDP",
  45         [17][0] = "LSDMA",
  46         [18][0] = "JPEG",
  47         [19][0] = "VCNU0",
  48         [21][0] = "VSCH",
  49         [22][0] = "VCNU1",
  50         [23][0] = "VCN1",
  51         [32+20][0] = "VCN0",
  52         [2][1] = "DBGUNBIO",
  53         [3][1] = "DCEDWB",
  54         [4][1] = "DCEDMC",
  55         [5][1] = "DCEVGA",
  56         [6][1] = "MP0",
  57         [7][1] = "MP1",
  58         [8][1] = "MPIO",
  59         [10][1] = "DBGU0",
  60         [11][1] = "DBGU1",
  61         [12][1] = "DBGU2",
  62         [13][1] = "DBGU3",
  63         [14][1] = "XDP",
  64         [15][1] = "OSSSYS",
  65         [16][1] = "HDP",
  66         [17][1] = "LSDMA",
  67         [18][1] = "JPEG",
  68         [19][1] = "VCNU0",
  69         [20][1] = "VCN0",
  70         [21][1] = "VSCH",
  71         [22][1] = "VCNU1",
  72         [23][1] = "VCN1",
  73 };
  74
  75 static uint32_t mmhub_v3_0_2_get_invalidate_req(unsigned int vmid,
  76                                               uint32_t flush_type)
  77 {
  78         u32 req = 0;
  79
  80         /* invalidate using legacy mode on vmid*/
  81         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  82                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  83         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  84         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  85         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  86         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  87         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  88         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  89         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  90                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  91
  92         return req;
  93 }
  94
  95 static void
  96 mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev,
  97                                              uint32_t status)
  98 {
  99         uint32_t cid, rw;
 100         const char *mmhub_cid = NULL;
 101
 102         cid = REG_GET_FIELD(status,
 103                             MMVM_L2_PROTECTION_FAULT_STATUS, CID);
 104         rw = REG_GET_FIELD(status,
 105                            MMVM_L2_PROTECTION_FAULT_STATUS, RW);
 106
 107         dev_err(adev->dev,
 108                 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 109                 status);
 110
 111         mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw];
 112         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 113                 mmhub_cid ? mmhub_cid : "unknown", cid);
 114         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 115                 REG_GET_FIELD(status,
 116                 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 117         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 118                 REG_GET_FIELD(status,
 119                 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 120         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 121                 REG_GET_FIELD(status,
 122                 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 123         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 124                 REG_GET_FIELD(status,
 125                 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 126         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 127 }
 128
 129 static void mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 130                                 uint64_t page_table_base)
 131 {
 132         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 133
 134         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 135                             hub->ctx_addr_distance * vmid,
 136                             lower_32_bits(page_table_base));
 137
 138         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 139                             hub->ctx_addr_distance * vmid,
 140                             upper_32_bits(page_table_base));
 141 }
 142
 143 static void mmhub_v3_0_2_init_gart_aperture_regs(struct amdgpu_device *adev)
 144 {
 145         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 146
 147         mmhub_v3_0_2_setup_vm_pt_regs(adev, 0, pt_base);
 148
 149         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 150                      (u32)(adev->gmc.gart_start >> 12));
 151         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 152                      (u32)(adev->gmc.gart_start >> 44));
 153
 154         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 155                      (u32)(adev->gmc.gart_end >> 12));
 156         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 157                      (u32)(adev->gmc.gart_end >> 44));
 158 }
 159
 160 static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev)
 161 {
 162         uint64_t value;
 163         uint32_t tmp;
 164
 165         /* Program the AGP BAR */
 166         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
 167         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 168         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 169
 170         if (!amdgpu_sriov_vf(adev)) {
 171                 /*
 172                  * the new L1 policy will block SRIOV guest from writing
 173                  * these regs, and they will be programed at host.
 174                  * so skip programing these regs.
 175                  */
 176                 /* Program the system aperture low logical page number. */
 177                 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 178                              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 179                 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 180                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 181         }
 182
 183         /* Set default page address. */
 184         value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
 185         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 186                      (u32)(value >> 12));
 187         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 188                      (u32)(value >> 44));
 189
 190         /* Program "protection fault". */
 191         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 192                      (u32)(adev->dummy_page_addr >> 12));
 193         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 194                      (u32)((u64)adev->dummy_page_addr >> 44));
 195
 196         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
 197         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
 198                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 199         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 200 }
 201
 202 static void mmhub_v3_0_2_init_tlb_regs(struct amdgpu_device *adev)
 203 {
 204         uint32_t tmp;
 205
 206         /* Setup TLB control */
 207         tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
 208
 209         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 210         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 211         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 212                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 213         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 214                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 215         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 216         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 217                             MTYPE, MTYPE_UC); /* UC, uncached */
 218
 219         WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
 220 }
 221
 222 static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
 223 {
 224         uint32_t tmp;
 225
 226         /* These registers are not accessible to VF-SRIOV.
 227          * The PF will program them instead.
 228          */
 229         if (amdgpu_sriov_vf(adev))
 230                 return;
 231
 232         /* Setup L2 cache */
 233         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
 234         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 235         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 236         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 237                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 238         /* XXX for emulation, Refer to closed source code.*/
 239         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 240                             0);
 241         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 242         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 243         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 244         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
 245
 246         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
 247         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 248         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 249         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
 250
 251         tmp = regMMVM_L2_CNTL3_DEFAULT;
 252         if (adev->gmc.translate_further) {
 253                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
 254                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 255                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 256         } else {
 257                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
 258                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 259                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 260         }
 261         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
 262
 263         tmp = regMMVM_L2_CNTL4_DEFAULT;
 264         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 265         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 266         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
 267
 268         tmp = regMMVM_L2_CNTL5_DEFAULT;
 269         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 270         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 271 }
 272
 273 static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)
 274 {
 275         uint32_t tmp;
 276
 277         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
 278         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 279         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 280         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 281                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 282         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
 283 }
 284
 285 static void mmhub_v3_0_2_disable_identity_aperture(struct amdgpu_device *adev)
 286 {
 287         /* These registers are not accessible to VF-SRIOV.
 288          * The PF will program them instead.
 289          */
 290         if (amdgpu_sriov_vf(adev))
 291                 return;
 292
 293         WREG32_SOC15(MMHUB, 0,
 294                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 295                      0xFFFFFFFF);
 296         WREG32_SOC15(MMHUB, 0,
 297                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 298                      0x0000000F);
 299
 300         WREG32_SOC15(MMHUB, 0,
 301                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 302         WREG32_SOC15(MMHUB, 0,
 303                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 304
 305         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 306                      0);
 307         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 308                      0);
 309 }
 310
 311 static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
 312 {
 313         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 314         int i;
 315         uint32_t tmp;
 316
 317         for (i = 0; i <= 14; i++) {
 318                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
 319                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 320                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 321                                     adev->vm_manager.num_level);
 322                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 323                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 324                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 325                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 326                                     1);
 327                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 328                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 329                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 330                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 331                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 332                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 333                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 334                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 335                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 336                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 337                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 338                                     PAGE_TABLE_BLOCK_SIZE,
 339                                     adev->vm_manager.block_size - 9);
 340                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 341                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 342                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 343                                     !amdgpu_noretry);
 344                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
 345                                     i * hub->ctx_distance, tmp);
 346                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 347                                     i * hub->ctx_addr_distance, 0);
 348                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 349                                     i * hub->ctx_addr_distance, 0);
 350                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 351                                     i * hub->ctx_addr_distance,
 352                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 353                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 354                                     i * hub->ctx_addr_distance,
 355                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 356         }
 357
 358         hub->vm_cntx_cntl = tmp;
 359 }
 360
 361 static void mmhub_v3_0_2_program_invalidation(struct amdgpu_device *adev)
 362 {
 363         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 364         unsigned i;
 365
 366         for (i = 0; i < 18; ++i) {
 367                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 368                                     i * hub->eng_addr_distance, 0xffffffff);
 369                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 370                                     i * hub->eng_addr_distance, 0x1f);
 371         }
 372 }
 373
 374 static int mmhub_v3_0_2_gart_enable(struct amdgpu_device *adev)
 375 {
 376         /* GART Enable. */
 377         mmhub_v3_0_2_init_gart_aperture_regs(adev);
 378         mmhub_v3_0_2_init_system_aperture_regs(adev);
 379         mmhub_v3_0_2_init_tlb_regs(adev);
 380         mmhub_v3_0_2_init_cache_regs(adev);
 381
 382         mmhub_v3_0_2_enable_system_domain(adev);
 383         mmhub_v3_0_2_disable_identity_aperture(adev);
 384         mmhub_v3_0_2_setup_vmid_config(adev);
 385         mmhub_v3_0_2_program_invalidation(adev);
 386
 387         return 0;
 388 }
 389
 390 static void mmhub_v3_0_2_gart_disable(struct amdgpu_device *adev)
 391 {
 392         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 393         u32 tmp;
 394         u32 i;
 395
 396         /* Disable all tables */
 397         for (i = 0; i < 16; i++)
 398                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
 399                                     i * hub->ctx_distance, 0);
 400
 401         /* Setup TLB control */
 402         tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
 403         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 404         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 405                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 406         WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
 407
 408         /* Setup L2 cache */
 409         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
 410         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 411         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
 412         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
 413 }
 414
 415 /**
 416  * mmhub_v3_0_2_set_fault_enable_default - update GART/VM fault handling
 417  *
 418  * @adev: amdgpu_device pointer
 419  * @value: true redirects VM faults to the default page
 420  */
 421 static void mmhub_v3_0_2_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 422 {
 423         u32 tmp;
 424
 425         /* These registers are not accessible to VF-SRIOV.
 426          * The PF will program them instead.
 427          */
 428         if (amdgpu_sriov_vf(adev))
 429                 return;
 430
 431         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
 432         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 433                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 434         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 435                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 436         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 437                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 438         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 439                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 440         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 441                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 442                             value);
 443         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 444                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 445         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 446                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 447         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 448                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 449         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 450                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 451         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 452                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 453         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 454                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 455         if (!value) {
 456                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 457                                 CRASH_ON_NO_RETRY_FAULT, 1);
 458                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 459                                 CRASH_ON_RETRY_FAULT, 1);
 460         }
 461         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 462 }
 463
 464 static const struct amdgpu_vmhub_funcs mmhub_v3_0_2_vmhub_funcs = {
 465         .print_l2_protection_fault_status = mmhub_v3_0_2_print_l2_protection_fault_status,
 466         .get_invalidate_req = mmhub_v3_0_2_get_invalidate_req,
 467 };
 468
 469 static void mmhub_v3_0_2_init(struct amdgpu_device *adev)
 470 {
 471         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 472
 473         hub->ctx0_ptb_addr_lo32 =
 474                 SOC15_REG_OFFSET(MMHUB, 0,
 475                                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 476         hub->ctx0_ptb_addr_hi32 =
 477                 SOC15_REG_OFFSET(MMHUB, 0,
 478                                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 479         hub->vm_inv_eng0_sem =
 480                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
 481         hub->vm_inv_eng0_req =
 482                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
 483         hub->vm_inv_eng0_ack =
 484                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
 485         hub->vm_context0_cntl =
 486                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
 487         hub->vm_l2_pro_fault_status =
 488                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
 489         hub->vm_l2_pro_fault_cntl =
 490                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
 491
 492         hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
 493         hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 494                 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 495         hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
 496                 regMMVM_INVALIDATE_ENG0_REQ;
 497         hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 498                 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 499
 500         hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 501                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 502                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 503                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 504                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 505                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 506                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 507
 508         hub->vm_l2_bank_select_reserved_cid2 =
 509                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
 510
 511         hub->vmhub_funcs = &mmhub_v3_0_2_vmhub_funcs;
 512 }
 513
 514 static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev)
 515 {
 516         u64 base;
 517
 518         base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
 519         base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
 520         base <<= 24;
 521
 522         return base;
 523 }
 524
 525 static u64 mmhub_v3_0_2_get_mc_fb_offset(struct amdgpu_device *adev)
 526 {
 527         return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
 528 }
 529
 530 static void mmhub_v3_0_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 531                                                         bool enable)
 532 {
 533         //TODO
 534 }
 535
 536 static void mmhub_v3_0_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 537                                                        bool enable)
 538 {
 539         //TODO
 540 }
 541
 542 static int mmhub_v3_0_2_set_clockgating(struct amdgpu_device *adev,
 543                                enum amd_clockgating_state state)
 544 {
 545         if (amdgpu_sriov_vf(adev))
 546                 return 0;
 547
 548         mmhub_v3_0_2_update_medium_grain_clock_gating(adev,
 549                         state == AMD_CG_STATE_GATE);
 550         mmhub_v3_0_2_update_medium_grain_light_sleep(adev,
 551                         state == AMD_CG_STATE_GATE);
 552         return 0;
 553 }
 554
 555 static void mmhub_v3_0_2_get_clockgating(struct amdgpu_device *adev, u64 *flags)
 556 {
 557         //TODO
 558 }
 559
 560 const struct amdgpu_mmhub_funcs mmhub_v3_0_2_funcs = {
 561         .init = mmhub_v3_0_2_init,
 562         .get_fb_location = mmhub_v3_0_2_get_fb_location,
 563         .get_mc_fb_offset = mmhub_v3_0_2_get_mc_fb_offset,
 564         .gart_enable = mmhub_v3_0_2_gart_enable,
 565         .set_fault_enable_default = mmhub_v3_0_2_set_fault_enable_default,
 566         .gart_disable = mmhub_v3_0_2_gart_disable,
 567         .set_clockgating = mmhub_v3_0_2_set_clockgating,
 568         .get_clockgating = mmhub_v3_0_2_get_clockgating,
 569         .setup_vm_pt_regs = mmhub_v3_0_2_setup_vm_pt_regs,
 570 };