drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/delay.h>
  24 #include <linux/kernel.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_gfx.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_smu.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "imu_v11_0.h"
  34 #include "soc21.h"
  35 #include "nvd.h"
  36
  37 #include "gc/gc_11_0_0_offset.h"
  38 #include "gc/gc_11_0_0_sh_mask.h"
  39 #include "smuio/smuio_13_0_6_offset.h"
  40 #include "smuio/smuio_13_0_6_sh_mask.h"
  41 #include "navi10_enum.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "clearstate_gfx11.h"
  47 #include "v11_structs.h"
  48 #include "gfx_v11_0.h"
  49 #include "gfx_v11_0_cleaner_shader.h"
  50 #include "gfx_v11_0_3.h"
  51 #include "nbio_v4_3.h"
  52 #include "mes_v11_0.h"
  53
  54 #define GFX11_NUM_GFX_RINGS             1
  55 #define GFX11_MEC_HPD_SIZE      2048
  56
  57 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  58 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1        0x1388
  59
  60 #define regCGTT_WD_CLK_CTRL             0x5086
  61 #define regCGTT_WD_CLK_CTRL_BASE_IDX    1
  62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1   0x4e7e
  63 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX  1
  64 #define regPC_CONFIG_CNTL_1             0x194d
  65 #define regPC_CONFIG_CNTL_1_BASE_IDX    1
  66
  67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
  68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
  69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
  70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
  71 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin");
  72 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
  73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
  74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");
  75 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin");
  76 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin");
  77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
  79 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
  81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
  82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
  83 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
  84 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
  85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
  86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
  87 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
  88 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
  89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin");
  90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
  91 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
  92 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
  93 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin");
  94 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin");
  95 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin");
  96 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin");
  97 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin");
  98 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin");
  99 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin");
 100 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin");
 101
 102 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
 103         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
 104         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
 105         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
 106         SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
 107         SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
 108         SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
 109         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
 110         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
 111         SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
 112         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
 113         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
 114         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
 115         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
 116         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
 117         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
 118         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
 119         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
 120         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
 121         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
 122         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
 123         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
 124         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
 125         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
 126         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),
 127         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
 128         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
 129         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
 130         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
 131         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
 132         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
 133         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
 134         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
 135         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
 136         SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
 137         SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
 138         SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
 139         SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
 140         SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
 141         SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
 142         SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
 143         SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
 144         SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
 145         SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
 146         SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
 147         SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
 148         SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
 149         SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
 150         SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),
 151         SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
 152         SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
 153         SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
 154         SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
 155         SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
 156         SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
 157         SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
 158         SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
 159         SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
 160         /* cp header registers */
 161         SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
 162         SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
 163         SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
 164         SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
 165         /* SE status registers */
 166         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
 167         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
 168         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
 169         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),
 170         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),
 171         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
 172 };
 173
 174 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = {
 175         /* compute registers */
 176         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
 177         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
 178         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
 179         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
 180         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
 181         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
 182         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
 183         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
 184         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
 185         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
 186         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
 187         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
 188         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
 189         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
 190         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
 191         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
 192         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
 193         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
 194         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
 195         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
 196         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
 197         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
 198         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
 199         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
 200         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
 201         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
 202         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
 203         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
 204         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
 205         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
 206         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
 207         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
 208         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
 209         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
 210         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
 211         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
 212         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
 213         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
 214         SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
 215 };
 216
 217 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = {
 218         /* gfx queue registers */
 219         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
 220         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
 221         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
 222         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
 223         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
 224         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
 225         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
 226         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
 227         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
 228         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
 229         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
 230         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
 231         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
 232         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
 233         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
 234         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
 235         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
 236         SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
 237         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
 238         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
 239         SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
 240         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
 241         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
 242         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
 243         SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
 244 };
 245
 246 static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
 248 };
 249
 250 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
 251 {
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
 261 };
 262
 263 #define DEFAULT_SH_MEM_CONFIG \
 264         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 265          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 266          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 267
 268 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
 269 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
 270 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
 271 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
 272 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
 273 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
 274 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
 275 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
 276                                  struct amdgpu_cu_info *cu_info);
 277 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 278 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 279                                    u32 sh_num, u32 instance, int xcc_id);
 280 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 281
 282 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 283 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
 284 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 285                                      uint32_t val);
 286 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 287 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 288                                            uint16_t pasid, uint32_t flush_type,
 289                                            bool all_hub, uint8_t dst_sel);
 290 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
 291 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
 292 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
 293                                       bool enable);
 294
 295 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 296 {
 297         struct amdgpu_device *adev = kiq_ring->adev;
 298         u64 shader_mc_addr;
 299
 300         /* Cleaner shader MC address */
 301         shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
 302
 303         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 304         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 305                           PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */
 306                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 307         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 308         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 309         amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
 310         amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
 311         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 312         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 313 }
 314
 315 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 316                                  struct amdgpu_ring *ring)
 317 {
 318         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 319         uint64_t wptr_addr = ring->wptr_gpu_addr;
 320         uint32_t me = 0, eng_sel = 0;
 321
 322         switch (ring->funcs->type) {
 323         case AMDGPU_RING_TYPE_COMPUTE:
 324                 me = 1;
 325                 eng_sel = 0;
 326                 break;
 327         case AMDGPU_RING_TYPE_GFX:
 328                 me = 0;
 329                 eng_sel = 4;
 330                 break;
 331         case AMDGPU_RING_TYPE_MES:
 332                 me = 2;
 333                 eng_sel = 5;
 334                 break;
 335         default:
 336                 WARN_ON(1);
 337         }
 338
 339         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 340         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 341         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 342                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 343                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 344                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 345                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 346                           PACKET3_MAP_QUEUES_ME((me)) |
 347                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 348                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 349                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 350                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 351         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 352         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 353         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 354         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 355         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 356 }
 357
 358 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 359                                    struct amdgpu_ring *ring,
 360                                    enum amdgpu_unmap_queues_action action,
 361                                    u64 gpu_addr, u64 seq)
 362 {
 363         struct amdgpu_device *adev = kiq_ring->adev;
 364         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 365
 366         if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
 367                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
 368                 return;
 369         }
 370
 371         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 372         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 373                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 374                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 375                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 376                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 377         amdgpu_ring_write(kiq_ring,
 378                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 379
 380         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 381                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 382                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 383                 amdgpu_ring_write(kiq_ring, seq);
 384         } else {
 385                 amdgpu_ring_write(kiq_ring, 0);
 386                 amdgpu_ring_write(kiq_ring, 0);
 387                 amdgpu_ring_write(kiq_ring, 0);
 388         }
 389 }
 390
 391 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,
 392                                    struct amdgpu_ring *ring,
 393                                    u64 addr,
 394                                    u64 seq)
 395 {
 396         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 397
 398         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 399         amdgpu_ring_write(kiq_ring,
 400                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 401                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 402                           PACKET3_QUERY_STATUS_COMMAND(2));
 403         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 404                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 405                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 406         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 407         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 408         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 409         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 410 }
 411
 412 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 413                                 uint16_t pasid, uint32_t flush_type,
 414                                 bool all_hub)
 415 {
 416         gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
 417 }
 418
 419 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = {
 420         .kiq_set_resources = gfx11_kiq_set_resources,
 421         .kiq_map_queues = gfx11_kiq_map_queues,
 422         .kiq_unmap_queues = gfx11_kiq_unmap_queues,
 423         .kiq_query_status = gfx11_kiq_query_status,
 424         .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs,
 425         .set_resources_size = 8,
 426         .map_queues_size = 7,
 427         .unmap_queues_size = 6,
 428         .query_status_size = 7,
 429         .invalidate_tlbs_size = 2,
 430 };
 431
 432 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 433 {
 434         adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;
 435 }
 436
 437 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
 438 {
 439         if (amdgpu_sriov_vf(adev))
 440                 return;
 441
 442         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 443         case IP_VERSION(11, 0, 1):
 444         case IP_VERSION(11, 0, 4):
 445                 soc15_program_register_sequence(adev,
 446                                                 golden_settings_gc_11_0_1,
 447                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
 448                 break;
 449         default:
 450                 break;
 451         }
 452         soc15_program_register_sequence(adev,
 453                                         golden_settings_gc_11_0,
 454                                         (const u32)ARRAY_SIZE(golden_settings_gc_11_0));
 455
 456 }
 457
 458 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 459                                        bool wc, uint32_t reg, uint32_t val)
 460 {
 461         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 462         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 463                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 464         amdgpu_ring_write(ring, reg);
 465         amdgpu_ring_write(ring, 0);
 466         amdgpu_ring_write(ring, val);
 467 }
 468
 469 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 470                                   int mem_space, int opt, uint32_t addr0,
 471                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 472                                   uint32_t inv)
 473 {
 474         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 475         amdgpu_ring_write(ring,
 476                           /* memory (1) or register (0) */
 477                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 478                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 479                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 480                            WAIT_REG_MEM_ENGINE(eng_sel)));
 481
 482         if (mem_space)
 483                 BUG_ON(addr0 & 0x3); /* Dword align */
 484         amdgpu_ring_write(ring, addr0);
 485         amdgpu_ring_write(ring, addr1);
 486         amdgpu_ring_write(ring, ref);
 487         amdgpu_ring_write(ring, mask);
 488         amdgpu_ring_write(ring, inv); /* poll interval */
 489 }
 490
 491 static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
 492 {
 493         /* Header itself is a NOP packet */
 494         if (num_nop == 1) {
 495                 amdgpu_ring_write(ring, ring->funcs->nop);
 496                 return;
 497         }
 498
 499         /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
 500         amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
 501
 502         /* Header is at index 0, followed by num_nops - 1 NOP packet's */
 503         amdgpu_ring_insert_nop(ring, num_nop - 1);
 504 }
 505
 506 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 507 {
 508         struct amdgpu_device *adev = ring->adev;
 509         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 510         uint32_t tmp = 0;
 511         unsigned i;
 512         int r;
 513
 514         WREG32(scratch, 0xCAFEDEAD);
 515         r = amdgpu_ring_alloc(ring, 5);
 516         if (r) {
 517                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 518                           ring->idx, r);
 519                 return r;
 520         }
 521
 522         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
 523                 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
 524         } else {
 525                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 526                 amdgpu_ring_write(ring, scratch -
 527                                   PACKET3_SET_UCONFIG_REG_START);
 528                 amdgpu_ring_write(ring, 0xDEADBEEF);
 529         }
 530         amdgpu_ring_commit(ring);
 531
 532         for (i = 0; i < adev->usec_timeout; i++) {
 533                 tmp = RREG32(scratch);
 534                 if (tmp == 0xDEADBEEF)
 535                         break;
 536                 if (amdgpu_emu_mode == 1)
 537                         msleep(1);
 538                 else
 539                         udelay(1);
 540         }
 541
 542         if (i >= adev->usec_timeout)
 543                 r = -ETIMEDOUT;
 544         return r;
 545 }
 546
 547 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 548 {
 549         struct amdgpu_device *adev = ring->adev;
 550         struct amdgpu_ib ib;
 551         struct dma_fence *f = NULL;
 552         unsigned index;
 553         uint64_t gpu_addr;
 554         volatile uint32_t *cpu_ptr;
 555         long r;
 556
 557         /* MES KIQ fw hasn't indirect buffer support for now */
 558         if (adev->enable_mes_kiq &&
 559             ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 560                 return 0;
 561
 562         memset(&ib, 0, sizeof(ib));
 563
 564         if (ring->is_mes_queue) {
 565                 uint32_t padding, offset;
 566
 567                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 568                 padding = amdgpu_mes_ctx_get_offs(ring,
 569                                                   AMDGPU_MES_CTX_PADDING_OFFS);
 570
 571                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 572                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 573
 574                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
 575                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
 576                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
 577         } else {
 578                 r = amdgpu_device_wb_get(adev, &index);
 579                 if (r)
 580                         return r;
 581
 582                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 583                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 584                 cpu_ptr = &adev->wb.wb[index];
 585
 586                 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
 587                 if (r) {
 588                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 589                         goto err1;
 590                 }
 591         }
 592
 593         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 594         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 595         ib.ptr[2] = lower_32_bits(gpu_addr);
 596         ib.ptr[3] = upper_32_bits(gpu_addr);
 597         ib.ptr[4] = 0xDEADBEEF;
 598         ib.length_dw = 5;
 599
 600         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 601         if (r)
 602                 goto err2;
 603
 604         r = dma_fence_wait_timeout(f, false, timeout);
 605         if (r == 0) {
 606                 r = -ETIMEDOUT;
 607                 goto err2;
 608         } else if (r < 0) {
 609                 goto err2;
 610         }
 611
 612         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
 613                 r = 0;
 614         else
 615                 r = -EINVAL;
 616 err2:
 617         if (!ring->is_mes_queue)
 618                 amdgpu_ib_free(&ib, NULL);
 619         dma_fence_put(f);
 620 err1:
 621         if (!ring->is_mes_queue)
 622                 amdgpu_device_wb_free(adev, index);
 623         return r;
 624 }
 625
 626 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
 627 {
 628         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 629         amdgpu_ucode_release(&adev->gfx.me_fw);
 630         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 631         amdgpu_ucode_release(&adev->gfx.mec_fw);
 632
 633         kfree(adev->gfx.rlc.register_list_format);
 634 }
 635
 636 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
 637 {
 638         const struct psp_firmware_header_v1_0 *toc_hdr;
 639         int err = 0;
 640
 641         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
 642                                    AMDGPU_UCODE_REQUIRED,
 643                                    "amdgpu/%s_toc.bin", ucode_prefix);
 644         if (err)
 645                 goto out;
 646
 647         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
 648         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
 649         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
 650         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
 651         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
 652                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
 653         return 0;
 654 out:
 655         amdgpu_ucode_release(&adev->psp.toc_fw);
 656         return err;
 657 }
 658
 659 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev)
 660 {
 661         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 662         case IP_VERSION(11, 0, 0):
 663         case IP_VERSION(11, 0, 2):
 664         case IP_VERSION(11, 0, 3):
 665                 if ((adev->gfx.me_fw_version >= 1505) &&
 666                     (adev->gfx.pfp_fw_version >= 1600) &&
 667                     (adev->gfx.mec_fw_version >= 512)) {
 668                         if (amdgpu_sriov_vf(adev))
 669                                 adev->gfx.cp_gfx_shadow = true;
 670                         else
 671                                 adev->gfx.cp_gfx_shadow = false;
 672                 }
 673                 break;
 674         default:
 675                 adev->gfx.cp_gfx_shadow = false;
 676                 break;
 677         }
 678 }
 679
 680 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
 681 {
 682         char ucode_prefix[25];
 683         int err;
 684         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 685         uint16_t version_major;
 686         uint16_t version_minor;
 687
 688         DRM_DEBUG("\n");
 689
 690         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 691         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
 692                                    AMDGPU_UCODE_REQUIRED,
 693                                    "amdgpu/%s_pfp.bin", ucode_prefix);
 694         if (err)
 695                 goto out;
 696         /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/
 697         adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
 698                                 (union amdgpu_firmware_header *)
 699                                 adev->gfx.pfp_fw->data, 2, 0);
 700         if (adev->gfx.rs64_enable) {
 701                 dev_info(adev->dev, "CP RS64 enable\n");
 702                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
 703                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
 704                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
 705         } else {
 706                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 707         }
 708
 709         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
 710                                    AMDGPU_UCODE_REQUIRED,
 711                                    "amdgpu/%s_me.bin", ucode_prefix);
 712         if (err)
 713                 goto out;
 714         if (adev->gfx.rs64_enable) {
 715                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
 716                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
 717                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
 718         } else {
 719                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 720         }
 721
 722         if (!amdgpu_sriov_vf(adev)) {
 723                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) &&
 724                     adev->pdev->revision == 0xCE)
 725                         err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
 726                                                    AMDGPU_UCODE_REQUIRED,
 727                                                    "amdgpu/gc_11_0_0_rlc_1.bin");
 728                 else
 729                         err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
 730                                                    AMDGPU_UCODE_REQUIRED,
 731                                                    "amdgpu/%s_rlc.bin", ucode_prefix);
 732                 if (err)
 733                         goto out;
 734                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 735                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 736                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 737                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 738                 if (err)
 739                         goto out;
 740         }
 741
 742         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
 743                                    AMDGPU_UCODE_REQUIRED,
 744                                    "amdgpu/%s_mec.bin", ucode_prefix);
 745         if (err)
 746                 goto out;
 747         if (adev->gfx.rs64_enable) {
 748                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
 749                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
 750                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
 751                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
 752                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
 753         } else {
 754                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 755                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 756         }
 757
 758         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
 759                 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix);
 760
 761         /* only one MEC for gfx 11.0.0. */
 762         adev->gfx.mec2_fw = NULL;
 763
 764         gfx_v11_0_check_fw_cp_gfx_shadow(adev);
 765
 766         if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) {
 767                 err = adev->gfx.imu.funcs->init_microcode(adev);
 768                 if (err)
 769                         DRM_ERROR("Failed to init imu firmware!\n");
 770                 return err;
 771         }
 772
 773 out:
 774         if (err) {
 775                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
 776                 amdgpu_ucode_release(&adev->gfx.me_fw);
 777                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 778                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 779         }
 780
 781         return err;
 782 }
 783
 784 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)
 785 {
 786         u32 count = 0;
 787         const struct cs_section_def *sect = NULL;
 788         const struct cs_extent_def *ext = NULL;
 789
 790         /* begin clear state */
 791         count += 2;
 792         /* context control state */
 793         count += 3;
 794
 795         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
 796                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 797                         if (sect->id == SECT_CONTEXT)
 798                                 count += 2 + ext->reg_count;
 799                         else
 800                                 return 0;
 801                 }
 802         }
 803
 804         /* set PA_SC_TILE_STEERING_OVERRIDE */
 805         count += 3;
 806         /* end clear state */
 807         count += 2;
 808         /* clear state */
 809         count += 2;
 810
 811         return count;
 812 }
 813
 814 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,
 815                                     volatile u32 *buffer)
 816 {
 817         u32 count = 0, i;
 818         const struct cs_section_def *sect = NULL;
 819         const struct cs_extent_def *ext = NULL;
 820         int ctx_reg_offset;
 821
 822         if (adev->gfx.rlc.cs_data == NULL)
 823                 return;
 824         if (buffer == NULL)
 825                 return;
 826
 827         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 828         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 829
 830         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 831         buffer[count++] = cpu_to_le32(0x80000000);
 832         buffer[count++] = cpu_to_le32(0x80000000);
 833
 834         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 835                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 836                         if (sect->id == SECT_CONTEXT) {
 837                                 buffer[count++] =
 838                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 839                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 840                                                 PACKET3_SET_CONTEXT_REG_START);
 841                                 for (i = 0; i < ext->reg_count; i++)
 842                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 843                         } else {
 844                                 return;
 845                         }
 846                 }
 847         }
 848
 849         ctx_reg_offset =
 850                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 851         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 852         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 853         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 854
 855         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 856         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 857
 858         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 859         buffer[count++] = cpu_to_le32(0);
 860 }
 861
 862 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)
 863 {
 864         /* clear state block */
 865         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 866                         &adev->gfx.rlc.clear_state_gpu_addr,
 867                         (void **)&adev->gfx.rlc.cs_ptr);
 868
 869         /* jump table block */
 870         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 871                         &adev->gfx.rlc.cp_table_gpu_addr,
 872                         (void **)&adev->gfx.rlc.cp_table_ptr);
 873 }
 874
 875 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 876 {
 877         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 878
 879         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
 880         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 881         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
 882         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
 883         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
 884         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
 885         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
 886         reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
 887         adev->gfx.rlc.rlcg_reg_access_supported = true;
 888 }
 889
 890 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 891 {
 892         const struct cs_section_def *cs_data;
 893         int r;
 894
 895         adev->gfx.rlc.cs_data = gfx11_cs_data;
 896
 897         cs_data = adev->gfx.rlc.cs_data;
 898
 899         if (cs_data) {
 900                 /* init clear state block */
 901                 r = amdgpu_gfx_rlc_init_csb(adev);
 902                 if (r)
 903                         return r;
 904         }
 905
 906         /* init spm vmid with 0xf */
 907         if (adev->gfx.rlc.funcs->update_spm_vmid)
 908                 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
 909
 910         return 0;
 911 }
 912
 913 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev)
 914 {
 915         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 916         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 917         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
 918 }
 919
 920 static void gfx_v11_0_me_init(struct amdgpu_device *adev)
 921 {
 922         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 923
 924         amdgpu_gfx_graphics_queue_acquire(adev);
 925 }
 926
 927 static int gfx_v11_0_mec_init(struct amdgpu_device *adev)
 928 {
 929         int r;
 930         u32 *hpd;
 931         size_t mec_hpd_size;
 932
 933         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 934
 935         /* take ownership of the relevant compute queues */
 936         amdgpu_gfx_compute_queue_acquire(adev);
 937         mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
 938
 939         if (mec_hpd_size) {
 940                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 941                                               AMDGPU_GEM_DOMAIN_GTT,
 942                                               &adev->gfx.mec.hpd_eop_obj,
 943                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 944                                               (void **)&hpd);
 945                 if (r) {
 946                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 947                         gfx_v11_0_mec_fini(adev);
 948                         return r;
 949                 }
 950
 951                 memset(hpd, 0, mec_hpd_size);
 952
 953                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 954                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 955         }
 956
 957         return 0;
 958 }
 959
 960 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
 961 {
 962         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 963                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 964                 (address << SQ_IND_INDEX__INDEX__SHIFT));
 965         return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 966 }
 967
 968 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
 969                            uint32_t thread, uint32_t regno,
 970                            uint32_t num, uint32_t *out)
 971 {
 972         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 973                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 974                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 975                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
 976                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 977         while (num--)
 978                 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 979 }
 980
 981 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 982 {
 983         /* in gfx11 the SIMD_ID is specified as part of the INSTANCE
 984          * field when performing a select_se_sh so it should be
 985          * zero here */
 986         WARN_ON(simd != 0);
 987
 988         /* type 3 wave data */
 989         dst[(*no_fields)++] = 3;
 990         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
 991         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
 992         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
 993         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
 994         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
 995         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
 996         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
 997         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
 998         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
 999         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1000         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1001         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1002         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1003         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1004         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
1005 }
1006
1007 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
1008                                      uint32_t wave, uint32_t start,
1009                                      uint32_t size, uint32_t *dst)
1010 {
1011         WARN_ON(simd != 0);
1012
1013         wave_read_regs(
1014                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1015                 dst);
1016 }
1017
1018 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
1019                                       uint32_t wave, uint32_t thread,
1020                                       uint32_t start, uint32_t size,
1021                                       uint32_t *dst)
1022 {
1023         wave_read_regs(
1024                 adev, wave, thread,
1025                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1026 }
1027
1028 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
1029                                         u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
1030 {
1031         soc21_grbm_select(adev, me, pipe, q, vm);
1032 }
1033
1034 /* all sizes are in bytes */
1035 #define MQD_SHADOW_BASE_SIZE      73728
1036 #define MQD_SHADOW_BASE_ALIGNMENT 256
1037 #define MQD_FWWORKAREA_SIZE       484
1038 #define MQD_FWWORKAREA_ALIGNMENT  256
1039
1040 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
1041                                          struct amdgpu_gfx_shadow_info *shadow_info)
1042 {
1043         if (adev->gfx.cp_gfx_shadow) {
1044                 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
1045                 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
1046                 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
1047                 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
1048                 return 0;
1049         } else {
1050                 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
1051                 return -ENOTSUPP;
1052         }
1053 }
1054
1055 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
1056         .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
1057         .select_se_sh = &gfx_v11_0_select_se_sh,
1058         .read_wave_data = &gfx_v11_0_read_wave_data,
1059         .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
1060         .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
1061         .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
1062         .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
1063         .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info,
1064 };
1065
1066 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
1067 {
1068         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1069         case IP_VERSION(11, 0, 0):
1070         case IP_VERSION(11, 0, 2):
1071                 adev->gfx.config.max_hw_contexts = 8;
1072                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1073                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1074                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1075                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1076                 break;
1077         case IP_VERSION(11, 0, 3):
1078                 adev->gfx.ras = &gfx_v11_0_3_ras;
1079                 adev->gfx.config.max_hw_contexts = 8;
1080                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1081                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1082                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1083                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1084                 break;
1085         case IP_VERSION(11, 0, 1):
1086         case IP_VERSION(11, 0, 4):
1087         case IP_VERSION(11, 5, 0):
1088         case IP_VERSION(11, 5, 1):
1089         case IP_VERSION(11, 5, 2):
1090                 adev->gfx.config.max_hw_contexts = 8;
1091                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1092                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1093                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
1094                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
1095                 break;
1096         default:
1097                 BUG();
1098                 break;
1099         }
1100
1101         return 0;
1102 }
1103
1104 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1105                                    int me, int pipe, int queue)
1106 {
1107         struct amdgpu_ring *ring;
1108         unsigned int irq_type;
1109         unsigned int hw_prio;
1110
1111         ring = &adev->gfx.gfx_ring[ring_id];
1112
1113         ring->me = me;
1114         ring->pipe = pipe;
1115         ring->queue = queue;
1116
1117         ring->ring_obj = NULL;
1118         ring->use_doorbell = true;
1119
1120         if (!ring_id)
1121                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1122         else
1123                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1124         ring->vm_hub = AMDGPU_GFXHUB(0);
1125         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1126
1127         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1128         hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
1129                 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1130         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1131                                 hw_prio, NULL);
1132 }
1133
1134 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1135                                        int mec, int pipe, int queue)
1136 {
1137         int r;
1138         unsigned irq_type;
1139         struct amdgpu_ring *ring;
1140         unsigned int hw_prio;
1141
1142         ring = &adev->gfx.compute_ring[ring_id];
1143
1144         /* mec0 is me1 */
1145         ring->me = mec + 1;
1146         ring->pipe = pipe;
1147         ring->queue = queue;
1148
1149         ring->ring_obj = NULL;
1150         ring->use_doorbell = true;
1151         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1152         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1153                                 + (ring_id * GFX11_MEC_HPD_SIZE);
1154         ring->vm_hub = AMDGPU_GFXHUB(0);
1155         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1156
1157         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1158                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1159                 + ring->pipe;
1160         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1161                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1162         /* type-2 packets are deprecated on MEC, use type-3 instead */
1163         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1164                              hw_prio, NULL);
1165         if (r)
1166                 return r;
1167
1168         return 0;
1169 }
1170
1171 static struct {
1172         SOC21_FIRMWARE_ID       id;
1173         unsigned int            offset;
1174         unsigned int            size;
1175 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX];
1176
1177 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1178 {
1179         RLC_TABLE_OF_CONTENT *ucode = rlc_toc;
1180
1181         while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) &&
1182                         (ucode->id < SOC21_FIRMWARE_ID_MAX)) {
1183                 rlc_autoload_info[ucode->id].id = ucode->id;
1184                 rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
1185                 rlc_autoload_info[ucode->id].size = ucode->size * 4;
1186
1187                 ucode++;
1188         }
1189 }
1190
1191 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)
1192 {
1193         uint32_t total_size = 0;
1194         SOC21_FIRMWARE_ID id;
1195
1196         gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1197
1198         for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++)
1199                 total_size += rlc_autoload_info[id].size;
1200
1201         /* In case the offset in rlc toc ucode is aligned */
1202         if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
1203                 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
1204                         rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size;
1205
1206         return total_size;
1207 }
1208
1209 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1210 {
1211         int r;
1212         uint32_t total_size;
1213
1214         total_size = gfx_v11_0_calc_toc_total_size(adev);
1215
1216         r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1217                                       AMDGPU_GEM_DOMAIN_VRAM |
1218                                       AMDGPU_GEM_DOMAIN_GTT,
1219                                       &adev->gfx.rlc.rlc_autoload_bo,
1220                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
1221                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1222
1223         if (r) {
1224                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1225                 return r;
1226         }
1227
1228         return 0;
1229 }
1230
1231 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1232                                               SOC21_FIRMWARE_ID id,
1233                                               const void *fw_data,
1234                                               uint32_t fw_size,
1235                                               uint32_t *fw_autoload_mask)
1236 {
1237         uint32_t toc_offset;
1238         uint32_t toc_fw_size;
1239         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1240
1241         if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX)
1242                 return;
1243
1244         toc_offset = rlc_autoload_info[id].offset;
1245         toc_fw_size = rlc_autoload_info[id].size;
1246
1247         if (fw_size == 0)
1248                 fw_size = toc_fw_size;
1249
1250         if (fw_size > toc_fw_size)
1251                 fw_size = toc_fw_size;
1252
1253         memcpy(ptr + toc_offset, fw_data, fw_size);
1254
1255         if (fw_size < toc_fw_size)
1256                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1257
1258         if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME))
1259                 *(uint64_t *)fw_autoload_mask |= 1ULL << id;
1260 }
1261
1262 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev,
1263                                                         uint32_t *fw_autoload_mask)
1264 {
1265         void *data;
1266         uint32_t size;
1267         uint64_t *toc_ptr;
1268
1269         *(uint64_t *)fw_autoload_mask |= 0x1;
1270
1271         DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);
1272
1273         data = adev->psp.toc.start_addr;
1274         size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size;
1275
1276         toc_ptr = (uint64_t *)data + size / 8 - 1;
1277         *toc_ptr = *(uint64_t *)fw_autoload_mask;
1278
1279         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC,
1280                                         data, size, fw_autoload_mask);
1281 }
1282
1283 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev,
1284                                                         uint32_t *fw_autoload_mask)
1285 {
1286         const __le32 *fw_data;
1287         uint32_t fw_size;
1288         const struct gfx_firmware_header_v1_0 *cp_hdr;
1289         const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1290         const struct rlc_firmware_header_v2_0 *rlc_hdr;
1291         const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1292         uint16_t version_major, version_minor;
1293
1294         if (adev->gfx.rs64_enable) {
1295                 /* pfp ucode */
1296                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1297                         adev->gfx.pfp_fw->data;
1298                 /* instruction */
1299                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1300                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1301                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1302                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP,
1303                                                 fw_data, fw_size, fw_autoload_mask);
1304                 /* data */
1305                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1306                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1307                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1308                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK,
1309                                                 fw_data, fw_size, fw_autoload_mask);
1310                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK,
1311                                                 fw_data, fw_size, fw_autoload_mask);
1312                 /* me ucode */
1313                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1314                         adev->gfx.me_fw->data;
1315                 /* instruction */
1316                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1317                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1318                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1319                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME,
1320                                                 fw_data, fw_size, fw_autoload_mask);
1321                 /* data */
1322                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1323                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1324                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1325                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK,
1326                                                 fw_data, fw_size, fw_autoload_mask);
1327                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK,
1328                                                 fw_data, fw_size, fw_autoload_mask);
1329                 /* mec ucode */
1330                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1331                         adev->gfx.mec_fw->data;
1332                 /* instruction */
1333                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1334                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1335                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1336                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC,
1337                                                 fw_data, fw_size, fw_autoload_mask);
1338                 /* data */
1339                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1340                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1341                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1342                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK,
1343                                                 fw_data, fw_size, fw_autoload_mask);
1344                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK,
1345                                                 fw_data, fw_size, fw_autoload_mask);
1346                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK,
1347                                                 fw_data, fw_size, fw_autoload_mask);
1348                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK,
1349                                                 fw_data, fw_size, fw_autoload_mask);
1350         } else {
1351                 /* pfp ucode */
1352                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1353                         adev->gfx.pfp_fw->data;
1354                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1355                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1356                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1357                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP,
1358                                                 fw_data, fw_size, fw_autoload_mask);
1359
1360                 /* me ucode */
1361                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1362                         adev->gfx.me_fw->data;
1363                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1364                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1365                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1366                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME,
1367                                                 fw_data, fw_size, fw_autoload_mask);
1368
1369                 /* mec ucode */
1370                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1371                         adev->gfx.mec_fw->data;
1372                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1373                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1374                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1375                         cp_hdr->jt_size * 4;
1376                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC,
1377                                                 fw_data, fw_size, fw_autoload_mask);
1378         }
1379
1380         /* rlc ucode */
1381         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1382                 adev->gfx.rlc_fw->data;
1383         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1384                         le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1385         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1386         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE,
1387                                         fw_data, fw_size, fw_autoload_mask);
1388
1389         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1390         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1391         if (version_major == 2) {
1392                 if (version_minor >= 2) {
1393                         rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1394
1395                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1396                                         le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1397                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1398                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE,
1399                                         fw_data, fw_size, fw_autoload_mask);
1400
1401                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1402                                         le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1403                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1404                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT,
1405                                         fw_data, fw_size, fw_autoload_mask);
1406                 }
1407         }
1408 }
1409
1410 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev,
1411                                                         uint32_t *fw_autoload_mask)
1412 {
1413         const __le32 *fw_data;
1414         uint32_t fw_size;
1415         const struct sdma_firmware_header_v2_0 *sdma_hdr;
1416
1417         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
1418                 adev->sdma.instance[0].fw->data;
1419         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1420                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
1421         fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
1422
1423         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1424                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask);
1425
1426         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1427                         le32_to_cpu(sdma_hdr->ctl_ucode_offset));
1428         fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
1429
1430         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1431                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask);
1432 }
1433
1434 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev,
1435                                                         uint32_t *fw_autoload_mask)
1436 {
1437         const __le32 *fw_data;
1438         unsigned fw_size;
1439         const struct mes_firmware_header_v1_0 *mes_hdr;
1440         int pipe, ucode_id, data_id;
1441
1442         for (pipe = 0; pipe < 2; pipe++) {
1443                 if (pipe==0) {
1444                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
1445                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
1446                 } else {
1447                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1;
1448                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK;
1449                 }
1450
1451                 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1452                         adev->mes.fw[pipe]->data;
1453
1454                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1455                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1456                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1457
1458                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1459                                 ucode_id, fw_data, fw_size, fw_autoload_mask);
1460
1461                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1462                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1463                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1464
1465                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1466                                 data_id, fw_data, fw_size, fw_autoload_mask);
1467         }
1468 }
1469
1470 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1471 {
1472         uint32_t rlc_g_offset, rlc_g_size;
1473         uint64_t gpu_addr;
1474         uint32_t autoload_fw_id[2];
1475
1476         memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);
1477
1478         /* RLC autoload sequence 2: copy ucode */
1479         gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id);
1480         gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id);
1481         gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id);
1482         gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id);
1483
1484         rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
1485         rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size;
1486         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1487
1488         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1489         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1490
1491         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1492
1493         /* RLC autoload sequence 3: load IMU fw */
1494         if (adev->gfx.imu.funcs->load_microcode)
1495                 adev->gfx.imu.funcs->load_microcode(adev);
1496         /* RLC autoload sequence 4 init IMU fw */
1497         if (adev->gfx.imu.funcs->setup_imu)
1498                 adev->gfx.imu.funcs->setup_imu(adev);
1499         if (adev->gfx.imu.funcs->start_imu)
1500                 adev->gfx.imu.funcs->start_imu(adev);
1501
1502         /* RLC autoload sequence 5 disable gpa mode */
1503         gfx_v11_0_disable_gpa_mode(adev);
1504
1505         return 0;
1506 }
1507
1508 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev)
1509 {
1510         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);
1511         uint32_t *ptr;
1512         uint32_t inst;
1513
1514         ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
1515         if (!ptr) {
1516                 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
1517                 adev->gfx.ip_dump_core = NULL;
1518         } else {
1519                 adev->gfx.ip_dump_core = ptr;
1520         }
1521
1522         /* Allocate memory for compute queue registers for all the instances */
1523         reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
1524         inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
1525                 adev->gfx.mec.num_queue_per_pipe;
1526
1527         ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1528         if (!ptr) {
1529                 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
1530                 adev->gfx.ip_dump_compute_queues = NULL;
1531         } else {
1532                 adev->gfx.ip_dump_compute_queues = ptr;
1533         }
1534
1535         /* Allocate memory for gfx queue registers for all the instances */
1536         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);
1537         inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
1538                 adev->gfx.me.num_queue_per_pipe;
1539
1540         ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1541         if (!ptr) {
1542                 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
1543                 adev->gfx.ip_dump_gfx_queues = NULL;
1544         } else {
1545                 adev->gfx.ip_dump_gfx_queues = ptr;
1546         }
1547 }
1548
1549 static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
1550 {
1551         int i, j, k, r, ring_id = 0;
1552         int xcc_id = 0;
1553         struct amdgpu_device *adev = ip_block->adev;
1554
1555         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1556         case IP_VERSION(11, 0, 0):
1557         case IP_VERSION(11, 0, 2):
1558         case IP_VERSION(11, 0, 3):
1559                 adev->gfx.me.num_me = 1;
1560                 adev->gfx.me.num_pipe_per_me = 1;
1561                 adev->gfx.me.num_queue_per_pipe = 1;
1562                 adev->gfx.mec.num_mec = 2;
1563                 adev->gfx.mec.num_pipe_per_mec = 4;
1564                 adev->gfx.mec.num_queue_per_pipe = 4;
1565                 break;
1566         case IP_VERSION(11, 0, 1):
1567         case IP_VERSION(11, 0, 4):
1568         case IP_VERSION(11, 5, 0):
1569         case IP_VERSION(11, 5, 1):
1570         case IP_VERSION(11, 5, 2):
1571                 adev->gfx.me.num_me = 1;
1572                 adev->gfx.me.num_pipe_per_me = 1;
1573                 adev->gfx.me.num_queue_per_pipe = 1;
1574                 adev->gfx.mec.num_mec = 1;
1575                 adev->gfx.mec.num_pipe_per_mec = 4;
1576                 adev->gfx.mec.num_queue_per_pipe = 4;
1577                 break;
1578         default:
1579                 adev->gfx.me.num_me = 1;
1580                 adev->gfx.me.num_pipe_per_me = 1;
1581                 adev->gfx.me.num_queue_per_pipe = 1;
1582                 adev->gfx.mec.num_mec = 1;
1583                 adev->gfx.mec.num_pipe_per_mec = 4;
1584                 adev->gfx.mec.num_queue_per_pipe = 8;
1585                 break;
1586         }
1587
1588         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1589         case IP_VERSION(11, 0, 0):
1590         case IP_VERSION(11, 0, 2):
1591         case IP_VERSION(11, 0, 3):
1592                 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex;
1593                 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex);
1594                 if (adev->gfx.me_fw_version  >= 2280 &&
1595                     adev->gfx.pfp_fw_version >= 2370 &&
1596                     adev->gfx.mec_fw_version >= 2450  &&
1597                     adev->mes.fw_version[0] >= 99) {
1598                         adev->gfx.enable_cleaner_shader = true;
1599                         r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
1600                         if (r) {
1601                                 adev->gfx.enable_cleaner_shader = false;
1602                                 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
1603                         }
1604                 }
1605                 break;
1606         default:
1607                 adev->gfx.enable_cleaner_shader = false;
1608                 break;
1609         }
1610
1611         /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */
1612         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) &&
1613             amdgpu_sriov_is_pp_one_vf(adev))
1614                 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG;
1615
1616         /* EOP Event */
1617         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1618                               GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1619                               &adev->gfx.eop_irq);
1620         if (r)
1621                 return r;
1622
1623         /* Bad opcode Event */
1624         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1625                               GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR,
1626                               &adev->gfx.bad_op_irq);
1627         if (r)
1628                 return r;
1629
1630         /* Privileged reg */
1631         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1632                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1633                               &adev->gfx.priv_reg_irq);
1634         if (r)
1635                 return r;
1636
1637         /* Privileged inst */
1638         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1639                               GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1640                               &adev->gfx.priv_inst_irq);
1641         if (r)
1642                 return r;
1643
1644         /* FED error */
1645         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1646                                   GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
1647                                   &adev->gfx.rlc_gc_fed_irq);
1648         if (r)
1649                 return r;
1650
1651         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1652
1653         gfx_v11_0_me_init(adev);
1654
1655         r = gfx_v11_0_rlc_init(adev);
1656         if (r) {
1657                 DRM_ERROR("Failed to init rlc BOs!\n");
1658                 return r;
1659         }
1660
1661         r = gfx_v11_0_mec_init(adev);
1662         if (r) {
1663                 DRM_ERROR("Failed to init MEC BOs!\n");
1664                 return r;
1665         }
1666
1667         /* set up the gfx ring */
1668         for (i = 0; i < adev->gfx.me.num_me; i++) {
1669                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1670                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1671                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1672                                         continue;
1673
1674                                 r = gfx_v11_0_gfx_ring_init(adev, ring_id,
1675                                                             i, k, j);
1676                                 if (r)
1677                                         return r;
1678                                 ring_id++;
1679                         }
1680                 }
1681         }
1682
1683         ring_id = 0;
1684         /* set up the compute queues - allocate horizontally across pipes */
1685         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1686                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1687                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1688                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
1689                                                                      k, j))
1690                                         continue;
1691
1692                                 r = gfx_v11_0_compute_ring_init(adev, ring_id,
1693                                                                 i, k, j);
1694                                 if (r)
1695                                         return r;
1696
1697                                 ring_id++;
1698                         }
1699                 }
1700         }
1701
1702         adev->gfx.gfx_supported_reset =
1703                 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
1704         adev->gfx.compute_supported_reset =
1705                 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
1706         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1707         case IP_VERSION(11, 0, 0):
1708         case IP_VERSION(11, 0, 2):
1709         case IP_VERSION(11, 0, 3):
1710                 if ((adev->gfx.me_fw_version >= 2280) &&
1711                             (adev->gfx.mec_fw_version >= 2410)) {
1712                                 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1713                                 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1714                 }
1715                 break;
1716         default:
1717                 break;
1718         }
1719
1720         if (!adev->enable_mes_kiq) {
1721                 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0);
1722                 if (r) {
1723                         DRM_ERROR("Failed to init KIQ BOs!\n");
1724                         return r;
1725                 }
1726
1727                 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
1728                 if (r)
1729                         return r;
1730         }
1731
1732         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0);
1733         if (r)
1734                 return r;
1735
1736         /* allocate visible FB for rlc auto-loading fw */
1737         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1738                 r = gfx_v11_0_rlc_autoload_buffer_init(adev);
1739                 if (r)
1740                         return r;
1741         }
1742
1743         r = gfx_v11_0_gpu_early_init(adev);
1744         if (r)
1745                 return r;
1746
1747         if (amdgpu_gfx_ras_sw_init(adev)) {
1748                 dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
1749                 return -EINVAL;
1750         }
1751
1752         gfx_v11_0_alloc_ip_dump(adev);
1753
1754         r = amdgpu_gfx_sysfs_init(adev);
1755         if (r)
1756                 return r;
1757
1758         return 0;
1759 }
1760
1761 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev)
1762 {
1763         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1764                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1765                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1766
1767         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1768                               &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1769                               (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1770 }
1771
1772 static void gfx_v11_0_me_fini(struct amdgpu_device *adev)
1773 {
1774         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1775                               &adev->gfx.me.me_fw_gpu_addr,
1776                               (void **)&adev->gfx.me.me_fw_ptr);
1777
1778         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1779                                &adev->gfx.me.me_fw_data_gpu_addr,
1780                                (void **)&adev->gfx.me.me_fw_data_ptr);
1781 }
1782
1783 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1784 {
1785         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1786                         &adev->gfx.rlc.rlc_autoload_gpu_addr,
1787                         (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1788 }
1789
1790 static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
1791 {
1792         int i;
1793         struct amdgpu_device *adev = ip_block->adev;
1794
1795         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1796                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1797         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1798                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1799
1800         amdgpu_gfx_mqd_sw_fini(adev, 0);
1801
1802         if (!adev->enable_mes_kiq) {
1803                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1804                 amdgpu_gfx_kiq_fini(adev, 0);
1805         }
1806
1807         amdgpu_gfx_cleaner_shader_sw_fini(adev);
1808
1809         gfx_v11_0_pfp_fini(adev);
1810         gfx_v11_0_me_fini(adev);
1811         gfx_v11_0_rlc_fini(adev);
1812         gfx_v11_0_mec_fini(adev);
1813
1814         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1815                 gfx_v11_0_rlc_autoload_buffer_fini(adev);
1816
1817         gfx_v11_0_free_microcode(adev);
1818
1819         amdgpu_gfx_sysfs_fini(adev);
1820
1821         kfree(adev->gfx.ip_dump_core);
1822         kfree(adev->gfx.ip_dump_compute_queues);
1823         kfree(adev->gfx.ip_dump_gfx_queues);
1824
1825         return 0;
1826 }
1827
1828 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1829                                    u32 sh_num, u32 instance, int xcc_id)
1830 {
1831         u32 data;
1832
1833         if (instance == 0xffffffff)
1834                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1835                                      INSTANCE_BROADCAST_WRITES, 1);
1836         else
1837                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1838                                      instance);
1839
1840         if (se_num == 0xffffffff)
1841                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1842                                      1);
1843         else
1844                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1845
1846         if (sh_num == 0xffffffff)
1847                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1848                                      1);
1849         else
1850                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1851
1852         WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1853 }
1854
1855 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1856 {
1857         u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1858
1859         gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);
1860         gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1861                                            CC_GC_SA_UNIT_DISABLE,
1862                                            SA_DISABLE);
1863         gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);
1864         gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1865                                                  GC_USER_SA_UNIT_DISABLE,
1866                                                  SA_DISABLE);
1867         sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1868                                             adev->gfx.config.max_shader_engines);
1869
1870         return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1871 }
1872
1873 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1874 {
1875         u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1876         u32 rb_mask;
1877
1878         gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1879         gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1880                                             CC_RB_BACKEND_DISABLE,
1881                                             BACKEND_DISABLE);
1882         gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1883         gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1884                                                  GC_USER_RB_BACKEND_DISABLE,
1885                                                  BACKEND_DISABLE);
1886         rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1887                                             adev->gfx.config.max_shader_engines);
1888
1889         return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1890 }
1891
1892 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
1893 {
1894         u32 rb_bitmap_width_per_sa;
1895         u32 max_sa;
1896         u32 active_sa_bitmap;
1897         u32 global_active_rb_bitmap;
1898         u32 active_rb_bitmap = 0;
1899         u32 i;
1900
1901         /* query sa bitmap from SA_UNIT_DISABLE registers */
1902         active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev);
1903         /* query rb bitmap from RB_BACKEND_DISABLE registers */
1904         global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev);
1905
1906         /* generate active rb bitmap according to active sa bitmap */
1907         max_sa = adev->gfx.config.max_shader_engines *
1908                  adev->gfx.config.max_sh_per_se;
1909         rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1910                                  adev->gfx.config.max_sh_per_se;
1911         for (i = 0; i < max_sa; i++) {
1912                 if (active_sa_bitmap & (1 << i))
1913                         active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));
1914         }
1915
1916         active_rb_bitmap &= global_active_rb_bitmap;
1917         adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1918         adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1919 }
1920
1921 #define DEFAULT_SH_MEM_BASES    (0x6000)
1922 #define LDS_APP_BASE           0x1
1923 #define SCRATCH_APP_BASE       0x2
1924
1925 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
1926 {
1927         int i;
1928         uint32_t sh_mem_bases;
1929         uint32_t data;
1930
1931         /*
1932          * Configure apertures:
1933          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1934          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1935          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1936          */
1937         sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1938                         SCRATCH_APP_BASE;
1939
1940         mutex_lock(&adev->srbm_mutex);
1941         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1942                 soc21_grbm_select(adev, 0, 0, 0, i);
1943                 /* CP and shaders */
1944                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1945                 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1946
1947                 /* Enable trap for each kfd vmid. */
1948                 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1949                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1950                 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1951         }
1952         soc21_grbm_select(adev, 0, 0, 0, 0);
1953         mutex_unlock(&adev->srbm_mutex);
1954
1955         /*
1956          * Initialize all compute VMIDs to have no GDS, GWS, or OA
1957          * access. These should be enabled by FW for target VMIDs.
1958          */
1959         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1960                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
1961                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
1962                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
1963                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
1964         }
1965 }
1966
1967 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev)
1968 {
1969         int vmid;
1970
1971         /*
1972          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1973          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1974          * the driver can enable them for graphics. VMID0 should maintain
1975          * access so that HWS firmware can save/restore entries.
1976          */
1977         for (vmid = 1; vmid < 16; vmid++) {
1978                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
1979                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
1980                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
1981                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
1982         }
1983 }
1984
1985 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev)
1986 {
1987         /* TODO: harvest feature to be added later. */
1988 }
1989
1990 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev)
1991 {
1992         /* TCCs are global (not instanced). */
1993         uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |
1994                                RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);
1995
1996         adev->gfx.config.tcc_disabled_mask =
1997                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1998                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1999 }
2000
2001 static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
2002 {
2003         u32 tmp;
2004         int i;
2005
2006         if (!amdgpu_sriov_vf(adev))
2007                 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
2008
2009         gfx_v11_0_setup_rb(adev);
2010         gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
2011         gfx_v11_0_get_tcc_info(adev);
2012         adev->gfx.config.pa_sc_tile_steering_override = 0;
2013
2014         /* Set whether texture coordinate truncation is conformant. */
2015         tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);
2016         adev->gfx.config.ta_cntl2_truncate_coord_mode =
2017                 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
2018
2019         /* XXX SH_MEM regs */
2020         /* where to put LDS, scratch, GPUVM in FSA64 space */
2021         mutex_lock(&adev->srbm_mutex);
2022         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
2023                 soc21_grbm_select(adev, 0, 0, 0, i);
2024                 /* CP and shaders */
2025                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
2026                 if (i != 0) {
2027                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
2028                                 (adev->gmc.private_aperture_start >> 48));
2029                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
2030                                 (adev->gmc.shared_aperture_start >> 48));
2031                         WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
2032                 }
2033         }
2034         soc21_grbm_select(adev, 0, 0, 0, 0);
2035
2036         mutex_unlock(&adev->srbm_mutex);
2037
2038         gfx_v11_0_init_compute_vmid(adev);
2039         gfx_v11_0_init_gds_vmid(adev);
2040 }
2041
2042 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev,
2043                                       int me, int pipe)
2044 {
2045         if (me != 0)
2046                 return 0;
2047
2048         switch (pipe) {
2049         case 0:
2050                 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
2051         case 1:
2052                 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
2053         default:
2054                 return 0;
2055         }
2056 }
2057
2058 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev,
2059                                       int me, int pipe)
2060 {
2061         /*
2062          * amdgpu controls only the first MEC. That's why this function only
2063          * handles the setting of interrupts for this specific MEC. All other
2064          * pipes' interrupts are set by amdkfd.
2065          */
2066         if (me != 1)
2067                 return 0;
2068
2069         switch (pipe) {
2070         case 0:
2071                 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
2072         case 1:
2073                 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
2074         case 2:
2075                 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
2076         case 3:
2077                 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
2078         default:
2079                 return 0;
2080         }
2081 }
2082
2083 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2084                                                bool enable)
2085 {
2086         u32 tmp, cp_int_cntl_reg;
2087         int i, j;
2088
2089         if (amdgpu_sriov_vf(adev))
2090                 return;
2091
2092         for (i = 0; i < adev->gfx.me.num_me; i++) {
2093                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
2094                         cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
2095
2096                         if (cp_int_cntl_reg) {
2097                                 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
2098                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
2099                                                     enable ? 1 : 0);
2100                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
2101                                                     enable ? 1 : 0);
2102                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
2103                                                     enable ? 1 : 0);
2104                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
2105                                                     enable ? 1 : 0);
2106                                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
2107                         }
2108                 }
2109         }
2110 }
2111
2112 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
2113 {
2114         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
2115
2116         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
2117                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
2118         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
2119                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
2120         WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
2121
2122         return 0;
2123 }
2124
2125 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
2126 {
2127         u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
2128
2129         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2130         WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
2131 }
2132
2133 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev)
2134 {
2135         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2136         udelay(50);
2137         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2138         udelay(50);
2139 }
2140
2141 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
2142                                              bool enable)
2143 {
2144         uint32_t rlc_pg_cntl;
2145
2146         rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
2147
2148         if (!enable) {
2149                 /* RLC_PG_CNTL[23] = 0 (default)
2150                  * RLC will wait for handshake acks with SMU
2151                  * GFXOFF will be enabled
2152                  * RLC_PG_CNTL[23] = 1
2153                  * RLC will not issue any message to SMU
2154                  * hence no handshake between SMU & RLC
2155                  * GFXOFF will be disabled
2156                  */
2157                 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
2158         } else
2159                 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
2160         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
2161 }
2162
2163 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev)
2164 {
2165         /* TODO: enable rlc & smu handshake until smu
2166          * and gfxoff feature works as expected */
2167         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
2168                 gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
2169
2170         WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2171         udelay(50);
2172 }
2173
2174 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev)
2175 {
2176         uint32_t tmp;
2177
2178         /* enable Save Restore Machine */
2179         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
2180         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2181         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
2182         WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
2183 }
2184
2185 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev)
2186 {
2187         const struct rlc_firmware_header_v2_0 *hdr;
2188         const __le32 *fw_data;
2189         unsigned i, fw_size;
2190
2191         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2192         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2193                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2194         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2195
2196         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
2197                      RLCG_UCODE_LOADING_START_ADDRESS);
2198
2199         for (i = 0; i < fw_size; i++)
2200                 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
2201                              le32_to_cpup(fw_data++));
2202
2203         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2204 }
2205
2206 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
2207 {
2208         const struct rlc_firmware_header_v2_2 *hdr;
2209         const __le32 *fw_data;
2210         unsigned i, fw_size;
2211         u32 tmp;
2212
2213         hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
2214
2215         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2216                         le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
2217         fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
2218
2219         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
2220
2221         for (i = 0; i < fw_size; i++) {
2222                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2223                         msleep(1);
2224                 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
2225                                 le32_to_cpup(fw_data++));
2226         }
2227
2228         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2229
2230         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2231                         le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
2232         fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
2233
2234         WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
2235         for (i = 0; i < fw_size; i++) {
2236                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2237                         msleep(1);
2238                 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
2239                                 le32_to_cpup(fw_data++));
2240         }
2241
2242         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2243
2244         tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
2245         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
2246         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
2247         WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
2248 }
2249
2250 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev)
2251 {
2252         const struct rlc_firmware_header_v2_3 *hdr;
2253         const __le32 *fw_data;
2254         unsigned i, fw_size;
2255         u32 tmp;
2256
2257         hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
2258
2259         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2260                         le32_to_cpu(hdr->rlcp_ucode_offset_bytes));
2261         fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4;
2262
2263         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);
2264
2265         for (i = 0; i < fw_size; i++) {
2266                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2267                         msleep(1);
2268                 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,
2269                                 le32_to_cpup(fw_data++));
2270         }
2271
2272         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
2273
2274         tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
2275         tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
2276         WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
2277
2278         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2279                         le32_to_cpu(hdr->rlcv_ucode_offset_bytes));
2280         fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4;
2281
2282         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);
2283
2284         for (i = 0; i < fw_size; i++) {
2285                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2286                         msleep(1);
2287                 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,
2288                                 le32_to_cpup(fw_data++));
2289         }
2290
2291         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
2292
2293         tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
2294         tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
2295         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
2296 }
2297
2298 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
2299 {
2300         const struct rlc_firmware_header_v2_0 *hdr;
2301         uint16_t version_major;
2302         uint16_t version_minor;
2303
2304         if (!adev->gfx.rlc_fw)
2305                 return -EINVAL;
2306
2307         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2308         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2309
2310         version_major = le16_to_cpu(hdr->header.header_version_major);
2311         version_minor = le16_to_cpu(hdr->header.header_version_minor);
2312
2313         if (version_major == 2) {
2314                 gfx_v11_0_load_rlcg_microcode(adev);
2315                 if (amdgpu_dpm == 1) {
2316                         if (version_minor >= 2)
2317                                 gfx_v11_0_load_rlc_iram_dram_microcode(adev);
2318                         if (version_minor == 3)
2319                                 gfx_v11_0_load_rlcp_rlcv_microcode(adev);
2320                 }
2321
2322                 return 0;
2323         }
2324
2325         return -EINVAL;
2326 }
2327
2328 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
2329 {
2330         int r;
2331
2332         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2333                 gfx_v11_0_init_csb(adev);
2334
2335                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2336                         gfx_v11_0_rlc_enable_srm(adev);
2337         } else {
2338                 if (amdgpu_sriov_vf(adev)) {
2339                         gfx_v11_0_init_csb(adev);
2340                         return 0;
2341                 }
2342
2343                 adev->gfx.rlc.funcs->stop(adev);
2344
2345                 /* disable CG */
2346                 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2347
2348                 /* disable PG */
2349                 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2350
2351                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2352                         /* legacy rlc firmware loading */
2353                         r = gfx_v11_0_rlc_load_microcode(adev);
2354                         if (r)
2355                                 return r;
2356                 }
2357
2358                 gfx_v11_0_init_csb(adev);
2359
2360                 adev->gfx.rlc.funcs->start(adev);
2361         }
2362         return 0;
2363 }
2364
2365 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
2366 {
2367         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2368         uint32_t tmp;
2369         int i;
2370
2371         /* Trigger an invalidation of the L1 instruction caches */
2372         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2373         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2374         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2375
2376         /* Wait for invalidation complete */
2377         for (i = 0; i < usec_timeout; i++) {
2378                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2379                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2380                                         INVALIDATE_CACHE_COMPLETE))
2381                         break;
2382                 udelay(1);
2383         }
2384
2385         if (i >= usec_timeout) {
2386                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2387                 return -EINVAL;
2388         }
2389
2390         if (amdgpu_emu_mode == 1)
2391                 adev->hdp.funcs->flush_hdp(adev, NULL);
2392
2393         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2394         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2395         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2396         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2397         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2398         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2399
2400         /* Program me ucode address into intruction cache address register */
2401         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2402                         lower_32_bits(addr) & 0xFFFFF000);
2403         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2404                         upper_32_bits(addr));
2405
2406         return 0;
2407 }
2408
2409 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
2410 {
2411         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2412         uint32_t tmp;
2413         int i;
2414
2415         /* Trigger an invalidation of the L1 instruction caches */
2416         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2417         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2418         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2419
2420         /* Wait for invalidation complete */
2421         for (i = 0; i < usec_timeout; i++) {
2422                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2423                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2424                                         INVALIDATE_CACHE_COMPLETE))
2425                         break;
2426                 udelay(1);
2427         }
2428
2429         if (i >= usec_timeout) {
2430                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2431                 return -EINVAL;
2432         }
2433
2434         if (amdgpu_emu_mode == 1)
2435                 adev->hdp.funcs->flush_hdp(adev, NULL);
2436
2437         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2438         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2439         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2440         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2441         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2442         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2443
2444         /* Program pfp ucode address into intruction cache address register */
2445         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2446                         lower_32_bits(addr) & 0xFFFFF000);
2447         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2448                         upper_32_bits(addr));
2449
2450         return 0;
2451 }
2452
2453 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
2454 {
2455         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2456         uint32_t tmp;
2457         int i;
2458
2459         /* Trigger an invalidation of the L1 instruction caches */
2460         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2461         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2462
2463         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2464
2465         /* Wait for invalidation complete */
2466         for (i = 0; i < usec_timeout; i++) {
2467                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2468                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2469                                         INVALIDATE_CACHE_COMPLETE))
2470                         break;
2471                 udelay(1);
2472         }
2473
2474         if (i >= usec_timeout) {
2475                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2476                 return -EINVAL;
2477         }
2478
2479         if (amdgpu_emu_mode == 1)
2480                 adev->hdp.funcs->flush_hdp(adev, NULL);
2481
2482         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2483         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2484         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2485         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2486         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2487
2488         /* Program mec1 ucode address into intruction cache address register */
2489         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2490                         lower_32_bits(addr) & 0xFFFFF000);
2491         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2492                         upper_32_bits(addr));
2493
2494         return 0;
2495 }
2496
2497 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2498 {
2499         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2500         uint32_t tmp;
2501         unsigned i, pipe_id;
2502         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2503
2504         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2505                 adev->gfx.pfp_fw->data;
2506
2507         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2508                 lower_32_bits(addr));
2509         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2510                 upper_32_bits(addr));
2511
2512         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2513         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2514         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2515         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2516         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2517
2518         /*
2519          * Programming any of the CP_PFP_IC_BASE registers
2520          * forces invalidation of the ME L1 I$. Wait for the
2521          * invalidation complete
2522          */
2523         for (i = 0; i < usec_timeout; i++) {
2524                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2525                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2526                         INVALIDATE_CACHE_COMPLETE))
2527                         break;
2528                 udelay(1);
2529         }
2530
2531         if (i >= usec_timeout) {
2532                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2533                 return -EINVAL;
2534         }
2535
2536         /* Prime the L1 instruction caches */
2537         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2538         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2539         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2540         /* Waiting for cache primed*/
2541         for (i = 0; i < usec_timeout; i++) {
2542                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2543                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2544                         ICACHE_PRIMED))
2545                         break;
2546                 udelay(1);
2547         }
2548
2549         if (i >= usec_timeout) {
2550                 dev_err(adev->dev, "failed to prime instruction cache\n");
2551                 return -EINVAL;
2552         }
2553
2554         mutex_lock(&adev->srbm_mutex);
2555         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2556                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2557                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2558                         (pfp_hdr->ucode_start_addr_hi << 30) |
2559                         (pfp_hdr->ucode_start_addr_lo >> 2));
2560                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2561                         pfp_hdr->ucode_start_addr_hi >> 2);
2562
2563                 /*
2564                  * Program CP_ME_CNTL to reset given PIPE to take
2565                  * effect of CP_PFP_PRGRM_CNTR_START.
2566                  */
2567                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2568                 if (pipe_id == 0)
2569                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2570                                         PFP_PIPE0_RESET, 1);
2571                 else
2572                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2573                                         PFP_PIPE1_RESET, 1);
2574                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2575
2576                 /* Clear pfp pipe0 reset bit. */
2577                 if (pipe_id == 0)
2578                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2579                                         PFP_PIPE0_RESET, 0);
2580                 else
2581                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2582                                         PFP_PIPE1_RESET, 0);
2583                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2584
2585                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2586                         lower_32_bits(addr2));
2587                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2588                         upper_32_bits(addr2));
2589         }
2590         soc21_grbm_select(adev, 0, 0, 0, 0);
2591         mutex_unlock(&adev->srbm_mutex);
2592
2593         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2594         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2595         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2596         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2597
2598         /* Invalidate the data caches */
2599         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2600         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2601         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2602
2603         for (i = 0; i < usec_timeout; i++) {
2604                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2605                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2606                         INVALIDATE_DCACHE_COMPLETE))
2607                         break;
2608                 udelay(1);
2609         }
2610
2611         if (i >= usec_timeout) {
2612                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2613                 return -EINVAL;
2614         }
2615
2616         return 0;
2617 }
2618
2619 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2620 {
2621         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2622         uint32_t tmp;
2623         unsigned i, pipe_id;
2624         const struct gfx_firmware_header_v2_0 *me_hdr;
2625
2626         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2627                 adev->gfx.me_fw->data;
2628
2629         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2630                 lower_32_bits(addr));
2631         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2632                 upper_32_bits(addr));
2633
2634         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2635         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2636         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2637         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2638         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2639
2640         /*
2641          * Programming any of the CP_ME_IC_BASE registers
2642          * forces invalidation of the ME L1 I$. Wait for the
2643          * invalidation complete
2644          */
2645         for (i = 0; i < usec_timeout; i++) {
2646                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2647                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2648                         INVALIDATE_CACHE_COMPLETE))
2649                         break;
2650                 udelay(1);
2651         }
2652
2653         if (i >= usec_timeout) {
2654                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2655                 return -EINVAL;
2656         }
2657
2658         /* Prime the instruction caches */
2659         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2660         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2661         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2662
2663         /* Waiting for instruction cache primed*/
2664         for (i = 0; i < usec_timeout; i++) {
2665                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2666                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2667                         ICACHE_PRIMED))
2668                         break;
2669                 udelay(1);
2670         }
2671
2672         if (i >= usec_timeout) {
2673                 dev_err(adev->dev, "failed to prime instruction cache\n");
2674                 return -EINVAL;
2675         }
2676
2677         mutex_lock(&adev->srbm_mutex);
2678         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2679                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2680                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2681                         (me_hdr->ucode_start_addr_hi << 30) |
2682                         (me_hdr->ucode_start_addr_lo >> 2) );
2683                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2684                         me_hdr->ucode_start_addr_hi>>2);
2685
2686                 /*
2687                  * Program CP_ME_CNTL to reset given PIPE to take
2688                  * effect of CP_PFP_PRGRM_CNTR_START.
2689                  */
2690                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2691                 if (pipe_id == 0)
2692                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2693                                         ME_PIPE0_RESET, 1);
2694                 else
2695                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2696                                         ME_PIPE1_RESET, 1);
2697                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2698
2699                 /* Clear pfp pipe0 reset bit. */
2700                 if (pipe_id == 0)
2701                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2702                                         ME_PIPE0_RESET, 0);
2703                 else
2704                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2705                                         ME_PIPE1_RESET, 0);
2706                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2707
2708                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2709                         lower_32_bits(addr2));
2710                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2711                         upper_32_bits(addr2));
2712         }
2713         soc21_grbm_select(adev, 0, 0, 0, 0);
2714         mutex_unlock(&adev->srbm_mutex);
2715
2716         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2717         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2718         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2719         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2720
2721         /* Invalidate the data caches */
2722         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2723         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2724         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2725
2726         for (i = 0; i < usec_timeout; i++) {
2727                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2728                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2729                         INVALIDATE_DCACHE_COMPLETE))
2730                         break;
2731                 udelay(1);
2732         }
2733
2734         if (i >= usec_timeout) {
2735                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2736                 return -EINVAL;
2737         }
2738
2739         return 0;
2740 }
2741
2742 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2743 {
2744         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2745         uint32_t tmp;
2746         unsigned i;
2747         const struct gfx_firmware_header_v2_0 *mec_hdr;
2748
2749         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2750                 adev->gfx.mec_fw->data;
2751
2752         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2753         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2754         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2755         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2756         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2757
2758         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2759         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2760         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2761         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2762
2763         mutex_lock(&adev->srbm_mutex);
2764         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2765                 soc21_grbm_select(adev, 1, i, 0, 0);
2766
2767                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);
2768                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2769                      upper_32_bits(addr2));
2770
2771                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2772                                         mec_hdr->ucode_start_addr_lo >> 2 |
2773                                         mec_hdr->ucode_start_addr_hi << 30);
2774                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2775                                         mec_hdr->ucode_start_addr_hi >> 2);
2776
2777                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);
2778                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2779                      upper_32_bits(addr));
2780         }
2781         mutex_unlock(&adev->srbm_mutex);
2782         soc21_grbm_select(adev, 0, 0, 0, 0);
2783
2784         /* Trigger an invalidation of the L1 instruction caches */
2785         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2786         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2787         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2788
2789         /* Wait for invalidation complete */
2790         for (i = 0; i < usec_timeout; i++) {
2791                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2792                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2793                                        INVALIDATE_DCACHE_COMPLETE))
2794                         break;
2795                 udelay(1);
2796         }
2797
2798         if (i >= usec_timeout) {
2799                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2800                 return -EINVAL;
2801         }
2802
2803         /* Trigger an invalidation of the L1 instruction caches */
2804         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2805         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2806         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2807
2808         /* Wait for invalidation complete */
2809         for (i = 0; i < usec_timeout; i++) {
2810                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2811                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2812                                        INVALIDATE_CACHE_COMPLETE))
2813                         break;
2814                 udelay(1);
2815         }
2816
2817         if (i >= usec_timeout) {
2818                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2819                 return -EINVAL;
2820         }
2821
2822         return 0;
2823 }
2824
2825 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
2826 {
2827         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2828         const struct gfx_firmware_header_v2_0 *me_hdr;
2829         const struct gfx_firmware_header_v2_0 *mec_hdr;
2830         uint32_t pipe_id, tmp;
2831
2832         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2833                 adev->gfx.mec_fw->data;
2834         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2835                 adev->gfx.me_fw->data;
2836         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2837                 adev->gfx.pfp_fw->data;
2838
2839         /* config pfp program start addr */
2840         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2841                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2842                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2843                         (pfp_hdr->ucode_start_addr_hi << 30) |
2844                         (pfp_hdr->ucode_start_addr_lo >> 2));
2845                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2846                         pfp_hdr->ucode_start_addr_hi >> 2);
2847         }
2848         soc21_grbm_select(adev, 0, 0, 0, 0);
2849
2850         /* reset pfp pipe */
2851         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2852         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2853         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2854         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2855
2856         /* clear pfp pipe reset */
2857         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2858         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2859         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2860
2861         /* config me program start addr */
2862         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2863                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2864                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2865                         (me_hdr->ucode_start_addr_hi << 30) |
2866                         (me_hdr->ucode_start_addr_lo >> 2) );
2867                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2868                         me_hdr->ucode_start_addr_hi>>2);
2869         }
2870         soc21_grbm_select(adev, 0, 0, 0, 0);
2871
2872         /* reset me pipe */
2873         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2874         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2875         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2876         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2877
2878         /* clear me pipe reset */
2879         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2880         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2881         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2882
2883         /* config mec program start addr */
2884         for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2885                 soc21_grbm_select(adev, 1, pipe_id, 0, 0);
2886                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2887                                         mec_hdr->ucode_start_addr_lo >> 2 |
2888                                         mec_hdr->ucode_start_addr_hi << 30);
2889                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2890                                         mec_hdr->ucode_start_addr_hi >> 2);
2891         }
2892         soc21_grbm_select(adev, 0, 0, 0, 0);
2893
2894         /* reset mec pipe */
2895         tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2896         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2897         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2898         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2899         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2900         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2901
2902         /* clear mec pipe reset */
2903         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2904         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2905         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2906         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2907         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2908 }
2909
2910 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2911 {
2912         uint32_t cp_status;
2913         uint32_t bootload_status;
2914         int i, r;
2915         uint64_t addr, addr2;
2916
2917         for (i = 0; i < adev->usec_timeout; i++) {
2918                 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2919
2920                 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
2921                             IP_VERSION(11, 0, 1) ||
2922                     amdgpu_ip_version(adev, GC_HWIP, 0) ==
2923                             IP_VERSION(11, 0, 4) ||
2924                     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) ||
2925                     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) ||
2926                     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2))
2927                         bootload_status = RREG32_SOC15(GC, 0,
2928                                         regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
2929                 else
2930                         bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2931
2932                 if ((cp_status == 0) &&
2933                     (REG_GET_FIELD(bootload_status,
2934                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2935                         break;
2936                 }
2937                 udelay(1);
2938         }
2939
2940         if (i >= adev->usec_timeout) {
2941                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2942                 return -ETIMEDOUT;
2943         }
2944
2945         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2946                 if (adev->gfx.rs64_enable) {
2947                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2948                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2949                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2950                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2951                         r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2);
2952                         if (r)
2953                                 return r;
2954                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2955                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2956                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2957                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2958                         r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2);
2959                         if (r)
2960                                 return r;
2961                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2962                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2963                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2964                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2965                         r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2);
2966                         if (r)
2967                                 return r;
2968                 } else {
2969                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2970                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2971                         r = gfx_v11_0_config_me_cache(adev, addr);
2972                         if (r)
2973                                 return r;
2974                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2975                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2976                         r = gfx_v11_0_config_pfp_cache(adev, addr);
2977                         if (r)
2978                                 return r;
2979                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2980                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
2981                         r = gfx_v11_0_config_mec_cache(adev, addr);
2982                         if (r)
2983                                 return r;
2984                 }
2985         }
2986
2987         return 0;
2988 }
2989
2990 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2991 {
2992         int i;
2993         u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2994
2995         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2996         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2997         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2998
2999         for (i = 0; i < adev->usec_timeout; i++) {
3000                 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
3001                         break;
3002                 udelay(1);
3003         }
3004
3005         if (i >= adev->usec_timeout)
3006                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
3007
3008         return 0;
3009 }
3010
3011 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
3012 {
3013         int r;
3014         const struct gfx_firmware_header_v1_0 *pfp_hdr;
3015         const __le32 *fw_data;
3016         unsigned i, fw_size;
3017
3018         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
3019                 adev->gfx.pfp_fw->data;
3020
3021         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3022
3023         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
3024                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3025         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
3026
3027         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
3028                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3029                                       &adev->gfx.pfp.pfp_fw_obj,
3030                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
3031                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
3032         if (r) {
3033                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
3034                 gfx_v11_0_pfp_fini(adev);
3035                 return r;
3036         }
3037
3038         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
3039
3040         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
3041         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
3042
3043         gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
3044
3045         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);
3046
3047         for (i = 0; i < pfp_hdr->jt_size; i++)
3048                 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,
3049                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
3050
3051         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3052
3053         return 0;
3054 }
3055
3056 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
3057 {
3058         int r;
3059         const struct gfx_firmware_header_v2_0 *pfp_hdr;
3060         const __le32 *fw_ucode, *fw_data;
3061         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
3062         uint32_t tmp;
3063         uint32_t usec_timeout = 50000;  /* wait for 50ms */
3064
3065         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
3066                 adev->gfx.pfp_fw->data;
3067
3068         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3069
3070         /* instruction */
3071         fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
3072                 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
3073         fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
3074         /* data */
3075         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
3076                 le32_to_cpu(pfp_hdr->data_offset_bytes));
3077         fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
3078
3079         /* 64kb align */
3080         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3081                                       64 * 1024,
3082                                       AMDGPU_GEM_DOMAIN_VRAM |
3083                                       AMDGPU_GEM_DOMAIN_GTT,
3084                                       &adev->gfx.pfp.pfp_fw_obj,
3085                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
3086                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
3087         if (r) {
3088                 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
3089                 gfx_v11_0_pfp_fini(adev);
3090                 return r;
3091         }
3092
3093         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3094                                       64 * 1024,
3095                                       AMDGPU_GEM_DOMAIN_VRAM |
3096                                       AMDGPU_GEM_DOMAIN_GTT,
3097                                       &adev->gfx.pfp.pfp_fw_data_obj,
3098                                       &adev->gfx.pfp.pfp_fw_data_gpu_addr,
3099                                       (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
3100         if (r) {
3101                 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
3102                 gfx_v11_0_pfp_fini(adev);
3103                 return r;
3104         }
3105
3106         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
3107         memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
3108
3109         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
3110         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
3111         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
3112         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
3113
3114         if (amdgpu_emu_mode == 1)
3115                 adev->hdp.funcs->flush_hdp(adev, NULL);
3116
3117         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
3118                 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
3119         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
3120                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
3121
3122         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
3123         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
3124         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
3125         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
3126         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
3127
3128         /*
3129          * Programming any of the CP_PFP_IC_BASE registers
3130          * forces invalidation of the ME L1 I$. Wait for the
3131          * invalidation complete
3132          */
3133         for (i = 0; i < usec_timeout; i++) {
3134                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
3135                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
3136                         INVALIDATE_CACHE_COMPLETE))
3137                         break;
3138                 udelay(1);
3139         }
3140
3141         if (i >= usec_timeout) {
3142                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3143                 return -EINVAL;
3144         }
3145
3146         /* Prime the L1 instruction caches */
3147         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
3148         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
3149         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
3150         /* Waiting for cache primed*/
3151         for (i = 0; i < usec_timeout; i++) {
3152                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
3153                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
3154                         ICACHE_PRIMED))
3155                         break;
3156                 udelay(1);
3157         }
3158
3159         if (i >= usec_timeout) {
3160                 dev_err(adev->dev, "failed to prime instruction cache\n");
3161                 return -EINVAL;
3162         }
3163
3164         mutex_lock(&adev->srbm_mutex);
3165         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
3166                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
3167                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
3168                         (pfp_hdr->ucode_start_addr_hi << 30) |
3169                         (pfp_hdr->ucode_start_addr_lo >> 2) );
3170                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
3171                         pfp_hdr->ucode_start_addr_hi>>2);
3172
3173                 /*
3174                  * Program CP_ME_CNTL to reset given PIPE to take
3175                  * effect of CP_PFP_PRGRM_CNTR_START.
3176                  */
3177                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
3178                 if (pipe_id == 0)
3179                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3180                                         PFP_PIPE0_RESET, 1);
3181                 else
3182                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3183                                         PFP_PIPE1_RESET, 1);
3184                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3185
3186                 /* Clear pfp pipe0 reset bit. */
3187                 if (pipe_id == 0)
3188                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3189                                         PFP_PIPE0_RESET, 0);
3190                 else
3191                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3192                                         PFP_PIPE1_RESET, 0);
3193                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3194
3195                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
3196                         lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
3197                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
3198                         upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
3199         }
3200         soc21_grbm_select(adev, 0, 0, 0, 0);
3201         mutex_unlock(&adev->srbm_mutex);
3202
3203         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
3204         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
3205         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
3206         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
3207
3208         /* Invalidate the data caches */
3209         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3210         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3211         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
3212
3213         for (i = 0; i < usec_timeout; i++) {
3214                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3215                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
3216                         INVALIDATE_DCACHE_COMPLETE))
3217                         break;
3218                 udelay(1);
3219         }
3220
3221         if (i >= usec_timeout) {
3222                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
3223                 return -EINVAL;
3224         }
3225
3226         return 0;
3227 }
3228
3229 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
3230 {
3231         int r;
3232         const struct gfx_firmware_header_v1_0 *me_hdr;
3233         const __le32 *fw_data;
3234         unsigned i, fw_size;
3235
3236         me_hdr = (const struct gfx_firmware_header_v1_0 *)
3237                 adev->gfx.me_fw->data;
3238
3239         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
3240
3241         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
3242                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3243         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
3244
3245         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
3246                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3247                                       &adev->gfx.me.me_fw_obj,
3248                                       &adev->gfx.me.me_fw_gpu_addr,
3249                                       (void **)&adev->gfx.me.me_fw_ptr);
3250         if (r) {
3251                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
3252                 gfx_v11_0_me_fini(adev);
3253                 return r;
3254         }
3255
3256         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
3257
3258         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
3259         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
3260
3261         gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
3262
3263         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);
3264
3265         for (i = 0; i < me_hdr->jt_size; i++)
3266                 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,
3267                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
3268
3269         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
3270
3271         return 0;
3272 }
3273
3274 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
3275 {
3276         int r;
3277         const struct gfx_firmware_header_v2_0 *me_hdr;
3278         const __le32 *fw_ucode, *fw_data;
3279         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
3280         uint32_t tmp;
3281         uint32_t usec_timeout = 50000;  /* wait for 50ms */
3282
3283         me_hdr = (const struct gfx_firmware_header_v2_0 *)
3284                 adev->gfx.me_fw->data;
3285
3286         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
3287
3288         /* instruction */
3289         fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
3290                 le32_to_cpu(me_hdr->ucode_offset_bytes));
3291         fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
3292         /* data */
3293         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
3294                 le32_to_cpu(me_hdr->data_offset_bytes));
3295         fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
3296
3297         /* 64kb align*/
3298         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3299                                       64 * 1024,
3300                                       AMDGPU_GEM_DOMAIN_VRAM |
3301                                       AMDGPU_GEM_DOMAIN_GTT,
3302                                       &adev->gfx.me.me_fw_obj,
3303                                       &adev->gfx.me.me_fw_gpu_addr,
3304                                       (void **)&adev->gfx.me.me_fw_ptr);
3305         if (r) {
3306                 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
3307                 gfx_v11_0_me_fini(adev);
3308                 return r;
3309         }
3310
3311         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3312                                       64 * 1024,
3313                                       AMDGPU_GEM_DOMAIN_VRAM |
3314                                       AMDGPU_GEM_DOMAIN_GTT,
3315                                       &adev->gfx.me.me_fw_data_obj,
3316                                       &adev->gfx.me.me_fw_data_gpu_addr,
3317                                       (void **)&adev->gfx.me.me_fw_data_ptr);
3318         if (r) {
3319                 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
3320                 gfx_v11_0_pfp_fini(adev);
3321                 return r;
3322         }
3323
3324         memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
3325         memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
3326
3327         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
3328         amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
3329         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
3330         amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
3331
3332         if (amdgpu_emu_mode == 1)
3333                 adev->hdp.funcs->flush_hdp(adev, NULL);
3334
3335         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
3336                 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
3337         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
3338                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
3339
3340         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
3341         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
3342         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
3343         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
3344         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
3345
3346         /*
3347          * Programming any of the CP_ME_IC_BASE registers
3348          * forces invalidation of the ME L1 I$. Wait for the
3349          * invalidation complete
3350          */
3351         for (i = 0; i < usec_timeout; i++) {
3352                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3353                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3354                         INVALIDATE_CACHE_COMPLETE))
3355                         break;
3356                 udelay(1);
3357         }
3358
3359         if (i >= usec_timeout) {
3360                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3361                 return -EINVAL;
3362         }
3363
3364         /* Prime the instruction caches */
3365         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3366         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
3367         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
3368
3369         /* Waiting for instruction cache primed*/
3370         for (i = 0; i < usec_timeout; i++) {
3371                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3372                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3373                         ICACHE_PRIMED))
3374                         break;
3375                 udelay(1);
3376         }
3377
3378         if (i >= usec_timeout) {
3379                 dev_err(adev->dev, "failed to prime instruction cache\n");
3380                 return -EINVAL;
3381         }
3382
3383         mutex_lock(&adev->srbm_mutex);
3384         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
3385                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
3386                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
3387                         (me_hdr->ucode_start_addr_hi << 30) |
3388                         (me_hdr->ucode_start_addr_lo >> 2) );
3389                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
3390                         me_hdr->ucode_start_addr_hi>>2);
3391
3392                 /*
3393                  * Program CP_ME_CNTL to reset given PIPE to take
3394                  * effect of CP_PFP_PRGRM_CNTR_START.
3395                  */
3396                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
3397                 if (pipe_id == 0)
3398                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3399                                         ME_PIPE0_RESET, 1);
3400                 else
3401                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3402                                         ME_PIPE1_RESET, 1);
3403                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3404
3405                 /* Clear pfp pipe0 reset bit. */
3406                 if (pipe_id == 0)
3407                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3408                                         ME_PIPE0_RESET, 0);
3409                 else
3410                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3411                                         ME_PIPE1_RESET, 0);
3412                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3413
3414                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
3415                         lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3416                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
3417                         upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3418         }
3419         soc21_grbm_select(adev, 0, 0, 0, 0);
3420         mutex_unlock(&adev->srbm_mutex);
3421
3422         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
3423         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
3424         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
3425         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
3426
3427         /* Invalidate the data caches */
3428         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3429         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3430         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
3431
3432         for (i = 0; i < usec_timeout; i++) {
3433                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3434                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
3435                         INVALIDATE_DCACHE_COMPLETE))
3436                         break;
3437                 udelay(1);
3438         }
3439
3440         if (i >= usec_timeout) {
3441                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
3442                 return -EINVAL;
3443         }
3444
3445         return 0;
3446 }
3447
3448 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3449 {
3450         int r;
3451
3452         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3453                 return -EINVAL;
3454
3455         gfx_v11_0_cp_gfx_enable(adev, false);
3456
3457         if (adev->gfx.rs64_enable)
3458                 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev);
3459         else
3460                 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev);
3461         if (r) {
3462                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
3463                 return r;
3464         }
3465
3466         if (adev->gfx.rs64_enable)
3467                 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev);
3468         else
3469                 r = gfx_v11_0_cp_gfx_load_me_microcode(adev);
3470         if (r) {
3471                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
3472                 return r;
3473         }
3474
3475         return 0;
3476 }
3477
3478 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev)
3479 {
3480         struct amdgpu_ring *ring;
3481         const struct cs_section_def *sect = NULL;
3482         const struct cs_extent_def *ext = NULL;
3483         int r, i;
3484         int ctx_reg_offset;
3485
3486         /* init the CP */
3487         WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
3488                      adev->gfx.config.max_hw_contexts - 1);
3489         WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
3490
3491         if (!amdgpu_async_gfx_ring)
3492                 gfx_v11_0_cp_gfx_enable(adev, true);
3493
3494         ring = &adev->gfx.gfx_ring[0];
3495         r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev));
3496         if (r) {
3497                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3498                 return r;
3499         }
3500
3501         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3502         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3503
3504         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3505         amdgpu_ring_write(ring, 0x80000000);
3506         amdgpu_ring_write(ring, 0x80000000);
3507
3508         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
3509                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3510                         if (sect->id == SECT_CONTEXT) {
3511                                 amdgpu_ring_write(ring,
3512                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
3513                                                           ext->reg_count));
3514                                 amdgpu_ring_write(ring, ext->reg_index -
3515                                                   PACKET3_SET_CONTEXT_REG_START);
3516                                 for (i = 0; i < ext->reg_count; i++)
3517                                         amdgpu_ring_write(ring, ext->extent[i]);
3518                         }
3519                 }
3520         }
3521
3522         ctx_reg_offset =
3523                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3524         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3525         amdgpu_ring_write(ring, ctx_reg_offset);
3526         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3527
3528         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3529         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3530
3531         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3532         amdgpu_ring_write(ring, 0);
3533
3534         amdgpu_ring_commit(ring);
3535
3536         /* submit cs packet to copy state 0 to next available state */
3537         if (adev->gfx.num_gfx_rings > 1) {
3538                 /* maximum supported gfx ring is 2 */
3539                 ring = &adev->gfx.gfx_ring[1];
3540                 r = amdgpu_ring_alloc(ring, 2);
3541                 if (r) {
3542                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3543                         return r;
3544                 }
3545
3546                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3547                 amdgpu_ring_write(ring, 0);
3548
3549                 amdgpu_ring_commit(ring);
3550         }
3551         return 0;
3552 }
3553
3554 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
3555                                          CP_PIPE_ID pipe)
3556 {
3557         u32 tmp;
3558
3559         tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
3560         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
3561
3562         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
3563 }
3564
3565 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
3566                                           struct amdgpu_ring *ring)
3567 {
3568         u32 tmp;
3569
3570         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3571         if (ring->use_doorbell) {
3572                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3573                                     DOORBELL_OFFSET, ring->doorbell_index);
3574                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3575                                     DOORBELL_EN, 1);
3576         } else {
3577                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3578                                     DOORBELL_EN, 0);
3579         }
3580         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
3581
3582         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3583                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
3584         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
3585
3586         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3587                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3588 }
3589
3590 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
3591 {
3592         struct amdgpu_ring *ring;
3593         u32 tmp;
3594         u32 rb_bufsz;
3595         u64 rb_addr, rptr_addr, wptr_gpu_addr;
3596
3597         /* Set the write pointer delay */
3598         WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
3599
3600         /* set the RB to use vmid 0 */
3601         WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
3602
3603         /* Init gfx ring 0 for pipe 0 */
3604         mutex_lock(&adev->srbm_mutex);
3605         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3606
3607         /* Set ring buffer size */
3608         ring = &adev->gfx.gfx_ring[0];
3609         rb_bufsz = order_base_2(ring->ring_size / 8);
3610         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3611         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3612         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3613
3614         /* Initialize the ring buffer's write pointers */
3615         ring->wptr = 0;
3616         WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
3617         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3618
3619         /* set the wb address whether it's enabled or not */
3620         rptr_addr = ring->rptr_gpu_addr;
3621         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3622         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3623                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3624
3625         wptr_gpu_addr = ring->wptr_gpu_addr;
3626         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3627                      lower_32_bits(wptr_gpu_addr));
3628         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3629                      upper_32_bits(wptr_gpu_addr));
3630
3631         mdelay(1);
3632         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3633
3634         rb_addr = ring->gpu_addr >> 8;
3635         WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
3636         WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3637
3638         WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
3639
3640         gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3641         mutex_unlock(&adev->srbm_mutex);
3642
3643         /* Init gfx ring 1 for pipe 1 */
3644         if (adev->gfx.num_gfx_rings > 1) {
3645                 mutex_lock(&adev->srbm_mutex);
3646                 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
3647                 /* maximum supported gfx ring is 2 */
3648                 ring = &adev->gfx.gfx_ring[1];
3649                 rb_bufsz = order_base_2(ring->ring_size / 8);
3650                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
3651                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
3652                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3653                 /* Initialize the ring buffer's write pointers */
3654                 ring->wptr = 0;
3655                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
3656                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
3657                 /* Set the wb address whether it's enabled or not */
3658                 rptr_addr = ring->rptr_gpu_addr;
3659                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
3660                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3661                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3662                 wptr_gpu_addr = ring->wptr_gpu_addr;
3663                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3664                              lower_32_bits(wptr_gpu_addr));
3665                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3666                              upper_32_bits(wptr_gpu_addr));
3667
3668                 mdelay(1);
3669                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3670
3671                 rb_addr = ring->gpu_addr >> 8;
3672                 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);
3673                 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));
3674                 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);
3675
3676                 gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3677                 mutex_unlock(&adev->srbm_mutex);
3678         }
3679         /* Switch to pipe 0 */
3680         mutex_lock(&adev->srbm_mutex);
3681         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3682         mutex_unlock(&adev->srbm_mutex);
3683
3684         /* start the ring */
3685         gfx_v11_0_cp_gfx_start(adev);
3686
3687         return 0;
3688 }
3689
3690 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3691 {
3692         u32 data;
3693
3694         if (adev->gfx.rs64_enable) {
3695                 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
3696                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
3697                                                          enable ? 0 : 1);
3698                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
3699                                                          enable ? 0 : 1);
3700                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
3701                                                          enable ? 0 : 1);
3702                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
3703                                                          enable ? 0 : 1);
3704                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
3705                                                          enable ? 0 : 1);
3706                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
3707                                                          enable ? 1 : 0);
3708                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
3709                                                          enable ? 1 : 0);
3710                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
3711                                                          enable ? 1 : 0);
3712                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
3713                                                          enable ? 1 : 0);
3714                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
3715                                                          enable ? 0 : 1);
3716                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
3717         } else {
3718                 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
3719
3720                 if (enable) {
3721                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3722                         if (!adev->enable_mes_kiq)
3723                                 data = REG_SET_FIELD(data, CP_MEC_CNTL,
3724                                                      MEC_ME2_HALT, 0);
3725                 } else {
3726                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3727                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
3728                 }
3729                 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
3730         }
3731
3732         udelay(50);
3733 }
3734
3735 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3736 {
3737         const struct gfx_firmware_header_v1_0 *mec_hdr;
3738         const __le32 *fw_data;
3739         unsigned i, fw_size;
3740         u32 *fw = NULL;
3741         int r;
3742
3743         if (!adev->gfx.mec_fw)
3744                 return -EINVAL;
3745
3746         gfx_v11_0_cp_compute_enable(adev, false);
3747
3748         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3749         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3750
3751         fw_data = (const __le32 *)
3752                 (adev->gfx.mec_fw->data +
3753                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3754         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3755
3756         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3757                                           PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3758                                           &adev->gfx.mec.mec_fw_obj,
3759                                           &adev->gfx.mec.mec_fw_gpu_addr,
3760                                           (void **)&fw);
3761         if (r) {
3762                 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3763                 gfx_v11_0_mec_fini(adev);
3764                 return r;
3765         }
3766
3767         memcpy(fw, fw_data, fw_size);
3768
3769         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3770         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3771
3772         gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3773
3774         /* MEC1 */
3775         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3776
3777         for (i = 0; i < mec_hdr->jt_size; i++)
3778                 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,
3779                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3780
3781         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3782
3783         return 0;
3784 }
3785
3786 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
3787 {
3788         const struct gfx_firmware_header_v2_0 *mec_hdr;
3789         const __le32 *fw_ucode, *fw_data;
3790         u32 tmp, fw_ucode_size, fw_data_size;
3791         u32 i, usec_timeout = 50000; /* Wait for 50 ms */
3792         u32 *fw_ucode_ptr, *fw_data_ptr;
3793         int r;
3794
3795         if (!adev->gfx.mec_fw)
3796                 return -EINVAL;
3797
3798         gfx_v11_0_cp_compute_enable(adev, false);
3799
3800         mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3801         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3802
3803         fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3804                                 le32_to_cpu(mec_hdr->ucode_offset_bytes));
3805         fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
3806
3807         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3808                                 le32_to_cpu(mec_hdr->data_offset_bytes));
3809         fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
3810
3811         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3812                                       64 * 1024,
3813                                       AMDGPU_GEM_DOMAIN_VRAM |
3814                                       AMDGPU_GEM_DOMAIN_GTT,
3815                                       &adev->gfx.mec.mec_fw_obj,
3816                                       &adev->gfx.mec.mec_fw_gpu_addr,
3817                                       (void **)&fw_ucode_ptr);
3818         if (r) {
3819                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3820                 gfx_v11_0_mec_fini(adev);
3821                 return r;
3822         }
3823
3824         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3825                                       64 * 1024,
3826                                       AMDGPU_GEM_DOMAIN_VRAM |
3827                                       AMDGPU_GEM_DOMAIN_GTT,
3828                                       &adev->gfx.mec.mec_fw_data_obj,
3829                                       &adev->gfx.mec.mec_fw_data_gpu_addr,
3830                                       (void **)&fw_data_ptr);
3831         if (r) {
3832                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3833                 gfx_v11_0_mec_fini(adev);
3834                 return r;
3835         }
3836
3837         memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
3838         memcpy(fw_data_ptr, fw_data, fw_data_size);
3839
3840         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3841         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3842         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3843         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3844
3845         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
3846         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3847         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
3848         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3849         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
3850
3851         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
3852         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
3853         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
3854         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
3855
3856         mutex_lock(&adev->srbm_mutex);
3857         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3858                 soc21_grbm_select(adev, 1, i, 0, 0);
3859
3860                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3861                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
3862                      upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3863
3864                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
3865                                         mec_hdr->ucode_start_addr_lo >> 2 |
3866                                         mec_hdr->ucode_start_addr_hi << 30);
3867                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
3868                                         mec_hdr->ucode_start_addr_hi >> 2);
3869
3870                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3871                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
3872                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3873         }
3874         mutex_unlock(&adev->srbm_mutex);
3875         soc21_grbm_select(adev, 0, 0, 0, 0);
3876
3877         /* Trigger an invalidation of the L1 instruction caches */
3878         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3879         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3880         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
3881
3882         /* Wait for invalidation complete */
3883         for (i = 0; i < usec_timeout; i++) {
3884                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3885                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
3886                                        INVALIDATE_DCACHE_COMPLETE))
3887                         break;
3888                 udelay(1);
3889         }
3890
3891         if (i >= usec_timeout) {
3892                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3893                 return -EINVAL;
3894         }
3895
3896         /* Trigger an invalidation of the L1 instruction caches */
3897         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3898         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
3899         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
3900
3901         /* Wait for invalidation complete */
3902         for (i = 0; i < usec_timeout; i++) {
3903                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3904                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
3905                                        INVALIDATE_CACHE_COMPLETE))
3906                         break;
3907                 udelay(1);
3908         }
3909
3910         if (i >= usec_timeout) {
3911                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3912                 return -EINVAL;
3913         }
3914
3915         return 0;
3916 }
3917
3918 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)
3919 {
3920         uint32_t tmp;
3921         struct amdgpu_device *adev = ring->adev;
3922
3923         /* tell RLC which is KIQ queue */
3924         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3925         tmp &= 0xffffff00;
3926         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3927         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
3928 }
3929
3930 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
3931 {
3932         /* set graphics engine doorbell range */
3933         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
3934                      (adev->doorbell_index.gfx_ring0 * 2) << 2);
3935         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3936                      (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
3937
3938         /* set compute engine doorbell range */
3939         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3940                      (adev->doorbell_index.kiq * 2) << 2);
3941         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3942                      (adev->doorbell_index.userqueue_end * 2) << 2);
3943 }
3944
3945 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
3946                                            struct v11_gfx_mqd *mqd,
3947                                            struct amdgpu_mqd_prop *prop)
3948 {
3949         bool priority = 0;
3950         u32 tmp;
3951
3952         /* set up default queue priority level
3953          * 0x0 = low priority, 0x1 = high priority
3954          */
3955         if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
3956                 priority = 1;
3957
3958         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3959         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
3960         mqd->cp_gfx_hqd_queue_priority = tmp;
3961 }
3962
3963 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
3964                                   struct amdgpu_mqd_prop *prop)
3965 {
3966         struct v11_gfx_mqd *mqd = m;
3967         uint64_t hqd_gpu_addr, wb_gpu_addr;
3968         uint32_t tmp;
3969         uint32_t rb_bufsz;
3970
3971         /* set up gfx hqd wptr */
3972         mqd->cp_gfx_hqd_wptr = 0;
3973         mqd->cp_gfx_hqd_wptr_hi = 0;
3974
3975         /* set the pointer to the MQD */
3976         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
3977         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3978
3979         /* set up mqd control */
3980         tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
3981         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
3982         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
3983         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
3984         mqd->cp_gfx_mqd_control = tmp;
3985
3986         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3987         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
3988         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3989         mqd->cp_gfx_hqd_vmid = 0;
3990
3991         /* set up gfx queue priority */
3992         gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop);
3993
3994         /* set up time quantum */
3995         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
3996         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3997         mqd->cp_gfx_hqd_quantum = tmp;
3998
3999         /* set up gfx hqd base. this is similar as CP_RB_BASE */
4000         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
4001         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
4002         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
4003
4004         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
4005         wb_gpu_addr = prop->rptr_gpu_addr;
4006         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
4007         mqd->cp_gfx_hqd_rptr_addr_hi =
4008                 upper_32_bits(wb_gpu_addr) & 0xffff;
4009
4010         /* set up rb_wptr_poll addr */
4011         wb_gpu_addr = prop->wptr_gpu_addr;
4012         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4013         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4014
4015         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
4016         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
4017         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
4018         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
4019         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
4020 #ifdef __BIG_ENDIAN
4021         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
4022 #endif
4023         mqd->cp_gfx_hqd_cntl = tmp;
4024
4025         /* set up cp_doorbell_control */
4026         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
4027         if (prop->use_doorbell) {
4028                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4029                                     DOORBELL_OFFSET, prop->doorbell_index);
4030                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4031                                     DOORBELL_EN, 1);
4032         } else
4033                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4034                                     DOORBELL_EN, 0);
4035         mqd->cp_rb_doorbell_control = tmp;
4036
4037         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4038         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
4039
4040         /* active the queue */
4041         mqd->cp_gfx_hqd_active = 1;
4042
4043         return 0;
4044 }
4045
4046 static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
4047 {
4048         struct amdgpu_device *adev = ring->adev;
4049         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
4050         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
4051
4052         if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
4053                 memset((void *)mqd, 0, sizeof(*mqd));
4054                 mutex_lock(&adev->srbm_mutex);
4055                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4056                 amdgpu_ring_init_mqd(ring);
4057                 soc21_grbm_select(adev, 0, 0, 0, 0);
4058                 mutex_unlock(&adev->srbm_mutex);
4059                 if (adev->gfx.me.mqd_backup[mqd_idx])
4060                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4061         } else {
4062                 /* restore mqd with the backup copy */
4063                 if (adev->gfx.me.mqd_backup[mqd_idx])
4064                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
4065                 /* reset the ring */
4066                 ring->wptr = 0;
4067                 *ring->wptr_cpu_addr = 0;
4068                 amdgpu_ring_clear_ring(ring);
4069         }
4070
4071         return 0;
4072 }
4073
4074 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
4075 {
4076         int r, i;
4077         struct amdgpu_ring *ring;
4078
4079         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4080                 ring = &adev->gfx.gfx_ring[i];
4081
4082                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4083                 if (unlikely(r != 0))
4084                         return r;
4085
4086                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4087                 if (!r) {
4088                         r = gfx_v11_0_kgq_init_queue(ring, false);
4089                         amdgpu_bo_kunmap(ring->mqd_obj);
4090                         ring->mqd_ptr = NULL;
4091                 }
4092                 amdgpu_bo_unreserve(ring->mqd_obj);
4093                 if (r)
4094                         return r;
4095         }
4096
4097         r = amdgpu_gfx_enable_kgq(adev, 0);
4098         if (r)
4099                 return r;
4100
4101         return gfx_v11_0_cp_gfx_start(adev);
4102 }
4103
4104 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
4105                                       struct amdgpu_mqd_prop *prop)
4106 {
4107         struct v11_compute_mqd *mqd = m;
4108         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4109         uint32_t tmp;
4110
4111         mqd->header = 0xC0310800;
4112         mqd->compute_pipelinestat_enable = 0x00000001;
4113         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4114         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4115         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4116         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4117         mqd->compute_misc_reserved = 0x00000007;
4118
4119         eop_base_addr = prop->eop_gpu_addr >> 8;
4120         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4121         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4122
4123         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4124         tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
4125         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4126                         (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
4127
4128         mqd->cp_hqd_eop_control = tmp;
4129
4130         /* enable doorbell? */
4131         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
4132
4133         if (prop->use_doorbell) {
4134                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4135                                     DOORBELL_OFFSET, prop->doorbell_index);
4136                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4137                                     DOORBELL_EN, 1);
4138                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4139                                     DOORBELL_SOURCE, 0);
4140                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4141                                     DOORBELL_HIT, 0);
4142         } else {
4143                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4144                                     DOORBELL_EN, 0);
4145         }
4146
4147         mqd->cp_hqd_pq_doorbell_control = tmp;
4148
4149         /* disable the queue if it's active */
4150         mqd->cp_hqd_dequeue_request = 0;
4151         mqd->cp_hqd_pq_rptr = 0;
4152         mqd->cp_hqd_pq_wptr_lo = 0;
4153         mqd->cp_hqd_pq_wptr_hi = 0;
4154
4155         /* set the pointer to the MQD */
4156         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
4157         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
4158
4159         /* set MQD vmid to 0 */
4160         tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
4161         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4162         mqd->cp_mqd_control = tmp;
4163
4164         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4165         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
4166         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4167         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4168
4169         /* set up the HQD, this is similar to CP_RB0_CNTL */
4170         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
4171         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4172                             (order_base_2(prop->queue_size / 4) - 1));
4173         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4174                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
4175         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
4176         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
4177                             prop->allow_tunneling);
4178         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4179         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4180         mqd->cp_hqd_pq_control = tmp;
4181
4182         /* set the wb address whether it's enabled or not */
4183         wb_gpu_addr = prop->rptr_gpu_addr;
4184         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4185         mqd->cp_hqd_pq_rptr_report_addr_hi =
4186                 upper_32_bits(wb_gpu_addr) & 0xffff;
4187
4188         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4189         wb_gpu_addr = prop->wptr_gpu_addr;
4190         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4191         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4192
4193         tmp = 0;
4194         /* enable the doorbell if requested */
4195         if (prop->use_doorbell) {
4196                 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
4197                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4198                                 DOORBELL_OFFSET, prop->doorbell_index);
4199
4200                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4201                                     DOORBELL_EN, 1);
4202                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4203                                     DOORBELL_SOURCE, 0);
4204                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4205                                     DOORBELL_HIT, 0);
4206         }
4207
4208         mqd->cp_hqd_pq_doorbell_control = tmp;
4209
4210         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4211         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
4212
4213         /* set the vmid for the queue */
4214         mqd->cp_hqd_vmid = 0;
4215
4216         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
4217         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
4218         mqd->cp_hqd_persistent_state = tmp;
4219
4220         /* set MIN_IB_AVAIL_SIZE */
4221         tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
4222         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4223         mqd->cp_hqd_ib_control = tmp;
4224
4225         /* set static priority for a compute queue/ring */
4226         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
4227         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
4228
4229         mqd->cp_hqd_active = prop->hqd_active;
4230
4231         return 0;
4232 }
4233
4234 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
4235 {
4236         struct amdgpu_device *adev = ring->adev;
4237         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4238         int j;
4239
4240         /* inactivate the queue */
4241         if (amdgpu_sriov_vf(adev))
4242                 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
4243
4244         /* disable wptr polling */
4245         WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
4246
4247         /* write the EOP addr */
4248         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
4249                mqd->cp_hqd_eop_base_addr_lo);
4250         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
4251                mqd->cp_hqd_eop_base_addr_hi);
4252
4253         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4254         WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
4255                mqd->cp_hqd_eop_control);
4256
4257         /* enable doorbell? */
4258         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
4259                mqd->cp_hqd_pq_doorbell_control);
4260
4261         /* disable the queue if it's active */
4262         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
4263                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
4264                 for (j = 0; j < adev->usec_timeout; j++) {
4265                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
4266                                 break;
4267                         udelay(1);
4268                 }
4269                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
4270                        mqd->cp_hqd_dequeue_request);
4271                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
4272                        mqd->cp_hqd_pq_rptr);
4273                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
4274                        mqd->cp_hqd_pq_wptr_lo);
4275                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
4276                        mqd->cp_hqd_pq_wptr_hi);
4277         }
4278
4279         /* set the pointer to the MQD */
4280         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
4281                mqd->cp_mqd_base_addr_lo);
4282         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
4283                mqd->cp_mqd_base_addr_hi);
4284
4285         /* set MQD vmid to 0 */
4286         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
4287                mqd->cp_mqd_control);
4288
4289         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4290         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
4291                mqd->cp_hqd_pq_base_lo);
4292         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
4293                mqd->cp_hqd_pq_base_hi);
4294
4295         /* set up the HQD, this is similar to CP_RB0_CNTL */
4296         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
4297                mqd->cp_hqd_pq_control);
4298
4299         /* set the wb address whether it's enabled or not */
4300         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
4301                 mqd->cp_hqd_pq_rptr_report_addr_lo);
4302         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4303                 mqd->cp_hqd_pq_rptr_report_addr_hi);
4304
4305         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4306         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
4307                mqd->cp_hqd_pq_wptr_poll_addr_lo);
4308         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
4309                mqd->cp_hqd_pq_wptr_poll_addr_hi);
4310
4311         /* enable the doorbell if requested */
4312         if (ring->use_doorbell) {
4313                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
4314                         (adev->doorbell_index.kiq * 2) << 2);
4315                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
4316                         (adev->doorbell_index.userqueue_end * 2) << 2);
4317         }
4318
4319         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
4320                mqd->cp_hqd_pq_doorbell_control);
4321
4322         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4323         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
4324                mqd->cp_hqd_pq_wptr_lo);
4325         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
4326                mqd->cp_hqd_pq_wptr_hi);
4327
4328         /* set the vmid for the queue */
4329         WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
4330
4331         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
4332                mqd->cp_hqd_persistent_state);
4333
4334         /* activate the queue */
4335         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
4336                mqd->cp_hqd_active);
4337
4338         if (ring->use_doorbell)
4339                 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4340
4341         return 0;
4342 }
4343
4344 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
4345 {
4346         struct amdgpu_device *adev = ring->adev;
4347         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4348
4349         gfx_v11_0_kiq_setting(ring);
4350
4351         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4352                 /* reset MQD to a clean status */
4353                 if (adev->gfx.kiq[0].mqd_backup)
4354                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
4355
4356                 /* reset ring buffer */
4357                 ring->wptr = 0;
4358                 amdgpu_ring_clear_ring(ring);
4359
4360                 mutex_lock(&adev->srbm_mutex);
4361                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4362                 gfx_v11_0_kiq_init_register(ring);
4363                 soc21_grbm_select(adev, 0, 0, 0, 0);
4364                 mutex_unlock(&adev->srbm_mutex);
4365         } else {
4366                 memset((void *)mqd, 0, sizeof(*mqd));
4367                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
4368                         amdgpu_ring_clear_ring(ring);
4369                 mutex_lock(&adev->srbm_mutex);
4370                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4371                 amdgpu_ring_init_mqd(ring);
4372                 gfx_v11_0_kiq_init_register(ring);
4373                 soc21_grbm_select(adev, 0, 0, 0, 0);
4374                 mutex_unlock(&adev->srbm_mutex);
4375
4376                 if (adev->gfx.kiq[0].mqd_backup)
4377                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
4378         }
4379
4380         return 0;
4381 }
4382
4383 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
4384 {
4385         struct amdgpu_device *adev = ring->adev;
4386         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4387         int mqd_idx = ring - &adev->gfx.compute_ring[0];
4388
4389         if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
4390                 memset((void *)mqd, 0, sizeof(*mqd));
4391                 mutex_lock(&adev->srbm_mutex);
4392                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4393                 amdgpu_ring_init_mqd(ring);
4394                 soc21_grbm_select(adev, 0, 0, 0, 0);
4395                 mutex_unlock(&adev->srbm_mutex);
4396
4397                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4398                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4399         } else {
4400                 /* restore MQD to a clean status */
4401                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4402                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4403                 /* reset ring buffer */
4404                 ring->wptr = 0;
4405                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
4406                 amdgpu_ring_clear_ring(ring);
4407         }
4408
4409         return 0;
4410 }
4411
4412 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4413 {
4414         struct amdgpu_ring *ring;
4415         int r;
4416
4417         ring = &adev->gfx.kiq[0].ring;
4418
4419         r = amdgpu_bo_reserve(ring->mqd_obj, false);
4420         if (unlikely(r != 0))
4421                 return r;
4422
4423         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4424         if (unlikely(r != 0)) {
4425                 amdgpu_bo_unreserve(ring->mqd_obj);
4426                 return r;
4427         }
4428
4429         gfx_v11_0_kiq_init_queue(ring);
4430         amdgpu_bo_kunmap(ring->mqd_obj);
4431         ring->mqd_ptr = NULL;
4432         amdgpu_bo_unreserve(ring->mqd_obj);
4433         ring->sched.ready = true;
4434         return 0;
4435 }
4436
4437 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4438 {
4439         struct amdgpu_ring *ring = NULL;
4440         int r = 0, i;
4441
4442         if (!amdgpu_async_gfx_ring)
4443                 gfx_v11_0_cp_compute_enable(adev, true);
4444
4445         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4446                 ring = &adev->gfx.compute_ring[i];
4447
4448                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4449                 if (unlikely(r != 0))
4450                         goto done;
4451                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4452                 if (!r) {
4453                         r = gfx_v11_0_kcq_init_queue(ring, false);
4454                         amdgpu_bo_kunmap(ring->mqd_obj);
4455                         ring->mqd_ptr = NULL;
4456                 }
4457                 amdgpu_bo_unreserve(ring->mqd_obj);
4458                 if (r)
4459                         goto done;
4460         }
4461
4462         r = amdgpu_gfx_enable_kcq(adev, 0);
4463 done:
4464         return r;
4465 }
4466
4467 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
4468 {
4469         int r, i;
4470         struct amdgpu_ring *ring;
4471
4472         if (!(adev->flags & AMD_IS_APU))
4473                 gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4474
4475         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4476                 /* legacy firmware loading */
4477                 r = gfx_v11_0_cp_gfx_load_microcode(adev);
4478                 if (r)
4479                         return r;
4480
4481                 if (adev->gfx.rs64_enable)
4482                         r = gfx_v11_0_cp_compute_load_microcode_rs64(adev);
4483                 else
4484                         r = gfx_v11_0_cp_compute_load_microcode(adev);
4485                 if (r)
4486                         return r;
4487         }
4488
4489         gfx_v11_0_cp_set_doorbell_range(adev);
4490
4491         if (amdgpu_async_gfx_ring) {
4492                 gfx_v11_0_cp_compute_enable(adev, true);
4493                 gfx_v11_0_cp_gfx_enable(adev, true);
4494         }
4495
4496         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
4497                 r = amdgpu_mes_kiq_hw_init(adev);
4498         else
4499                 r = gfx_v11_0_kiq_resume(adev);
4500         if (r)
4501                 return r;
4502
4503         r = gfx_v11_0_kcq_resume(adev);
4504         if (r)
4505                 return r;
4506
4507         if (!amdgpu_async_gfx_ring) {
4508                 r = gfx_v11_0_cp_gfx_resume(adev);
4509                 if (r)
4510                         return r;
4511         } else {
4512                 r = gfx_v11_0_cp_async_gfx_ring_resume(adev);
4513                 if (r)
4514                         return r;
4515         }
4516
4517         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4518                 ring = &adev->gfx.gfx_ring[i];
4519                 r = amdgpu_ring_test_helper(ring);
4520                 if (r)
4521                         return r;
4522         }
4523
4524         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4525                 ring = &adev->gfx.compute_ring[i];
4526                 r = amdgpu_ring_test_helper(ring);
4527                 if (r)
4528                         return r;
4529         }
4530
4531         return 0;
4532 }
4533
4534 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
4535 {
4536         gfx_v11_0_cp_gfx_enable(adev, enable);
4537         gfx_v11_0_cp_compute_enable(adev, enable);
4538 }
4539
4540 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
4541 {
4542         int r;
4543         bool value;
4544
4545         r = adev->gfxhub.funcs->gart_enable(adev);
4546         if (r)
4547                 return r;
4548
4549         adev->hdp.funcs->flush_hdp(adev, NULL);
4550
4551         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
4552                 false : true;
4553
4554         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
4555         /* TODO investigate why this and the hdp flush above is needed,
4556          * are we missing a flush somewhere else? */
4557         adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
4558
4559         return 0;
4560 }
4561
4562 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
4563 {
4564         u32 tmp;
4565
4566         /* select RS64 */
4567         if (adev->gfx.rs64_enable) {
4568                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4569                 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
4570                 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
4571
4572                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
4573                 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
4574                 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
4575         }
4576
4577         if (amdgpu_emu_mode == 1)
4578                 msleep(100);
4579 }
4580
4581 static int get_gb_addr_config(struct amdgpu_device * adev)
4582 {
4583         u32 gb_addr_config;
4584
4585         gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
4586         if (gb_addr_config == 0)
4587                 return -EINVAL;
4588
4589         adev->gfx.config.gb_addr_config_fields.num_pkrs =
4590                 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4591
4592         adev->gfx.config.gb_addr_config = gb_addr_config;
4593
4594         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4595                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4596                                       GB_ADDR_CONFIG, NUM_PIPES);
4597
4598         adev->gfx.config.max_tile_pipes =
4599                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4600
4601         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4602                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4603                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4604         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4605                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4606                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4607         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4608                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4609                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4610         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4611                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4612                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4613
4614         return 0;
4615 }
4616
4617 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)
4618 {
4619         uint32_t data;
4620
4621         data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
4622         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
4623         WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
4624
4625         data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
4626         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
4627         WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
4628 }
4629
4630 static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
4631 {
4632         int r;
4633         struct amdgpu_device *adev = ip_block->adev;
4634
4635         amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
4636                                        adev->gfx.cleaner_shader_ptr);
4637
4638         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4639                 if (adev->gfx.imu.funcs) {
4640                         /* RLC autoload sequence 1: Program rlc ram */
4641                         if (adev->gfx.imu.funcs->program_rlc_ram)
4642                                 adev->gfx.imu.funcs->program_rlc_ram(adev);
4643                         /* rlc autoload firmware */
4644                         r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);
4645                         if (r)
4646                                 return r;
4647                 }
4648         } else {
4649                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4650                         if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4651                                 if (adev->gfx.imu.funcs->load_microcode)
4652                                         adev->gfx.imu.funcs->load_microcode(adev);
4653                                 if (adev->gfx.imu.funcs->setup_imu)
4654                                         adev->gfx.imu.funcs->setup_imu(adev);
4655                                 if (adev->gfx.imu.funcs->start_imu)
4656                                         adev->gfx.imu.funcs->start_imu(adev);
4657                         }
4658
4659                         /* disable gpa mode in backdoor loading */
4660                         gfx_v11_0_disable_gpa_mode(adev);
4661                 }
4662         }
4663
4664         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
4665             (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
4666                 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev);
4667                 if (r) {
4668                         dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
4669                         return r;
4670                 }
4671         }
4672
4673         adev->gfx.is_poweron = true;
4674
4675         if(get_gb_addr_config(adev))
4676                 DRM_WARN("Invalid gb_addr_config !\n");
4677
4678         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
4679             adev->gfx.rs64_enable)
4680                 gfx_v11_0_config_gfx_rs64(adev);
4681
4682         r = gfx_v11_0_gfxhub_enable(adev);
4683         if (r)
4684                 return r;
4685
4686         if (!amdgpu_emu_mode)
4687                 gfx_v11_0_init_golden_registers(adev);
4688
4689         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
4690             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
4691                 /**
4692                  * For gfx 11, rlc firmware loading relies on smu firmware is
4693                  * loaded firstly, so in direct type, it has to load smc ucode
4694                  * here before rlc.
4695                  */
4696                 r = amdgpu_pm_load_smu_firmware(adev, NULL);
4697                 if (r)
4698                         return r;
4699         }
4700
4701         gfx_v11_0_constants_init(adev);
4702
4703         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
4704                 gfx_v11_0_select_cp_fw_arch(adev);
4705
4706         if (adev->nbio.funcs->gc_doorbell_init)
4707                 adev->nbio.funcs->gc_doorbell_init(adev);
4708
4709         r = gfx_v11_0_rlc_resume(adev);
4710         if (r)
4711                 return r;
4712
4713         /*
4714          * init golden registers and rlc resume may override some registers,
4715          * reconfig them here
4716          */
4717         gfx_v11_0_tcp_harvest(adev);
4718
4719         r = gfx_v11_0_cp_resume(adev);
4720         if (r)
4721                 return r;
4722
4723         /* get IMU version from HW if it's not set */
4724         if (!adev->gfx.imu_fw_version)
4725                 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);
4726
4727         return r;
4728 }
4729
4730 static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)
4731 {
4732         struct amdgpu_device *adev = ip_block->adev;
4733
4734         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4735         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4736         amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
4737
4738         if (!adev->no_hw_access) {
4739                 if (amdgpu_async_gfx_ring) {
4740                         if (amdgpu_gfx_disable_kgq(adev, 0))
4741                                 DRM_ERROR("KGQ disable failed\n");
4742                 }
4743
4744                 if (amdgpu_gfx_disable_kcq(adev, 0))
4745                         DRM_ERROR("KCQ disable failed\n");
4746
4747                 amdgpu_mes_kiq_hw_fini(adev);
4748         }
4749
4750         if (amdgpu_sriov_vf(adev))
4751                 /* Remove the steps disabling CPG and clearing KIQ position,
4752                  * so that CP could perform IDLE-SAVE during switch. Those
4753                  * steps are necessary to avoid a DMAR error in gfx9 but it is
4754                  * not reproduced on gfx11.
4755                  */
4756                 return 0;
4757
4758         gfx_v11_0_cp_enable(adev, false);
4759         gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4760
4761         adev->gfxhub.funcs->gart_disable(adev);
4762
4763         adev->gfx.is_poweron = false;
4764
4765         return 0;
4766 }
4767
4768 static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block)
4769 {
4770         return gfx_v11_0_hw_fini(ip_block);
4771 }
4772
4773 static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block)
4774 {
4775         return gfx_v11_0_hw_init(ip_block);
4776 }
4777
4778 static bool gfx_v11_0_is_idle(void *handle)
4779 {
4780         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4781
4782         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
4783                                 GRBM_STATUS, GUI_ACTIVE))
4784                 return false;
4785         else
4786                 return true;
4787 }
4788
4789 static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
4790 {
4791         unsigned i;
4792         u32 tmp;
4793         struct amdgpu_device *adev = ip_block->adev;
4794
4795         for (i = 0; i < adev->usec_timeout; i++) {
4796                 /* read MC_STATUS */
4797                 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
4798                         GRBM_STATUS__GUI_ACTIVE_MASK;
4799
4800                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4801                         return 0;
4802                 udelay(1);
4803         }
4804         return -ETIMEDOUT;
4805 }
4806
4807 int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,
4808                                       bool req)
4809 {
4810         u32 i, tmp, val;
4811
4812         for (i = 0; i < adev->usec_timeout; i++) {
4813                 /* Request with MeId=2, PipeId=0 */
4814                 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);
4815                 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);
4816                 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);
4817
4818                 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);
4819                 if (req) {
4820                         if (val == tmp)
4821                                 break;
4822                 } else {
4823                         tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,
4824                                             REQUEST, 1);
4825
4826                         /* unlocked or locked by firmware */
4827                         if (val != tmp)
4828                                 break;
4829                 }
4830                 udelay(1);
4831         }
4832
4833         if (i >= adev->usec_timeout)
4834                 return -EINVAL;
4835
4836         return 0;
4837 }
4838
4839 static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block)
4840 {
4841         u32 grbm_soft_reset = 0;
4842         u32 tmp;
4843         int r, i, j, k;
4844         struct amdgpu_device *adev = ip_block->adev;
4845
4846         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4847
4848         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4849         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
4850         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
4851         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
4852         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
4853         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4854
4855         mutex_lock(&adev->srbm_mutex);
4856         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4857                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4858                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4859                                 soc21_grbm_select(adev, i, k, j, 0);
4860
4861                                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
4862                                 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
4863                         }
4864                 }
4865         }
4866         for (i = 0; i < adev->gfx.me.num_me; ++i) {
4867                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4868                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4869                                 soc21_grbm_select(adev, i, k, j, 0);
4870
4871                                 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
4872                         }
4873                 }
4874         }
4875         soc21_grbm_select(adev, 0, 0, 0, 0);
4876         mutex_unlock(&adev->srbm_mutex);
4877
4878         /* Try to acquire the gfx mutex before access to CP_VMID_RESET */
4879         mutex_lock(&adev->gfx.reset_sem_mutex);
4880         r = gfx_v11_0_request_gfx_index_mutex(adev, true);
4881         if (r) {
4882                 mutex_unlock(&adev->gfx.reset_sem_mutex);
4883                 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n");
4884                 return r;
4885         }
4886
4887         WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);
4888
4889         // Read CP_VMID_RESET register three times.
4890         // to get sufficient time for GFX_HQD_ACTIVE reach 0
4891         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4892         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4893         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4894
4895         /* release the gfx mutex */
4896         r = gfx_v11_0_request_gfx_index_mutex(adev, false);
4897         mutex_unlock(&adev->gfx.reset_sem_mutex);
4898         if (r) {
4899                 DRM_ERROR("Failed to release the gfx mutex during soft reset\n");
4900                 return r;
4901         }
4902
4903         for (i = 0; i < adev->usec_timeout; i++) {
4904                 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
4905                     !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
4906                         break;
4907                 udelay(1);
4908         }
4909         if (i >= adev->usec_timeout) {
4910                 printk("Failed to wait all pipes clean\n");
4911                 return -EINVAL;
4912         }
4913
4914         /**********  trigger soft reset  ***********/
4915         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4916         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4917                                         SOFT_RESET_CP, 1);
4918         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4919                                         SOFT_RESET_GFX, 1);
4920         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4921                                         SOFT_RESET_CPF, 1);
4922         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4923                                         SOFT_RESET_CPC, 1);
4924         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4925                                         SOFT_RESET_CPG, 1);
4926         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4927         /**********  exit soft reset  ***********/
4928         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4929         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4930                                         SOFT_RESET_CP, 0);
4931         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4932                                         SOFT_RESET_GFX, 0);
4933         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4934                                         SOFT_RESET_CPF, 0);
4935         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4936                                         SOFT_RESET_CPC, 0);
4937         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4938                                         SOFT_RESET_CPG, 0);
4939         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4940
4941         tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
4942         tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
4943         WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
4944
4945         WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);
4946         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);
4947
4948         for (i = 0; i < adev->usec_timeout; i++) {
4949                 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))
4950                         break;
4951                 udelay(1);
4952         }
4953         if (i >= adev->usec_timeout) {
4954                 printk("Failed to wait CP_VMID_RESET to 0\n");
4955                 return -EINVAL;
4956         }
4957
4958         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4959         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4960         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4961         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4962         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4963         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4964
4965         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4966
4967         return gfx_v11_0_cp_resume(adev);
4968 }
4969
4970 static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
4971 {
4972         int i, r;
4973         struct amdgpu_device *adev = ip_block->adev;
4974         struct amdgpu_ring *ring;
4975         long tmo = msecs_to_jiffies(1000);
4976
4977         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4978                 ring = &adev->gfx.gfx_ring[i];
4979                 r = amdgpu_ring_test_ib(ring, tmo);
4980                 if (r)
4981                         return true;
4982         }
4983
4984         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4985                 ring = &adev->gfx.compute_ring[i];
4986                 r = amdgpu_ring_test_ib(ring, tmo);
4987                 if (r)
4988                         return true;
4989         }
4990
4991         return false;
4992 }
4993
4994 static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block)
4995 {
4996         struct amdgpu_device *adev = ip_block->adev;
4997         /**
4998          * GFX soft reset will impact MES, need resume MES when do GFX soft reset
4999          */
5000         return amdgpu_mes_resume(adev);
5001 }
5002
5003 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5004 {
5005         uint64_t clock;
5006         uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
5007
5008         if (amdgpu_sriov_vf(adev)) {
5009                 amdgpu_gfx_off_ctrl(adev, false);
5010                 mutex_lock(&adev->gfx.gpu_clock_mutex);
5011                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
5012                 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
5013                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
5014                 if (clock_counter_hi_pre != clock_counter_hi_after)
5015                         clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
5016                 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5017                 amdgpu_gfx_off_ctrl(adev, true);
5018         } else {
5019                 preempt_disable();
5020                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
5021                 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
5022                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
5023                 if (clock_counter_hi_pre != clock_counter_hi_after)
5024                         clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
5025                 preempt_enable();
5026         }
5027         clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
5028
5029         return clock;
5030 }
5031
5032 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5033                                            uint32_t vmid,
5034                                            uint32_t gds_base, uint32_t gds_size,
5035                                            uint32_t gws_base, uint32_t gws_size,
5036                                            uint32_t oa_base, uint32_t oa_size)
5037 {
5038         struct amdgpu_device *adev = ring->adev;
5039
5040         /* GDS Base */
5041         gfx_v11_0_write_data_to_reg(ring, 0, false,
5042                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
5043                                     gds_base);
5044
5045         /* GDS Size */
5046         gfx_v11_0_write_data_to_reg(ring, 0, false,
5047                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
5048                                     gds_size);
5049
5050         /* GWS */
5051         gfx_v11_0_write_data_to_reg(ring, 0, false,
5052                                     SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
5053                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5054
5055         /* OA */
5056         gfx_v11_0_write_data_to_reg(ring, 0, false,
5057                                     SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
5058                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
5059 }
5060
5061 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
5062 {
5063         struct amdgpu_device *adev = ip_block->adev;
5064
5065         adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
5066
5067         adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
5068         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
5069                                           AMDGPU_MAX_COMPUTE_RINGS);
5070
5071         gfx_v11_0_set_kiq_pm4_funcs(adev);
5072         gfx_v11_0_set_ring_funcs(adev);
5073         gfx_v11_0_set_irq_funcs(adev);
5074         gfx_v11_0_set_gds_init(adev);
5075         gfx_v11_0_set_rlc_funcs(adev);
5076         gfx_v11_0_set_mqd_funcs(adev);
5077         gfx_v11_0_set_imu_funcs(adev);
5078
5079         gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
5080
5081         return gfx_v11_0_init_microcode(adev);
5082 }
5083
5084 static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block)
5085 {
5086         struct amdgpu_device *adev = ip_block->adev;
5087         int r;
5088
5089         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5090         if (r)
5091                 return r;
5092
5093         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5094         if (r)
5095                 return r;
5096
5097         r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
5098         if (r)
5099                 return r;
5100         return 0;
5101 }
5102
5103 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
5104 {
5105         uint32_t rlc_cntl;
5106
5107         /* if RLC is not enabled, do nothing */
5108         rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
5109         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
5110 }
5111
5112 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
5113 {
5114         uint32_t data;
5115         unsigned i;
5116
5117         data = RLC_SAFE_MODE__CMD_MASK;
5118         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5119
5120         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
5121
5122         /* wait for RLC_SAFE_MODE */
5123         for (i = 0; i < adev->usec_timeout; i++) {
5124                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
5125                                    RLC_SAFE_MODE, CMD))
5126                         break;
5127                 udelay(1);
5128         }
5129 }
5130
5131 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
5132 {
5133         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
5134 }
5135
5136 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
5137                                       bool enable)
5138 {
5139         uint32_t def, data;
5140
5141         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
5142                 return;
5143
5144         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5145
5146         if (enable)
5147                 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
5148         else
5149                 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
5150
5151         if (def != data)
5152                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
5153 }
5154
5155 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
5156                                        bool enable)
5157 {
5158         uint32_t def, data;
5159
5160         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
5161                 return;
5162
5163         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5164
5165         if (enable)
5166                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
5167         else
5168                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
5169
5170         if (def != data)
5171                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
5172 }
5173
5174 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
5175                                            bool enable)
5176 {
5177         uint32_t def, data;
5178
5179         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
5180                 return;
5181
5182         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5183
5184         if (enable)
5185                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
5186         else
5187                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
5188
5189         if (def != data)
5190                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
5191 }
5192
5193 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5194                                                        bool enable)
5195 {
5196         uint32_t data, def;
5197
5198         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
5199                 return;
5200
5201         /* It is disabled by HW by default */
5202         if (enable) {
5203                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5204                         /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5205                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5206
5207                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
5208                                   RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
5209                                   RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
5210
5211                         if (def != data)
5212                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
5213                 }
5214         } else {
5215                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5216                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5217
5218                         data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
5219                                  RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
5220                                  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
5221
5222                         if (def != data)
5223                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
5224                 }
5225         }
5226 }
5227
5228 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5229                                                        bool enable)
5230 {
5231         uint32_t def, data;
5232
5233         if (!(adev->cg_flags &
5234               (AMD_CG_SUPPORT_GFX_CGCG |
5235               AMD_CG_SUPPORT_GFX_CGLS |
5236               AMD_CG_SUPPORT_GFX_3D_CGCG |
5237               AMD_CG_SUPPORT_GFX_3D_CGLS)))
5238                 return;
5239
5240         if (enable) {
5241                 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5242
5243                 /* unset CGCG override */
5244                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
5245                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
5246                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
5247                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
5248                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
5249                     adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
5250                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
5251
5252                 /* update CGCG override bits */
5253                 if (def != data)
5254                         WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
5255
5256                 /* enable cgcg FSM(0x0000363F) */
5257                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5258
5259                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5260                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
5261                         data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
5262                                  RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5263                 }
5264
5265                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5266                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
5267                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
5268                                  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5269                 }
5270
5271                 if (def != data)
5272                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
5273
5274                 /* Program RLC_CGCG_CGLS_CTRL_3D */
5275                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5276
5277                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5278                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
5279                         data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
5280                                  RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
5281                 }
5282
5283                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5284                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
5285                         data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
5286                                  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
5287                 }
5288
5289                 if (def != data)
5290                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
5291
5292                 /* set IDLE_POLL_COUNT(0x00900100) */
5293                 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
5294
5295                 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
5296                 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
5297                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
5298
5299                 if (def != data)
5300                         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
5301
5302                 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
5303                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
5304                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
5305                 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
5306                 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
5307                 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
5308
5309                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
5310                 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
5311                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
5312
5313                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
5314                 if (adev->sdma.num_instances > 1) {
5315                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
5316                         data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
5317                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
5318                 }
5319         } else {
5320                 /* Program RLC_CGCG_CGLS_CTRL */
5321                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5322
5323                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
5324                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5325
5326                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
5327                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5328
5329                 if (def != data)
5330                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
5331
5332                 /* Program RLC_CGCG_CGLS_CTRL_3D */
5333                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5334
5335                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
5336                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
5337                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
5338                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
5339
5340                 if (def != data)
5341                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
5342
5343                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
5344                 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
5345                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
5346
5347                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
5348                 if (adev->sdma.num_instances > 1) {
5349                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
5350                         data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
5351                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
5352                 }
5353         }
5354 }
5355
5356 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5357                                             bool enable)
5358 {
5359         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5360
5361         gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
5362
5363         gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
5364
5365         gfx_v11_0_update_repeater_fgcg(adev, enable);
5366
5367         gfx_v11_0_update_sram_fgcg(adev, enable);
5368
5369         gfx_v11_0_update_perf_clk(adev, enable);
5370
5371         if (adev->cg_flags &
5372             (AMD_CG_SUPPORT_GFX_MGCG |
5373              AMD_CG_SUPPORT_GFX_CGLS |
5374              AMD_CG_SUPPORT_GFX_CGCG |
5375              AMD_CG_SUPPORT_GFX_3D_CGCG |
5376              AMD_CG_SUPPORT_GFX_3D_CGLS))
5377                 gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
5378
5379         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5380
5381         return 0;
5382 }
5383
5384 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
5385 {
5386         u32 reg, pre_data, data;
5387
5388         amdgpu_gfx_off_ctrl(adev, false);
5389         reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
5390         if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
5391                 pre_data = RREG32_NO_KIQ(reg);
5392         else
5393                 pre_data = RREG32(reg);
5394
5395         data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
5396         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
5397
5398         if (pre_data != data) {
5399                 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
5400                         WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
5401                 } else
5402                         WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
5403         }
5404         amdgpu_gfx_off_ctrl(adev, true);
5405
5406         if (ring
5407                 && amdgpu_sriov_is_pp_one_vf(adev)
5408                 && (pre_data != data)
5409                 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
5410                         || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
5411                 amdgpu_ring_emit_wreg(ring, reg, data);
5412         }
5413 }
5414
5415 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
5416         .is_rlc_enabled = gfx_v11_0_is_rlc_enabled,
5417         .set_safe_mode = gfx_v11_0_set_safe_mode,
5418         .unset_safe_mode = gfx_v11_0_unset_safe_mode,
5419         .init = gfx_v11_0_rlc_init,
5420         .get_csb_size = gfx_v11_0_get_csb_size,
5421         .get_csb_buffer = gfx_v11_0_get_csb_buffer,
5422         .resume = gfx_v11_0_rlc_resume,
5423         .stop = gfx_v11_0_rlc_stop,
5424         .reset = gfx_v11_0_rlc_reset,
5425         .start = gfx_v11_0_rlc_start,
5426         .update_spm_vmid = gfx_v11_0_update_spm_vmid,
5427 };
5428
5429 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
5430 {
5431         u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
5432
5433         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5434                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5435         else
5436                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5437
5438         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
5439
5440         // Program RLC_PG_DELAY3 for CGPG hysteresis
5441         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
5442                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5443                 case IP_VERSION(11, 0, 1):
5444                 case IP_VERSION(11, 0, 4):
5445                 case IP_VERSION(11, 5, 0):
5446                 case IP_VERSION(11, 5, 1):
5447                 case IP_VERSION(11, 5, 2):
5448                         WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
5449                         break;
5450                 default:
5451                         break;
5452                 }
5453         }
5454 }
5455
5456 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
5457 {
5458         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5459
5460         gfx_v11_cntl_power_gating(adev, enable);
5461
5462         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5463 }
5464
5465 static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
5466                                            enum amd_powergating_state state)
5467 {
5468         struct amdgpu_device *adev = ip_block->adev;
5469         bool enable = (state == AMD_PG_STATE_GATE);
5470
5471         if (amdgpu_sriov_vf(adev))
5472                 return 0;
5473
5474         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5475         case IP_VERSION(11, 0, 0):
5476         case IP_VERSION(11, 0, 2):
5477         case IP_VERSION(11, 0, 3):
5478                 amdgpu_gfx_off_ctrl(adev, enable);
5479                 break;
5480         case IP_VERSION(11, 0, 1):
5481         case IP_VERSION(11, 0, 4):
5482         case IP_VERSION(11, 5, 0):
5483         case IP_VERSION(11, 5, 1):
5484         case IP_VERSION(11, 5, 2):
5485                 if (!enable)
5486                         amdgpu_gfx_off_ctrl(adev, false);
5487
5488                 gfx_v11_cntl_pg(adev, enable);
5489
5490                 if (enable)
5491                         amdgpu_gfx_off_ctrl(adev, true);
5492
5493                 break;
5494         default:
5495                 break;
5496         }
5497
5498         return 0;
5499 }
5500
5501 static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
5502                                           enum amd_clockgating_state state)
5503 {
5504         struct amdgpu_device *adev = ip_block->adev;
5505
5506         if (amdgpu_sriov_vf(adev))
5507                 return 0;
5508
5509         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5510         case IP_VERSION(11, 0, 0):
5511         case IP_VERSION(11, 0, 1):
5512         case IP_VERSION(11, 0, 2):
5513         case IP_VERSION(11, 0, 3):
5514         case IP_VERSION(11, 0, 4):
5515         case IP_VERSION(11, 5, 0):
5516         case IP_VERSION(11, 5, 1):
5517         case IP_VERSION(11, 5, 2):
5518                 gfx_v11_0_update_gfx_clock_gating(adev,
5519                                 state ==  AMD_CG_STATE_GATE);
5520                 break;
5521         default:
5522                 break;
5523         }
5524
5525         return 0;
5526 }
5527
5528 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
5529 {
5530         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5531         int data;
5532
5533         /* AMD_CG_SUPPORT_GFX_MGCG */
5534         data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5535         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5536                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5537
5538         /* AMD_CG_SUPPORT_REPEATER_FGCG */
5539         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
5540                 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
5541
5542         /* AMD_CG_SUPPORT_GFX_FGCG */
5543         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
5544                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
5545
5546         /* AMD_CG_SUPPORT_GFX_PERF_CLK */
5547         if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
5548                 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
5549
5550         /* AMD_CG_SUPPORT_GFX_CGCG */
5551         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5552         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5553                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5554
5555         /* AMD_CG_SUPPORT_GFX_CGLS */
5556         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5557                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5558
5559         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5560         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5561         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5562                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5563
5564         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5565         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5566                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5567 }
5568
5569 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5570 {
5571         /* gfx11 is 32bit rptr*/
5572         return *(uint32_t *)ring->rptr_cpu_addr;
5573 }
5574
5575 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5576 {
5577         struct amdgpu_device *adev = ring->adev;
5578         u64 wptr;
5579
5580         /* XXX check if swapping is necessary on BE */
5581         if (ring->use_doorbell) {
5582                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5583         } else {
5584                 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
5585                 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
5586         }
5587
5588         return wptr;
5589 }
5590
5591 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5592 {
5593         struct amdgpu_device *adev = ring->adev;
5594
5595         if (ring->use_doorbell) {
5596                 /* XXX check if swapping is necessary on BE */
5597                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5598                              ring->wptr);
5599                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5600         } else {
5601                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5602                              lower_32_bits(ring->wptr));
5603                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5604                              upper_32_bits(ring->wptr));
5605         }
5606 }
5607
5608 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5609 {
5610         /* gfx11 hardware is 32bit rptr */
5611         return *(uint32_t *)ring->rptr_cpu_addr;
5612 }
5613
5614 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5615 {
5616         u64 wptr;
5617
5618         /* XXX check if swapping is necessary on BE */
5619         if (ring->use_doorbell)
5620                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5621         else
5622                 BUG();
5623         return wptr;
5624 }
5625
5626 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5627 {
5628         struct amdgpu_device *adev = ring->adev;
5629
5630         /* XXX check if swapping is necessary on BE */
5631         if (ring->use_doorbell) {
5632                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5633                              ring->wptr);
5634                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5635         } else {
5636                 BUG(); /* only DOORBELL method supported on gfx11 now */
5637         }
5638 }
5639
5640 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5641 {
5642         struct amdgpu_device *adev = ring->adev;
5643         u32 ref_and_mask, reg_mem_engine;
5644         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5645
5646         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5647                 switch (ring->me) {
5648                 case 1:
5649                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5650                         break;
5651                 case 2:
5652                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5653                         break;
5654                 default:
5655                         return;
5656                 }
5657                 reg_mem_engine = 0;
5658         } else {
5659                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
5660                 reg_mem_engine = 1; /* pfp */
5661         }
5662
5663         gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5664                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5665                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5666                                ref_and_mask, ref_and_mask, 0x20);
5667 }
5668
5669 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5670                                        struct amdgpu_job *job,
5671                                        struct amdgpu_ib *ib,
5672                                        uint32_t flags)
5673 {
5674         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5675         u32 header, control = 0;
5676
5677         BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
5678
5679         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5680
5681         control |= ib->length_dw | (vmid << 24);
5682
5683         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5684                 control |= INDIRECT_BUFFER_PRE_ENB(1);
5685
5686                 if (flags & AMDGPU_IB_PREEMPTED)
5687                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
5688
5689                 if (vmid)
5690                         gfx_v11_0_ring_emit_de_meta(ring,
5691                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
5692         }
5693
5694         if (ring->is_mes_queue)
5695                 /* inherit vmid from mqd */
5696                 control |= 0x400000;
5697
5698         amdgpu_ring_write(ring, header);
5699         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5700         amdgpu_ring_write(ring,
5701 #ifdef __BIG_ENDIAN
5702                 (2 << 0) |
5703 #endif
5704                 lower_32_bits(ib->gpu_addr));
5705         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5706         amdgpu_ring_write(ring, control);
5707 }
5708
5709 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5710                                            struct amdgpu_job *job,
5711                                            struct amdgpu_ib *ib,
5712                                            uint32_t flags)
5713 {
5714         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5715         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5716
5717         if (ring->is_mes_queue)
5718                 /* inherit vmid from mqd */
5719                 control |= 0x40000000;
5720
5721         /* Currently, there is a high possibility to get wave ID mismatch
5722          * between ME and GDS, leading to a hw deadlock, because ME generates
5723          * different wave IDs than the GDS expects. This situation happens
5724          * randomly when at least 5 compute pipes use GDS ordered append.
5725          * The wave IDs generated by ME are also wrong after suspend/resume.
5726          * Those are probably bugs somewhere else in the kernel driver.
5727          *
5728          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5729          * GDS to 0 for this ring (me/pipe).
5730          */
5731         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5732                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5733                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
5734                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5735         }
5736
5737         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5738         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5739         amdgpu_ring_write(ring,
5740 #ifdef __BIG_ENDIAN
5741                                 (2 << 0) |
5742 #endif
5743                                 lower_32_bits(ib->gpu_addr));
5744         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5745         amdgpu_ring_write(ring, control);
5746 }
5747
5748 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5749                                      u64 seq, unsigned flags)
5750 {
5751         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5752         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5753
5754         /* RELEASE_MEM - flush caches, send int */
5755         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5756         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5757                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
5758                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
5759                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
5760                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5761                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5762                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5763         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
5764                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
5765
5766         /*
5767          * the address should be Qword aligned if 64bit write, Dword
5768          * aligned if only send 32bit data low (discard data high)
5769          */
5770         if (write64bit)
5771                 BUG_ON(addr & 0x7);
5772         else
5773                 BUG_ON(addr & 0x3);
5774         amdgpu_ring_write(ring, lower_32_bits(addr));
5775         amdgpu_ring_write(ring, upper_32_bits(addr));
5776         amdgpu_ring_write(ring, lower_32_bits(seq));
5777         amdgpu_ring_write(ring, upper_32_bits(seq));
5778         amdgpu_ring_write(ring, ring->is_mes_queue ?
5779                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
5780 }
5781
5782 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5783 {
5784         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5785         uint32_t seq = ring->fence_drv.sync_seq;
5786         uint64_t addr = ring->fence_drv.gpu_addr;
5787
5788         gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
5789                                upper_32_bits(addr), seq, 0xffffffff, 4);
5790 }
5791
5792 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
5793                                    uint16_t pasid, uint32_t flush_type,
5794                                    bool all_hub, uint8_t dst_sel)
5795 {
5796         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
5797         amdgpu_ring_write(ring,
5798                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
5799                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
5800                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
5801                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
5802 }
5803
5804 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5805                                          unsigned vmid, uint64_t pd_addr)
5806 {
5807         if (ring->is_mes_queue)
5808                 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
5809         else
5810                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5811
5812         /* compute doesn't have PFP */
5813         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5814                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5815                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5816                 amdgpu_ring_write(ring, 0x0);
5817         }
5818
5819         /* Make sure that we can't skip the SET_Q_MODE packets when the VM
5820          * changed in any way.
5821          */
5822         ring->set_q_mode_offs = 0;
5823         ring->set_q_mode_ptr = NULL;
5824 }
5825
5826 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5827                                           u64 seq, unsigned int flags)
5828 {
5829         struct amdgpu_device *adev = ring->adev;
5830
5831         /* we only allocate 32bit for each seq wb address */
5832         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5833
5834         /* write fence seq to the "addr" */
5835         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5836         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5837                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5838         amdgpu_ring_write(ring, lower_32_bits(addr));
5839         amdgpu_ring_write(ring, upper_32_bits(addr));
5840         amdgpu_ring_write(ring, lower_32_bits(seq));
5841
5842         if (flags & AMDGPU_FENCE_FLAG_INT) {
5843                 /* set register to trigger INT */
5844                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5845                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5846                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5847                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
5848                 amdgpu_ring_write(ring, 0);
5849                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5850         }
5851 }
5852
5853 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
5854                                          uint32_t flags)
5855 {
5856         uint32_t dw2 = 0;
5857
5858         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5859         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5860                 /* set load_global_config & load_global_uconfig */
5861                 dw2 |= 0x8001;
5862                 /* set load_cs_sh_regs */
5863                 dw2 |= 0x01000000;
5864                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5865                 dw2 |= 0x10002;
5866         }
5867
5868         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5869         amdgpu_ring_write(ring, dw2);
5870         amdgpu_ring_write(ring, 0);
5871 }
5872
5873 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
5874                                                    uint64_t addr)
5875 {
5876         unsigned ret;
5877
5878         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5879         amdgpu_ring_write(ring, lower_32_bits(addr));
5880         amdgpu_ring_write(ring, upper_32_bits(addr));
5881         /* discard following DWs if *cond_exec_gpu_addr==0 */
5882         amdgpu_ring_write(ring, 0);
5883         ret = ring->wptr & ring->buf_mask;
5884         /* patch dummy value later */
5885         amdgpu_ring_write(ring, 0);
5886
5887         return ret;
5888 }
5889
5890 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,
5891                                            u64 shadow_va, u64 csa_va,
5892                                            u64 gds_va, bool init_shadow,
5893                                            int vmid)
5894 {
5895         struct amdgpu_device *adev = ring->adev;
5896         unsigned int offs, end;
5897
5898         if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj)
5899                 return;
5900
5901         /*
5902          * The logic here isn't easy to understand because we need to keep state
5903          * accross multiple executions of the function as well as between the
5904          * CPU and GPU. The general idea is that the newly written GPU command
5905          * has a condition on the previous one and only executed if really
5906          * necessary.
5907          */
5908
5909         /*
5910          * The dw in the NOP controls if the next SET_Q_MODE packet should be
5911          * executed or not. Reserve 64bits just to be on the save side.
5912          */
5913         amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1));
5914         offs = ring->wptr & ring->buf_mask;
5915
5916         /*
5917          * We start with skipping the prefix SET_Q_MODE and always executing
5918          * the postfix SET_Q_MODE packet. This is changed below with a
5919          * WRITE_DATA command when the postfix executed.
5920          */
5921         amdgpu_ring_write(ring, shadow_va ? 1 : 0);
5922         amdgpu_ring_write(ring, 0);
5923
5924         if (ring->set_q_mode_offs) {
5925                 uint64_t addr;
5926
5927                 addr = amdgpu_bo_gpu_offset(ring->ring_obj);
5928                 addr += ring->set_q_mode_offs << 2;
5929                 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr);
5930         }
5931
5932         /*
5933          * When the postfix SET_Q_MODE packet executes we need to make sure that the
5934          * next prefix SET_Q_MODE packet executes as well.
5935          */
5936         if (!shadow_va) {
5937                 uint64_t addr;
5938
5939                 addr = amdgpu_bo_gpu_offset(ring->ring_obj);
5940                 addr += offs << 2;
5941                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5942                 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
5943                 amdgpu_ring_write(ring, lower_32_bits(addr));
5944                 amdgpu_ring_write(ring, upper_32_bits(addr));
5945                 amdgpu_ring_write(ring, 0x1);
5946         }
5947
5948         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7));
5949         amdgpu_ring_write(ring, lower_32_bits(shadow_va));
5950         amdgpu_ring_write(ring, upper_32_bits(shadow_va));
5951         amdgpu_ring_write(ring, lower_32_bits(gds_va));
5952         amdgpu_ring_write(ring, upper_32_bits(gds_va));
5953         amdgpu_ring_write(ring, lower_32_bits(csa_va));
5954         amdgpu_ring_write(ring, upper_32_bits(csa_va));
5955         amdgpu_ring_write(ring, shadow_va ?
5956                           PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0);
5957         amdgpu_ring_write(ring, init_shadow ?
5958                           PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);
5959
5960         if (ring->set_q_mode_offs)
5961                 amdgpu_ring_patch_cond_exec(ring, end);
5962
5963         if (shadow_va) {
5964                 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid;
5965
5966                 /*
5967                  * If the tokens match try to skip the last postfix SET_Q_MODE
5968                  * packet to avoid saving/restoring the state all the time.
5969                  */
5970                 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token)
5971                         *ring->set_q_mode_ptr = 0;
5972
5973                 ring->set_q_mode_token = token;
5974         } else {
5975                 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs];
5976         }
5977
5978         ring->set_q_mode_offs = offs;
5979 }
5980
5981 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
5982 {
5983         int i, r = 0;
5984         struct amdgpu_device *adev = ring->adev;
5985         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
5986         struct amdgpu_ring *kiq_ring = &kiq->ring;
5987         unsigned long flags;
5988
5989         if (adev->enable_mes)
5990                 return -EINVAL;
5991
5992         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5993                 return -EINVAL;
5994
5995         spin_lock_irqsave(&kiq->ring_lock, flags);
5996
5997         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5998                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
5999                 return -ENOMEM;
6000         }
6001
6002         /* assert preemption condition */
6003         amdgpu_ring_set_preempt_cond_exec(ring, false);
6004
6005         /* assert IB preemption, emit the trailing fence */
6006         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
6007                                    ring->trail_fence_gpu_addr,
6008                                    ++ring->trail_seq);
6009         amdgpu_ring_commit(kiq_ring);
6010
6011         spin_unlock_irqrestore(&kiq->ring_lock, flags);
6012
6013         /* poll the trailing fence */
6014         for (i = 0; i < adev->usec_timeout; i++) {
6015                 if (ring->trail_seq ==
6016                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
6017                         break;
6018                 udelay(1);
6019         }
6020
6021         if (i >= adev->usec_timeout) {
6022                 r = -EINVAL;
6023                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
6024         }
6025
6026         /* deassert preemption condition */
6027         amdgpu_ring_set_preempt_cond_exec(ring, true);
6028         return r;
6029 }
6030
6031 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
6032 {
6033         struct amdgpu_device *adev = ring->adev;
6034         struct v10_de_ib_state de_payload = {0};
6035         uint64_t offset, gds_addr, de_payload_gpu_addr;
6036         void *de_payload_cpu_addr;
6037         int cnt;
6038
6039         if (ring->is_mes_queue) {
6040                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
6041                                   gfx[0].gfx_meta_data) +
6042                         offsetof(struct v10_gfx_meta_data, de_payload);
6043                 de_payload_gpu_addr =
6044                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
6045                 de_payload_cpu_addr =
6046                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
6047
6048                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
6049                                   gfx[0].gds_backup) +
6050                         offsetof(struct v10_gfx_meta_data, de_payload);
6051                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
6052         } else {
6053                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
6054                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
6055                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
6056
6057                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
6058                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
6059                                  PAGE_SIZE);
6060         }
6061
6062         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
6063         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
6064
6065         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
6066         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
6067         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
6068                                  WRITE_DATA_DST_SEL(8) |
6069                                  WR_CONFIRM) |
6070                                  WRITE_DATA_CACHE_POLICY(0));
6071         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
6072         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
6073
6074         if (resume)
6075                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
6076                                            sizeof(de_payload) >> 2);
6077         else
6078                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
6079                                            sizeof(de_payload) >> 2);
6080 }
6081
6082 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
6083                                     bool secure)
6084 {
6085         uint32_t v = secure ? FRAME_TMZ : 0;
6086
6087         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
6088         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
6089 }
6090
6091 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
6092                                      uint32_t reg_val_offs)
6093 {
6094         struct amdgpu_device *adev = ring->adev;
6095
6096         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6097         amdgpu_ring_write(ring, 0 |     /* src: register*/
6098                                 (5 << 8) |      /* dst: memory */
6099                                 (1 << 20));     /* write confirm */
6100         amdgpu_ring_write(ring, reg);
6101         amdgpu_ring_write(ring, 0);
6102         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6103                                 reg_val_offs * 4));
6104         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6105                                 reg_val_offs * 4));
6106 }
6107
6108 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6109                                    uint32_t val)
6110 {
6111         uint32_t cmd = 0;
6112
6113         switch (ring->funcs->type) {
6114         case AMDGPU_RING_TYPE_GFX:
6115                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6116                 break;
6117         case AMDGPU_RING_TYPE_KIQ:
6118                 cmd = (1 << 16); /* no inc addr */
6119                 break;
6120         default:
6121                 cmd = WR_CONFIRM;
6122                 break;
6123         }
6124         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6125         amdgpu_ring_write(ring, cmd);
6126         amdgpu_ring_write(ring, reg);
6127         amdgpu_ring_write(ring, 0);
6128         amdgpu_ring_write(ring, val);
6129 }
6130
6131 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
6132                                         uint32_t val, uint32_t mask)
6133 {
6134         gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
6135 }
6136
6137 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
6138                                                    uint32_t reg0, uint32_t reg1,
6139                                                    uint32_t ref, uint32_t mask)
6140 {
6141         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6142
6143         gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
6144                                ref, mask, 0x20);
6145 }
6146
6147 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
6148                                          unsigned vmid)
6149 {
6150         struct amdgpu_device *adev = ring->adev;
6151         uint32_t value = 0;
6152
6153         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6154         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6155         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6156         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6157         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
6158         WREG32_SOC15(GC, 0, regSQ_CMD, value);
6159         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
6160 }
6161
6162 static void
6163 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6164                                       uint32_t me, uint32_t pipe,
6165                                       enum amdgpu_interrupt_state state)
6166 {
6167         uint32_t cp_int_cntl, cp_int_cntl_reg;
6168
6169         if (!me) {
6170                 switch (pipe) {
6171                 case 0:
6172                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
6173                         break;
6174                 case 1:
6175                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
6176                         break;
6177                 default:
6178                         DRM_DEBUG("invalid pipe %d\n", pipe);
6179                         return;
6180                 }
6181         } else {
6182                 DRM_DEBUG("invalid me %d\n", me);
6183                 return;
6184         }
6185
6186         switch (state) {
6187         case AMDGPU_IRQ_STATE_DISABLE:
6188                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6189                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6190                                             TIME_STAMP_INT_ENABLE, 0);
6191                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6192                                             GENERIC0_INT_ENABLE, 0);
6193                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
6194                 break;
6195         case AMDGPU_IRQ_STATE_ENABLE:
6196                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6197                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6198                                             TIME_STAMP_INT_ENABLE, 1);
6199                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6200                                             GENERIC0_INT_ENABLE, 1);
6201                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
6202                 break;
6203         default:
6204                 break;
6205         }
6206 }
6207
6208 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6209                                                      int me, int pipe,
6210                                                      enum amdgpu_interrupt_state state)
6211 {
6212         u32 mec_int_cntl, mec_int_cntl_reg;
6213
6214         /*
6215          * amdgpu controls only the first MEC. That's why this function only
6216          * handles the setting of interrupts for this specific MEC. All other
6217          * pipes' interrupts are set by amdkfd.
6218          */
6219
6220         if (me == 1) {
6221                 switch (pipe) {
6222                 case 0:
6223                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6224                         break;
6225                 case 1:
6226                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
6227                         break;
6228                 case 2:
6229                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
6230                         break;
6231                 case 3:
6232                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
6233                         break;
6234                 default:
6235                         DRM_DEBUG("invalid pipe %d\n", pipe);
6236                         return;
6237                 }
6238         } else {
6239                 DRM_DEBUG("invalid me %d\n", me);
6240                 return;
6241         }
6242
6243         switch (state) {
6244         case AMDGPU_IRQ_STATE_DISABLE:
6245                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
6246                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6247                                              TIME_STAMP_INT_ENABLE, 0);
6248                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6249                                              GENERIC0_INT_ENABLE, 0);
6250                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
6251                 break;
6252         case AMDGPU_IRQ_STATE_ENABLE:
6253                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
6254                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6255                                              TIME_STAMP_INT_ENABLE, 1);
6256                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6257                                              GENERIC0_INT_ENABLE, 1);
6258                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
6259                 break;
6260         default:
6261                 break;
6262         }
6263 }
6264
6265 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6266                                             struct amdgpu_irq_src *src,
6267                                             unsigned type,
6268                                             enum amdgpu_interrupt_state state)
6269 {
6270         switch (type) {
6271         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
6272                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
6273                 break;
6274         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
6275                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
6276                 break;
6277         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6278                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6279                 break;
6280         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6281                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6282                 break;
6283         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6284                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6285                 break;
6286         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6287                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6288                 break;
6289         default:
6290                 break;
6291         }
6292         return 0;
6293 }
6294
6295 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
6296                              struct amdgpu_irq_src *source,
6297                              struct amdgpu_iv_entry *entry)
6298 {
6299         int i;
6300         u8 me_id, pipe_id, queue_id;
6301         struct amdgpu_ring *ring;
6302         uint32_t mes_queue_id = entry->src_data[0];
6303
6304         DRM_DEBUG("IH: CP EOP\n");
6305
6306         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
6307                 struct amdgpu_mes_queue *queue;
6308
6309                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
6310
6311                 spin_lock(&adev->mes.queue_id_lock);
6312                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
6313                 if (queue) {
6314                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
6315                         amdgpu_fence_process(queue->ring);
6316                 }
6317                 spin_unlock(&adev->mes.queue_id_lock);
6318         } else {
6319                 me_id = (entry->ring_id & 0x0c) >> 2;
6320                 pipe_id = (entry->ring_id & 0x03) >> 0;
6321                 queue_id = (entry->ring_id & 0x70) >> 4;
6322
6323                 switch (me_id) {
6324                 case 0:
6325                         if (pipe_id == 0)
6326                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6327                         else
6328                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
6329                         break;
6330                 case 1:
6331                 case 2:
6332                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6333                                 ring = &adev->gfx.compute_ring[i];
6334                                 /* Per-queue interrupt is supported for MEC starting from VI.
6335                                  * The interrupt can only be enabled/disabled per pipe instead
6336                                  * of per queue.
6337                                  */
6338                                 if ((ring->me == me_id) &&
6339                                     (ring->pipe == pipe_id) &&
6340                                     (ring->queue == queue_id))
6341                                         amdgpu_fence_process(ring);
6342                         }
6343                         break;
6344                 }
6345         }
6346
6347         return 0;
6348 }
6349
6350 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6351                                               struct amdgpu_irq_src *source,
6352                                               unsigned int type,
6353                                               enum amdgpu_interrupt_state state)
6354 {
6355         u32 cp_int_cntl_reg, cp_int_cntl;
6356         int i, j;
6357
6358         switch (state) {
6359         case AMDGPU_IRQ_STATE_DISABLE:
6360         case AMDGPU_IRQ_STATE_ENABLE:
6361                 for (i = 0; i < adev->gfx.me.num_me; i++) {
6362                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
6363                                 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
6364
6365                                 if (cp_int_cntl_reg) {
6366                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6367                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6368                                                                     PRIV_REG_INT_ENABLE,
6369                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
6370                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
6371                                 }
6372                         }
6373                 }
6374                 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
6375                         for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
6376                                 /* MECs start at 1 */
6377                                 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j);
6378
6379                                 if (cp_int_cntl_reg) {
6380                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6381                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6382                                                                     PRIV_REG_INT_ENABLE,
6383                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
6384                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
6385                                 }
6386                         }
6387                 }
6388                 break;
6389         default:
6390                 break;
6391         }
6392
6393         return 0;
6394 }
6395
6396 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev,
6397                                             struct amdgpu_irq_src *source,
6398                                             unsigned type,
6399                                             enum amdgpu_interrupt_state state)
6400 {
6401         u32 cp_int_cntl_reg, cp_int_cntl;
6402         int i, j;
6403
6404         switch (state) {
6405         case AMDGPU_IRQ_STATE_DISABLE:
6406         case AMDGPU_IRQ_STATE_ENABLE:
6407                 for (i = 0; i < adev->gfx.me.num_me; i++) {
6408                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
6409                                 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
6410
6411                                 if (cp_int_cntl_reg) {
6412                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6413                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6414                                                                     OPCODE_ERROR_INT_ENABLE,
6415                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
6416                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
6417                                 }
6418                         }
6419                 }
6420                 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
6421                         for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
6422                                 /* MECs start at 1 */
6423                                 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j);
6424
6425                                 if (cp_int_cntl_reg) {
6426                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6427                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6428                                                                     OPCODE_ERROR_INT_ENABLE,
6429                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
6430                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
6431                                 }
6432                         }
6433                 }
6434                 break;
6435         default:
6436                 break;
6437         }
6438         return 0;
6439 }
6440
6441 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6442                                                struct amdgpu_irq_src *source,
6443                                                unsigned int type,
6444                                                enum amdgpu_interrupt_state state)
6445 {
6446         u32 cp_int_cntl_reg, cp_int_cntl;
6447         int i, j;
6448
6449         switch (state) {
6450         case AMDGPU_IRQ_STATE_DISABLE:
6451         case AMDGPU_IRQ_STATE_ENABLE:
6452                 for (i = 0; i < adev->gfx.me.num_me; i++) {
6453                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
6454                                 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
6455
6456                                 if (cp_int_cntl_reg) {
6457                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6458                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6459                                                                     PRIV_INSTR_INT_ENABLE,
6460                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
6461                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
6462                                 }
6463                         }
6464                 }
6465                 break;
6466         default:
6467                 break;
6468         }
6469
6470         return 0;
6471 }
6472
6473 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
6474                                         struct amdgpu_iv_entry *entry)
6475 {
6476         u8 me_id, pipe_id, queue_id;
6477         struct amdgpu_ring *ring;
6478         int i;
6479
6480         me_id = (entry->ring_id & 0x0c) >> 2;
6481         pipe_id = (entry->ring_id & 0x03) >> 0;
6482         queue_id = (entry->ring_id & 0x70) >> 4;
6483
6484         switch (me_id) {
6485         case 0:
6486                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6487                         ring = &adev->gfx.gfx_ring[i];
6488                         if (ring->me == me_id && ring->pipe == pipe_id &&
6489                             ring->queue == queue_id)
6490                                 drm_sched_fault(&ring->sched);
6491                 }
6492                 break;
6493         case 1:
6494         case 2:
6495                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6496                         ring = &adev->gfx.compute_ring[i];
6497                         if (ring->me == me_id && ring->pipe == pipe_id &&
6498                             ring->queue == queue_id)
6499                                 drm_sched_fault(&ring->sched);
6500                 }
6501                 break;
6502         default:
6503                 BUG();
6504                 break;
6505         }
6506 }
6507
6508 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
6509                                   struct amdgpu_irq_src *source,
6510                                   struct amdgpu_iv_entry *entry)
6511 {
6512         DRM_ERROR("Illegal register access in command stream\n");
6513         gfx_v11_0_handle_priv_fault(adev, entry);
6514         return 0;
6515 }
6516
6517 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev,
6518                                 struct amdgpu_irq_src *source,
6519                                 struct amdgpu_iv_entry *entry)
6520 {
6521         DRM_ERROR("Illegal opcode in command stream \n");
6522         gfx_v11_0_handle_priv_fault(adev, entry);
6523         return 0;
6524 }
6525
6526 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
6527                                    struct amdgpu_irq_src *source,
6528                                    struct amdgpu_iv_entry *entry)
6529 {
6530         DRM_ERROR("Illegal instruction in command stream\n");
6531         gfx_v11_0_handle_priv_fault(adev, entry);
6532         return 0;
6533 }
6534
6535 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev,
6536                                   struct amdgpu_irq_src *source,
6537                                   struct amdgpu_iv_entry *entry)
6538 {
6539         if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq)
6540                 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry);
6541
6542         return 0;
6543 }
6544
6545 #if 0
6546 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
6547                                              struct amdgpu_irq_src *src,
6548                                              unsigned int type,
6549                                              enum amdgpu_interrupt_state state)
6550 {
6551         uint32_t tmp, target;
6552         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6553
6554         target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6555         target += ring->pipe;
6556
6557         switch (type) {
6558         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
6559                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
6560                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6561                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6562                                             GENERIC2_INT_ENABLE, 0);
6563                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6564
6565                         tmp = RREG32_SOC15_IP(GC, target);
6566                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6567                                             GENERIC2_INT_ENABLE, 0);
6568                         WREG32_SOC15_IP(GC, target, tmp);
6569                 } else {
6570                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6571                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6572                                             GENERIC2_INT_ENABLE, 1);
6573                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6574
6575                         tmp = RREG32_SOC15_IP(GC, target);
6576                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6577                                             GENERIC2_INT_ENABLE, 1);
6578                         WREG32_SOC15_IP(GC, target, tmp);
6579                 }
6580                 break;
6581         default:
6582                 BUG(); /* kiq only support GENERIC2_INT now */
6583                 break;
6584         }
6585         return 0;
6586 }
6587 #endif
6588
6589 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
6590 {
6591         const unsigned int gcr_cntl =
6592                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
6593                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
6594                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
6595                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
6596                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
6597                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
6598                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
6599                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
6600
6601         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
6602         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
6603         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
6604         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6605         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6606         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6607         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6608         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6609         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
6610 }
6611
6612 static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
6613 {
6614         struct amdgpu_device *adev = ring->adev;
6615         int r;
6616
6617         if (amdgpu_sriov_vf(adev))
6618                 return -EINVAL;
6619
6620         r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
6621         if (r)
6622                 return r;
6623
6624         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6625         if (unlikely(r != 0)) {
6626                 dev_err(adev->dev, "fail to resv mqd_obj\n");
6627                 return r;
6628         }
6629         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6630         if (!r) {
6631                 r = gfx_v11_0_kgq_init_queue(ring, true);
6632                 amdgpu_bo_kunmap(ring->mqd_obj);
6633                 ring->mqd_ptr = NULL;
6634         }
6635         amdgpu_bo_unreserve(ring->mqd_obj);
6636         if (r) {
6637                 dev_err(adev->dev, "fail to unresv mqd_obj\n");
6638                 return r;
6639         }
6640
6641         r = amdgpu_mes_map_legacy_queue(adev, ring);
6642         if (r) {
6643                 dev_err(adev->dev, "failed to remap kgq\n");
6644                 return r;
6645         }
6646
6647         return amdgpu_ring_test_ring(ring);
6648 }
6649
6650 static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
6651 {
6652         struct amdgpu_device *adev = ring->adev;
6653         int r = 0;
6654
6655         if (amdgpu_sriov_vf(adev))
6656                 return -EINVAL;
6657
6658         r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
6659         if (r) {
6660                 dev_err(adev->dev, "reset via MMIO failed %d\n", r);
6661                 return r;
6662         }
6663
6664         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6665         if (unlikely(r != 0)) {
6666                 dev_err(adev->dev, "fail to resv mqd_obj\n");
6667                 return r;
6668         }
6669         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6670         if (!r) {
6671                 r = gfx_v11_0_kcq_init_queue(ring, true);
6672                 amdgpu_bo_kunmap(ring->mqd_obj);
6673                 ring->mqd_ptr = NULL;
6674         }
6675         amdgpu_bo_unreserve(ring->mqd_obj);
6676         if (r) {
6677                 dev_err(adev->dev, "fail to unresv mqd_obj\n");
6678                 return r;
6679         }
6680         r = amdgpu_mes_map_legacy_queue(adev, ring);
6681         if (r) {
6682                 dev_err(adev->dev, "failed to remap kcq\n");
6683                 return r;
6684         }
6685
6686         return amdgpu_ring_test_ring(ring);
6687 }
6688
6689 static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
6690 {
6691         struct amdgpu_device *adev = ip_block->adev;
6692         uint32_t i, j, k, reg, index = 0;
6693         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);
6694
6695         if (!adev->gfx.ip_dump_core)
6696                 return;
6697
6698         for (i = 0; i < reg_count; i++)
6699                 drm_printf(p, "%-50s \t 0x%08x\n",
6700                            gc_reg_list_11_0[i].reg_name,
6701                            adev->gfx.ip_dump_core[i]);
6702
6703         /* print compute queue registers for all instances */
6704         if (!adev->gfx.ip_dump_compute_queues)
6705                 return;
6706
6707         reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
6708         drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
6709                    adev->gfx.mec.num_mec,
6710                    adev->gfx.mec.num_pipe_per_mec,
6711                    adev->gfx.mec.num_queue_per_pipe);
6712
6713         for (i = 0; i < adev->gfx.mec.num_mec; i++) {
6714                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
6715                         for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
6716                                 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
6717                                 for (reg = 0; reg < reg_count; reg++) {
6718                                         drm_printf(p, "%-50s \t 0x%08x\n",
6719                                                    gc_cp_reg_list_11[reg].reg_name,
6720                                                    adev->gfx.ip_dump_compute_queues[index + reg]);
6721                                 }
6722                                 index += reg_count;
6723                         }
6724                 }
6725         }
6726
6727         /* print gfx queue registers for all instances */
6728         if (!adev->gfx.ip_dump_gfx_queues)
6729                 return;
6730
6731         index = 0;
6732         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);
6733         drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
6734                    adev->gfx.me.num_me,
6735                    adev->gfx.me.num_pipe_per_me,
6736                    adev->gfx.me.num_queue_per_pipe);
6737
6738         for (i = 0; i < adev->gfx.me.num_me; i++) {
6739                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
6740                         for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
6741                                 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
6742                                 for (reg = 0; reg < reg_count; reg++) {
6743                                         drm_printf(p, "%-50s \t 0x%08x\n",
6744                                                    gc_gfx_queue_reg_list_11[reg].reg_name,
6745                                                    adev->gfx.ip_dump_gfx_queues[index + reg]);
6746                                 }
6747                                 index += reg_count;
6748                         }
6749                 }
6750         }
6751 }
6752
6753 static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block)
6754 {
6755         struct amdgpu_device *adev = ip_block->adev;
6756         uint32_t i, j, k, reg, index = 0;
6757         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);
6758
6759         if (!adev->gfx.ip_dump_core)
6760                 return;
6761
6762         amdgpu_gfx_off_ctrl(adev, false);
6763         for (i = 0; i < reg_count; i++)
6764                 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i]));
6765         amdgpu_gfx_off_ctrl(adev, true);
6766
6767         /* dump compute queue registers for all instances */
6768         if (!adev->gfx.ip_dump_compute_queues)
6769                 return;
6770
6771         reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
6772         amdgpu_gfx_off_ctrl(adev, false);
6773         mutex_lock(&adev->srbm_mutex);
6774         for (i = 0; i < adev->gfx.mec.num_mec; i++) {
6775                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
6776                         for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
6777                                 /* ME0 is for GFX so start from 1 for CP */
6778                                 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
6779                                 for (reg = 0; reg < reg_count; reg++) {
6780                                         adev->gfx.ip_dump_compute_queues[index + reg] =
6781                                                 RREG32(SOC15_REG_ENTRY_OFFSET(
6782                                                         gc_cp_reg_list_11[reg]));
6783                                 }
6784                                 index += reg_count;
6785                         }
6786                 }
6787         }
6788         soc21_grbm_select(adev, 0, 0, 0, 0);
6789         mutex_unlock(&adev->srbm_mutex);
6790         amdgpu_gfx_off_ctrl(adev, true);
6791
6792         /* dump gfx queue registers for all instances */
6793         if (!adev->gfx.ip_dump_gfx_queues)
6794                 return;
6795
6796         index = 0;
6797         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);
6798         amdgpu_gfx_off_ctrl(adev, false);
6799         mutex_lock(&adev->srbm_mutex);
6800         for (i = 0; i < adev->gfx.me.num_me; i++) {
6801                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
6802                         for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
6803                                 soc21_grbm_select(adev, i, j, k, 0);
6804
6805                                 for (reg = 0; reg < reg_count; reg++) {
6806                                         adev->gfx.ip_dump_gfx_queues[index + reg] =
6807                                                 RREG32(SOC15_REG_ENTRY_OFFSET(
6808                                                         gc_gfx_queue_reg_list_11[reg]));
6809                                 }
6810                                 index += reg_count;
6811                         }
6812                 }
6813         }
6814         soc21_grbm_select(adev, 0, 0, 0, 0);
6815         mutex_unlock(&adev->srbm_mutex);
6816         amdgpu_gfx_off_ctrl(adev, true);
6817 }
6818
6819 static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
6820 {
6821         /* Emit the cleaner shader */
6822         amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
6823         amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */
6824 }
6825
6826 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
6827         .name = "gfx_v11_0",
6828         .early_init = gfx_v11_0_early_init,
6829         .late_init = gfx_v11_0_late_init,
6830         .sw_init = gfx_v11_0_sw_init,
6831         .sw_fini = gfx_v11_0_sw_fini,
6832         .hw_init = gfx_v11_0_hw_init,
6833         .hw_fini = gfx_v11_0_hw_fini,
6834         .suspend = gfx_v11_0_suspend,
6835         .resume = gfx_v11_0_resume,
6836         .is_idle = gfx_v11_0_is_idle,
6837         .wait_for_idle = gfx_v11_0_wait_for_idle,
6838         .soft_reset = gfx_v11_0_soft_reset,
6839         .check_soft_reset = gfx_v11_0_check_soft_reset,
6840         .post_soft_reset = gfx_v11_0_post_soft_reset,
6841         .set_clockgating_state = gfx_v11_0_set_clockgating_state,
6842         .set_powergating_state = gfx_v11_0_set_powergating_state,
6843         .get_clockgating_state = gfx_v11_0_get_clockgating_state,
6844         .dump_ip_state = gfx_v11_ip_dump,
6845         .print_ip_state = gfx_v11_ip_print,
6846 };
6847
6848 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
6849         .type = AMDGPU_RING_TYPE_GFX,
6850         .align_mask = 0xff,
6851         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6852         .support_64bit_ptrs = true,
6853         .secure_submission_supported = true,
6854         .get_rptr = gfx_v11_0_ring_get_rptr_gfx,
6855         .get_wptr = gfx_v11_0_ring_get_wptr_gfx,
6856         .set_wptr = gfx_v11_0_ring_set_wptr_gfx,
6857         .emit_frame_size = /* totally 247 maximum if 16 IBs */
6858                 5 + /* update_spm_vmid */
6859                 5 + /* COND_EXEC */
6860                 22 + /* SET_Q_PREEMPTION_MODE */
6861                 7 + /* PIPELINE_SYNC */
6862                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6863                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6864                 4 + /* VM_FLUSH */
6865                 8 + /* FENCE for VM_FLUSH */
6866                 20 + /* GDS switch */
6867                 5 + /* COND_EXEC */
6868                 7 + /* HDP_flush */
6869                 4 + /* VGT_flush */
6870                 31 + /* DE_META */
6871                 3 + /* CNTX_CTRL */
6872                 5 + /* HDP_INVL */
6873                 22 + /* SET_Q_PREEMPTION_MODE */
6874                 8 + 8 + /* FENCE x2 */
6875                 8 + /* gfx_v11_0_emit_mem_sync */
6876                 2, /* gfx_v11_0_ring_emit_cleaner_shader */
6877         .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */
6878         .emit_ib = gfx_v11_0_ring_emit_ib_gfx,
6879         .emit_fence = gfx_v11_0_ring_emit_fence,
6880         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6881         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6882         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6883         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6884         .test_ring = gfx_v11_0_ring_test_ring,
6885         .test_ib = gfx_v11_0_ring_test_ib,
6886         .insert_nop = gfx_v11_ring_insert_nop,
6887         .pad_ib = amdgpu_ring_generic_pad_ib,
6888         .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
6889         .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,
6890         .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
6891         .preempt_ib = gfx_v11_0_ring_preempt_ib,
6892         .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
6893         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6894         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6895         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6896         .soft_recovery = gfx_v11_0_ring_soft_recovery,
6897         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6898         .reset = gfx_v11_0_reset_kgq,
6899         .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader,
6900         .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
6901         .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
6902 };
6903
6904 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
6905         .type = AMDGPU_RING_TYPE_COMPUTE,
6906         .align_mask = 0xff,
6907         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6908         .support_64bit_ptrs = true,
6909         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6910         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6911         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6912         .emit_frame_size =
6913                 5 + /* update_spm_vmid */
6914                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6915                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6916                 5 + /* hdp invalidate */
6917                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6918                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6919                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6920                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6921                 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
6922                 8 + /* gfx_v11_0_emit_mem_sync */
6923                 2, /* gfx_v11_0_ring_emit_cleaner_shader */
6924         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6925         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6926         .emit_fence = gfx_v11_0_ring_emit_fence,
6927         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6928         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6929         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6930         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6931         .test_ring = gfx_v11_0_ring_test_ring,
6932         .test_ib = gfx_v11_0_ring_test_ib,
6933         .insert_nop = gfx_v11_ring_insert_nop,
6934         .pad_ib = amdgpu_ring_generic_pad_ib,
6935         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6936         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6937         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6938         .soft_recovery = gfx_v11_0_ring_soft_recovery,
6939         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6940         .reset = gfx_v11_0_reset_kcq,
6941         .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader,
6942         .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
6943         .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
6944 };
6945
6946 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
6947         .type = AMDGPU_RING_TYPE_KIQ,
6948         .align_mask = 0xff,
6949         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6950         .support_64bit_ptrs = true,
6951         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6952         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6953         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6954         .emit_frame_size =
6955                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6956                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6957                 5 + /*hdp invalidate */
6958                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6959                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6960                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6961                 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6962         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6963         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6964         .emit_fence = gfx_v11_0_ring_emit_fence_kiq,
6965         .test_ring = gfx_v11_0_ring_test_ring,
6966         .test_ib = gfx_v11_0_ring_test_ib,
6967         .insert_nop = amdgpu_ring_insert_nop,
6968         .pad_ib = amdgpu_ring_generic_pad_ib,
6969         .emit_rreg = gfx_v11_0_ring_emit_rreg,
6970         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6971         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6972         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6973 };
6974
6975 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
6976 {
6977         int i;
6978
6979         adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6980
6981         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6982                 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6983
6984         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6985                 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6986 }
6987
6988 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = {
6989         .set = gfx_v11_0_set_eop_interrupt_state,
6990         .process = gfx_v11_0_eop_irq,
6991 };
6992
6993 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
6994         .set = gfx_v11_0_set_priv_reg_fault_state,
6995         .process = gfx_v11_0_priv_reg_irq,
6996 };
6997
6998 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = {
6999         .set = gfx_v11_0_set_bad_op_fault_state,
7000         .process = gfx_v11_0_bad_op_irq,
7001 };
7002
7003 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
7004         .set = gfx_v11_0_set_priv_inst_fault_state,
7005         .process = gfx_v11_0_priv_inst_irq,
7006 };
7007
7008 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
7009         .process = gfx_v11_0_rlc_gc_fed_irq,
7010 };
7011
7012 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
7013 {
7014         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7015         adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
7016
7017         adev->gfx.priv_reg_irq.num_types = 1;
7018         adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
7019
7020         adev->gfx.bad_op_irq.num_types = 1;
7021         adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs;
7022
7023         adev->gfx.priv_inst_irq.num_types = 1;
7024         adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
7025
7026         adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
7027         adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
7028
7029 }
7030
7031 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
7032 {
7033         if (adev->flags & AMD_IS_APU)
7034                 adev->gfx.imu.mode = MISSION_MODE;
7035         else
7036                 adev->gfx.imu.mode = DEBUG_MODE;
7037
7038         adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
7039 }
7040
7041 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev)
7042 {
7043         adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
7044 }
7045
7046 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev)
7047 {
7048         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
7049                             adev->gfx.config.max_sh_per_se *
7050                             adev->gfx.config.max_shader_engines;
7051
7052         adev->gds.gds_size = 0x1000;
7053         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
7054         adev->gds.gws_size = 64;
7055         adev->gds.oa_size = 16;
7056 }
7057
7058 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
7059 {
7060         /* set gfx eng mqd */
7061         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
7062                 sizeof(struct v11_gfx_mqd);
7063         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
7064                 gfx_v11_0_gfx_mqd_init;
7065         /* set compute eng mqd */
7066         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
7067                 sizeof(struct v11_compute_mqd);
7068         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
7069                 gfx_v11_0_compute_mqd_init;
7070 }
7071
7072 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
7073                                                           u32 bitmap)
7074 {
7075         u32 data;
7076
7077         if (!bitmap)
7078                 return;
7079
7080         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
7081         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
7082
7083         WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
7084 }
7085
7086 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
7087 {
7088         u32 data, wgp_bitmask;
7089         data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
7090         data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
7091
7092         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
7093         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
7094
7095         wgp_bitmask =
7096                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
7097
7098         return (~data) & wgp_bitmask;
7099 }
7100
7101 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
7102 {
7103         u32 wgp_idx, wgp_active_bitmap;
7104         u32 cu_bitmap_per_wgp, cu_active_bitmap;
7105
7106         wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev);
7107         cu_active_bitmap = 0;
7108
7109         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
7110                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
7111                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
7112                 if (wgp_active_bitmap & (1 << wgp_idx))
7113                         cu_active_bitmap |= cu_bitmap_per_wgp;
7114         }
7115
7116         return cu_active_bitmap;
7117 }
7118
7119 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
7120                                  struct amdgpu_cu_info *cu_info)
7121 {
7122         int i, j, k, counter, active_cu_number = 0;
7123         u32 mask, bitmap;
7124         unsigned disable_masks[8 * 2];
7125
7126         if (!adev || !cu_info)
7127                 return -EINVAL;
7128
7129         amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
7130
7131         mutex_lock(&adev->grbm_idx_mutex);
7132         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7133                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7134                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
7135                         if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1))
7136                                 continue;
7137                         mask = 1;
7138                         counter = 0;
7139                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0);
7140                         if (i < 8 && j < 2)
7141                                 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(
7142                                         adev, disable_masks[i * 2 + j]);
7143                         bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev);
7144
7145                         /**
7146                          * GFX11 could support more than 4 SEs, while the bitmap
7147                          * in cu_info struct is 4x4 and ioctl interface struct
7148                          * drm_amdgpu_info_device should keep stable.
7149                          * So we use last two columns of bitmap to store cu mask for
7150                          * SEs 4 to 7, the layout of the bitmap is as below:
7151                          *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
7152                          *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
7153                          *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
7154                          *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
7155                          *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
7156                          *    SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
7157                          *    SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
7158                          *    SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
7159                          */
7160                         cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
7161
7162                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
7163                                 if (bitmap & mask)
7164                                         counter++;
7165
7166                                 mask <<= 1;
7167                         }
7168                         active_cu_number += counter;
7169                 }
7170         }
7171         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
7172         mutex_unlock(&adev->grbm_idx_mutex);
7173
7174         cu_info->number = active_cu_number;
7175         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7176
7177         return 0;
7178 }
7179
7180 const struct amdgpu_ip_block_version gfx_v11_0_ip_block =
7181 {
7182         .type = AMD_IP_BLOCK_TYPE_GFX,
7183         .major = 11,
7184         .minor = 0,
7185         .rev = 0,
7186         .funcs = &gfx_v11_0_ip_funcs,
7187 };