drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      2
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
 109
 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 114
 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 119
 120 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 126 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 128 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 130 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 132 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 134 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 136 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 139
 140 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 142 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 144 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 146 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 148 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 150 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 152
 153 #define mmCPG_PSP_DEBUG                         0x5c10
 154 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 155 #define mmCPC_PSP_DEBUG                         0x5c11
 156 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 159
 160 //CC_GC_SA_UNIT_DISABLE
 161 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 165 //GC_USER_SA_UNIT_DISABLE
 166 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 170 //PA_SC_ENHANCE_3
 171 #define mmPA_SC_ENHANCE_3                       0x1085
 172 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 175
 176 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 178
 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 183
 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 186
 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 189
 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 196
 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 208
 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 215
 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 222
 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 229
 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 236
 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 243
 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 250
 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 257
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 264
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 271
 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 278
 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
 280         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
 281         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
 282         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
 283         SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
 284         SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
 285         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
 286         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
 287         SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
 288         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
 289         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
 290         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
 291         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
 292         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
 293         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
 294         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
 295         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
 296         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
 297         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
 298         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
 299         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
 300         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
 301         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
 302         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
 303         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
 304         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
 305         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
 306         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
 307         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
 308         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
 309         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
 310         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
 311         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
 312         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
 313         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
 314         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
 315         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
 316         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
 317         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
 318         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
 319         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
 320         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
 321         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
 322         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
 323         SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
 324         SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
 325         SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
 326         SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
 327         SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
 328         SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
 329         SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
 330         SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
 331         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
 332         SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
 333         SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
 334         SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
 335         SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
 336         SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
 337         SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
 338         SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
 339         SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
 340         SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
 341         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
 342         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
 343         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
 344         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
 345         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
 346         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
 347         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
 348         SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
 349         SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
 350         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
 351         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
 352         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
 353         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
 354         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
 355         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
 356         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
 357         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
 358         SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
 359         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
 360         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
 361         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
 362         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
 363         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
 364         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
 365         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
 366         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
 367         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
 368         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
 369         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
 370         /* cp header registers */
 371         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
 372         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
 373         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
 374         SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
 375         SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
 376         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
 377         /* SE status registers */
 378         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
 379         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
 380         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
 381         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 382 };
 383
 384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
 385         /* compute registers */
 386         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
 387         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
 388         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
 389         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
 390         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
 391         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
 392         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
 393         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
 394         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
 395         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
 396         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
 397         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
 398         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
 399         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
 400         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
 401         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
 402         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
 403         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
 404         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
 405         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
 406         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
 407         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
 408         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
 409         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
 410         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
 411         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
 412         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
 413         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
 414         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
 415         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
 416         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
 417         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
 418         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
 419         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
 420         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
 421         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
 422         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
 423         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
 424         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
 425 };
 426
 427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
 428         /* gfx queue registers */
 429         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
 430         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
 431         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
 432         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
 433         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
 434         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
 435         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
 436         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
 437         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
 438         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
 439         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
 440         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
 441         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
 442         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
 443         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
 444         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
 445         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
 446         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
 447         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
 448         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
 449         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
 450         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
 451         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
 452 };
 453
 454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 495 };
 496
 497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
 498         /* Pending on emulation bring up */
 499 };
 500
 501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1554 };
1555
1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1595 };
1596
1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1640 };
1641
1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1643         /* Pending on emulation bring up */
1644 };
1645
1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2267 };
2268
2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2270         /* Pending on emulation bring up */
2271 };
2272
2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3326 };
3327
3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3372 };
3373
3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3375         /* Pending on emulation bring up */
3376 };
3377
3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3420
3421         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3423 };
3424
3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3450
3451         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3453 };
3454
3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3476 };
3477
3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3515 };
3516
3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3550 };
3551
3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3587 };
3588
3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3612 };
3613
3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3637 };
3638
3639 #define DEFAULT_SH_MEM_CONFIG \
3640         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3641          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3642          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3643          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3644
3645 /* TODO: pending on golden setting value of gb address config */
3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3647
3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3654                                  struct amdgpu_cu_info *cu_info);
3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3657                                    u32 sh_num, u32 instance, int xcc_id);
3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3659
3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3671                                            uint16_t pasid, uint32_t flush_type,
3672                                            bool all_hub, uint8_t dst_sel);
3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3674                                                unsigned int vmid);
3675
3676 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3677                                           enum amd_powergating_state state);
3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3679 {
3680         struct amdgpu_device *adev = kiq_ring->adev;
3681         u64 shader_mc_addr;
3682
3683         /* Cleaner shader MC address */
3684         shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
3685
3686         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3687         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3688                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3689         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3690         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3691         amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
3692         amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
3693         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3694         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3695 }
3696
3697 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3698                                  struct amdgpu_ring *ring)
3699 {
3700         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3701         uint64_t wptr_addr = ring->wptr_gpu_addr;
3702         uint32_t eng_sel = 0;
3703
3704         switch (ring->funcs->type) {
3705         case AMDGPU_RING_TYPE_COMPUTE:
3706                 eng_sel = 0;
3707                 break;
3708         case AMDGPU_RING_TYPE_GFX:
3709                 eng_sel = 4;
3710                 break;
3711         case AMDGPU_RING_TYPE_MES:
3712                 eng_sel = 5;
3713                 break;
3714         default:
3715                 WARN_ON(1);
3716         }
3717
3718         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3719         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3720         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3721                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3722                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3723                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3724                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3725                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3726                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3727                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3728                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3729                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3730         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3731         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3732         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3733         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3734         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3735 }
3736
3737 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3738                                    struct amdgpu_ring *ring,
3739                                    enum amdgpu_unmap_queues_action action,
3740                                    u64 gpu_addr, u64 seq)
3741 {
3742         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3743
3744         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3745         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3746                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3747                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3748                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3749                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3750         amdgpu_ring_write(kiq_ring,
3751                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3752
3753         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3754                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3755                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3756                 amdgpu_ring_write(kiq_ring, seq);
3757         } else {
3758                 amdgpu_ring_write(kiq_ring, 0);
3759                 amdgpu_ring_write(kiq_ring, 0);
3760                 amdgpu_ring_write(kiq_ring, 0);
3761         }
3762 }
3763
3764 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3765                                    struct amdgpu_ring *ring,
3766                                    u64 addr,
3767                                    u64 seq)
3768 {
3769         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3770
3771         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3772         amdgpu_ring_write(kiq_ring,
3773                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3774                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3775                           PACKET3_QUERY_STATUS_COMMAND(2));
3776         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3777                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3778                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3779         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3780         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3781         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3782         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3783 }
3784
3785 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3786                                 uint16_t pasid, uint32_t flush_type,
3787                                 bool all_hub)
3788 {
3789         gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3790 }
3791
3792 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3793         .kiq_set_resources = gfx10_kiq_set_resources,
3794         .kiq_map_queues = gfx10_kiq_map_queues,
3795         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3796         .kiq_query_status = gfx10_kiq_query_status,
3797         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3798         .set_resources_size = 8,
3799         .map_queues_size = 7,
3800         .unmap_queues_size = 6,
3801         .query_status_size = 7,
3802         .invalidate_tlbs_size = 2,
3803 };
3804
3805 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3806 {
3807         adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3808 }
3809
3810 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3811 {
3812         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3813         case IP_VERSION(10, 1, 10):
3814                 soc15_program_register_sequence(adev,
3815                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3816                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3817                 break;
3818         case IP_VERSION(10, 1, 1):
3819                 soc15_program_register_sequence(adev,
3820                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3821                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3822                 break;
3823         case IP_VERSION(10, 1, 2):
3824                 soc15_program_register_sequence(adev,
3825                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3826                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3827                 break;
3828         default:
3829                 break;
3830         }
3831 }
3832
3833 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3834 {
3835         if (amdgpu_sriov_vf(adev))
3836                 return;
3837
3838         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3839         case IP_VERSION(10, 1, 10):
3840                 soc15_program_register_sequence(adev,
3841                                                 golden_settings_gc_10_1,
3842                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3843                 soc15_program_register_sequence(adev,
3844                                                 golden_settings_gc_10_0_nv10,
3845                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3846                 break;
3847         case IP_VERSION(10, 1, 1):
3848                 soc15_program_register_sequence(adev,
3849                                                 golden_settings_gc_10_1_1,
3850                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3851                 soc15_program_register_sequence(adev,
3852                                                 golden_settings_gc_10_1_nv14,
3853                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3854                 break;
3855         case IP_VERSION(10, 1, 2):
3856                 soc15_program_register_sequence(adev,
3857                                                 golden_settings_gc_10_1_2,
3858                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3859                 soc15_program_register_sequence(adev,
3860                                                 golden_settings_gc_10_1_2_nv12,
3861                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3862                 break;
3863         case IP_VERSION(10, 3, 0):
3864                 soc15_program_register_sequence(adev,
3865                                                 golden_settings_gc_10_3,
3866                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3867                 soc15_program_register_sequence(adev,
3868                                                 golden_settings_gc_10_3_sienna_cichlid,
3869                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3870                 break;
3871         case IP_VERSION(10, 3, 2):
3872                 soc15_program_register_sequence(adev,
3873                                                 golden_settings_gc_10_3_2,
3874                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3875                 break;
3876         case IP_VERSION(10, 3, 1):
3877                 soc15_program_register_sequence(adev,
3878                                                 golden_settings_gc_10_3_vangogh,
3879                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3880                 break;
3881         case IP_VERSION(10, 3, 3):
3882                 soc15_program_register_sequence(adev,
3883                                                 golden_settings_gc_10_3_3,
3884                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3885                 break;
3886         case IP_VERSION(10, 3, 4):
3887                 soc15_program_register_sequence(adev,
3888                                                 golden_settings_gc_10_3_4,
3889                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3890                 break;
3891         case IP_VERSION(10, 3, 5):
3892                 soc15_program_register_sequence(adev,
3893                                                 golden_settings_gc_10_3_5,
3894                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3895                 break;
3896         case IP_VERSION(10, 1, 3):
3897         case IP_VERSION(10, 1, 4):
3898                 soc15_program_register_sequence(adev,
3899                                                 golden_settings_gc_10_0_cyan_skillfish,
3900                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3901                 break;
3902         case IP_VERSION(10, 3, 6):
3903                 soc15_program_register_sequence(adev,
3904                                                 golden_settings_gc_10_3_6,
3905                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3906                 break;
3907         case IP_VERSION(10, 3, 7):
3908                 soc15_program_register_sequence(adev,
3909                                                 golden_settings_gc_10_3_7,
3910                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3911                 break;
3912         default:
3913                 break;
3914         }
3915         gfx_v10_0_init_spm_golden_registers(adev);
3916 }
3917
3918 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3919                                        bool wc, uint32_t reg, uint32_t val)
3920 {
3921         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3922         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3923                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3924         amdgpu_ring_write(ring, reg);
3925         amdgpu_ring_write(ring, 0);
3926         amdgpu_ring_write(ring, val);
3927 }
3928
3929 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3930                                   int mem_space, int opt, uint32_t addr0,
3931                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3932                                   uint32_t inv)
3933 {
3934         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3935         amdgpu_ring_write(ring,
3936                           /* memory (1) or register (0) */
3937                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3938                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3939                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3940                            WAIT_REG_MEM_ENGINE(eng_sel)));
3941
3942         if (mem_space)
3943                 BUG_ON(addr0 & 0x3); /* Dword align */
3944         amdgpu_ring_write(ring, addr0);
3945         amdgpu_ring_write(ring, addr1);
3946         amdgpu_ring_write(ring, ref);
3947         amdgpu_ring_write(ring, mask);
3948         amdgpu_ring_write(ring, inv); /* poll interval */
3949 }
3950
3951 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3952 {
3953         struct amdgpu_device *adev = ring->adev;
3954         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3955         uint32_t tmp = 0;
3956         unsigned int i;
3957         int r;
3958
3959         WREG32(scratch, 0xCAFEDEAD);
3960         r = amdgpu_ring_alloc(ring, 3);
3961         if (r) {
3962                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3963                           ring->idx, r);
3964                 return r;
3965         }
3966
3967         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3968         amdgpu_ring_write(ring, scratch -
3969                           PACKET3_SET_UCONFIG_REG_START);
3970         amdgpu_ring_write(ring, 0xDEADBEEF);
3971         amdgpu_ring_commit(ring);
3972
3973         for (i = 0; i < adev->usec_timeout; i++) {
3974                 tmp = RREG32(scratch);
3975                 if (tmp == 0xDEADBEEF)
3976                         break;
3977                 if (amdgpu_emu_mode == 1)
3978                         msleep(1);
3979                 else
3980                         udelay(1);
3981         }
3982
3983         if (i >= adev->usec_timeout)
3984                 r = -ETIMEDOUT;
3985
3986         return r;
3987 }
3988
3989 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3990 {
3991         struct amdgpu_device *adev = ring->adev;
3992         struct amdgpu_ib ib;
3993         struct dma_fence *f = NULL;
3994         unsigned int index;
3995         uint64_t gpu_addr;
3996         volatile uint32_t *cpu_ptr;
3997         long r;
3998
3999         memset(&ib, 0, sizeof(ib));
4000
4001         r = amdgpu_device_wb_get(adev, &index);
4002         if (r)
4003                 return r;
4004
4005         gpu_addr = adev->wb.gpu_addr + (index * 4);
4006         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
4007         cpu_ptr = &adev->wb.wb[index];
4008
4009         r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
4010         if (r) {
4011                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
4012                 goto err1;
4013         }
4014
4015         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
4016         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
4017         ib.ptr[2] = lower_32_bits(gpu_addr);
4018         ib.ptr[3] = upper_32_bits(gpu_addr);
4019         ib.ptr[4] = 0xDEADBEEF;
4020         ib.length_dw = 5;
4021
4022         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4023         if (r)
4024                 goto err2;
4025
4026         r = dma_fence_wait_timeout(f, false, timeout);
4027         if (r == 0) {
4028                 r = -ETIMEDOUT;
4029                 goto err2;
4030         } else if (r < 0) {
4031                 goto err2;
4032         }
4033
4034         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
4035                 r = 0;
4036         else
4037                 r = -EINVAL;
4038 err2:
4039         amdgpu_ib_free(&ib, NULL);
4040         dma_fence_put(f);
4041 err1:
4042         amdgpu_device_wb_free(adev, index);
4043         return r;
4044 }
4045
4046 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
4047 {
4048         amdgpu_ucode_release(&adev->gfx.pfp_fw);
4049         amdgpu_ucode_release(&adev->gfx.me_fw);
4050         amdgpu_ucode_release(&adev->gfx.ce_fw);
4051         amdgpu_ucode_release(&adev->gfx.rlc_fw);
4052         amdgpu_ucode_release(&adev->gfx.mec_fw);
4053         amdgpu_ucode_release(&adev->gfx.mec2_fw);
4054
4055         kfree(adev->gfx.rlc.register_list_format);
4056 }
4057
4058 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
4059 {
4060         adev->gfx.cp_fw_write_wait = false;
4061
4062         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4063         case IP_VERSION(10, 1, 10):
4064         case IP_VERSION(10, 1, 2):
4065         case IP_VERSION(10, 1, 1):
4066         case IP_VERSION(10, 1, 3):
4067         case IP_VERSION(10, 1, 4):
4068                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
4069                     (adev->gfx.me_feature_version >= 27) &&
4070                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
4071                     (adev->gfx.pfp_feature_version >= 27) &&
4072                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
4073                     (adev->gfx.mec_feature_version >= 27))
4074                         adev->gfx.cp_fw_write_wait = true;
4075                 break;
4076         case IP_VERSION(10, 3, 0):
4077         case IP_VERSION(10, 3, 2):
4078         case IP_VERSION(10, 3, 1):
4079         case IP_VERSION(10, 3, 4):
4080         case IP_VERSION(10, 3, 5):
4081         case IP_VERSION(10, 3, 6):
4082         case IP_VERSION(10, 3, 3):
4083         case IP_VERSION(10, 3, 7):
4084                 adev->gfx.cp_fw_write_wait = true;
4085                 break;
4086         default:
4087                 break;
4088         }
4089
4090         if (!adev->gfx.cp_fw_write_wait)
4091                 DRM_WARN_ONCE("CP firmware version too old, please update!");
4092 }
4093
4094 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4095 {
4096         bool ret = false;
4097
4098         switch (adev->pdev->revision) {
4099         case 0xc2:
4100         case 0xc3:
4101                 ret = true;
4102                 break;
4103         default:
4104                 ret = false;
4105                 break;
4106         }
4107
4108         return ret;
4109 }
4110
4111 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4112 {
4113         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4114         case IP_VERSION(10, 1, 10):
4115                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4116                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4117                 break;
4118         default:
4119                 break;
4120         }
4121 }
4122
4123 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4124 {
4125         char fw_name[53];
4126         char ucode_prefix[30];
4127         const char *wks = "";
4128         int err;
4129         const struct rlc_firmware_header_v2_0 *rlc_hdr;
4130         uint16_t version_major;
4131         uint16_t version_minor;
4132
4133         DRM_DEBUG("\n");
4134
4135         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4136             (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4137                 wks = "_wks";
4138         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4139
4140         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
4141                                    AMDGPU_UCODE_REQUIRED,
4142                                    "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4143         if (err)
4144                 goto out;
4145         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4146
4147         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
4148                                    AMDGPU_UCODE_REQUIRED,
4149                                    "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4150         if (err)
4151                 goto out;
4152         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4153
4154         err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
4155                                    AMDGPU_UCODE_REQUIRED,
4156                                    "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4157         if (err)
4158                 goto out;
4159         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4160
4161         if (!amdgpu_sriov_vf(adev)) {
4162                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4163                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4164                 if (err)
4165                         goto out;
4166
4167                 /* don't validate this firmware. There are apparently firmwares
4168                  * in the wild with incorrect size in the header
4169                  */
4170                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4171                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4172                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4173                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4174                 if (err)
4175                         goto out;
4176         }
4177
4178         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
4179                                    AMDGPU_UCODE_REQUIRED,
4180                                    "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4181         if (err)
4182                 goto out;
4183         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4184         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4185
4186         err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
4187                                    AMDGPU_UCODE_REQUIRED,
4188                                    "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4189         if (!err) {
4190                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4191                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4192         } else {
4193                 err = 0;
4194                 adev->gfx.mec2_fw = NULL;
4195         }
4196
4197         gfx_v10_0_check_fw_write_wait(adev);
4198 out:
4199         if (err) {
4200                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4201                 amdgpu_ucode_release(&adev->gfx.me_fw);
4202                 amdgpu_ucode_release(&adev->gfx.ce_fw);
4203                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4204                 amdgpu_ucode_release(&adev->gfx.mec_fw);
4205                 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4206         }
4207
4208         gfx_v10_0_check_gfxoff_flag(adev);
4209
4210         return err;
4211 }
4212
4213 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4214 {
4215         u32 count = 0;
4216         const struct cs_section_def *sect = NULL;
4217         const struct cs_extent_def *ext = NULL;
4218
4219         /* begin clear state */
4220         count += 2;
4221         /* context control state */
4222         count += 3;
4223
4224         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4225                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4226                         if (sect->id == SECT_CONTEXT)
4227                                 count += 2 + ext->reg_count;
4228                         else
4229                                 return 0;
4230                 }
4231         }
4232
4233         /* set PA_SC_TILE_STEERING_OVERRIDE */
4234         count += 3;
4235         /* end clear state */
4236         count += 2;
4237         /* clear state */
4238         count += 2;
4239
4240         return count;
4241 }
4242
4243 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4244                                     volatile u32 *buffer)
4245 {
4246         u32 count = 0, i;
4247         const struct cs_section_def *sect = NULL;
4248         const struct cs_extent_def *ext = NULL;
4249         int ctx_reg_offset;
4250
4251         if (adev->gfx.rlc.cs_data == NULL)
4252                 return;
4253         if (buffer == NULL)
4254                 return;
4255
4256         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4257         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4258
4259         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4260         buffer[count++] = cpu_to_le32(0x80000000);
4261         buffer[count++] = cpu_to_le32(0x80000000);
4262
4263         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4264                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4265                         if (sect->id == SECT_CONTEXT) {
4266                                 buffer[count++] =
4267                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4268                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4269                                                 PACKET3_SET_CONTEXT_REG_START);
4270                                 for (i = 0; i < ext->reg_count; i++)
4271                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4272                         } else {
4273                                 return;
4274                         }
4275                 }
4276         }
4277
4278         ctx_reg_offset =
4279                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4280         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4281         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4282         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4283
4284         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4285         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4286
4287         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4288         buffer[count++] = cpu_to_le32(0);
4289 }
4290
4291 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4292 {
4293         /* clear state block */
4294         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4295                         &adev->gfx.rlc.clear_state_gpu_addr,
4296                         (void **)&adev->gfx.rlc.cs_ptr);
4297
4298         /* jump table block */
4299         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4300                         &adev->gfx.rlc.cp_table_gpu_addr,
4301                         (void **)&adev->gfx.rlc.cp_table_ptr);
4302 }
4303
4304 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4305 {
4306         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4307
4308         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4309         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4310         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4311         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4312         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4313         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4314         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4315         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4316         case IP_VERSION(10, 3, 0):
4317                 reg_access_ctrl->spare_int =
4318                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4319                 break;
4320         default:
4321                 reg_access_ctrl->spare_int =
4322                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4323                 break;
4324         }
4325         adev->gfx.rlc.rlcg_reg_access_supported = true;
4326 }
4327
4328 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4329 {
4330         const struct cs_section_def *cs_data;
4331         int r;
4332
4333         adev->gfx.rlc.cs_data = gfx10_cs_data;
4334
4335         cs_data = adev->gfx.rlc.cs_data;
4336
4337         if (cs_data) {
4338                 /* init clear state block */
4339                 r = amdgpu_gfx_rlc_init_csb(adev);
4340                 if (r)
4341                         return r;
4342         }
4343
4344         return 0;
4345 }
4346
4347 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4348 {
4349         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4350         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4351 }
4352
4353 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4354 {
4355         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4356
4357         amdgpu_gfx_graphics_queue_acquire(adev);
4358 }
4359
4360 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4361 {
4362         int r;
4363         u32 *hpd;
4364         const __le32 *fw_data = NULL;
4365         unsigned int fw_size;
4366         u32 *fw = NULL;
4367         size_t mec_hpd_size;
4368
4369         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4370
4371         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4372
4373         /* take ownership of the relevant compute queues */
4374         amdgpu_gfx_compute_queue_acquire(adev);
4375         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4376
4377         if (mec_hpd_size) {
4378                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4379                                               AMDGPU_GEM_DOMAIN_GTT,
4380                                               &adev->gfx.mec.hpd_eop_obj,
4381                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4382                                               (void **)&hpd);
4383                 if (r) {
4384                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4385                         gfx_v10_0_mec_fini(adev);
4386                         return r;
4387                 }
4388
4389                 memset(hpd, 0, mec_hpd_size);
4390
4391                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4392                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4393         }
4394
4395         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4396                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4397
4398                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4399                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4400                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4401
4402                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4403                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4404                                               &adev->gfx.mec.mec_fw_obj,
4405                                               &adev->gfx.mec.mec_fw_gpu_addr,
4406                                               (void **)&fw);
4407                 if (r) {
4408                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4409                         gfx_v10_0_mec_fini(adev);
4410                         return r;
4411                 }
4412
4413                 memcpy(fw, fw_data, fw_size);
4414
4415                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4416                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4417         }
4418
4419         return 0;
4420 }
4421
4422 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4423 {
4424         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4425                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4426                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4427         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4428 }
4429
4430 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4431                            uint32_t thread, uint32_t regno,
4432                            uint32_t num, uint32_t *out)
4433 {
4434         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4435                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4436                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4437                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4438                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4439         while (num--)
4440                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4441 }
4442
4443 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4444 {
4445         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4446          * field when performing a select_se_sh so it should be
4447          * zero here
4448          */
4449         WARN_ON(simd != 0);
4450
4451         /* type 2 wave data */
4452         dst[(*no_fields)++] = 2;
4453         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4454         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4455         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4456         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4457         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4458         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4459         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4460         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4461         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4462         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4463         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4464         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4465         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4466         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4467         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4468         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4469 }
4470
4471 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4472                                      uint32_t wave, uint32_t start,
4473                                      uint32_t size, uint32_t *dst)
4474 {
4475         WARN_ON(simd != 0);
4476
4477         wave_read_regs(
4478                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4479                 dst);
4480 }
4481
4482 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4483                                       uint32_t wave, uint32_t thread,
4484                                       uint32_t start, uint32_t size,
4485                                       uint32_t *dst)
4486 {
4487         wave_read_regs(
4488                 adev, wave, thread,
4489                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4490 }
4491
4492 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4493                                        u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4494 {
4495         nv_grbm_select(adev, me, pipe, q, vm);
4496 }
4497
4498 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4499                                           bool enable)
4500 {
4501         uint32_t data, def;
4502
4503         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4504
4505         if (enable)
4506                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4507         else
4508                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4509
4510         if (data != def)
4511                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4512 }
4513
4514 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4515         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4516         .select_se_sh = &gfx_v10_0_select_se_sh,
4517         .read_wave_data = &gfx_v10_0_read_wave_data,
4518         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4519         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4520         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4521         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4522         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4523 };
4524
4525 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4526 {
4527         u32 gb_addr_config;
4528
4529         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4530         case IP_VERSION(10, 1, 10):
4531         case IP_VERSION(10, 1, 1):
4532         case IP_VERSION(10, 1, 2):
4533                 adev->gfx.config.max_hw_contexts = 8;
4534                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4535                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4536                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4537                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4538                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4539                 break;
4540         case IP_VERSION(10, 3, 0):
4541         case IP_VERSION(10, 3, 2):
4542         case IP_VERSION(10, 3, 1):
4543         case IP_VERSION(10, 3, 4):
4544         case IP_VERSION(10, 3, 5):
4545         case IP_VERSION(10, 3, 6):
4546         case IP_VERSION(10, 3, 3):
4547         case IP_VERSION(10, 3, 7):
4548                 adev->gfx.config.max_hw_contexts = 8;
4549                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4550                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4551                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4552                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4553                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4554                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4555                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4556                 break;
4557         case IP_VERSION(10, 1, 3):
4558         case IP_VERSION(10, 1, 4):
4559                 adev->gfx.config.max_hw_contexts = 8;
4560                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4561                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4562                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4563                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4564                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4565                 break;
4566         default:
4567                 BUG();
4568                 break;
4569         }
4570
4571         adev->gfx.config.gb_addr_config = gb_addr_config;
4572
4573         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4574                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4575                                       GB_ADDR_CONFIG, NUM_PIPES);
4576
4577         adev->gfx.config.max_tile_pipes =
4578                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4579
4580         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4581                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4582                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4583         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4584                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4585                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4586         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4587                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4588                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4589         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4590                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4591                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4592 }
4593
4594 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4595                                    int me, int pipe, int queue)
4596 {
4597         struct amdgpu_ring *ring;
4598         unsigned int irq_type;
4599         unsigned int hw_prio;
4600
4601         ring = &adev->gfx.gfx_ring[ring_id];
4602
4603         ring->me = me;
4604         ring->pipe = pipe;
4605         ring->queue = queue;
4606
4607         ring->ring_obj = NULL;
4608         ring->use_doorbell = true;
4609
4610         if (!ring_id)
4611                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4612         else
4613                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4614         ring->vm_hub = AMDGPU_GFXHUB(0);
4615         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4616
4617         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4618         hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4619                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4620         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4621                                 hw_prio, NULL);
4622 }
4623
4624 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4625                                        int mec, int pipe, int queue)
4626 {
4627         unsigned int irq_type;
4628         struct amdgpu_ring *ring;
4629         unsigned int hw_prio;
4630
4631         ring = &adev->gfx.compute_ring[ring_id];
4632
4633         /* mec0 is me1 */
4634         ring->me = mec + 1;
4635         ring->pipe = pipe;
4636         ring->queue = queue;
4637
4638         ring->ring_obj = NULL;
4639         ring->use_doorbell = true;
4640         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4641         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4642                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4643         ring->vm_hub = AMDGPU_GFXHUB(0);
4644         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4645
4646         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4647                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4648                 + ring->pipe;
4649         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4650                         AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4651         /* type-2 packets are deprecated on MEC, use type-3 instead */
4652         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4653                              hw_prio, NULL);
4654 }
4655
4656 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
4657 {
4658         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4659         uint32_t *ptr;
4660         uint32_t inst;
4661
4662         ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4663         if (!ptr) {
4664                 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
4665                 adev->gfx.ip_dump_core = NULL;
4666         } else {
4667                 adev->gfx.ip_dump_core = ptr;
4668         }
4669
4670         /* Allocate memory for compute queue registers for all the instances */
4671         reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
4672         inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
4673                 adev->gfx.mec.num_queue_per_pipe;
4674
4675         ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4676         if (!ptr) {
4677                 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
4678                 adev->gfx.ip_dump_compute_queues = NULL;
4679         } else {
4680                 adev->gfx.ip_dump_compute_queues = ptr;
4681         }
4682
4683         /* Allocate memory for gfx queue registers for all the instances */
4684         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
4685         inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
4686                 adev->gfx.me.num_queue_per_pipe;
4687
4688         ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4689         if (!ptr) {
4690                 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
4691                 adev->gfx.ip_dump_gfx_queues = NULL;
4692         } else {
4693                 adev->gfx.ip_dump_gfx_queues = ptr;
4694         }
4695 }
4696
4697 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
4698 {
4699         int i, j, k, r, ring_id = 0;
4700         int xcc_id = 0;
4701         struct amdgpu_device *adev = ip_block->adev;
4702
4703         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4704         case IP_VERSION(10, 1, 10):
4705         case IP_VERSION(10, 1, 1):
4706         case IP_VERSION(10, 1, 2):
4707         case IP_VERSION(10, 1, 3):
4708         case IP_VERSION(10, 1, 4):
4709                 adev->gfx.me.num_me = 1;
4710                 adev->gfx.me.num_pipe_per_me = 1;
4711                 adev->gfx.me.num_queue_per_pipe = 1;
4712                 adev->gfx.mec.num_mec = 2;
4713                 adev->gfx.mec.num_pipe_per_mec = 4;
4714                 adev->gfx.mec.num_queue_per_pipe = 8;
4715                 break;
4716         case IP_VERSION(10, 3, 0):
4717         case IP_VERSION(10, 3, 2):
4718         case IP_VERSION(10, 3, 1):
4719         case IP_VERSION(10, 3, 4):
4720         case IP_VERSION(10, 3, 5):
4721         case IP_VERSION(10, 3, 6):
4722         case IP_VERSION(10, 3, 3):
4723         case IP_VERSION(10, 3, 7):
4724                 adev->gfx.me.num_me = 1;
4725                 adev->gfx.me.num_pipe_per_me = 2;
4726                 adev->gfx.me.num_queue_per_pipe = 1;
4727                 adev->gfx.mec.num_mec = 2;
4728                 adev->gfx.mec.num_pipe_per_mec = 4;
4729                 adev->gfx.mec.num_queue_per_pipe = 4;
4730                 break;
4731         default:
4732                 adev->gfx.me.num_me = 1;
4733                 adev->gfx.me.num_pipe_per_me = 1;
4734                 adev->gfx.me.num_queue_per_pipe = 1;
4735                 adev->gfx.mec.num_mec = 1;
4736                 adev->gfx.mec.num_pipe_per_mec = 4;
4737                 adev->gfx.mec.num_queue_per_pipe = 8;
4738                 break;
4739         }
4740         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4741         default:
4742                 adev->gfx.enable_cleaner_shader = false;
4743                 break;
4744         }
4745
4746         /* KIQ event */
4747         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4748                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4749                               &adev->gfx.kiq[0].irq);
4750         if (r)
4751                 return r;
4752
4753         /* EOP Event */
4754         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4755                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4756                               &adev->gfx.eop_irq);
4757         if (r)
4758                 return r;
4759
4760         /* Bad opcode Event */
4761         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4762                               GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
4763                               &adev->gfx.bad_op_irq);
4764         if (r)
4765                 return r;
4766
4767         /* Privileged reg */
4768         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4769                               &adev->gfx.priv_reg_irq);
4770         if (r)
4771                 return r;
4772
4773         /* Privileged inst */
4774         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4775                               &adev->gfx.priv_inst_irq);
4776         if (r)
4777                 return r;
4778
4779         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4780
4781         gfx_v10_0_me_init(adev);
4782
4783         if (adev->gfx.rlc.funcs) {
4784                 if (adev->gfx.rlc.funcs->init) {
4785                         r = adev->gfx.rlc.funcs->init(adev);
4786                         if (r) {
4787                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4788                                 return r;
4789                         }
4790                 }
4791         }
4792
4793         r = gfx_v10_0_mec_init(adev);
4794         if (r) {
4795                 DRM_ERROR("Failed to init MEC BOs!\n");
4796                 return r;
4797         }
4798
4799         /* set up the gfx ring */
4800         for (i = 0; i < adev->gfx.me.num_me; i++) {
4801                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4802                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4803                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4804                                         continue;
4805
4806                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4807                                                             i, k, j);
4808                                 if (r)
4809                                         return r;
4810                                 ring_id++;
4811                         }
4812                 }
4813         }
4814
4815         ring_id = 0;
4816         /* set up the compute queues - allocate horizontally across pipes */
4817         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4818                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4819                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4820                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4821                                                                      k, j))
4822                                         continue;
4823
4824                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4825                                                                 i, k, j);
4826                                 if (r)
4827                                         return r;
4828
4829                                 ring_id++;
4830                         }
4831                 }
4832         }
4833         /* TODO: Add queue reset mask when FW fully supports it */
4834         adev->gfx.gfx_supported_reset =
4835                 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
4836         adev->gfx.compute_supported_reset =
4837                 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4838
4839         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4840         if (r) {
4841                 DRM_ERROR("Failed to init KIQ BOs!\n");
4842                 return r;
4843         }
4844
4845         r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4846         if (r)
4847                 return r;
4848
4849         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4850         if (r)
4851                 return r;
4852
4853         /* allocate visible FB for rlc auto-loading fw */
4854         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4855                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4856                 if (r)
4857                         return r;
4858         }
4859
4860         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4861
4862         gfx_v10_0_gpu_early_init(adev);
4863
4864         gfx_v10_0_alloc_ip_dump(adev);
4865
4866         r = amdgpu_gfx_sysfs_init(adev);
4867         if (r)
4868                 return r;
4869
4870         return 0;
4871 }
4872
4873 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4874 {
4875         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4876                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4877                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4878 }
4879
4880 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4881 {
4882         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4883                               &adev->gfx.ce.ce_fw_gpu_addr,
4884                               (void **)&adev->gfx.ce.ce_fw_ptr);
4885 }
4886
4887 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4888 {
4889         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4890                               &adev->gfx.me.me_fw_gpu_addr,
4891                               (void **)&adev->gfx.me.me_fw_ptr);
4892 }
4893
4894 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
4895 {
4896         int i;
4897         struct amdgpu_device *adev = ip_block->adev;
4898
4899         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4900                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4901         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4902                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4903
4904         amdgpu_gfx_mqd_sw_fini(adev, 0);
4905
4906         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4907         amdgpu_gfx_kiq_fini(adev, 0);
4908
4909         amdgpu_gfx_cleaner_shader_sw_fini(adev);
4910
4911         gfx_v10_0_pfp_fini(adev);
4912         gfx_v10_0_ce_fini(adev);
4913         gfx_v10_0_me_fini(adev);
4914         gfx_v10_0_rlc_fini(adev);
4915         gfx_v10_0_mec_fini(adev);
4916
4917         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4918                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4919
4920         gfx_v10_0_free_microcode(adev);
4921         amdgpu_gfx_sysfs_fini(adev);
4922
4923         kfree(adev->gfx.ip_dump_core);
4924         kfree(adev->gfx.ip_dump_compute_queues);
4925         kfree(adev->gfx.ip_dump_gfx_queues);
4926
4927         return 0;
4928 }
4929
4930 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4931                                    u32 sh_num, u32 instance, int xcc_id)
4932 {
4933         u32 data;
4934
4935         if (instance == 0xffffffff)
4936                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4937                                      INSTANCE_BROADCAST_WRITES, 1);
4938         else
4939                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4940                                      instance);
4941
4942         if (se_num == 0xffffffff)
4943                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4944                                      1);
4945         else
4946                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4947
4948         if (sh_num == 0xffffffff)
4949                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4950                                      1);
4951         else
4952                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4953
4954         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4955 }
4956
4957 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4958 {
4959         u32 data, mask;
4960
4961         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4962         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4963
4964         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4965         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4966
4967         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4968                                          adev->gfx.config.max_sh_per_se);
4969
4970         return (~data) & mask;
4971 }
4972
4973 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4974 {
4975         int i, j;
4976         u32 data;
4977         u32 active_rbs = 0;
4978         u32 bitmap;
4979         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4980                                         adev->gfx.config.max_sh_per_se;
4981
4982         mutex_lock(&adev->grbm_idx_mutex);
4983         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4984                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4985                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4986                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
4987                               IP_VERSION(10, 3, 0)) ||
4988                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4989                               IP_VERSION(10, 3, 3)) ||
4990                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4991                               IP_VERSION(10, 3, 6))) &&
4992                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4993                                 continue;
4994                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4995                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4996                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4997                                                rb_bitmap_width_per_sh);
4998                 }
4999         }
5000         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5001         mutex_unlock(&adev->grbm_idx_mutex);
5002
5003         adev->gfx.config.backend_enable_mask = active_rbs;
5004         adev->gfx.config.num_rbs = hweight32(active_rbs);
5005 }
5006
5007 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5008 {
5009         uint32_t num_sc;
5010         uint32_t enabled_rb_per_sh;
5011         uint32_t active_rb_bitmap;
5012         uint32_t num_rb_per_sc;
5013         uint32_t num_packer_per_sc;
5014         uint32_t pa_sc_tile_steering_override;
5015
5016         /* for ASICs that integrates GFX v10.3
5017          * pa_sc_tile_steering_override should be set to 0
5018          */
5019         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
5020                 return 0;
5021
5022         /* init num_sc */
5023         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5024                         adev->gfx.config.num_sc_per_sh;
5025         /* init num_rb_per_sc */
5026         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5027         enabled_rb_per_sh = hweight32(active_rb_bitmap);
5028         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5029         /* init num_packer_per_sc */
5030         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5031
5032         pa_sc_tile_steering_override = 0;
5033         pa_sc_tile_steering_override |=
5034                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5035                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5036         pa_sc_tile_steering_override |=
5037                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5038                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5039         pa_sc_tile_steering_override |=
5040                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5041                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5042
5043         return pa_sc_tile_steering_override;
5044 }
5045
5046 #define DEFAULT_SH_MEM_BASES    (0x6000)
5047
5048 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
5049                                 uint32_t first_vmid,
5050                                 uint32_t last_vmid)
5051 {
5052         uint32_t data;
5053         uint32_t trap_config_vmid_mask = 0;
5054         int i;
5055
5056         /* Calculate trap config vmid mask */
5057         for (i = first_vmid; i < last_vmid; i++)
5058                 trap_config_vmid_mask |= (1 << i);
5059
5060         data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
5061                         VMID_SEL, trap_config_vmid_mask);
5062         data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
5063                         TRAP_EN, 1);
5064         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
5065         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
5066
5067         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
5068         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
5069 }
5070
5071 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5072 {
5073         int i;
5074         uint32_t sh_mem_bases;
5075
5076         /*
5077          * Configure apertures:
5078          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5079          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5080          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5081          */
5082         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5083
5084         mutex_lock(&adev->srbm_mutex);
5085         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5086                 nv_grbm_select(adev, 0, 0, 0, i);
5087                 /* CP and shaders */
5088                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5089                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5090         }
5091         nv_grbm_select(adev, 0, 0, 0, 0);
5092         mutex_unlock(&adev->srbm_mutex);
5093
5094         /*
5095          * Initialize all compute VMIDs to have no GDS, GWS, or OA
5096          * access. These should be enabled by FW for target VMIDs.
5097          */
5098         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5099                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5100                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5101                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5102                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5103         }
5104
5105         gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
5106                                         AMDGPU_NUM_VMID);
5107 }
5108
5109 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5110 {
5111         int vmid;
5112
5113         /*
5114          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5115          * access. Compute VMIDs should be enabled by FW for target VMIDs,
5116          * the driver can enable them for graphics. VMID0 should maintain
5117          * access so that HWS firmware can save/restore entries.
5118          */
5119         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5120                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5121                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5122                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5123                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5124         }
5125 }
5126
5127
5128 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5129 {
5130         int i, j, k;
5131         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5132         u32 tmp, wgp_active_bitmap = 0;
5133         u32 gcrd_targets_disable_tcp = 0;
5134         u32 utcl_invreq_disable = 0;
5135         /*
5136          * GCRD_TARGETS_DISABLE field contains
5137          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5138          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5139          */
5140         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5141                 2 * max_wgp_per_sh + /* TCP */
5142                 max_wgp_per_sh + /* SQC */
5143                 4); /* GL1C */
5144         /*
5145          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5146          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5147          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5148          */
5149         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5150                 2 * max_wgp_per_sh + /* TCP */
5151                 2 * max_wgp_per_sh + /* SQC */
5152                 4 + /* RMI */
5153                 1); /* SQG */
5154
5155         mutex_lock(&adev->grbm_idx_mutex);
5156         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5157                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5158                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5159                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5160                         /*
5161                          * Set corresponding TCP bits for the inactive WGPs in
5162                          * GCRD_SA_TARGETS_DISABLE
5163                          */
5164                         gcrd_targets_disable_tcp = 0;
5165                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5166                         utcl_invreq_disable = 0;
5167
5168                         for (k = 0; k < max_wgp_per_sh; k++) {
5169                                 if (!(wgp_active_bitmap & (1 << k))) {
5170                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
5171                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5172                                         utcl_invreq_disable |= (3 << (2 * k)) |
5173                                                 (3 << (2 * (max_wgp_per_sh + k)));
5174                                 }
5175                         }
5176
5177                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5178                         /* only override TCP & SQC bits */
5179                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5180                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5181                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5182
5183                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5184                         /* only override TCP & SQC bits */
5185                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5186                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5187                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5188                 }
5189         }
5190
5191         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5192         mutex_unlock(&adev->grbm_idx_mutex);
5193 }
5194
5195 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5196 {
5197         /* TCCs are global (not instanced). */
5198         uint32_t tcc_disable;
5199
5200         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5201                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5202                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5203         } else {
5204                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5205                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5206         }
5207
5208         adev->gfx.config.tcc_disabled_mask =
5209                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5210                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5211 }
5212
5213 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5214 {
5215         u32 tmp;
5216         int i;
5217
5218         if (!amdgpu_sriov_vf(adev))
5219                 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5220
5221         gfx_v10_0_setup_rb(adev);
5222         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5223         gfx_v10_0_get_tcc_info(adev);
5224         adev->gfx.config.pa_sc_tile_steering_override =
5225                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5226
5227         /* XXX SH_MEM regs */
5228         /* where to put LDS, scratch, GPUVM in FSA64 space */
5229         mutex_lock(&adev->srbm_mutex);
5230         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5231                 nv_grbm_select(adev, 0, 0, 0, i);
5232                 /* CP and shaders */
5233                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5234                 if (i != 0) {
5235                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5236                                 (adev->gmc.private_aperture_start >> 48));
5237                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5238                                 (adev->gmc.shared_aperture_start >> 48));
5239                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5240                 }
5241         }
5242         nv_grbm_select(adev, 0, 0, 0, 0);
5243
5244         mutex_unlock(&adev->srbm_mutex);
5245
5246         gfx_v10_0_init_compute_vmid(adev);
5247         gfx_v10_0_init_gds_vmid(adev);
5248
5249 }
5250
5251 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
5252                                       int me, int pipe)
5253 {
5254         if (me != 0)
5255                 return 0;
5256
5257         switch (pipe) {
5258         case 0:
5259                 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
5260         case 1:
5261                 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
5262         default:
5263                 return 0;
5264         }
5265 }
5266
5267 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
5268                                       int me, int pipe)
5269 {
5270         /*
5271          * amdgpu controls only the first MEC. That's why this function only
5272          * handles the setting of interrupts for this specific MEC. All other
5273          * pipes' interrupts are set by amdkfd.
5274          */
5275         if (me != 1)
5276                 return 0;
5277
5278         switch (pipe) {
5279         case 0:
5280                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5281         case 1:
5282                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5283         case 2:
5284                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5285         case 3:
5286                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5287         default:
5288                 return 0;
5289         }
5290 }
5291
5292 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5293                                                bool enable)
5294 {
5295         u32 tmp, cp_int_cntl_reg;
5296         int i, j;
5297
5298         if (amdgpu_sriov_vf(adev))
5299                 return;
5300
5301         for (i = 0; i < adev->gfx.me.num_me; i++) {
5302                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5303                         cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
5304
5305                         if (cp_int_cntl_reg) {
5306                                 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5307                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5308                                                     enable ? 1 : 0);
5309                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5310                                                     enable ? 1 : 0);
5311                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5312                                                     enable ? 1 : 0);
5313                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5314                                                     enable ? 1 : 0);
5315                                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
5316                         }
5317                 }
5318         }
5319 }
5320
5321 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5322 {
5323         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5324
5325         /* csib */
5326         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5327                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5328                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5329                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5330                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5331                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5332         } else {
5333                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5334                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5335                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5336                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5337                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5338         }
5339         return 0;
5340 }
5341
5342 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5343 {
5344         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5345
5346         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5347         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5348 }
5349
5350 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5351 {
5352         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5353         udelay(50);
5354         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5355         udelay(50);
5356 }
5357
5358 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5359                                              bool enable)
5360 {
5361         uint32_t rlc_pg_cntl;
5362
5363         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5364
5365         if (!enable) {
5366                 /* RLC_PG_CNTL[23] = 0 (default)
5367                  * RLC will wait for handshake acks with SMU
5368                  * GFXOFF will be enabled
5369                  * RLC_PG_CNTL[23] = 1
5370                  * RLC will not issue any message to SMU
5371                  * hence no handshake between SMU & RLC
5372                  * GFXOFF will be disabled
5373                  */
5374                 rlc_pg_cntl |= 0x800000;
5375         } else
5376                 rlc_pg_cntl &= ~0x800000;
5377         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5378 }
5379
5380 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5381 {
5382         /*
5383          * TODO: enable rlc & smu handshake until smu
5384          * and gfxoff feature works as expected
5385          */
5386         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5387                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5388
5389         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5390         udelay(50);
5391 }
5392
5393 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5394 {
5395         uint32_t tmp;
5396
5397         /* enable Save Restore Machine */
5398         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5399         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5400         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5401         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5402 }
5403
5404 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5405 {
5406         const struct rlc_firmware_header_v2_0 *hdr;
5407         const __le32 *fw_data;
5408         unsigned int i, fw_size;
5409
5410         if (!adev->gfx.rlc_fw)
5411                 return -EINVAL;
5412
5413         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5414         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5415
5416         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5417                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5418         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5419
5420         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5421                      RLCG_UCODE_LOADING_START_ADDRESS);
5422
5423         for (i = 0; i < fw_size; i++)
5424                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5425                              le32_to_cpup(fw_data++));
5426
5427         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5428
5429         return 0;
5430 }
5431
5432 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5433 {
5434         int r;
5435
5436         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5437                 adev->psp.autoload_supported) {
5438
5439                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5440                 if (r)
5441                         return r;
5442
5443                 gfx_v10_0_init_csb(adev);
5444
5445                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5446
5447                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5448                         gfx_v10_0_rlc_enable_srm(adev);
5449         } else {
5450                 if (amdgpu_sriov_vf(adev)) {
5451                         gfx_v10_0_init_csb(adev);
5452                         return 0;
5453                 }
5454
5455                 adev->gfx.rlc.funcs->stop(adev);
5456
5457                 /* disable CG */
5458                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5459
5460                 /* disable PG */
5461                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5462
5463                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5464                         /* legacy rlc firmware loading */
5465                         r = gfx_v10_0_rlc_load_microcode(adev);
5466                         if (r)
5467                                 return r;
5468                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5469                         /* rlc backdoor autoload firmware */
5470                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5471                         if (r)
5472                                 return r;
5473                 }
5474
5475                 gfx_v10_0_init_csb(adev);
5476
5477                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5478
5479                 adev->gfx.rlc.funcs->start(adev);
5480
5481                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5482                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5483                         if (r)
5484                                 return r;
5485                 }
5486         }
5487
5488         return 0;
5489 }
5490
5491 static struct {
5492         FIRMWARE_ID     id;
5493         unsigned int    offset;
5494         unsigned int    size;
5495 } rlc_autoload_info[FIRMWARE_ID_MAX];
5496
5497 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5498 {
5499         int ret;
5500         RLC_TABLE_OF_CONTENT *rlc_toc;
5501
5502         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5503                                         AMDGPU_GEM_DOMAIN_GTT,
5504                                         &adev->gfx.rlc.rlc_toc_bo,
5505                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5506                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5507         if (ret) {
5508                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5509                 return ret;
5510         }
5511
5512         /* Copy toc from psp sos fw to rlc toc buffer */
5513         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5514
5515         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5516         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5517                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5518                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5519                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5520                         /* Offset needs 4KB alignment */
5521                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5522                 }
5523
5524                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5525                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5526                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5527
5528                 rlc_toc++;
5529         }
5530
5531         return 0;
5532 }
5533
5534 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5535 {
5536         uint32_t total_size = 0;
5537         FIRMWARE_ID id;
5538         int ret;
5539
5540         ret = gfx_v10_0_parse_rlc_toc(adev);
5541         if (ret) {
5542                 dev_err(adev->dev, "failed to parse rlc toc\n");
5543                 return 0;
5544         }
5545
5546         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5547                 total_size += rlc_autoload_info[id].size;
5548
5549         /* In case the offset in rlc toc ucode is aligned */
5550         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5551                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5552                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5553
5554         return total_size;
5555 }
5556
5557 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5558 {
5559         int r;
5560         uint32_t total_size;
5561
5562         total_size = gfx_v10_0_calc_toc_total_size(adev);
5563
5564         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5565                                       AMDGPU_GEM_DOMAIN_GTT,
5566                                       &adev->gfx.rlc.rlc_autoload_bo,
5567                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5568                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5569         if (r) {
5570                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5571                 return r;
5572         }
5573
5574         return 0;
5575 }
5576
5577 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5578 {
5579         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5580                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5581                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5582         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5583                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5584                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5585 }
5586
5587 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5588                                                        FIRMWARE_ID id,
5589                                                        const void *fw_data,
5590                                                        uint32_t fw_size)
5591 {
5592         uint32_t toc_offset;
5593         uint32_t toc_fw_size;
5594         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5595
5596         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5597                 return;
5598
5599         toc_offset = rlc_autoload_info[id].offset;
5600         toc_fw_size = rlc_autoload_info[id].size;
5601
5602         if (fw_size == 0)
5603                 fw_size = toc_fw_size;
5604
5605         if (fw_size > toc_fw_size)
5606                 fw_size = toc_fw_size;
5607
5608         memcpy(ptr + toc_offset, fw_data, fw_size);
5609
5610         if (fw_size < toc_fw_size)
5611                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5612 }
5613
5614 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5615 {
5616         void *data;
5617         uint32_t size;
5618
5619         data = adev->gfx.rlc.rlc_toc_buf;
5620         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5621
5622         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5623                                                    FIRMWARE_ID_RLC_TOC,
5624                                                    data, size);
5625 }
5626
5627 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5628 {
5629         const __le32 *fw_data;
5630         uint32_t fw_size;
5631         const struct gfx_firmware_header_v1_0 *cp_hdr;
5632         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5633
5634         /* pfp ucode */
5635         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5636                 adev->gfx.pfp_fw->data;
5637         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5638                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5639         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5640         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5641                                                    FIRMWARE_ID_CP_PFP,
5642                                                    fw_data, fw_size);
5643
5644         /* ce ucode */
5645         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5646                 adev->gfx.ce_fw->data;
5647         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5648                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5649         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5650         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5651                                                    FIRMWARE_ID_CP_CE,
5652                                                    fw_data, fw_size);
5653
5654         /* me ucode */
5655         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5656                 adev->gfx.me_fw->data;
5657         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5658                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5659         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5660         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5661                                                    FIRMWARE_ID_CP_ME,
5662                                                    fw_data, fw_size);
5663
5664         /* rlc ucode */
5665         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5666                 adev->gfx.rlc_fw->data;
5667         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5668                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5669         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5670         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5671                                                    FIRMWARE_ID_RLC_G_UCODE,
5672                                                    fw_data, fw_size);
5673
5674         /* mec1 ucode */
5675         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5676                 adev->gfx.mec_fw->data;
5677         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5678                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5679         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5680                 cp_hdr->jt_size * 4;
5681         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5682                                                    FIRMWARE_ID_CP_MEC,
5683                                                    fw_data, fw_size);
5684         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5685 }
5686
5687 /* Temporarily put sdma part here */
5688 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5689 {
5690         const __le32 *fw_data;
5691         uint32_t fw_size;
5692         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5693         int i;
5694
5695         for (i = 0; i < adev->sdma.num_instances; i++) {
5696                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5697                         adev->sdma.instance[i].fw->data;
5698                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5699                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5700                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5701
5702                 if (i == 0) {
5703                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5704                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5705                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5706                                 FIRMWARE_ID_SDMA0_JT,
5707                                 (uint32_t *)fw_data +
5708                                 sdma_hdr->jt_offset,
5709                                 sdma_hdr->jt_size * 4);
5710                 } else if (i == 1) {
5711                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5712                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5713                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5714                                 FIRMWARE_ID_SDMA1_JT,
5715                                 (uint32_t *)fw_data +
5716                                 sdma_hdr->jt_offset,
5717                                 sdma_hdr->jt_size * 4);
5718                 }
5719         }
5720 }
5721
5722 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5723 {
5724         uint32_t rlc_g_offset, rlc_g_size, tmp;
5725         uint64_t gpu_addr;
5726
5727         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5728         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5729         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5730
5731         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5732         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5733         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5734
5735         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5736         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5737         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5738
5739         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5740         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5741                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5742                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5743                 return -EINVAL;
5744         }
5745
5746         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5747         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5748                 DRM_ERROR("RLC ROM should halt itself\n");
5749                 return -EINVAL;
5750         }
5751
5752         return 0;
5753 }
5754
5755 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5756 {
5757         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5758         uint32_t tmp;
5759         int i;
5760         uint64_t addr;
5761
5762         /* Trigger an invalidation of the L1 instruction caches */
5763         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5764         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5765         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5766
5767         /* Wait for invalidation complete */
5768         for (i = 0; i < usec_timeout; i++) {
5769                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5770                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5771                         INVALIDATE_CACHE_COMPLETE))
5772                         break;
5773                 udelay(1);
5774         }
5775
5776         if (i >= usec_timeout) {
5777                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5778                 return -EINVAL;
5779         }
5780
5781         /* Program me ucode address into intruction cache address register */
5782         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5783                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5784         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5785                         lower_32_bits(addr) & 0xFFFFF000);
5786         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5787                         upper_32_bits(addr));
5788
5789         return 0;
5790 }
5791
5792 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5793 {
5794         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5795         uint32_t tmp;
5796         int i;
5797         uint64_t addr;
5798
5799         /* Trigger an invalidation of the L1 instruction caches */
5800         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5801         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5802         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5803
5804         /* Wait for invalidation complete */
5805         for (i = 0; i < usec_timeout; i++) {
5806                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5807                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5808                         INVALIDATE_CACHE_COMPLETE))
5809                         break;
5810                 udelay(1);
5811         }
5812
5813         if (i >= usec_timeout) {
5814                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5815                 return -EINVAL;
5816         }
5817
5818         /* Program ce ucode address into intruction cache address register */
5819         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5820                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5821         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5822                         lower_32_bits(addr) & 0xFFFFF000);
5823         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5824                         upper_32_bits(addr));
5825
5826         return 0;
5827 }
5828
5829 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5830 {
5831         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5832         uint32_t tmp;
5833         int i;
5834         uint64_t addr;
5835
5836         /* Trigger an invalidation of the L1 instruction caches */
5837         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5838         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5839         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5840
5841         /* Wait for invalidation complete */
5842         for (i = 0; i < usec_timeout; i++) {
5843                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5844                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5845                         INVALIDATE_CACHE_COMPLETE))
5846                         break;
5847                 udelay(1);
5848         }
5849
5850         if (i >= usec_timeout) {
5851                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5852                 return -EINVAL;
5853         }
5854
5855         /* Program pfp ucode address into intruction cache address register */
5856         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5857                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5858         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5859                         lower_32_bits(addr) & 0xFFFFF000);
5860         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5861                         upper_32_bits(addr));
5862
5863         return 0;
5864 }
5865
5866 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5867 {
5868         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5869         uint32_t tmp;
5870         int i;
5871         uint64_t addr;
5872
5873         /* Trigger an invalidation of the L1 instruction caches */
5874         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5875         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5876         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5877
5878         /* Wait for invalidation complete */
5879         for (i = 0; i < usec_timeout; i++) {
5880                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5881                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5882                         INVALIDATE_CACHE_COMPLETE))
5883                         break;
5884                 udelay(1);
5885         }
5886
5887         if (i >= usec_timeout) {
5888                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5889                 return -EINVAL;
5890         }
5891
5892         /* Program mec1 ucode address into intruction cache address register */
5893         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5894                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5895         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5896                         lower_32_bits(addr) & 0xFFFFF000);
5897         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5898                         upper_32_bits(addr));
5899
5900         return 0;
5901 }
5902
5903 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5904 {
5905         uint32_t cp_status;
5906         uint32_t bootload_status;
5907         int i, r;
5908
5909         for (i = 0; i < adev->usec_timeout; i++) {
5910                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5911                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5912                 if ((cp_status == 0) &&
5913                     (REG_GET_FIELD(bootload_status,
5914                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5915                         break;
5916                 }
5917                 udelay(1);
5918         }
5919
5920         if (i >= adev->usec_timeout) {
5921                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5922                 return -ETIMEDOUT;
5923         }
5924
5925         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5926                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5927                 if (r)
5928                         return r;
5929
5930                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5931                 if (r)
5932                         return r;
5933
5934                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5935                 if (r)
5936                         return r;
5937
5938                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5939                 if (r)
5940                         return r;
5941         }
5942
5943         return 0;
5944 }
5945
5946 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5947 {
5948         int i;
5949         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5950
5951         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5952         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5953         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5954
5955         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
5956                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5957         else
5958                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5959
5960         if (adev->job_hang && !enable)
5961                 return 0;
5962
5963         for (i = 0; i < adev->usec_timeout; i++) {
5964                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5965                         break;
5966                 udelay(1);
5967         }
5968
5969         if (i >= adev->usec_timeout)
5970                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5971
5972         return 0;
5973 }
5974
5975 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5976 {
5977         int r;
5978         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5979         const __le32 *fw_data;
5980         unsigned int i, fw_size;
5981         uint32_t tmp;
5982         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5983
5984         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5985                 adev->gfx.pfp_fw->data;
5986
5987         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5988
5989         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5990                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5991         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5992
5993         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5994                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5995                                       &adev->gfx.pfp.pfp_fw_obj,
5996                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5997                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5998         if (r) {
5999                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6000                 gfx_v10_0_pfp_fini(adev);
6001                 return r;
6002         }
6003
6004         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6005
6006         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6007         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6008
6009         /* Trigger an invalidation of the L1 instruction caches */
6010         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6011         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6012         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6013
6014         /* Wait for invalidation complete */
6015         for (i = 0; i < usec_timeout; i++) {
6016                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6017                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6018                         INVALIDATE_CACHE_COMPLETE))
6019                         break;
6020                 udelay(1);
6021         }
6022
6023         if (i >= usec_timeout) {
6024                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6025                 return -EINVAL;
6026         }
6027
6028         if (amdgpu_emu_mode == 1)
6029                 adev->hdp.funcs->flush_hdp(adev, NULL);
6030
6031         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6032         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6033         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6034         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6035         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6036         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6037         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6038                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6039         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6040                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6041
6042         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6043
6044         for (i = 0; i < pfp_hdr->jt_size; i++)
6045                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6046                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6047
6048         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6049
6050         return 0;
6051 }
6052
6053 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6054 {
6055         int r;
6056         const struct gfx_firmware_header_v1_0 *ce_hdr;
6057         const __le32 *fw_data;
6058         unsigned int i, fw_size;
6059         uint32_t tmp;
6060         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6061
6062         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6063                 adev->gfx.ce_fw->data;
6064
6065         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6066
6067         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6068                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6069         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6070
6071         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6072                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6073                                       &adev->gfx.ce.ce_fw_obj,
6074                                       &adev->gfx.ce.ce_fw_gpu_addr,
6075                                       (void **)&adev->gfx.ce.ce_fw_ptr);
6076         if (r) {
6077                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6078                 gfx_v10_0_ce_fini(adev);
6079                 return r;
6080         }
6081
6082         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6083
6084         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6085         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6086
6087         /* Trigger an invalidation of the L1 instruction caches */
6088         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6089         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6090         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6091
6092         /* Wait for invalidation complete */
6093         for (i = 0; i < usec_timeout; i++) {
6094                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6095                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6096                         INVALIDATE_CACHE_COMPLETE))
6097                         break;
6098                 udelay(1);
6099         }
6100
6101         if (i >= usec_timeout) {
6102                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6103                 return -EINVAL;
6104         }
6105
6106         if (amdgpu_emu_mode == 1)
6107                 adev->hdp.funcs->flush_hdp(adev, NULL);
6108
6109         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6110         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6111         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6112         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6113         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6114         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6115                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6116         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6117                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6118
6119         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6120
6121         for (i = 0; i < ce_hdr->jt_size; i++)
6122                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6123                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6124
6125         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6126
6127         return 0;
6128 }
6129
6130 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6131 {
6132         int r;
6133         const struct gfx_firmware_header_v1_0 *me_hdr;
6134         const __le32 *fw_data;
6135         unsigned int i, fw_size;
6136         uint32_t tmp;
6137         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6138
6139         me_hdr = (const struct gfx_firmware_header_v1_0 *)
6140                 adev->gfx.me_fw->data;
6141
6142         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6143
6144         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6145                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6146         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6147
6148         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6149                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6150                                       &adev->gfx.me.me_fw_obj,
6151                                       &adev->gfx.me.me_fw_gpu_addr,
6152                                       (void **)&adev->gfx.me.me_fw_ptr);
6153         if (r) {
6154                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6155                 gfx_v10_0_me_fini(adev);
6156                 return r;
6157         }
6158
6159         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6160
6161         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6162         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6163
6164         /* Trigger an invalidation of the L1 instruction caches */
6165         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6166         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6167         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6168
6169         /* Wait for invalidation complete */
6170         for (i = 0; i < usec_timeout; i++) {
6171                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6172                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6173                         INVALIDATE_CACHE_COMPLETE))
6174                         break;
6175                 udelay(1);
6176         }
6177
6178         if (i >= usec_timeout) {
6179                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6180                 return -EINVAL;
6181         }
6182
6183         if (amdgpu_emu_mode == 1)
6184                 adev->hdp.funcs->flush_hdp(adev, NULL);
6185
6186         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6187         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6188         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6189         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6190         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6191         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6192                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6193         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6194                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6195
6196         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6197
6198         for (i = 0; i < me_hdr->jt_size; i++)
6199                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6200                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6201
6202         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6203
6204         return 0;
6205 }
6206
6207 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6208 {
6209         int r;
6210
6211         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6212                 return -EINVAL;
6213
6214         gfx_v10_0_cp_gfx_enable(adev, false);
6215
6216         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6217         if (r) {
6218                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6219                 return r;
6220         }
6221
6222         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6223         if (r) {
6224                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6225                 return r;
6226         }
6227
6228         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6229         if (r) {
6230                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6231                 return r;
6232         }
6233
6234         return 0;
6235 }
6236
6237 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6238 {
6239         struct amdgpu_ring *ring;
6240         const struct cs_section_def *sect = NULL;
6241         const struct cs_extent_def *ext = NULL;
6242         int r, i;
6243         int ctx_reg_offset;
6244
6245         /* init the CP */
6246         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6247                      adev->gfx.config.max_hw_contexts - 1);
6248         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6249
6250         gfx_v10_0_cp_gfx_enable(adev, true);
6251
6252         ring = &adev->gfx.gfx_ring[0];
6253         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6254         if (r) {
6255                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6256                 return r;
6257         }
6258
6259         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6260         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6261
6262         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6263         amdgpu_ring_write(ring, 0x80000000);
6264         amdgpu_ring_write(ring, 0x80000000);
6265
6266         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6267                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6268                         if (sect->id == SECT_CONTEXT) {
6269                                 amdgpu_ring_write(ring,
6270                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6271                                                           ext->reg_count));
6272                                 amdgpu_ring_write(ring, ext->reg_index -
6273                                                   PACKET3_SET_CONTEXT_REG_START);
6274                                 for (i = 0; i < ext->reg_count; i++)
6275                                         amdgpu_ring_write(ring, ext->extent[i]);
6276                         }
6277                 }
6278         }
6279
6280         ctx_reg_offset =
6281                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6282         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6283         amdgpu_ring_write(ring, ctx_reg_offset);
6284         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6285
6286         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6287         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6288
6289         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6290         amdgpu_ring_write(ring, 0);
6291
6292         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6293         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6294         amdgpu_ring_write(ring, 0x8000);
6295         amdgpu_ring_write(ring, 0x8000);
6296
6297         amdgpu_ring_commit(ring);
6298
6299         /* submit cs packet to copy state 0 to next available state */
6300         if (adev->gfx.num_gfx_rings > 1) {
6301                 /* maximum supported gfx ring is 2 */
6302                 ring = &adev->gfx.gfx_ring[1];
6303                 r = amdgpu_ring_alloc(ring, 2);
6304                 if (r) {
6305                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6306                         return r;
6307                 }
6308
6309                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6310                 amdgpu_ring_write(ring, 0);
6311
6312                 amdgpu_ring_commit(ring);
6313         }
6314         return 0;
6315 }
6316
6317 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6318                                          CP_PIPE_ID pipe)
6319 {
6320         u32 tmp;
6321
6322         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6323         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6324
6325         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6326 }
6327
6328 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6329                                           struct amdgpu_ring *ring)
6330 {
6331         u32 tmp;
6332
6333         if (!amdgpu_async_gfx_ring) {
6334                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6335                 if (ring->use_doorbell) {
6336                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6337                                                 DOORBELL_OFFSET, ring->doorbell_index);
6338                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6339                                                 DOORBELL_EN, 1);
6340                 } else {
6341                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6342                                                 DOORBELL_EN, 0);
6343                 }
6344                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6345         }
6346         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6347         case IP_VERSION(10, 3, 0):
6348         case IP_VERSION(10, 3, 2):
6349         case IP_VERSION(10, 3, 1):
6350         case IP_VERSION(10, 3, 4):
6351         case IP_VERSION(10, 3, 5):
6352         case IP_VERSION(10, 3, 6):
6353         case IP_VERSION(10, 3, 3):
6354         case IP_VERSION(10, 3, 7):
6355                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6356                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6357                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6358
6359                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6360                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6361                 break;
6362         default:
6363                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6364                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6365                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6366
6367                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6368                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6369                 break;
6370         }
6371 }
6372
6373 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6374 {
6375         struct amdgpu_ring *ring;
6376         u32 tmp;
6377         u32 rb_bufsz;
6378         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6379
6380         /* Set the write pointer delay */
6381         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6382
6383         /* set the RB to use vmid 0 */
6384         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6385
6386         /* Init gfx ring 0 for pipe 0 */
6387         mutex_lock(&adev->srbm_mutex);
6388         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6389
6390         /* Set ring buffer size */
6391         ring = &adev->gfx.gfx_ring[0];
6392         rb_bufsz = order_base_2(ring->ring_size / 8);
6393         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6394         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6395 #ifdef __BIG_ENDIAN
6396         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6397 #endif
6398         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6399
6400         /* Initialize the ring buffer's write pointers */
6401         ring->wptr = 0;
6402         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6403         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6404
6405         /* set the wb address whether it's enabled or not */
6406         rptr_addr = ring->rptr_gpu_addr;
6407         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6408         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6409                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6410
6411         wptr_gpu_addr = ring->wptr_gpu_addr;
6412         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6413                      lower_32_bits(wptr_gpu_addr));
6414         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6415                      upper_32_bits(wptr_gpu_addr));
6416
6417         mdelay(1);
6418         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6419
6420         rb_addr = ring->gpu_addr >> 8;
6421         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6422         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6423
6424         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6425
6426         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6427         mutex_unlock(&adev->srbm_mutex);
6428
6429         /* Init gfx ring 1 for pipe 1 */
6430         if (adev->gfx.num_gfx_rings > 1) {
6431                 mutex_lock(&adev->srbm_mutex);
6432                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6433                 /* maximum supported gfx ring is 2 */
6434                 ring = &adev->gfx.gfx_ring[1];
6435                 rb_bufsz = order_base_2(ring->ring_size / 8);
6436                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6437                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6438                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6439                 /* Initialize the ring buffer's write pointers */
6440                 ring->wptr = 0;
6441                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6442                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6443                 /* Set the wb address whether it's enabled or not */
6444                 rptr_addr = ring->rptr_gpu_addr;
6445                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6446                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6447                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6448                 wptr_gpu_addr = ring->wptr_gpu_addr;
6449                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6450                              lower_32_bits(wptr_gpu_addr));
6451                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6452                              upper_32_bits(wptr_gpu_addr));
6453
6454                 mdelay(1);
6455                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6456
6457                 rb_addr = ring->gpu_addr >> 8;
6458                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6459                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6460                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6461
6462                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6463                 mutex_unlock(&adev->srbm_mutex);
6464         }
6465         /* Switch to pipe 0 */
6466         mutex_lock(&adev->srbm_mutex);
6467         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6468         mutex_unlock(&adev->srbm_mutex);
6469
6470         /* start the ring */
6471         gfx_v10_0_cp_gfx_start(adev);
6472
6473         return 0;
6474 }
6475
6476 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6477 {
6478         if (enable) {
6479                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6480                 case IP_VERSION(10, 3, 0):
6481                 case IP_VERSION(10, 3, 2):
6482                 case IP_VERSION(10, 3, 1):
6483                 case IP_VERSION(10, 3, 4):
6484                 case IP_VERSION(10, 3, 5):
6485                 case IP_VERSION(10, 3, 6):
6486                 case IP_VERSION(10, 3, 3):
6487                 case IP_VERSION(10, 3, 7):
6488                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6489                         break;
6490                 default:
6491                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6492                         break;
6493                 }
6494         } else {
6495                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6496                 case IP_VERSION(10, 3, 0):
6497                 case IP_VERSION(10, 3, 2):
6498                 case IP_VERSION(10, 3, 1):
6499                 case IP_VERSION(10, 3, 4):
6500                 case IP_VERSION(10, 3, 5):
6501                 case IP_VERSION(10, 3, 6):
6502                 case IP_VERSION(10, 3, 3):
6503                 case IP_VERSION(10, 3, 7):
6504                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6505                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6506                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6507                         break;
6508                 default:
6509                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6510                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6511                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6512                         break;
6513                 }
6514                 adev->gfx.kiq[0].ring.sched.ready = false;
6515         }
6516         udelay(50);
6517 }
6518
6519 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6520 {
6521         const struct gfx_firmware_header_v1_0 *mec_hdr;
6522         const __le32 *fw_data;
6523         unsigned int i;
6524         u32 tmp;
6525         u32 usec_timeout = 50000; /* Wait for 50 ms */
6526
6527         if (!adev->gfx.mec_fw)
6528                 return -EINVAL;
6529
6530         gfx_v10_0_cp_compute_enable(adev, false);
6531
6532         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6533         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6534
6535         fw_data = (const __le32 *)
6536                 (adev->gfx.mec_fw->data +
6537                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6538
6539         /* Trigger an invalidation of the L1 instruction caches */
6540         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6541         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6542         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6543
6544         /* Wait for invalidation complete */
6545         for (i = 0; i < usec_timeout; i++) {
6546                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6547                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6548                                        INVALIDATE_CACHE_COMPLETE))
6549                         break;
6550                 udelay(1);
6551         }
6552
6553         if (i >= usec_timeout) {
6554                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6555                 return -EINVAL;
6556         }
6557
6558         if (amdgpu_emu_mode == 1)
6559                 adev->hdp.funcs->flush_hdp(adev, NULL);
6560
6561         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6562         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6563         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6564         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6565         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6566
6567         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6568                      0xFFFFF000);
6569         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6570                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6571
6572         /* MEC1 */
6573         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6574
6575         for (i = 0; i < mec_hdr->jt_size; i++)
6576                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6577                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6578
6579         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6580
6581         /*
6582          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6583          * different microcode than MEC1.
6584          */
6585
6586         return 0;
6587 }
6588
6589 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6590 {
6591         uint32_t tmp;
6592         struct amdgpu_device *adev = ring->adev;
6593
6594         /* tell RLC which is KIQ queue */
6595         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6596         case IP_VERSION(10, 3, 0):
6597         case IP_VERSION(10, 3, 2):
6598         case IP_VERSION(10, 3, 1):
6599         case IP_VERSION(10, 3, 4):
6600         case IP_VERSION(10, 3, 5):
6601         case IP_VERSION(10, 3, 6):
6602         case IP_VERSION(10, 3, 3):
6603         case IP_VERSION(10, 3, 7):
6604                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6605                 tmp &= 0xffffff00;
6606                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6607                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
6608                 break;
6609         default:
6610                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6611                 tmp &= 0xffffff00;
6612                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6613                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
6614                 break;
6615         }
6616 }
6617
6618 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6619                                            struct v10_gfx_mqd *mqd,
6620                                            struct amdgpu_mqd_prop *prop)
6621 {
6622         bool priority = 0;
6623         u32 tmp;
6624
6625         /* set up default queue priority level
6626          * 0x0 = low priority, 0x1 = high priority
6627          */
6628         if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6629                 priority = 1;
6630
6631         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6632         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6633         mqd->cp_gfx_hqd_queue_priority = tmp;
6634 }
6635
6636 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6637                                   struct amdgpu_mqd_prop *prop)
6638 {
6639         struct v10_gfx_mqd *mqd = m;
6640         uint64_t hqd_gpu_addr, wb_gpu_addr;
6641         uint32_t tmp;
6642         uint32_t rb_bufsz;
6643
6644         /* set up gfx hqd wptr */
6645         mqd->cp_gfx_hqd_wptr = 0;
6646         mqd->cp_gfx_hqd_wptr_hi = 0;
6647
6648         /* set the pointer to the MQD */
6649         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6650         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6651
6652         /* set up mqd control */
6653         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6654         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6655         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6656         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6657         mqd->cp_gfx_mqd_control = tmp;
6658
6659         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6660         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6661         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6662         mqd->cp_gfx_hqd_vmid = 0;
6663
6664         /* set up gfx queue priority */
6665         gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6666
6667         /* set up time quantum */
6668         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6669         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6670         mqd->cp_gfx_hqd_quantum = tmp;
6671
6672         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6673         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6674         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6675         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6676
6677         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6678         wb_gpu_addr = prop->rptr_gpu_addr;
6679         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6680         mqd->cp_gfx_hqd_rptr_addr_hi =
6681                 upper_32_bits(wb_gpu_addr) & 0xffff;
6682
6683         /* set up rb_wptr_poll addr */
6684         wb_gpu_addr = prop->wptr_gpu_addr;
6685         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6686         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6687
6688         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6689         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6690         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6691         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6692         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6693 #ifdef __BIG_ENDIAN
6694         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6695 #endif
6696         mqd->cp_gfx_hqd_cntl = tmp;
6697
6698         /* set up cp_doorbell_control */
6699         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6700         if (prop->use_doorbell) {
6701                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6702                                     DOORBELL_OFFSET, prop->doorbell_index);
6703                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6704                                     DOORBELL_EN, 1);
6705         } else
6706                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6707                                     DOORBELL_EN, 0);
6708         mqd->cp_rb_doorbell_control = tmp;
6709
6710         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6711         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6712
6713         /* active the queue */
6714         mqd->cp_gfx_hqd_active = 1;
6715
6716         return 0;
6717 }
6718
6719 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
6720 {
6721         struct amdgpu_device *adev = ring->adev;
6722         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6723         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6724
6725         if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
6726                 memset((void *)mqd, 0, sizeof(*mqd));
6727                 mutex_lock(&adev->srbm_mutex);
6728                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6729                 amdgpu_ring_init_mqd(ring);
6730
6731                 /*
6732                  * if there are 2 gfx rings, set the lower doorbell
6733                  * range of the first ring, otherwise the range of
6734                  * the second ring will override the first ring
6735                  */
6736                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6737                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6738
6739                 nv_grbm_select(adev, 0, 0, 0, 0);
6740                 mutex_unlock(&adev->srbm_mutex);
6741                 if (adev->gfx.me.mqd_backup[mqd_idx])
6742                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6743         } else {
6744                 mutex_lock(&adev->srbm_mutex);
6745                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6746                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6747                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6748
6749                 nv_grbm_select(adev, 0, 0, 0, 0);
6750                 mutex_unlock(&adev->srbm_mutex);
6751                 /* restore mqd with the backup copy */
6752                 if (adev->gfx.me.mqd_backup[mqd_idx])
6753                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6754                 /* reset the ring */
6755                 ring->wptr = 0;
6756                 *ring->wptr_cpu_addr = 0;
6757                 amdgpu_ring_clear_ring(ring);
6758         }
6759
6760         return 0;
6761 }
6762
6763 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6764 {
6765         int r, i;
6766         struct amdgpu_ring *ring;
6767
6768         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6769                 ring = &adev->gfx.gfx_ring[i];
6770
6771                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6772                 if (unlikely(r != 0))
6773                         return r;
6774
6775                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6776                 if (!r) {
6777                         r = gfx_v10_0_kgq_init_queue(ring, false);
6778                         amdgpu_bo_kunmap(ring->mqd_obj);
6779                         ring->mqd_ptr = NULL;
6780                 }
6781                 amdgpu_bo_unreserve(ring->mqd_obj);
6782                 if (r)
6783                         return r;
6784         }
6785
6786         r = amdgpu_gfx_enable_kgq(adev, 0);
6787         if (r)
6788                 return r;
6789
6790         return gfx_v10_0_cp_gfx_start(adev);
6791 }
6792
6793 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6794                                       struct amdgpu_mqd_prop *prop)
6795 {
6796         struct v10_compute_mqd *mqd = m;
6797         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6798         uint32_t tmp;
6799
6800         mqd->header = 0xC0310800;
6801         mqd->compute_pipelinestat_enable = 0x00000001;
6802         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6803         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6804         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6805         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6806         mqd->compute_misc_reserved = 0x00000003;
6807
6808         eop_base_addr = prop->eop_gpu_addr >> 8;
6809         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6810         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6811
6812         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6813         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6814         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6815                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6816
6817         mqd->cp_hqd_eop_control = tmp;
6818
6819         /* enable doorbell? */
6820         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6821
6822         if (prop->use_doorbell) {
6823                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6824                                     DOORBELL_OFFSET, prop->doorbell_index);
6825                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6826                                     DOORBELL_EN, 1);
6827                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6828                                     DOORBELL_SOURCE, 0);
6829                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6830                                     DOORBELL_HIT, 0);
6831         } else {
6832                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6833                                     DOORBELL_EN, 0);
6834         }
6835
6836         mqd->cp_hqd_pq_doorbell_control = tmp;
6837
6838         /* disable the queue if it's active */
6839         mqd->cp_hqd_dequeue_request = 0;
6840         mqd->cp_hqd_pq_rptr = 0;
6841         mqd->cp_hqd_pq_wptr_lo = 0;
6842         mqd->cp_hqd_pq_wptr_hi = 0;
6843
6844         /* set the pointer to the MQD */
6845         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6846         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6847
6848         /* set MQD vmid to 0 */
6849         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6850         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6851         mqd->cp_mqd_control = tmp;
6852
6853         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6854         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6855         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6856         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6857
6858         /* set up the HQD, this is similar to CP_RB0_CNTL */
6859         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6860         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6861                             (order_base_2(prop->queue_size / 4) - 1));
6862         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6863                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6864 #ifdef __BIG_ENDIAN
6865         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6866 #endif
6867         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6868         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6869                             prop->allow_tunneling);
6870         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6871         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6872         mqd->cp_hqd_pq_control = tmp;
6873
6874         /* set the wb address whether it's enabled or not */
6875         wb_gpu_addr = prop->rptr_gpu_addr;
6876         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6877         mqd->cp_hqd_pq_rptr_report_addr_hi =
6878                 upper_32_bits(wb_gpu_addr) & 0xffff;
6879
6880         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6881         wb_gpu_addr = prop->wptr_gpu_addr;
6882         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6883         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6884
6885         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6886         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6887
6888         /* set the vmid for the queue */
6889         mqd->cp_hqd_vmid = 0;
6890
6891         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6892         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6893         mqd->cp_hqd_persistent_state = tmp;
6894
6895         /* set MIN_IB_AVAIL_SIZE */
6896         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6897         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6898         mqd->cp_hqd_ib_control = tmp;
6899
6900         /* set static priority for a compute queue/ring */
6901         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6902         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6903
6904         mqd->cp_hqd_active = prop->hqd_active;
6905
6906         return 0;
6907 }
6908
6909 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6910 {
6911         struct amdgpu_device *adev = ring->adev;
6912         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6913         int j;
6914
6915         /* inactivate the queue */
6916         if (amdgpu_sriov_vf(adev))
6917                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6918
6919         /* disable wptr polling */
6920         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6921
6922         /* disable the queue if it's active */
6923         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6924                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6925                 for (j = 0; j < adev->usec_timeout; j++) {
6926                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6927                                 break;
6928                         udelay(1);
6929                 }
6930                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6931                        mqd->cp_hqd_dequeue_request);
6932                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6933                        mqd->cp_hqd_pq_rptr);
6934                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6935                        mqd->cp_hqd_pq_wptr_lo);
6936                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6937                        mqd->cp_hqd_pq_wptr_hi);
6938         }
6939
6940         /* disable doorbells */
6941         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6942
6943         /* write the EOP addr */
6944         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6945                mqd->cp_hqd_eop_base_addr_lo);
6946         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6947                mqd->cp_hqd_eop_base_addr_hi);
6948
6949         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6950         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6951                mqd->cp_hqd_eop_control);
6952
6953         /* set the pointer to the MQD */
6954         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6955                mqd->cp_mqd_base_addr_lo);
6956         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6957                mqd->cp_mqd_base_addr_hi);
6958
6959         /* set MQD vmid to 0 */
6960         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6961                mqd->cp_mqd_control);
6962
6963         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6964         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6965                mqd->cp_hqd_pq_base_lo);
6966         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6967                mqd->cp_hqd_pq_base_hi);
6968
6969         /* set up the HQD, this is similar to CP_RB0_CNTL */
6970         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6971                mqd->cp_hqd_pq_control);
6972
6973         /* set the wb address whether it's enabled or not */
6974         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6975                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6976         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6977                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6978
6979         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6980         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6981                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6982         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6983                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6984
6985         /* enable the doorbell if requested */
6986         if (ring->use_doorbell) {
6987                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6988                         (adev->doorbell_index.kiq * 2) << 2);
6989                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6990                         (adev->doorbell_index.userqueue_end * 2) << 2);
6991         }
6992
6993         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6994                mqd->cp_hqd_pq_doorbell_control);
6995
6996         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6997         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6998                mqd->cp_hqd_pq_wptr_lo);
6999         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7000                mqd->cp_hqd_pq_wptr_hi);
7001
7002         /* set the vmid for the queue */
7003         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7004
7005         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7006                mqd->cp_hqd_persistent_state);
7007
7008         /* activate the queue */
7009         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7010                mqd->cp_hqd_active);
7011
7012         if (ring->use_doorbell)
7013                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7014
7015         return 0;
7016 }
7017
7018 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7019 {
7020         struct amdgpu_device *adev = ring->adev;
7021         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7022
7023         gfx_v10_0_kiq_setting(ring);
7024
7025         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7026                 /* reset MQD to a clean status */
7027                 if (adev->gfx.kiq[0].mqd_backup)
7028                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
7029
7030                 /* reset ring buffer */
7031                 ring->wptr = 0;
7032                 amdgpu_ring_clear_ring(ring);
7033
7034                 mutex_lock(&adev->srbm_mutex);
7035                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7036                 gfx_v10_0_kiq_init_register(ring);
7037                 nv_grbm_select(adev, 0, 0, 0, 0);
7038                 mutex_unlock(&adev->srbm_mutex);
7039         } else {
7040                 memset((void *)mqd, 0, sizeof(*mqd));
7041                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
7042                         amdgpu_ring_clear_ring(ring);
7043                 mutex_lock(&adev->srbm_mutex);
7044                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7045                 amdgpu_ring_init_mqd(ring);
7046                 gfx_v10_0_kiq_init_register(ring);
7047                 nv_grbm_select(adev, 0, 0, 0, 0);
7048                 mutex_unlock(&adev->srbm_mutex);
7049
7050                 if (adev->gfx.kiq[0].mqd_backup)
7051                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
7052         }
7053
7054         return 0;
7055 }
7056
7057 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
7058 {
7059         struct amdgpu_device *adev = ring->adev;
7060         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7061         int mqd_idx = ring - &adev->gfx.compute_ring[0];
7062
7063         if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {
7064                 memset((void *)mqd, 0, sizeof(*mqd));
7065                 mutex_lock(&adev->srbm_mutex);
7066                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7067                 amdgpu_ring_init_mqd(ring);
7068                 nv_grbm_select(adev, 0, 0, 0, 0);
7069                 mutex_unlock(&adev->srbm_mutex);
7070
7071                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7072                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7073         } else {
7074                 /* restore MQD to a clean status */
7075                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7076                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7077                 /* reset ring buffer */
7078                 ring->wptr = 0;
7079                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7080                 amdgpu_ring_clear_ring(ring);
7081         }
7082
7083         return 0;
7084 }
7085
7086 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7087 {
7088         struct amdgpu_ring *ring;
7089         int r;
7090
7091         ring = &adev->gfx.kiq[0].ring;
7092
7093         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7094         if (unlikely(r != 0))
7095                 return r;
7096
7097         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7098         if (unlikely(r != 0)) {
7099                 amdgpu_bo_unreserve(ring->mqd_obj);
7100                 return r;
7101         }
7102
7103         gfx_v10_0_kiq_init_queue(ring);
7104         amdgpu_bo_kunmap(ring->mqd_obj);
7105         ring->mqd_ptr = NULL;
7106         amdgpu_bo_unreserve(ring->mqd_obj);
7107         return 0;
7108 }
7109
7110 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7111 {
7112         struct amdgpu_ring *ring = NULL;
7113         int r = 0, i;
7114
7115         gfx_v10_0_cp_compute_enable(adev, true);
7116
7117         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7118                 ring = &adev->gfx.compute_ring[i];
7119
7120                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7121                 if (unlikely(r != 0))
7122                         goto done;
7123                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7124                 if (!r) {
7125                         r = gfx_v10_0_kcq_init_queue(ring, false);
7126                         amdgpu_bo_kunmap(ring->mqd_obj);
7127                         ring->mqd_ptr = NULL;
7128                 }
7129                 amdgpu_bo_unreserve(ring->mqd_obj);
7130                 if (r)
7131                         goto done;
7132         }
7133
7134         r = amdgpu_gfx_enable_kcq(adev, 0);
7135 done:
7136         return r;
7137 }
7138
7139 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7140 {
7141         int r, i;
7142         struct amdgpu_ring *ring;
7143
7144         if (!(adev->flags & AMD_IS_APU))
7145                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7146
7147         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7148                 /* legacy firmware loading */
7149                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7150                 if (r)
7151                         return r;
7152
7153                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7154                 if (r)
7155                         return r;
7156         }
7157
7158         r = gfx_v10_0_kiq_resume(adev);
7159         if (r)
7160                 return r;
7161
7162         r = gfx_v10_0_kcq_resume(adev);
7163         if (r)
7164                 return r;
7165
7166         if (!amdgpu_async_gfx_ring) {
7167                 r = gfx_v10_0_cp_gfx_resume(adev);
7168                 if (r)
7169                         return r;
7170         } else {
7171                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7172                 if (r)
7173                         return r;
7174         }
7175
7176         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7177                 ring = &adev->gfx.gfx_ring[i];
7178                 r = amdgpu_ring_test_helper(ring);
7179                 if (r)
7180                         return r;
7181         }
7182
7183         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7184                 ring = &adev->gfx.compute_ring[i];
7185                 r = amdgpu_ring_test_helper(ring);
7186                 if (r)
7187                         return r;
7188         }
7189
7190         return 0;
7191 }
7192
7193 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7194 {
7195         gfx_v10_0_cp_gfx_enable(adev, enable);
7196         gfx_v10_0_cp_compute_enable(adev, enable);
7197 }
7198
7199 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7200 {
7201         uint32_t data, pattern = 0xDEADBEEF;
7202
7203         /*
7204          * check if mmVGT_ESGS_RING_SIZE_UMD
7205          * has been remapped to mmVGT_ESGS_RING_SIZE
7206          */
7207         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7208         case IP_VERSION(10, 3, 0):
7209         case IP_VERSION(10, 3, 2):
7210         case IP_VERSION(10, 3, 4):
7211         case IP_VERSION(10, 3, 5):
7212                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7213                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7214                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7215
7216                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7217                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7218                         return true;
7219                 }
7220                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7221                 break;
7222         case IP_VERSION(10, 3, 1):
7223         case IP_VERSION(10, 3, 3):
7224         case IP_VERSION(10, 3, 6):
7225         case IP_VERSION(10, 3, 7):
7226                 return true;
7227         default:
7228                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7229                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7230                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7231
7232                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7233                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7234                         return true;
7235                 }
7236                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7237                 break;
7238         }
7239
7240         return false;
7241 }
7242
7243 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7244 {
7245         uint32_t data;
7246
7247         if (amdgpu_sriov_vf(adev))
7248                 return;
7249
7250         /*
7251          * Initialize cam_index to 0
7252          * index will auto-inc after each data writing
7253          */
7254         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7255
7256         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7257         case IP_VERSION(10, 3, 0):
7258         case IP_VERSION(10, 3, 2):
7259         case IP_VERSION(10, 3, 1):
7260         case IP_VERSION(10, 3, 4):
7261         case IP_VERSION(10, 3, 5):
7262         case IP_VERSION(10, 3, 6):
7263         case IP_VERSION(10, 3, 3):
7264         case IP_VERSION(10, 3, 7):
7265                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7266                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7267                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7268                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7269                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7270                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7271                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7272
7273                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7274                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7275                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7276                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7277                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7278                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7279                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7280
7281                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7282                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7283                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7284                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7285                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7286                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7287                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7288
7289                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7290                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7291                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7292                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7293                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7294                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7295                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7296
7297                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7298                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7299                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7300                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7301                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7302                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7303                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7304
7305                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7306                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7307                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7308                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7309                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7310                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7311                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7312
7313                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7314                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7315                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7316                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7317                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7318                 break;
7319         default:
7320                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7321                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7322                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7323                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7324                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7325                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7326                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7327
7328                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7329                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7330                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7331                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7332                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7333                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7334                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7335
7336                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7337                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7338                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7339                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7340                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7341                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7342                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7343
7344                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7345                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7346                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7347                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7348                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7349                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7350                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7351
7352                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7353                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7354                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7355                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7356                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7357                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7358                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7359
7360                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7361                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7362                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7363                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7364                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7365                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7366                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7367
7368                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7369                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7370                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7371                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7372                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7373                 break;
7374         }
7375
7376         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7377         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7378 }
7379
7380 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7381 {
7382         uint32_t data;
7383
7384         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7385         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7386         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7387
7388         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7389         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7390         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7391 }
7392
7393 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
7394 {
7395         int r;
7396         struct amdgpu_device *adev = ip_block->adev;
7397
7398         if (!amdgpu_emu_mode)
7399                 gfx_v10_0_init_golden_registers(adev);
7400
7401         amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
7402                                        adev->gfx.cleaner_shader_ptr);
7403
7404         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7405                 /**
7406                  * For gfx 10, rlc firmware loading relies on smu firmware is
7407                  * loaded firstly, so in direct type, it has to load smc ucode
7408                  * here before rlc.
7409                  */
7410                 r = amdgpu_pm_load_smu_firmware(adev, NULL);
7411                 if (r)
7412                         return r;
7413                 gfx_v10_0_disable_gpa_mode(adev);
7414         }
7415
7416         /* if GRBM CAM not remapped, set up the remapping */
7417         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7418                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7419
7420         gfx_v10_0_constants_init(adev);
7421
7422         r = gfx_v10_0_rlc_resume(adev);
7423         if (r)
7424                 return r;
7425
7426         /*
7427          * init golden registers and rlc resume may override some registers,
7428          * reconfig them here
7429          */
7430         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7431             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7432             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7433                 gfx_v10_0_tcp_harvest(adev);
7434
7435         r = gfx_v10_0_cp_resume(adev);
7436         if (r)
7437                 return r;
7438
7439         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7440                 gfx_v10_3_program_pbb_mode(adev);
7441
7442         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7443                 gfx_v10_3_set_power_brake_sequence(adev);
7444
7445         return r;
7446 }
7447
7448 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
7449 {
7450         struct amdgpu_device *adev = ip_block->adev;
7451
7452         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7453         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7454         amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
7455
7456         /* WA added for Vangogh asic fixing the SMU suspend failure
7457          * It needs to set power gating again during gfxoff control
7458          * otherwise the gfxoff disallowing will be failed to set.
7459          */
7460         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7461                 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
7462
7463         if (!adev->no_hw_access) {
7464                 if (amdgpu_async_gfx_ring) {
7465                         if (amdgpu_gfx_disable_kgq(adev, 0))
7466                                 DRM_ERROR("KGQ disable failed\n");
7467                 }
7468
7469                 if (amdgpu_gfx_disable_kcq(adev, 0))
7470                         DRM_ERROR("KCQ disable failed\n");
7471         }
7472
7473         if (amdgpu_sriov_vf(adev)) {
7474                 gfx_v10_0_cp_gfx_enable(adev, false);
7475                 /* Remove the steps of clearing KIQ position.
7476                  * It causes GFX hang when another Win guest is rendering.
7477                  */
7478                 return 0;
7479         }
7480         gfx_v10_0_cp_enable(adev, false);
7481         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7482
7483         return 0;
7484 }
7485
7486 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)
7487 {
7488         return gfx_v10_0_hw_fini(ip_block);
7489 }
7490
7491 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
7492 {
7493         return gfx_v10_0_hw_init(ip_block);
7494 }
7495
7496 static bool gfx_v10_0_is_idle(void *handle)
7497 {
7498         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7499
7500         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7501                                 GRBM_STATUS, GUI_ACTIVE))
7502                 return false;
7503         else
7504                 return true;
7505 }
7506
7507 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
7508 {
7509         unsigned int i;
7510         u32 tmp;
7511         struct amdgpu_device *adev = ip_block->adev;
7512
7513         for (i = 0; i < adev->usec_timeout; i++) {
7514                 /* read MC_STATUS */
7515                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7516                         GRBM_STATUS__GUI_ACTIVE_MASK;
7517
7518                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7519                         return 0;
7520                 udelay(1);
7521         }
7522         return -ETIMEDOUT;
7523 }
7524
7525 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
7526 {
7527         u32 grbm_soft_reset = 0;
7528         u32 tmp;
7529         struct amdgpu_device *adev = ip_block->adev;
7530
7531         /* GRBM_STATUS */
7532         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7533         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7534                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7535                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7536                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7537                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7538                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7539                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7540                                                 1);
7541                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7542                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7543                                                 1);
7544         }
7545
7546         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7547                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7548                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7549                                                 1);
7550         }
7551
7552         /* GRBM_STATUS2 */
7553         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7554         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7555         case IP_VERSION(10, 3, 0):
7556         case IP_VERSION(10, 3, 2):
7557         case IP_VERSION(10, 3, 1):
7558         case IP_VERSION(10, 3, 4):
7559         case IP_VERSION(10, 3, 5):
7560         case IP_VERSION(10, 3, 6):
7561         case IP_VERSION(10, 3, 3):
7562                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7563                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7564                                                         GRBM_SOFT_RESET,
7565                                                         SOFT_RESET_RLC,
7566                                                         1);
7567                 break;
7568         default:
7569                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7570                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7571                                                         GRBM_SOFT_RESET,
7572                                                         SOFT_RESET_RLC,
7573                                                         1);
7574                 break;
7575         }
7576
7577         if (grbm_soft_reset) {
7578                 /* stop the rlc */
7579                 gfx_v10_0_rlc_stop(adev);
7580
7581                 /* Disable GFX parsing/prefetching */
7582                 gfx_v10_0_cp_gfx_enable(adev, false);
7583
7584                 /* Disable MEC parsing/prefetching */
7585                 gfx_v10_0_cp_compute_enable(adev, false);
7586
7587                 if (grbm_soft_reset) {
7588                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7589                         tmp |= grbm_soft_reset;
7590                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7591                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7592                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7593
7594                         udelay(50);
7595
7596                         tmp &= ~grbm_soft_reset;
7597                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7598                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7599                 }
7600
7601                 /* Wait a little for things to settle down */
7602                 udelay(50);
7603         }
7604         return 0;
7605 }
7606
7607 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7608 {
7609         uint64_t clock, clock_lo, clock_hi, hi_check;
7610
7611         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7612         case IP_VERSION(10, 1, 3):
7613         case IP_VERSION(10, 1, 4):
7614                 preempt_disable();
7615                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7616                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7617                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7618                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7619                  * roughly every 42 seconds.
7620                  */
7621                 if (hi_check != clock_hi) {
7622                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7623                         clock_hi = hi_check;
7624                 }
7625                 preempt_enable();
7626                 clock = clock_lo | (clock_hi << 32ULL);
7627                 break;
7628         case IP_VERSION(10, 3, 1):
7629         case IP_VERSION(10, 3, 3):
7630         case IP_VERSION(10, 3, 7):
7631                 preempt_disable();
7632                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7633                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7634                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7635                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7636                  * roughly every 42 seconds.
7637                  */
7638                 if (hi_check != clock_hi) {
7639                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7640                         clock_hi = hi_check;
7641                 }
7642                 preempt_enable();
7643                 clock = clock_lo | (clock_hi << 32ULL);
7644                 break;
7645         case IP_VERSION(10, 3, 6):
7646                 preempt_disable();
7647                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7648                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7649                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7650                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7651                  * roughly every 42 seconds.
7652                  */
7653                 if (hi_check != clock_hi) {
7654                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7655                         clock_hi = hi_check;
7656                 }
7657                 preempt_enable();
7658                 clock = clock_lo | (clock_hi << 32ULL);
7659                 break;
7660         default:
7661                 preempt_disable();
7662                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7663                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7664                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7665                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7666                  * roughly every 42 seconds.
7667                  */
7668                 if (hi_check != clock_hi) {
7669                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7670                         clock_hi = hi_check;
7671                 }
7672                 preempt_enable();
7673                 clock = clock_lo | (clock_hi << 32ULL);
7674                 break;
7675         }
7676         return clock;
7677 }
7678
7679 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7680                                            uint32_t vmid,
7681                                            uint32_t gds_base, uint32_t gds_size,
7682                                            uint32_t gws_base, uint32_t gws_size,
7683                                            uint32_t oa_base, uint32_t oa_size)
7684 {
7685         struct amdgpu_device *adev = ring->adev;
7686
7687         /* GDS Base */
7688         gfx_v10_0_write_data_to_reg(ring, 0, false,
7689                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7690                                     gds_base);
7691
7692         /* GDS Size */
7693         gfx_v10_0_write_data_to_reg(ring, 0, false,
7694                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7695                                     gds_size);
7696
7697         /* GWS */
7698         gfx_v10_0_write_data_to_reg(ring, 0, false,
7699                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7700                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7701
7702         /* OA */
7703         gfx_v10_0_write_data_to_reg(ring, 0, false,
7704                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7705                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7706 }
7707
7708 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)
7709 {
7710         struct amdgpu_device *adev = ip_block->adev;
7711
7712         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7713
7714         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7715         case IP_VERSION(10, 1, 10):
7716         case IP_VERSION(10, 1, 1):
7717         case IP_VERSION(10, 1, 2):
7718         case IP_VERSION(10, 1, 3):
7719         case IP_VERSION(10, 1, 4):
7720                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7721                 break;
7722         case IP_VERSION(10, 3, 0):
7723         case IP_VERSION(10, 3, 2):
7724         case IP_VERSION(10, 3, 1):
7725         case IP_VERSION(10, 3, 4):
7726         case IP_VERSION(10, 3, 5):
7727         case IP_VERSION(10, 3, 6):
7728         case IP_VERSION(10, 3, 3):
7729         case IP_VERSION(10, 3, 7):
7730                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7731                 break;
7732         default:
7733                 break;
7734         }
7735
7736         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7737                                           AMDGPU_MAX_COMPUTE_RINGS);
7738
7739         gfx_v10_0_set_kiq_pm4_funcs(adev);
7740         gfx_v10_0_set_ring_funcs(adev);
7741         gfx_v10_0_set_irq_funcs(adev);
7742         gfx_v10_0_set_gds_init(adev);
7743         gfx_v10_0_set_rlc_funcs(adev);
7744         gfx_v10_0_set_mqd_funcs(adev);
7745
7746         /* init rlcg reg access ctrl */
7747         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7748
7749         return gfx_v10_0_init_microcode(adev);
7750 }
7751
7752 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)
7753 {
7754         struct amdgpu_device *adev = ip_block->adev;
7755         int r;
7756
7757         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7758         if (r)
7759                 return r;
7760
7761         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7762         if (r)
7763                 return r;
7764
7765         r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
7766         if (r)
7767                 return r;
7768
7769         return 0;
7770 }
7771
7772 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7773 {
7774         uint32_t rlc_cntl;
7775
7776         /* if RLC is not enabled, do nothing */
7777         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7778         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7779 }
7780
7781 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7782 {
7783         uint32_t data;
7784         unsigned int i;
7785
7786         data = RLC_SAFE_MODE__CMD_MASK;
7787         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7788
7789         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7790         case IP_VERSION(10, 3, 0):
7791         case IP_VERSION(10, 3, 2):
7792         case IP_VERSION(10, 3, 1):
7793         case IP_VERSION(10, 3, 4):
7794         case IP_VERSION(10, 3, 5):
7795         case IP_VERSION(10, 3, 6):
7796         case IP_VERSION(10, 3, 3):
7797         case IP_VERSION(10, 3, 7):
7798                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7799
7800                 /* wait for RLC_SAFE_MODE */
7801                 for (i = 0; i < adev->usec_timeout; i++) {
7802                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7803                                            RLC_SAFE_MODE, CMD))
7804                                 break;
7805                         udelay(1);
7806                 }
7807                 break;
7808         default:
7809                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7810
7811                 /* wait for RLC_SAFE_MODE */
7812                 for (i = 0; i < adev->usec_timeout; i++) {
7813                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7814                                            RLC_SAFE_MODE, CMD))
7815                                 break;
7816                         udelay(1);
7817                 }
7818                 break;
7819         }
7820 }
7821
7822 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7823 {
7824         uint32_t data;
7825
7826         data = RLC_SAFE_MODE__CMD_MASK;
7827         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7828         case IP_VERSION(10, 3, 0):
7829         case IP_VERSION(10, 3, 2):
7830         case IP_VERSION(10, 3, 1):
7831         case IP_VERSION(10, 3, 4):
7832         case IP_VERSION(10, 3, 5):
7833         case IP_VERSION(10, 3, 6):
7834         case IP_VERSION(10, 3, 3):
7835         case IP_VERSION(10, 3, 7):
7836                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7837                 break;
7838         default:
7839                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7840                 break;
7841         }
7842 }
7843
7844 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7845                                                       bool enable)
7846 {
7847         uint32_t data, def;
7848
7849         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7850                 return;
7851
7852         /* It is disabled by HW by default */
7853         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7854                 /* 0 - Disable some blocks' MGCG */
7855                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7856                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7857                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7858                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7859
7860                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7861                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7862                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7863                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7864                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7865                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7866                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7867                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7868
7869                 if (def != data)
7870                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7871
7872                 /* MGLS is a global flag to control all MGLS in GFX */
7873                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7874                         /* 2 - RLC memory Light sleep */
7875                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7876                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7877                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7878                                 if (def != data)
7879                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7880                         }
7881                         /* 3 - CP memory Light sleep */
7882                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7883                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7884                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7885                                 if (def != data)
7886                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7887                         }
7888                 }
7889         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7890                 /* 1 - MGCG_OVERRIDE */
7891                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7892                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7893                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7894                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7895                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7896                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7897                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7898                 if (def != data)
7899                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7900
7901                 /* 2 - disable MGLS in CP */
7902                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7903                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7904                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7905                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7906                 }
7907
7908                 /* 3 - disable MGLS in RLC */
7909                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7910                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7911                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7912                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7913                 }
7914
7915         }
7916 }
7917
7918 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7919                                            bool enable)
7920 {
7921         uint32_t data, def;
7922
7923         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7924                 return;
7925
7926         /* Enable 3D CGCG/CGLS */
7927         if (enable) {
7928                 /* write cmd to clear cgcg/cgls ov */
7929                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7930
7931                 /* unset CGCG override */
7932                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7933                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7934
7935                 /* update CGCG and CGLS override bits */
7936                 if (def != data)
7937                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7938
7939                 /* enable 3Dcgcg FSM(0x0000363f) */
7940                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7941                 data = 0;
7942
7943                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7944                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7945                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7946
7947                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7948                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7949                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7950
7951                 if (def != data)
7952                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7953
7954                 /* set IDLE_POLL_COUNT(0x00900100) */
7955                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7956                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7957                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7958                 if (def != data)
7959                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7960         } else {
7961                 /* Disable CGCG/CGLS */
7962                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7963
7964                 /* disable cgcg, cgls should be disabled */
7965                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7966                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7967
7968                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7969                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7970
7971                 /* disable cgcg and cgls in FSM */
7972                 if (def != data)
7973                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7974         }
7975 }
7976
7977 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7978                                                       bool enable)
7979 {
7980         uint32_t def, data;
7981
7982         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7983                 return;
7984
7985         if (enable) {
7986                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7987
7988                 /* unset CGCG override */
7989                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7990                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7991
7992                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7993                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7994
7995                 /* update CGCG and CGLS override bits */
7996                 if (def != data)
7997                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7998
7999                 /* enable cgcg FSM(0x0000363F) */
8000                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8001                 data = 0;
8002
8003                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8004                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8005                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8006
8007                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8008                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8009                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8010
8011                 if (def != data)
8012                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8013
8014                 /* set IDLE_POLL_COUNT(0x00900100) */
8015                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8016                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8017                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8018                 if (def != data)
8019                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8020         } else {
8021                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8022
8023                 /* reset CGCG/CGLS bits */
8024                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8025                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8026
8027                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8028                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8029
8030                 /* disable cgcg and cgls in FSM */
8031                 if (def != data)
8032                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8033         }
8034 }
8035
8036 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8037                                                       bool enable)
8038 {
8039         uint32_t def, data;
8040
8041         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8042                 return;
8043
8044         if (enable) {
8045                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8046                 /* unset FGCG override */
8047                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8048                 /* update FGCG override bits */
8049                 if (def != data)
8050                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8051
8052                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8053                 /* unset RLC SRAM CLK GATER override */
8054                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8055                 /* update RLC SRAM CLK GATER override bits */
8056                 if (def != data)
8057                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8058         } else {
8059                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8060                 /* reset FGCG bits */
8061                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8062                 /* disable FGCG*/
8063                 if (def != data)
8064                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8065
8066                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8067                 /* reset RLC SRAM CLK GATER bits */
8068                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8069                 /* disable RLC SRAM CLK*/
8070                 if (def != data)
8071                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8072         }
8073 }
8074
8075 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8076 {
8077         uint32_t reg_data = 0;
8078         uint32_t reg_idx = 0;
8079         uint32_t i;
8080
8081         const uint32_t tcp_ctrl_regs[] = {
8082                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8083                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8084                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8085                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8086                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8087                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8088                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8089                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8090                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8091                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8092                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8093                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8094                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8095                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8096                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8097                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8098                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8099                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8100                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8101                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8102                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8103                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8104                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8105                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8106         };
8107
8108         const uint32_t tcp_ctrl_regs_nv12[] = {
8109                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8110                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8111                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8112                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8113                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8114                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8115                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8116                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8117                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8118                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8119                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8120                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8121                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8122                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8123                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8124                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8125                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8126                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8127                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8128                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8129         };
8130
8131         const uint32_t sm_ctlr_regs[] = {
8132                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8133                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8134                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8135                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8136         };
8137
8138         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
8139                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8140                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8141                                   tcp_ctrl_regs_nv12[i];
8142                         reg_data = RREG32(reg_idx);
8143                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8144                         WREG32(reg_idx, reg_data);
8145                 }
8146         } else {
8147                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8148                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8149                                   tcp_ctrl_regs[i];
8150                         reg_data = RREG32(reg_idx);
8151                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8152                         WREG32(reg_idx, reg_data);
8153                 }
8154         }
8155
8156         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8157                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8158                           sm_ctlr_regs[i];
8159                 reg_data = RREG32(reg_idx);
8160                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8161                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8162                 WREG32(reg_idx, reg_data);
8163         }
8164 }
8165
8166 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8167                                             bool enable)
8168 {
8169         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8170
8171         if (enable) {
8172                 /* enable FGCG firstly*/
8173                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8174                 /* CGCG/CGLS should be enabled after MGCG/MGLS
8175                  * ===  MGCG + MGLS ===
8176                  */
8177                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8178                 /* ===  CGCG /CGLS for GFX 3D Only === */
8179                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8180                 /* ===  CGCG + CGLS === */
8181                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8182
8183                 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8184                      IP_VERSION(10, 1, 10)) ||
8185                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8186                      IP_VERSION(10, 1, 1)) ||
8187                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8188                      IP_VERSION(10, 1, 2)))
8189                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8190         } else {
8191                 /* CGCG/CGLS should be disabled before MGCG/MGLS
8192                  * ===  CGCG + CGLS ===
8193                  */
8194                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8195                 /* ===  CGCG /CGLS for GFX 3D Only === */
8196                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8197                 /* ===  MGCG + MGLS === */
8198                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8199                 /* disable fgcg at last*/
8200                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8201         }
8202
8203         if (adev->cg_flags &
8204             (AMD_CG_SUPPORT_GFX_MGCG |
8205              AMD_CG_SUPPORT_GFX_CGLS |
8206              AMD_CG_SUPPORT_GFX_CGCG |
8207              AMD_CG_SUPPORT_GFX_3D_CGCG |
8208              AMD_CG_SUPPORT_GFX_3D_CGLS))
8209                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8210
8211         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8212
8213         return 0;
8214 }
8215
8216 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8217                                                unsigned int vmid)
8218 {
8219         u32 reg, pre_data, data;
8220
8221         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8222         /* not for *_SOC15 */
8223         if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
8224                 pre_data = RREG32_NO_KIQ(reg);
8225         else
8226                 pre_data = RREG32(reg);
8227
8228         data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
8229         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8230
8231         if (pre_data != data) {
8232                 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
8233                         WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8234                 } else
8235                         WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8236         }
8237 }
8238
8239 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8240 {
8241         amdgpu_gfx_off_ctrl(adev, false);
8242
8243         gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8244
8245         amdgpu_gfx_off_ctrl(adev, true);
8246 }
8247
8248 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8249                                         uint32_t offset,
8250                                         struct soc15_reg_rlcg *entries, int arr_size)
8251 {
8252         int i;
8253         uint32_t reg;
8254
8255         if (!entries)
8256                 return false;
8257
8258         for (i = 0; i < arr_size; i++) {
8259                 const struct soc15_reg_rlcg *entry;
8260
8261                 entry = &entries[i];
8262                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8263                 if (offset == reg)
8264                         return true;
8265         }
8266
8267         return false;
8268 }
8269
8270 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8271 {
8272         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8273 }
8274
8275 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8276 {
8277         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8278
8279         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8280                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8281         else
8282                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8283
8284         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8285
8286         /*
8287          * CGPG enablement required and the register to program the hysteresis value
8288          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8289          * in refclk count. Note that RLC FW is modified to take 16 bits from
8290          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8291          *
8292          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8293          * of CGPG enablement starting point.
8294          * Power/performance team will optimize it and might give a new value later.
8295          */
8296         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8297                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8298                 case IP_VERSION(10, 3, 1):
8299                 case IP_VERSION(10, 3, 3):
8300                 case IP_VERSION(10, 3, 6):
8301                 case IP_VERSION(10, 3, 7):
8302                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8303                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8304                         break;
8305                 default:
8306                         break;
8307                 }
8308         }
8309 }
8310
8311 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8312 {
8313         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8314
8315         gfx_v10_cntl_power_gating(adev, enable);
8316
8317         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8318 }
8319
8320 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8321         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8322         .set_safe_mode = gfx_v10_0_set_safe_mode,
8323         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8324         .init = gfx_v10_0_rlc_init,
8325         .get_csb_size = gfx_v10_0_get_csb_size,
8326         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8327         .resume = gfx_v10_0_rlc_resume,
8328         .stop = gfx_v10_0_rlc_stop,
8329         .reset = gfx_v10_0_rlc_reset,
8330         .start = gfx_v10_0_rlc_start,
8331         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8332 };
8333
8334 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8335         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8336         .set_safe_mode = gfx_v10_0_set_safe_mode,
8337         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8338         .init = gfx_v10_0_rlc_init,
8339         .get_csb_size = gfx_v10_0_get_csb_size,
8340         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8341         .resume = gfx_v10_0_rlc_resume,
8342         .stop = gfx_v10_0_rlc_stop,
8343         .reset = gfx_v10_0_rlc_reset,
8344         .start = gfx_v10_0_rlc_start,
8345         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8346         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8347 };
8348
8349 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
8350                                           enum amd_powergating_state state)
8351 {
8352         struct amdgpu_device *adev = ip_block->adev;
8353         bool enable = (state == AMD_PG_STATE_GATE);
8354
8355         if (amdgpu_sriov_vf(adev))
8356                 return 0;
8357
8358         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8359         case IP_VERSION(10, 1, 10):
8360         case IP_VERSION(10, 1, 1):
8361         case IP_VERSION(10, 1, 2):
8362         case IP_VERSION(10, 3, 0):
8363         case IP_VERSION(10, 3, 2):
8364         case IP_VERSION(10, 3, 4):
8365         case IP_VERSION(10, 3, 5):
8366                 amdgpu_gfx_off_ctrl(adev, enable);
8367                 break;
8368         case IP_VERSION(10, 3, 1):
8369         case IP_VERSION(10, 3, 3):
8370         case IP_VERSION(10, 3, 6):
8371         case IP_VERSION(10, 3, 7):
8372                 if (!enable)
8373                         amdgpu_gfx_off_ctrl(adev, false);
8374
8375                 gfx_v10_cntl_pg(adev, enable);
8376
8377                 if (enable)
8378                         amdgpu_gfx_off_ctrl(adev, true);
8379
8380                 break;
8381         default:
8382                 break;
8383         }
8384         return 0;
8385 }
8386
8387 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
8388                                           enum amd_clockgating_state state)
8389 {
8390         struct amdgpu_device *adev = ip_block->adev;
8391
8392         if (amdgpu_sriov_vf(adev))
8393                 return 0;
8394
8395         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8396         case IP_VERSION(10, 1, 10):
8397         case IP_VERSION(10, 1, 1):
8398         case IP_VERSION(10, 1, 2):
8399         case IP_VERSION(10, 3, 0):
8400         case IP_VERSION(10, 3, 2):
8401         case IP_VERSION(10, 3, 1):
8402         case IP_VERSION(10, 3, 4):
8403         case IP_VERSION(10, 3, 5):
8404         case IP_VERSION(10, 3, 6):
8405         case IP_VERSION(10, 3, 3):
8406         case IP_VERSION(10, 3, 7):
8407                 gfx_v10_0_update_gfx_clock_gating(adev,
8408                                                  state == AMD_CG_STATE_GATE);
8409                 break;
8410         default:
8411                 break;
8412         }
8413         return 0;
8414 }
8415
8416 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8417 {
8418         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8419         int data;
8420
8421         /* AMD_CG_SUPPORT_GFX_FGCG */
8422         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8423         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8424                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8425
8426         /* AMD_CG_SUPPORT_GFX_MGCG */
8427         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8428         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8429                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8430
8431         /* AMD_CG_SUPPORT_GFX_CGCG */
8432         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8433         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8434                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8435
8436         /* AMD_CG_SUPPORT_GFX_CGLS */
8437         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8438                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8439
8440         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8441         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8442         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8443                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8444
8445         /* AMD_CG_SUPPORT_GFX_CP_LS */
8446         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8447         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8448                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8449
8450         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8451         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8452         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8453                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8454
8455         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8456         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8457                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8458 }
8459
8460 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8461 {
8462         /* gfx10 is 32bit rptr*/
8463         return *(uint32_t *)ring->rptr_cpu_addr;
8464 }
8465
8466 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8467 {
8468         struct amdgpu_device *adev = ring->adev;
8469         u64 wptr;
8470
8471         /* XXX check if swapping is necessary on BE */
8472         if (ring->use_doorbell) {
8473                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8474         } else {
8475                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8476                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8477         }
8478
8479         return wptr;
8480 }
8481
8482 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8483 {
8484         struct amdgpu_device *adev = ring->adev;
8485
8486         if (ring->use_doorbell) {
8487                 /* XXX check if swapping is necessary on BE */
8488                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8489                              ring->wptr);
8490                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8491         } else {
8492                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8493                              lower_32_bits(ring->wptr));
8494                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8495                              upper_32_bits(ring->wptr));
8496         }
8497 }
8498
8499 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8500 {
8501         /* gfx10 hardware is 32bit rptr */
8502         return *(uint32_t *)ring->rptr_cpu_addr;
8503 }
8504
8505 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8506 {
8507         u64 wptr;
8508
8509         /* XXX check if swapping is necessary on BE */
8510         if (ring->use_doorbell)
8511                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8512         else
8513                 BUG();
8514         return wptr;
8515 }
8516
8517 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8518 {
8519         struct amdgpu_device *adev = ring->adev;
8520
8521         if (ring->use_doorbell) {
8522                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8523                              ring->wptr);
8524                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8525         } else {
8526                 BUG(); /* only DOORBELL method supported on gfx10 now */
8527         }
8528 }
8529
8530 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8531 {
8532         struct amdgpu_device *adev = ring->adev;
8533         u32 ref_and_mask, reg_mem_engine;
8534         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8535
8536         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8537                 switch (ring->me) {
8538                 case 1:
8539                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8540                         break;
8541                 case 2:
8542                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8543                         break;
8544                 default:
8545                         return;
8546                 }
8547                 reg_mem_engine = 0;
8548         } else {
8549                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8550                 reg_mem_engine = 1; /* pfp */
8551         }
8552
8553         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8554                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8555                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8556                                ref_and_mask, ref_and_mask, 0x20);
8557 }
8558
8559 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8560                                        struct amdgpu_job *job,
8561                                        struct amdgpu_ib *ib,
8562                                        uint32_t flags)
8563 {
8564         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8565         u32 header, control = 0;
8566
8567         if (ib->flags & AMDGPU_IB_FLAG_CE)
8568                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8569         else
8570                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8571
8572         control |= ib->length_dw | (vmid << 24);
8573
8574         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8575                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8576
8577                 if (flags & AMDGPU_IB_PREEMPTED)
8578                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8579
8580                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8581                         gfx_v10_0_ring_emit_de_meta(ring,
8582                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8583         }
8584
8585         amdgpu_ring_write(ring, header);
8586         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8587         amdgpu_ring_write(ring,
8588 #ifdef __BIG_ENDIAN
8589                 (2 << 0) |
8590 #endif
8591                 lower_32_bits(ib->gpu_addr));
8592         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8593         amdgpu_ring_write(ring, control);
8594 }
8595
8596 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8597                                            struct amdgpu_job *job,
8598                                            struct amdgpu_ib *ib,
8599                                            uint32_t flags)
8600 {
8601         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8602         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8603
8604         /* Currently, there is a high possibility to get wave ID mismatch
8605          * between ME and GDS, leading to a hw deadlock, because ME generates
8606          * different wave IDs than the GDS expects. This situation happens
8607          * randomly when at least 5 compute pipes use GDS ordered append.
8608          * The wave IDs generated by ME are also wrong after suspend/resume.
8609          * Those are probably bugs somewhere else in the kernel driver.
8610          *
8611          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8612          * GDS to 0 for this ring (me/pipe).
8613          */
8614         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8615                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8616                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8617                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8618         }
8619
8620         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8621         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8622         amdgpu_ring_write(ring,
8623 #ifdef __BIG_ENDIAN
8624                                 (2 << 0) |
8625 #endif
8626                                 lower_32_bits(ib->gpu_addr));
8627         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8628         amdgpu_ring_write(ring, control);
8629 }
8630
8631 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8632                                      u64 seq, unsigned int flags)
8633 {
8634         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8635         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8636
8637         /* RELEASE_MEM - flush caches, send int */
8638         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8639         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8640                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8641                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8642                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8643                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8644                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8645                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8646         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8647                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8648
8649         /*
8650          * the address should be Qword aligned if 64bit write, Dword
8651          * aligned if only send 32bit data low (discard data high)
8652          */
8653         if (write64bit)
8654                 BUG_ON(addr & 0x7);
8655         else
8656                 BUG_ON(addr & 0x3);
8657         amdgpu_ring_write(ring, lower_32_bits(addr));
8658         amdgpu_ring_write(ring, upper_32_bits(addr));
8659         amdgpu_ring_write(ring, lower_32_bits(seq));
8660         amdgpu_ring_write(ring, upper_32_bits(seq));
8661         amdgpu_ring_write(ring, 0);
8662 }
8663
8664 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8665 {
8666         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8667         uint32_t seq = ring->fence_drv.sync_seq;
8668         uint64_t addr = ring->fence_drv.gpu_addr;
8669
8670         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8671                                upper_32_bits(addr), seq, 0xffffffff, 4);
8672 }
8673
8674 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8675                                    uint16_t pasid, uint32_t flush_type,
8676                                    bool all_hub, uint8_t dst_sel)
8677 {
8678         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8679         amdgpu_ring_write(ring,
8680                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8681                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8682                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8683                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8684 }
8685
8686 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8687                                          unsigned int vmid, uint64_t pd_addr)
8688 {
8689         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8690
8691         /* compute doesn't have PFP */
8692         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8693                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8694                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8695                 amdgpu_ring_write(ring, 0x0);
8696         }
8697 }
8698
8699 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8700                                           u64 seq, unsigned int flags)
8701 {
8702         struct amdgpu_device *adev = ring->adev;
8703
8704         /* we only allocate 32bit for each seq wb address */
8705         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8706
8707         /* write fence seq to the "addr" */
8708         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8709         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8710                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8711         amdgpu_ring_write(ring, lower_32_bits(addr));
8712         amdgpu_ring_write(ring, upper_32_bits(addr));
8713         amdgpu_ring_write(ring, lower_32_bits(seq));
8714
8715         if (flags & AMDGPU_FENCE_FLAG_INT) {
8716                 /* set register to trigger INT */
8717                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8718                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8719                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8720                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8721                 amdgpu_ring_write(ring, 0);
8722                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8723         }
8724 }
8725
8726 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8727 {
8728         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8729         amdgpu_ring_write(ring, 0);
8730 }
8731
8732 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8733                                          uint32_t flags)
8734 {
8735         uint32_t dw2 = 0;
8736
8737         if (ring->adev->gfx.mcbp)
8738                 gfx_v10_0_ring_emit_ce_meta(ring,
8739                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8740
8741         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8742         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8743                 /* set load_global_config & load_global_uconfig */
8744                 dw2 |= 0x8001;
8745                 /* set load_cs_sh_regs */
8746                 dw2 |= 0x01000000;
8747                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8748                 dw2 |= 0x10002;
8749
8750                 /* set load_ce_ram if preamble presented */
8751                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8752                         dw2 |= 0x10000000;
8753         } else {
8754                 /* still load_ce_ram if this is the first time preamble presented
8755                  * although there is no context switch happens.
8756                  */
8757                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8758                         dw2 |= 0x10000000;
8759         }
8760
8761         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8762         amdgpu_ring_write(ring, dw2);
8763         amdgpu_ring_write(ring, 0);
8764 }
8765
8766 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8767                                                        uint64_t addr)
8768 {
8769         unsigned int ret;
8770
8771         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8772         amdgpu_ring_write(ring, lower_32_bits(addr));
8773         amdgpu_ring_write(ring, upper_32_bits(addr));
8774         /* discard following DWs if *cond_exec_gpu_addr==0 */
8775         amdgpu_ring_write(ring, 0);
8776         ret = ring->wptr & ring->buf_mask;
8777         /* patch dummy value later */
8778         amdgpu_ring_write(ring, 0);
8779
8780         return ret;
8781 }
8782
8783 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8784 {
8785         int i, r = 0;
8786         struct amdgpu_device *adev = ring->adev;
8787         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8788         struct amdgpu_ring *kiq_ring = &kiq->ring;
8789         unsigned long flags;
8790
8791         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8792                 return -EINVAL;
8793
8794         spin_lock_irqsave(&kiq->ring_lock, flags);
8795
8796         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8797                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8798                 return -ENOMEM;
8799         }
8800
8801         /* assert preemption condition */
8802         amdgpu_ring_set_preempt_cond_exec(ring, false);
8803
8804         /* assert IB preemption, emit the trailing fence */
8805         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8806                                    ring->trail_fence_gpu_addr,
8807                                    ++ring->trail_seq);
8808         amdgpu_ring_commit(kiq_ring);
8809
8810         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8811
8812         /* poll the trailing fence */
8813         for (i = 0; i < adev->usec_timeout; i++) {
8814                 if (ring->trail_seq ==
8815                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8816                         break;
8817                 udelay(1);
8818         }
8819
8820         if (i >= adev->usec_timeout) {
8821                 r = -EINVAL;
8822                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8823         }
8824
8825         /* deassert preemption condition */
8826         amdgpu_ring_set_preempt_cond_exec(ring, true);
8827         return r;
8828 }
8829
8830 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8831 {
8832         struct amdgpu_device *adev = ring->adev;
8833         struct v10_ce_ib_state ce_payload = {0};
8834         uint64_t offset, ce_payload_gpu_addr;
8835         void *ce_payload_cpu_addr;
8836         int cnt;
8837
8838         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8839
8840         offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8841         ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8842         ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8843
8844         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8845         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8846                                  WRITE_DATA_DST_SEL(8) |
8847                                  WR_CONFIRM) |
8848                                  WRITE_DATA_CACHE_POLICY(0));
8849         amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8850         amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8851
8852         if (resume)
8853                 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8854                                            sizeof(ce_payload) >> 2);
8855         else
8856                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8857                                            sizeof(ce_payload) >> 2);
8858 }
8859
8860 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8861 {
8862         struct amdgpu_device *adev = ring->adev;
8863         struct v10_de_ib_state de_payload = {0};
8864         uint64_t offset, gds_addr, de_payload_gpu_addr;
8865         void *de_payload_cpu_addr;
8866         int cnt;
8867
8868         offset = offsetof(struct v10_gfx_meta_data, de_payload);
8869         de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8870         de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8871
8872         gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8873                          AMDGPU_CSA_SIZE - adev->gds.gds_size,
8874                          PAGE_SIZE);
8875
8876         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8877         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8878
8879         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8880         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8881         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8882                                  WRITE_DATA_DST_SEL(8) |
8883                                  WR_CONFIRM) |
8884                                  WRITE_DATA_CACHE_POLICY(0));
8885         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8886         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8887
8888         if (resume)
8889                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8890                                            sizeof(de_payload) >> 2);
8891         else
8892                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8893                                            sizeof(de_payload) >> 2);
8894 }
8895
8896 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8897                                     bool secure)
8898 {
8899         uint32_t v = secure ? FRAME_TMZ : 0;
8900
8901         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8902         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8903 }
8904
8905 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8906                                      uint32_t reg_val_offs)
8907 {
8908         struct amdgpu_device *adev = ring->adev;
8909
8910         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8911         amdgpu_ring_write(ring, 0 |     /* src: register*/
8912                                 (5 << 8) |      /* dst: memory */
8913                                 (1 << 20));     /* write confirm */
8914         amdgpu_ring_write(ring, reg);
8915         amdgpu_ring_write(ring, 0);
8916         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8917                                 reg_val_offs * 4));
8918         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8919                                 reg_val_offs * 4));
8920 }
8921
8922 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8923                                    uint32_t val)
8924 {
8925         uint32_t cmd = 0;
8926
8927         switch (ring->funcs->type) {
8928         case AMDGPU_RING_TYPE_GFX:
8929                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8930                 break;
8931         case AMDGPU_RING_TYPE_KIQ:
8932                 cmd = (1 << 16); /* no inc addr */
8933                 break;
8934         default:
8935                 cmd = WR_CONFIRM;
8936                 break;
8937         }
8938         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8939         amdgpu_ring_write(ring, cmd);
8940         amdgpu_ring_write(ring, reg);
8941         amdgpu_ring_write(ring, 0);
8942         amdgpu_ring_write(ring, val);
8943 }
8944
8945 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8946                                         uint32_t val, uint32_t mask)
8947 {
8948         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8949 }
8950
8951 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8952                                                    uint32_t reg0, uint32_t reg1,
8953                                                    uint32_t ref, uint32_t mask)
8954 {
8955         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8956         struct amdgpu_device *adev = ring->adev;
8957         bool fw_version_ok = false;
8958
8959         fw_version_ok = adev->gfx.cp_fw_write_wait;
8960
8961         if (fw_version_ok)
8962                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8963                                        ref, mask, 0x20);
8964         else
8965                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8966                                                            ref, mask);
8967 }
8968
8969 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8970                                          unsigned int vmid)
8971 {
8972         struct amdgpu_device *adev = ring->adev;
8973         uint32_t value = 0;
8974
8975         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8976         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8977         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8978         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8979         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8980         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8981         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8982 }
8983
8984 static void
8985 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8986                                       uint32_t me, uint32_t pipe,
8987                                       enum amdgpu_interrupt_state state)
8988 {
8989         uint32_t cp_int_cntl, cp_int_cntl_reg;
8990
8991         if (!me) {
8992                 switch (pipe) {
8993                 case 0:
8994                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8995                         break;
8996                 case 1:
8997                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8998                         break;
8999                 default:
9000                         DRM_DEBUG("invalid pipe %d\n", pipe);
9001                         return;
9002                 }
9003         } else {
9004                 DRM_DEBUG("invalid me %d\n", me);
9005                 return;
9006         }
9007
9008         switch (state) {
9009         case AMDGPU_IRQ_STATE_DISABLE:
9010                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9011                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9012                                             TIME_STAMP_INT_ENABLE, 0);
9013                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9014                 break;
9015         case AMDGPU_IRQ_STATE_ENABLE:
9016                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9017                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9018                                             TIME_STAMP_INT_ENABLE, 1);
9019                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9020                 break;
9021         default:
9022                 break;
9023         }
9024 }
9025
9026 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9027                                                      int me, int pipe,
9028                                                      enum amdgpu_interrupt_state state)
9029 {
9030         u32 mec_int_cntl, mec_int_cntl_reg;
9031
9032         /*
9033          * amdgpu controls only the first MEC. That's why this function only
9034          * handles the setting of interrupts for this specific MEC. All other
9035          * pipes' interrupts are set by amdkfd.
9036          */
9037
9038         if (me == 1) {
9039                 switch (pipe) {
9040                 case 0:
9041                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9042                         break;
9043                 case 1:
9044                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9045                         break;
9046                 case 2:
9047                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9048                         break;
9049                 case 3:
9050                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9051                         break;
9052                 default:
9053                         DRM_DEBUG("invalid pipe %d\n", pipe);
9054                         return;
9055                 }
9056         } else {
9057                 DRM_DEBUG("invalid me %d\n", me);
9058                 return;
9059         }
9060
9061         switch (state) {
9062         case AMDGPU_IRQ_STATE_DISABLE:
9063                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9064                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9065                                              TIME_STAMP_INT_ENABLE, 0);
9066                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9067                 break;
9068         case AMDGPU_IRQ_STATE_ENABLE:
9069                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9070                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9071                                              TIME_STAMP_INT_ENABLE, 1);
9072                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9073                 break;
9074         default:
9075                 break;
9076         }
9077 }
9078
9079 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9080                                             struct amdgpu_irq_src *src,
9081                                             unsigned int type,
9082                                             enum amdgpu_interrupt_state state)
9083 {
9084         switch (type) {
9085         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9086                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9087                 break;
9088         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9089                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9090                 break;
9091         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9092                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9093                 break;
9094         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9095                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9096                 break;
9097         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9098                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9099                 break;
9100         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9101                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9102                 break;
9103         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9104                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9105                 break;
9106         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9107                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9108                 break;
9109         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9110                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9111                 break;
9112         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9113                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9114                 break;
9115         default:
9116                 break;
9117         }
9118         return 0;
9119 }
9120
9121 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9122                              struct amdgpu_irq_src *source,
9123                              struct amdgpu_iv_entry *entry)
9124 {
9125         int i;
9126         u8 me_id, pipe_id, queue_id;
9127         struct amdgpu_ring *ring;
9128
9129         DRM_DEBUG("IH: CP EOP\n");
9130
9131         me_id = (entry->ring_id & 0x0c) >> 2;
9132         pipe_id = (entry->ring_id & 0x03) >> 0;
9133         queue_id = (entry->ring_id & 0x70) >> 4;
9134
9135         switch (me_id) {
9136         case 0:
9137                 if (pipe_id == 0)
9138                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9139                 else
9140                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9141                 break;
9142         case 1:
9143         case 2:
9144                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9145                         ring = &adev->gfx.compute_ring[i];
9146                         /* Per-queue interrupt is supported for MEC starting from VI.
9147                          * The interrupt can only be enabled/disabled per pipe instead
9148                          * of per queue.
9149                          */
9150                         if ((ring->me == me_id) &&
9151                             (ring->pipe == pipe_id) &&
9152                             (ring->queue == queue_id))
9153                                 amdgpu_fence_process(ring);
9154                 }
9155                 break;
9156         }
9157
9158         return 0;
9159 }
9160
9161 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9162                                               struct amdgpu_irq_src *source,
9163                                               unsigned int type,
9164                                               enum amdgpu_interrupt_state state)
9165 {
9166         u32 cp_int_cntl_reg, cp_int_cntl;
9167         int i, j;
9168
9169         switch (state) {
9170         case AMDGPU_IRQ_STATE_DISABLE:
9171         case AMDGPU_IRQ_STATE_ENABLE:
9172                 for (i = 0; i < adev->gfx.me.num_me; i++) {
9173                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9174                                 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9175
9176                                 if (cp_int_cntl_reg) {
9177                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9178                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9179                                                                     PRIV_REG_INT_ENABLE,
9180                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9181                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9182                                 }
9183                         }
9184                 }
9185                 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9186                         for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9187                                 /* MECs start at 1 */
9188                                 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9189
9190                                 if (cp_int_cntl_reg) {
9191                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9192                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9193                                                                     PRIV_REG_INT_ENABLE,
9194                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9195                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9196                                 }
9197                         }
9198                 }
9199                 break;
9200         default:
9201                 break;
9202         }
9203
9204         return 0;
9205 }
9206
9207 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
9208                                             struct amdgpu_irq_src *source,
9209                                             unsigned type,
9210                                             enum amdgpu_interrupt_state state)
9211 {
9212         u32 cp_int_cntl_reg, cp_int_cntl;
9213         int i, j;
9214
9215         switch (state) {
9216         case AMDGPU_IRQ_STATE_DISABLE:
9217         case AMDGPU_IRQ_STATE_ENABLE:
9218                 for (i = 0; i < adev->gfx.me.num_me; i++) {
9219                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9220                                 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9221
9222                                 if (cp_int_cntl_reg) {
9223                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9224                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9225                                                                     OPCODE_ERROR_INT_ENABLE,
9226                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9227                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9228                                 }
9229                         }
9230                 }
9231                 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9232                         for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9233                                 /* MECs start at 1 */
9234                                 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9235
9236                                 if (cp_int_cntl_reg) {
9237                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9238                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9239                                                                     OPCODE_ERROR_INT_ENABLE,
9240                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9241                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9242                                 }
9243                         }
9244                 }
9245                 break;
9246         default:
9247                 break;
9248         }
9249         return 0;
9250 }
9251
9252 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9253                                                struct amdgpu_irq_src *source,
9254                                                unsigned int type,
9255                                                enum amdgpu_interrupt_state state)
9256 {
9257         u32 cp_int_cntl_reg, cp_int_cntl;
9258         int i, j;
9259
9260         switch (state) {
9261         case AMDGPU_IRQ_STATE_DISABLE:
9262         case AMDGPU_IRQ_STATE_ENABLE:
9263                 for (i = 0; i < adev->gfx.me.num_me; i++) {
9264                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9265                                 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9266
9267                                 if (cp_int_cntl_reg) {
9268                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9269                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9270                                                                     PRIV_INSTR_INT_ENABLE,
9271                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9272                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9273                                 }
9274                         }
9275                 }
9276                 break;
9277         default:
9278                 break;
9279         }
9280
9281         return 0;
9282 }
9283
9284 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9285                                         struct amdgpu_iv_entry *entry)
9286 {
9287         u8 me_id, pipe_id, queue_id;
9288         struct amdgpu_ring *ring;
9289         int i;
9290
9291         me_id = (entry->ring_id & 0x0c) >> 2;
9292         pipe_id = (entry->ring_id & 0x03) >> 0;
9293         queue_id = (entry->ring_id & 0x70) >> 4;
9294
9295         switch (me_id) {
9296         case 0:
9297                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9298                         ring = &adev->gfx.gfx_ring[i];
9299                         if (ring->me == me_id && ring->pipe == pipe_id &&
9300                             ring->queue == queue_id)
9301                                 drm_sched_fault(&ring->sched);
9302                 }
9303                 break;
9304         case 1:
9305         case 2:
9306                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9307                         ring = &adev->gfx.compute_ring[i];
9308                         if (ring->me == me_id && ring->pipe == pipe_id &&
9309                             ring->queue == queue_id)
9310                                 drm_sched_fault(&ring->sched);
9311                 }
9312                 break;
9313         default:
9314                 BUG();
9315         }
9316 }
9317
9318 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9319                                   struct amdgpu_irq_src *source,
9320                                   struct amdgpu_iv_entry *entry)
9321 {
9322         DRM_ERROR("Illegal register access in command stream\n");
9323         gfx_v10_0_handle_priv_fault(adev, entry);
9324         return 0;
9325 }
9326
9327 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
9328                                 struct amdgpu_irq_src *source,
9329                                 struct amdgpu_iv_entry *entry)
9330 {
9331         DRM_ERROR("Illegal opcode in command stream \n");
9332         gfx_v10_0_handle_priv_fault(adev, entry);
9333         return 0;
9334 }
9335
9336 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9337                                    struct amdgpu_irq_src *source,
9338                                    struct amdgpu_iv_entry *entry)
9339 {
9340         DRM_ERROR("Illegal instruction in command stream\n");
9341         gfx_v10_0_handle_priv_fault(adev, entry);
9342         return 0;
9343 }
9344
9345 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9346                                              struct amdgpu_irq_src *src,
9347                                              unsigned int type,
9348                                              enum amdgpu_interrupt_state state)
9349 {
9350         uint32_t tmp, target;
9351         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9352
9353         if (ring->me == 1)
9354                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9355         else
9356                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9357         target += ring->pipe;
9358
9359         switch (type) {
9360         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9361                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9362                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9363                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9364                                             GENERIC2_INT_ENABLE, 0);
9365                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9366
9367                         tmp = RREG32_SOC15_IP(GC, target);
9368                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9369                                             GENERIC2_INT_ENABLE, 0);
9370                         WREG32_SOC15_IP(GC, target, tmp);
9371                 } else {
9372                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9373                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9374                                             GENERIC2_INT_ENABLE, 1);
9375                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9376
9377                         tmp = RREG32_SOC15_IP(GC, target);
9378                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9379                                             GENERIC2_INT_ENABLE, 1);
9380                         WREG32_SOC15_IP(GC, target, tmp);
9381                 }
9382                 break;
9383         default:
9384                 BUG(); /* kiq only support GENERIC2_INT now */
9385                 break;
9386         }
9387         return 0;
9388 }
9389
9390 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9391                              struct amdgpu_irq_src *source,
9392                              struct amdgpu_iv_entry *entry)
9393 {
9394         u8 me_id, pipe_id, queue_id;
9395         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9396
9397         me_id = (entry->ring_id & 0x0c) >> 2;
9398         pipe_id = (entry->ring_id & 0x03) >> 0;
9399         queue_id = (entry->ring_id & 0x70) >> 4;
9400         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9401                    me_id, pipe_id, queue_id);
9402
9403         amdgpu_fence_process(ring);
9404         return 0;
9405 }
9406
9407 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9408 {
9409         const unsigned int gcr_cntl =
9410                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9411                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9412                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9413                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9414                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9415                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9416                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9417                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9418
9419         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9420         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9421         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9422         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9423         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9424         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9425         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9426         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9427         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9428 }
9429
9430 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
9431 {
9432         /* Header itself is a NOP packet */
9433         if (num_nop == 1) {
9434                 amdgpu_ring_write(ring, ring->funcs->nop);
9435                 return;
9436         }
9437
9438         /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
9439         amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
9440
9441         /* Header is at index 0, followed by num_nops - 1 NOP packet's */
9442         amdgpu_ring_insert_nop(ring, num_nop - 1);
9443 }
9444
9445 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
9446 {
9447         struct amdgpu_device *adev = ring->adev;
9448         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9449         struct amdgpu_ring *kiq_ring = &kiq->ring;
9450         unsigned long flags;
9451         u32 tmp;
9452         u64 addr;
9453         int r;
9454
9455         if (amdgpu_sriov_vf(adev))
9456                 return -EINVAL;
9457
9458         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9459                 return -EINVAL;
9460
9461         spin_lock_irqsave(&kiq->ring_lock, flags);
9462
9463         if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
9464                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9465                 return -ENOMEM;
9466         }
9467
9468         addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +
9469                 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);
9470         tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
9471         if (ring->pipe == 0)
9472                 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
9473         else
9474                 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
9475
9476         gfx_v10_0_ring_emit_wreg(kiq_ring,
9477                                  SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
9478         gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,
9479                                lower_32_bits(addr), upper_32_bits(addr),
9480                                0, 1, 0x20);
9481         gfx_v10_0_ring_emit_reg_wait(kiq_ring,
9482                                      SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
9483         kiq->pmf->kiq_map_queues(kiq_ring, ring);
9484         amdgpu_ring_commit(kiq_ring);
9485
9486         spin_unlock_irqrestore(&kiq->ring_lock, flags);
9487
9488         r = amdgpu_ring_test_ring(kiq_ring);
9489         if (r)
9490                 return r;
9491
9492         r = amdgpu_bo_reserve(ring->mqd_obj, false);
9493         if (unlikely(r != 0)) {
9494                 DRM_ERROR("fail to resv mqd_obj\n");
9495                 return r;
9496         }
9497         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9498         if (!r) {
9499                 r = gfx_v10_0_kgq_init_queue(ring, true);
9500                 amdgpu_bo_kunmap(ring->mqd_obj);
9501                 ring->mqd_ptr = NULL;
9502         }
9503         amdgpu_bo_unreserve(ring->mqd_obj);
9504         if (r) {
9505                 DRM_ERROR("fail to unresv mqd_obj\n");
9506                 return r;
9507         }
9508
9509         return amdgpu_ring_test_ring(ring);
9510 }
9511
9512 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
9513                                unsigned int vmid)
9514 {
9515         struct amdgpu_device *adev = ring->adev;
9516         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9517         struct amdgpu_ring *kiq_ring = &kiq->ring;
9518         unsigned long flags;
9519         int i, r;
9520
9521         if (amdgpu_sriov_vf(adev))
9522                 return -EINVAL;
9523
9524         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9525                 return -EINVAL;
9526
9527         spin_lock_irqsave(&kiq->ring_lock, flags);
9528
9529         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
9530                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9531                 return -ENOMEM;
9532         }
9533
9534         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
9535                                    0, 0);
9536         amdgpu_ring_commit(kiq_ring);
9537         spin_unlock_irqrestore(&kiq->ring_lock, flags);
9538
9539         r = amdgpu_ring_test_ring(kiq_ring);
9540         if (r)
9541                 return r;
9542
9543         /* make sure dequeue is complete*/
9544         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9545         mutex_lock(&adev->srbm_mutex);
9546         nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
9547         for (i = 0; i < adev->usec_timeout; i++) {
9548                 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
9549                         break;
9550                 udelay(1);
9551         }
9552         if (i >= adev->usec_timeout)
9553                 r = -ETIMEDOUT;
9554         nv_grbm_select(adev, 0, 0, 0, 0);
9555         mutex_unlock(&adev->srbm_mutex);
9556         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9557         if (r) {
9558                 dev_err(adev->dev, "fail to wait on hqd deactivate\n");
9559                 return r;
9560         }
9561
9562         r = amdgpu_bo_reserve(ring->mqd_obj, false);
9563         if (unlikely(r != 0)) {
9564                 dev_err(adev->dev, "fail to resv mqd_obj\n");
9565                 return r;
9566         }
9567         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9568         if (!r) {
9569                 r = gfx_v10_0_kcq_init_queue(ring, true);
9570                 amdgpu_bo_kunmap(ring->mqd_obj);
9571                 ring->mqd_ptr = NULL;
9572         }
9573         amdgpu_bo_unreserve(ring->mqd_obj);
9574         if (r) {
9575                 dev_err(adev->dev, "fail to unresv mqd_obj\n");
9576                 return r;
9577         }
9578
9579         spin_lock_irqsave(&kiq->ring_lock, flags);
9580         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
9581                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9582                 return -ENOMEM;
9583         }
9584         kiq->pmf->kiq_map_queues(kiq_ring, ring);
9585         amdgpu_ring_commit(kiq_ring);
9586         spin_unlock_irqrestore(&kiq->ring_lock, flags);
9587
9588         r = amdgpu_ring_test_ring(kiq_ring);
9589         if (r)
9590                 return r;
9591
9592         return amdgpu_ring_test_ring(ring);
9593 }
9594
9595 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
9596 {
9597         struct amdgpu_device *adev = ip_block->adev;
9598         uint32_t i, j, k, reg, index = 0;
9599         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9600
9601         if (!adev->gfx.ip_dump_core)
9602                 return;
9603
9604         for (i = 0; i < reg_count; i++)
9605                 drm_printf(p, "%-50s \t 0x%08x\n",
9606                            gc_reg_list_10_1[i].reg_name,
9607                            adev->gfx.ip_dump_core[i]);
9608
9609         /* print compute queue registers for all instances */
9610         if (!adev->gfx.ip_dump_compute_queues)
9611                 return;
9612
9613         reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9614         drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
9615                    adev->gfx.mec.num_mec,
9616                    adev->gfx.mec.num_pipe_per_mec,
9617                    adev->gfx.mec.num_queue_per_pipe);
9618
9619         for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9620                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9621                         for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9622                                 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
9623                                 for (reg = 0; reg < reg_count; reg++) {
9624                                         drm_printf(p, "%-50s \t 0x%08x\n",
9625                                                    gc_cp_reg_list_10[reg].reg_name,
9626                                                    adev->gfx.ip_dump_compute_queues[index + reg]);
9627                                 }
9628                                 index += reg_count;
9629                         }
9630                 }
9631         }
9632
9633         /* print gfx queue registers for all instances */
9634         if (!adev->gfx.ip_dump_gfx_queues)
9635                 return;
9636
9637         index = 0;
9638         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9639         drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
9640                    adev->gfx.me.num_me,
9641                    adev->gfx.me.num_pipe_per_me,
9642                    adev->gfx.me.num_queue_per_pipe);
9643
9644         for (i = 0; i < adev->gfx.me.num_me; i++) {
9645                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9646                         for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9647                                 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
9648                                 for (reg = 0; reg < reg_count; reg++) {
9649                                         drm_printf(p, "%-50s \t 0x%08x\n",
9650                                                    gc_gfx_queue_reg_list_10[reg].reg_name,
9651                                                    adev->gfx.ip_dump_gfx_queues[index + reg]);
9652                                 }
9653                                 index += reg_count;
9654                         }
9655                 }
9656         }
9657 }
9658
9659 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
9660 {
9661         struct amdgpu_device *adev = ip_block->adev;
9662         uint32_t i, j, k, reg, index = 0;
9663         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9664
9665         if (!adev->gfx.ip_dump_core)
9666                 return;
9667
9668         amdgpu_gfx_off_ctrl(adev, false);
9669         for (i = 0; i < reg_count; i++)
9670                 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9671         amdgpu_gfx_off_ctrl(adev, true);
9672
9673         /* dump compute queue registers for all instances */
9674         if (!adev->gfx.ip_dump_compute_queues)
9675                 return;
9676
9677         reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9678         amdgpu_gfx_off_ctrl(adev, false);
9679         mutex_lock(&adev->srbm_mutex);
9680         for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9681                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9682                         for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9683                                 /* ME0 is for GFX so start from 1 for CP */
9684                                 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
9685
9686                                 for (reg = 0; reg < reg_count; reg++) {
9687                                         adev->gfx.ip_dump_compute_queues[index + reg] =
9688                                                 RREG32(SOC15_REG_ENTRY_OFFSET(
9689                                                         gc_cp_reg_list_10[reg]));
9690                                 }
9691                                 index += reg_count;
9692                         }
9693                 }
9694         }
9695         nv_grbm_select(adev, 0, 0, 0, 0);
9696         mutex_unlock(&adev->srbm_mutex);
9697         amdgpu_gfx_off_ctrl(adev, true);
9698
9699         /* dump gfx queue registers for all instances */
9700         if (!adev->gfx.ip_dump_gfx_queues)
9701                 return;
9702
9703         index = 0;
9704         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9705         amdgpu_gfx_off_ctrl(adev, false);
9706         mutex_lock(&adev->srbm_mutex);
9707         for (i = 0; i < adev->gfx.me.num_me; i++) {
9708                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9709                         for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9710                                 nv_grbm_select(adev, i, j, k, 0);
9711
9712                                 for (reg = 0; reg < reg_count; reg++) {
9713                                         adev->gfx.ip_dump_gfx_queues[index + reg] =
9714                                                 RREG32(SOC15_REG_ENTRY_OFFSET(
9715                                                         gc_gfx_queue_reg_list_10[reg]));
9716                                 }
9717                                 index += reg_count;
9718                         }
9719                 }
9720         }
9721         nv_grbm_select(adev, 0, 0, 0, 0);
9722         mutex_unlock(&adev->srbm_mutex);
9723         amdgpu_gfx_off_ctrl(adev, true);
9724 }
9725
9726 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
9727 {
9728         /* Emit the cleaner shader */
9729         amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
9730         amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */
9731 }
9732
9733 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9734         .name = "gfx_v10_0",
9735         .early_init = gfx_v10_0_early_init,
9736         .late_init = gfx_v10_0_late_init,
9737         .sw_init = gfx_v10_0_sw_init,
9738         .sw_fini = gfx_v10_0_sw_fini,
9739         .hw_init = gfx_v10_0_hw_init,
9740         .hw_fini = gfx_v10_0_hw_fini,
9741         .suspend = gfx_v10_0_suspend,
9742         .resume = gfx_v10_0_resume,
9743         .is_idle = gfx_v10_0_is_idle,
9744         .wait_for_idle = gfx_v10_0_wait_for_idle,
9745         .soft_reset = gfx_v10_0_soft_reset,
9746         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9747         .set_powergating_state = gfx_v10_0_set_powergating_state,
9748         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9749         .dump_ip_state = gfx_v10_ip_dump,
9750         .print_ip_state = gfx_v10_ip_print,
9751 };
9752
9753 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9754         .type = AMDGPU_RING_TYPE_GFX,
9755         .align_mask = 0xff,
9756         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9757         .support_64bit_ptrs = true,
9758         .secure_submission_supported = true,
9759         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9760         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9761         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9762         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9763                 5 + /* COND_EXEC */
9764                 7 + /* PIPELINE_SYNC */
9765                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9766                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9767                 4 + /* VM_FLUSH */
9768                 8 + /* FENCE for VM_FLUSH */
9769                 20 + /* GDS switch */
9770                 4 + /* double SWITCH_BUFFER,
9771                      * the first COND_EXEC jump to the place
9772                      * just prior to this double SWITCH_BUFFER
9773                      */
9774                 5 + /* COND_EXEC */
9775                 7 + /* HDP_flush */
9776                 4 + /* VGT_flush */
9777                 14 + /* CE_META */
9778                 31 + /* DE_META */
9779                 3 + /* CNTX_CTRL */
9780                 5 + /* HDP_INVL */
9781                 8 + 8 + /* FENCE x2 */
9782                 2 + /* SWITCH_BUFFER */
9783                 8 + /* gfx_v10_0_emit_mem_sync */
9784                 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9785         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9786         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9787         .emit_fence = gfx_v10_0_ring_emit_fence,
9788         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9789         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9790         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9791         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9792         .test_ring = gfx_v10_0_ring_test_ring,
9793         .test_ib = gfx_v10_0_ring_test_ib,
9794         .insert_nop = gfx_v10_ring_insert_nop,
9795         .pad_ib = amdgpu_ring_generic_pad_ib,
9796         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9797         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9798         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9799         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9800         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9801         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9802         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9803         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9804         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9805         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9806         .reset = gfx_v10_0_reset_kgq,
9807         .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9808         .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
9809         .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
9810 };
9811
9812 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9813         .type = AMDGPU_RING_TYPE_COMPUTE,
9814         .align_mask = 0xff,
9815         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9816         .support_64bit_ptrs = true,
9817         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9818         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9819         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9820         .emit_frame_size =
9821                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9822                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9823                 5 + /* hdp invalidate */
9824                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9825                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9826                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9827                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9828                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9829                 8 + /* gfx_v10_0_emit_mem_sync */
9830                 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9831         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9832         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9833         .emit_fence = gfx_v10_0_ring_emit_fence,
9834         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9835         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9836         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9837         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9838         .test_ring = gfx_v10_0_ring_test_ring,
9839         .test_ib = gfx_v10_0_ring_test_ib,
9840         .insert_nop = gfx_v10_ring_insert_nop,
9841         .pad_ib = amdgpu_ring_generic_pad_ib,
9842         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9843         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9844         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9845         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9846         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9847         .reset = gfx_v10_0_reset_kcq,
9848         .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9849         .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
9850         .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
9851 };
9852
9853 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9854         .type = AMDGPU_RING_TYPE_KIQ,
9855         .align_mask = 0xff,
9856         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9857         .support_64bit_ptrs = true,
9858         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9859         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9860         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9861         .emit_frame_size =
9862                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9863                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9864                 5 + /*hdp invalidate */
9865                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9866                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9867                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9868                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9869         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9870         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9871         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9872         .test_ring = gfx_v10_0_ring_test_ring,
9873         .test_ib = gfx_v10_0_ring_test_ib,
9874         .insert_nop = amdgpu_ring_insert_nop,
9875         .pad_ib = amdgpu_ring_generic_pad_ib,
9876         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9877         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9878         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9879         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9880 };
9881
9882 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9883 {
9884         int i;
9885
9886         adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9887
9888         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9889                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9890
9891         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9892                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9893 }
9894
9895 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9896         .set = gfx_v10_0_set_eop_interrupt_state,
9897         .process = gfx_v10_0_eop_irq,
9898 };
9899
9900 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9901         .set = gfx_v10_0_set_priv_reg_fault_state,
9902         .process = gfx_v10_0_priv_reg_irq,
9903 };
9904
9905 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
9906         .set = gfx_v10_0_set_bad_op_fault_state,
9907         .process = gfx_v10_0_bad_op_irq,
9908 };
9909
9910 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9911         .set = gfx_v10_0_set_priv_inst_fault_state,
9912         .process = gfx_v10_0_priv_inst_irq,
9913 };
9914
9915 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9916         .set = gfx_v10_0_kiq_set_interrupt_state,
9917         .process = gfx_v10_0_kiq_irq,
9918 };
9919
9920 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9921 {
9922         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9923         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9924
9925         adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9926         adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9927
9928         adev->gfx.priv_reg_irq.num_types = 1;
9929         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9930
9931         adev->gfx.bad_op_irq.num_types = 1;
9932         adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
9933
9934         adev->gfx.priv_inst_irq.num_types = 1;
9935         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9936 }
9937
9938 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9939 {
9940         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9941         case IP_VERSION(10, 1, 10):
9942         case IP_VERSION(10, 1, 1):
9943         case IP_VERSION(10, 1, 3):
9944         case IP_VERSION(10, 1, 4):
9945         case IP_VERSION(10, 3, 2):
9946         case IP_VERSION(10, 3, 1):
9947         case IP_VERSION(10, 3, 4):
9948         case IP_VERSION(10, 3, 5):
9949         case IP_VERSION(10, 3, 6):
9950         case IP_VERSION(10, 3, 3):
9951         case IP_VERSION(10, 3, 7):
9952                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9953                 break;
9954         case IP_VERSION(10, 1, 2):
9955         case IP_VERSION(10, 3, 0):
9956                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9957                 break;
9958         default:
9959                 break;
9960         }
9961 }
9962
9963 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9964 {
9965         unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9966                             adev->gfx.config.max_sh_per_se *
9967                             adev->gfx.config.max_shader_engines;
9968
9969         adev->gds.gds_size = 0x10000;
9970         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9971         adev->gds.gws_size = 64;
9972         adev->gds.oa_size = 16;
9973 }
9974
9975 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9976 {
9977         /* set gfx eng mqd */
9978         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9979                 sizeof(struct v10_gfx_mqd);
9980         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9981                 gfx_v10_0_gfx_mqd_init;
9982         /* set compute eng mqd */
9983         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9984                 sizeof(struct v10_compute_mqd);
9985         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9986                 gfx_v10_0_compute_mqd_init;
9987 }
9988
9989 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9990                                                           u32 bitmap)
9991 {
9992         u32 data;
9993
9994         if (!bitmap)
9995                 return;
9996
9997         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9998         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9999
10000         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
10001 }
10002
10003 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
10004 {
10005         u32 disabled_mask =
10006                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
10007         u32 efuse_setting = 0;
10008         u32 vbios_setting = 0;
10009
10010         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
10011         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10012         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10013
10014         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
10015         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10016         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10017
10018         disabled_mask |= efuse_setting | vbios_setting;
10019
10020         return (~disabled_mask);
10021 }
10022
10023 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
10024 {
10025         u32 wgp_idx, wgp_active_bitmap;
10026         u32 cu_bitmap_per_wgp, cu_active_bitmap;
10027
10028         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
10029         cu_active_bitmap = 0;
10030
10031         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
10032                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
10033                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
10034                 if (wgp_active_bitmap & (1 << wgp_idx))
10035                         cu_active_bitmap |= cu_bitmap_per_wgp;
10036         }
10037
10038         return cu_active_bitmap;
10039 }
10040
10041 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
10042                                  struct amdgpu_cu_info *cu_info)
10043 {
10044         int i, j, k, counter, active_cu_number = 0;
10045         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
10046         unsigned int disable_masks[4 * 2];
10047
10048         if (!adev || !cu_info)
10049                 return -EINVAL;
10050
10051         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
10052
10053         mutex_lock(&adev->grbm_idx_mutex);
10054         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
10055                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
10056                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
10057                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
10058                               IP_VERSION(10, 3, 0)) ||
10059                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10060                               IP_VERSION(10, 3, 3)) ||
10061                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10062                               IP_VERSION(10, 3, 6)) ||
10063                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10064                               IP_VERSION(10, 3, 7))) &&
10065                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
10066                                 continue;
10067                         mask = 1;
10068                         ao_bitmap = 0;
10069                         counter = 0;
10070                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
10071                         if (i < 4 && j < 2)
10072                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
10073                                         adev, disable_masks[i * 2 + j]);
10074                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
10075                         cu_info->bitmap[0][i][j] = bitmap;
10076
10077                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
10078                                 if (bitmap & mask) {
10079                                         if (counter < adev->gfx.config.max_cu_per_sh)
10080                                                 ao_bitmap |= mask;
10081                                         counter++;
10082                                 }
10083                                 mask <<= 1;
10084                         }
10085                         active_cu_number += counter;
10086                         if (i < 2 && j < 2)
10087                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
10088                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
10089                 }
10090         }
10091         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
10092         mutex_unlock(&adev->grbm_idx_mutex);
10093
10094         cu_info->number = active_cu_number;
10095         cu_info->ao_cu_mask = ao_cu_mask;
10096         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
10097
10098         return 0;
10099 }
10100
10101 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
10102 {
10103         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
10104
10105         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
10106         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10107         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10108
10109         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
10110         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10111         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10112
10113         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
10114                                                 adev->gfx.config.max_shader_engines);
10115         disabled_sa = efuse_setting | vbios_setting;
10116         disabled_sa &= max_sa_mask;
10117
10118         return disabled_sa;
10119 }
10120
10121 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
10122 {
10123         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
10124         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
10125
10126         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
10127
10128         max_sa_per_se = adev->gfx.config.max_sh_per_se;
10129         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
10130         max_shader_engines = adev->gfx.config.max_shader_engines;
10131
10132         for (se_index = 0; max_shader_engines > se_index; se_index++) {
10133                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
10134                 disabled_sa_per_se &= max_sa_per_se_mask;
10135                 if (disabled_sa_per_se == max_sa_per_se_mask) {
10136                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
10137                         break;
10138                 }
10139         }
10140 }
10141
10142 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
10143 {
10144         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
10145                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
10146                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
10147                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
10148
10149         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
10150         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
10151                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
10152                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
10153                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
10154                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
10155
10156         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
10157                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
10158                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
10159                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
10160
10161         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
10162
10163         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
10164                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
10165 }
10166
10167 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
10168         .type = AMD_IP_BLOCK_TYPE_GFX,
10169         .major = 10,
10170         .minor = 0,
10171         .rev = 0,
10172         .funcs = &gfx_v10_0_ip_funcs,
10173 };