drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/drm_cache.h>
  29 #include "amdgpu.h"
  30 #include "gmc_v6_0.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "bif/bif_3_0_d.h"
  35 #include "bif/bif_3_0_sh_mask.h"
  36 #include "oss/oss_1_0_d.h"
  37 #include "oss/oss_1_0_sh_mask.h"
  38 #include "gmc/gmc_6_0_d.h"
  39 #include "gmc/gmc_6_0_sh_mask.h"
  40 #include "dce/dce_6_0_d.h"
  41 #include "dce/dce_6_0_sh_mask.h"
  42 #include "si_enums.h"
  43
  44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
  45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int gmc_v6_0_wait_for_idle(void *handle);
  47
  48 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
  49 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
  50 MODULE_FIRMWARE("amdgpu/verde_mc.bin");
  51 MODULE_FIRMWARE("amdgpu/oland_mc.bin");
  52 MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
  53 MODULE_FIRMWARE("amdgpu/si58_mc.bin");
  54
  55 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  56 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  57 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  58 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  59 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  60 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  61 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  62 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  63
  64
  65 static const u32 crtc_offsets[6] =
  66 {
  67         SI_CRTC0_REGISTER_OFFSET,
  68         SI_CRTC1_REGISTER_OFFSET,
  69         SI_CRTC2_REGISTER_OFFSET,
  70         SI_CRTC3_REGISTER_OFFSET,
  71         SI_CRTC4_REGISTER_OFFSET,
  72         SI_CRTC5_REGISTER_OFFSET
  73 };
  74
  75 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
  76 {
  77         u32 blackout;
  78
  79         gmc_v6_0_wait_for_idle((void *)adev);
  80
  81         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  82         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  83                 /* Block CPU access */
  84                 WREG32(mmBIF_FB_EN, 0);
  85                 /* blackout the MC */
  86                 blackout = REG_SET_FIELD(blackout,
  87                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  88                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  89         }
  90         /* wait for the MC to settle */
  91         udelay(100);
  92
  93 }
  94
  95 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
  96 {
  97         u32 tmp;
  98
  99         /* unblackout the MC */
 100         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 101         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 102         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 103         /* allow CPU access */
 104         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 105         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 106         WREG32(mmBIF_FB_EN, tmp);
 107 }
 108
 109 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 110 {
 111         const char *chip_name;
 112         char fw_name[30];
 113         int err;
 114         bool is_58_fw = false;
 115
 116         DRM_DEBUG("\n");
 117
 118         switch (adev->asic_type) {
 119         case CHIP_TAHITI:
 120                 chip_name = "tahiti";
 121                 break;
 122         case CHIP_PITCAIRN:
 123                 chip_name = "pitcairn";
 124                 break;
 125         case CHIP_VERDE:
 126                 chip_name = "verde";
 127                 break;
 128         case CHIP_OLAND:
 129                 chip_name = "oland";
 130                 break;
 131         case CHIP_HAINAN:
 132                 chip_name = "hainan";
 133                 break;
 134         default: BUG();
 135         }
 136
 137         /* this memory configuration requires special firmware */
 138         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 139                 is_58_fw = true;
 140
 141         if (is_58_fw)
 142                 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");
 143         else
 144                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 145         err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
 146         if (err)
 147                 goto out;
 148
 149         err = amdgpu_ucode_validate(adev->gmc.fw);
 150
 151 out:
 152         if (err) {
 153                 dev_err(adev->dev,
 154                        "si_mc: Failed to load firmware \"%s\"\n",
 155                        fw_name);
 156                 release_firmware(adev->gmc.fw);
 157                 adev->gmc.fw = NULL;
 158         }
 159         return err;
 160 }
 161
 162 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 163 {
 164         const __le32 *new_fw_data = NULL;
 165         u32 running;
 166         const __le32 *new_io_mc_regs = NULL;
 167         int i, regs_size, ucode_size;
 168         const struct mc_firmware_header_v1_0 *hdr;
 169
 170         if (!adev->gmc.fw)
 171                 return -EINVAL;
 172
 173         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 174
 175         amdgpu_ucode_print_mc_hdr(&hdr->header);
 176
 177         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 178         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 179         new_io_mc_regs = (const __le32 *)
 180                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 181         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 182         new_fw_data = (const __le32 *)
 183                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 184
 185         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 186
 187         if (running == 0) {
 188
 189                 /* reset the engine and set to writable */
 190                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 191                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 192
 193                 /* load mc io regs */
 194                 for (i = 0; i < regs_size; i++) {
 195                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 196                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 197                 }
 198                 /* load the MC ucode */
 199                 for (i = 0; i < ucode_size; i++) {
 200                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 201                 }
 202
 203                 /* put the engine back into the active state */
 204                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 205                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 206                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 207
 208                 /* wait for training to complete */
 209                 for (i = 0; i < adev->usec_timeout; i++) {
 210                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 211                                 break;
 212                         udelay(1);
 213                 }
 214                 for (i = 0; i < adev->usec_timeout; i++) {
 215                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 216                                 break;
 217                         udelay(1);
 218                 }
 219
 220         }
 221
 222         return 0;
 223 }
 224
 225 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 226                                        struct amdgpu_gmc *mc)
 227 {
 228         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 229         base <<= 24;
 230
 231         amdgpu_gmc_vram_location(adev, mc, base);
 232         amdgpu_gmc_gart_location(adev, mc);
 233 }
 234
 235 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 236 {
 237         int i, j;
 238
 239         /* Initialize HDP */
 240         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 241                 WREG32((0xb05 + j), 0x00000000);
 242                 WREG32((0xb06 + j), 0x00000000);
 243                 WREG32((0xb07 + j), 0x00000000);
 244                 WREG32((0xb08 + j), 0x00000000);
 245                 WREG32((0xb09 + j), 0x00000000);
 246         }
 247         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 248
 249         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 250                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 251         }
 252
 253         if (adev->mode_info.num_crtc) {
 254                 u32 tmp;
 255
 256                 /* Lockout access through VGA aperture*/
 257                 tmp = RREG32(mmVGA_HDP_CONTROL);
 258                 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
 259                 WREG32(mmVGA_HDP_CONTROL, tmp);
 260
 261                 /* disable VGA render */
 262                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 263                 tmp &= ~VGA_VSTATUS_CNTL;
 264                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 265         }
 266         /* Update configuration */
 267         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 268                adev->gmc.vram_start >> 12);
 269         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 270                adev->gmc.vram_end >> 12);
 271         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 272                adev->vram_scratch.gpu_addr >> 12);
 273         WREG32(mmMC_VM_AGP_BASE, 0);
 274         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 275         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 276
 277         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 278                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 279         }
 280 }
 281
 282 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 283 {
 284
 285         u32 tmp;
 286         int chansize, numchan;
 287         int r;
 288
 289         tmp = RREG32(mmMC_ARB_RAMCFG);
 290         if (tmp & (1 << 11)) {
 291                 chansize = 16;
 292         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 293                 chansize = 64;
 294         } else {
 295                 chansize = 32;
 296         }
 297         tmp = RREG32(mmMC_SHARED_CHMAP);
 298         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 299         case 0:
 300         default:
 301                 numchan = 1;
 302                 break;
 303         case 1:
 304                 numchan = 2;
 305                 break;
 306         case 2:
 307                 numchan = 4;
 308                 break;
 309         case 3:
 310                 numchan = 8;
 311                 break;
 312         case 4:
 313                 numchan = 3;
 314                 break;
 315         case 5:
 316                 numchan = 6;
 317                 break;
 318         case 6:
 319                 numchan = 10;
 320                 break;
 321         case 7:
 322                 numchan = 12;
 323                 break;
 324         case 8:
 325                 numchan = 16;
 326                 break;
 327         }
 328         adev->gmc.vram_width = numchan * chansize;
 329         /* size in MB on si */
 330         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 331         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 332
 333         if (!(adev->flags & AMD_IS_APU)) {
 334                 r = amdgpu_device_resize_fb_bar(adev);
 335                 if (r)
 336                         return r;
 337         }
 338         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 339         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 340         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 341
 342         /* set the gart size */
 343         if (amdgpu_gart_size == -1) {
 344                 switch (adev->asic_type) {
 345                 case CHIP_HAINAN:    /* no MM engines */
 346                 default:
 347                         adev->gmc.gart_size = 256ULL << 20;
 348                         break;
 349                 case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
 350                 case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
 351                 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
 352                 case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
 353                         adev->gmc.gart_size = 1024ULL << 20;
 354                         break;
 355                 }
 356         } else {
 357                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 358         }
 359
 360         gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
 361
 362         return 0;
 363 }
 364
 365 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev,
 366                                 uint32_t vmid, uint32_t flush_type)
 367 {
 368         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 369 }
 370
 371 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 372                                             unsigned vmid, uint64_t pd_addr)
 373 {
 374         uint32_t reg;
 375
 376         /* write new base address */
 377         if (vmid < 8)
 378                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 379         else
 380                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
 381         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 382
 383         /* bits 0-15 are the VM contexts0-15 */
 384         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 385
 386         return pd_addr;
 387 }
 388
 389 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
 390                                           uint32_t flags)
 391 {
 392         uint64_t pte_flag = 0;
 393
 394         if (flags & AMDGPU_VM_PAGE_READABLE)
 395                 pte_flag |= AMDGPU_PTE_READABLE;
 396         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 397                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 398         if (flags & AMDGPU_VM_PAGE_PRT)
 399                 pte_flag |= AMDGPU_PTE_PRT;
 400
 401         return pte_flag;
 402 }
 403
 404 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
 405                                 uint64_t *addr, uint64_t *flags)
 406 {
 407         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 408 }
 409
 410 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 411                                               bool value)
 412 {
 413         u32 tmp;
 414
 415         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 416         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 417                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 418         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 419                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 420         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 421                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 422         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 423                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 424         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 425                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 426         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 427                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 428         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 429 }
 430
 431  /**
 432    + * gmc_v8_0_set_prt - set PRT VM fault
 433    + *
 434    + * @adev: amdgpu_device pointer
 435    + * @enable: enable/disable VM fault handling for PRT
 436    +*/
 437 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 438 {
 439         u32 tmp;
 440
 441         if (enable && !adev->gmc.prt_warning) {
 442                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 443                 adev->gmc.prt_warning = true;
 444         }
 445
 446         tmp = RREG32(mmVM_PRT_CNTL);
 447         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 448                             CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 449                             enable);
 450         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 451                             TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 452                             enable);
 453         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 454                             L2_CACHE_STORE_INVALID_ENTRIES,
 455                             enable);
 456         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 457                             L1_TLB_STORE_INVALID_ENTRIES,
 458                             enable);
 459         WREG32(mmVM_PRT_CNTL, tmp);
 460
 461         if (enable) {
 462                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 463                 uint32_t high = adev->vm_manager.max_pfn -
 464                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 465
 466                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 467                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 468                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 469                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 470                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 471                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 472                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 473                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 474         } else {
 475                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 476                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 477                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 478                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 479                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 480                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 481                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 482                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 483         }
 484 }
 485
 486 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 487 {
 488         uint64_t table_addr;
 489         int r, i;
 490         u32 field;
 491
 492         if (adev->gart.bo == NULL) {
 493                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 494                 return -EINVAL;
 495         }
 496         r = amdgpu_gart_table_vram_pin(adev);
 497         if (r)
 498                 return r;
 499
 500         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 501
 502         /* Setup TLB control */
 503         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 504                (0xA << 7) |
 505                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 506                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 507                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 508                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 509                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 510         /* Setup L2 cache */
 511         WREG32(mmVM_L2_CNTL,
 512                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 513                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 514                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 515                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 516                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 517                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 518         WREG32(mmVM_L2_CNTL2,
 519                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 520                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 521
 522         field = adev->vm_manager.fragment_size;
 523         WREG32(mmVM_L2_CNTL3,
 524                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 525                (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 526                (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 527         /* setup context0 */
 528         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 529         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 530         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 531         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 532                         (u32)(adev->dummy_page_addr >> 12));
 533         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 534         WREG32(mmVM_CONTEXT0_CNTL,
 535                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 536                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 537                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 538
 539         WREG32(0x575, 0);
 540         WREG32(0x576, 0);
 541         WREG32(0x577, 0);
 542
 543         /* empty context1-15 */
 544         /* set vm size, must be a multiple of 4 */
 545         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 546         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 547         /* Assign the pt base to something valid for now; the pts used for
 548          * the VMs are determined by the application and setup and assigned
 549          * on the fly in the vm part of radeon_gart.c
 550          */
 551         for (i = 1; i < 16; i++) {
 552                 if (i < 8)
 553                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 554                                table_addr >> 12);
 555                 else
 556                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 557                                table_addr >> 12);
 558         }
 559
 560         /* enable context1-15 */
 561         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 562                (u32)(adev->dummy_page_addr >> 12));
 563         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 564         WREG32(mmVM_CONTEXT1_CNTL,
 565                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 566                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 567                ((adev->vm_manager.block_size - 9)
 568                << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 569         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 570                 gmc_v6_0_set_fault_enable_default(adev, false);
 571         else
 572                 gmc_v6_0_set_fault_enable_default(adev, true);
 573
 574         gmc_v6_0_flush_gpu_tlb(adev, 0, 0);
 575         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 576                  (unsigned)(adev->gmc.gart_size >> 20),
 577                  (unsigned long long)table_addr);
 578         adev->gart.ready = true;
 579         return 0;
 580 }
 581
 582 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 583 {
 584         int r;
 585
 586         if (adev->gart.bo) {
 587                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 588                 return 0;
 589         }
 590         r = amdgpu_gart_init(adev);
 591         if (r)
 592                 return r;
 593         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 594         adev->gart.gart_pte_flags = 0;
 595         return amdgpu_gart_table_vram_alloc(adev);
 596 }
 597
 598 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 599 {
 600         /*unsigned i;
 601
 602         for (i = 1; i < 16; ++i) {
 603                 uint32_t reg;
 604                 if (i < 8)
 605                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 606                 else
 607                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 608                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 609         }*/
 610
 611         /* Disable all tables */
 612         WREG32(mmVM_CONTEXT0_CNTL, 0);
 613         WREG32(mmVM_CONTEXT1_CNTL, 0);
 614         /* Setup TLB control */
 615         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 616                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 617                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 618         /* Setup L2 cache */
 619         WREG32(mmVM_L2_CNTL,
 620                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 621                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 622                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 623                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 624         WREG32(mmVM_L2_CNTL2, 0);
 625         WREG32(mmVM_L2_CNTL3,
 626                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 627                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 628         amdgpu_gart_table_vram_unpin(adev);
 629 }
 630
 631 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 632                                      u32 status, u32 addr, u32 mc_client)
 633 {
 634         u32 mc_id;
 635         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 636         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 637                                         PROTECTIONS);
 638         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 639                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 640
 641         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 642                               MEMORY_CLIENT_ID);
 643
 644         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 645                protections, vmid, addr,
 646                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 647                              MEMORY_CLIENT_RW) ?
 648                "write" : "read", block, mc_client, mc_id);
 649 }
 650
 651 /*
 652 static const u32 mc_cg_registers[] = {
 653         MC_HUB_MISC_HUB_CG,
 654         MC_HUB_MISC_SIP_CG,
 655         MC_HUB_MISC_VM_CG,
 656         MC_XPB_CLK_GAT,
 657         ATC_MISC_CG,
 658         MC_CITF_MISC_WR_CG,
 659         MC_CITF_MISC_RD_CG,
 660         MC_CITF_MISC_VM_CG,
 661         VM_L2_CG,
 662 };
 663
 664 static const u32 mc_cg_ls_en[] = {
 665         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 666         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 667         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 668         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 669         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 670         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 671         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 672         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 673         VM_L2_CG__MEM_LS_ENABLE_MASK,
 674 };
 675
 676 static const u32 mc_cg_en[] = {
 677         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 678         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 679         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 680         MC_XPB_CLK_GAT__ENABLE_MASK,
 681         ATC_MISC_CG__ENABLE_MASK,
 682         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 683         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 684         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 685         VM_L2_CG__ENABLE_MASK,
 686 };
 687
 688 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 689                                   bool enable)
 690 {
 691         int i;
 692         u32 orig, data;
 693
 694         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 695                 orig = data = RREG32(mc_cg_registers[i]);
 696                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 697                         data |= mc_cg_ls_en[i];
 698                 else
 699                         data &= ~mc_cg_ls_en[i];
 700                 if (data != orig)
 701                         WREG32(mc_cg_registers[i], data);
 702         }
 703 }
 704
 705 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 706                                     bool enable)
 707 {
 708         int i;
 709         u32 orig, data;
 710
 711         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 712                 orig = data = RREG32(mc_cg_registers[i]);
 713                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 714                         data |= mc_cg_en[i];
 715                 else
 716                         data &= ~mc_cg_en[i];
 717                 if (data != orig)
 718                         WREG32(mc_cg_registers[i], data);
 719         }
 720 }
 721
 722 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 723                                      bool enable)
 724 {
 725         u32 orig, data;
 726
 727         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 728
 729         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 730                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 731                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 732                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 733                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 734         } else {
 735                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 736                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 737                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 738                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 739         }
 740
 741         if (orig != data)
 742                 WREG32_PCIE(ixPCIE_CNTL2, data);
 743 }
 744
 745 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 746                                      bool enable)
 747 {
 748         u32 orig, data;
 749
 750         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 751
 752         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 753                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 754         else
 755                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 756
 757         if (orig != data)
 758                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 759 }
 760
 761 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 762                                    bool enable)
 763 {
 764         u32 orig, data;
 765
 766         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 767
 768         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 769                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 770         else
 771                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 772
 773         if (orig != data)
 774                 WREG32(mmHDP_MEM_POWER_LS, data);
 775 }
 776 */
 777
 778 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 779 {
 780         switch (mc_seq_vram_type) {
 781         case MC_SEQ_MISC0__MT__GDDR1:
 782                 return AMDGPU_VRAM_TYPE_GDDR1;
 783         case MC_SEQ_MISC0__MT__DDR2:
 784                 return AMDGPU_VRAM_TYPE_DDR2;
 785         case MC_SEQ_MISC0__MT__GDDR3:
 786                 return AMDGPU_VRAM_TYPE_GDDR3;
 787         case MC_SEQ_MISC0__MT__GDDR4:
 788                 return AMDGPU_VRAM_TYPE_GDDR4;
 789         case MC_SEQ_MISC0__MT__GDDR5:
 790                 return AMDGPU_VRAM_TYPE_GDDR5;
 791         case MC_SEQ_MISC0__MT__DDR3:
 792                 return AMDGPU_VRAM_TYPE_DDR3;
 793         default:
 794                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 795         }
 796 }
 797
 798 static int gmc_v6_0_early_init(void *handle)
 799 {
 800         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 801
 802         gmc_v6_0_set_gmc_funcs(adev);
 803         gmc_v6_0_set_irq_funcs(adev);
 804
 805         return 0;
 806 }
 807
 808 static int gmc_v6_0_late_init(void *handle)
 809 {
 810         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 811
 812         amdgpu_bo_late_init(adev);
 813
 814         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 815                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 816         else
 817                 return 0;
 818 }
 819
 820 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
 821 {
 822         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
 823         unsigned size;
 824
 825         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 826                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 827         } else {
 828                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
 829                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 830                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 831                         4);
 832         }
 833         /* return 0 if the pre-OS buffer uses up most of vram */
 834         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 835                 return 0;
 836         return size;
 837 }
 838
 839 static int gmc_v6_0_sw_init(void *handle)
 840 {
 841         int r;
 842         int dma_bits;
 843         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 844
 845         if (adev->flags & AMD_IS_APU) {
 846                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 847         } else {
 848                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 849                 tmp &= MC_SEQ_MISC0__MT__MASK;
 850                 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 851         }
 852
 853         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
 854         if (r)
 855                 return r;
 856
 857         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
 858         if (r)
 859                 return r;
 860
 861         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
 862
 863         adev->gmc.mc_mask = 0xffffffffffULL;
 864
 865         adev->need_dma32 = false;
 866         dma_bits = adev->need_dma32 ? 32 : 40;
 867         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 868         if (r) {
 869                 adev->need_dma32 = true;
 870                 dma_bits = 32;
 871                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 872         }
 873         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 874         if (r) {
 875                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 876                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 877         }
 878         adev->need_swiotlb = drm_need_swiotlb(dma_bits);
 879
 880         r = gmc_v6_0_init_microcode(adev);
 881         if (r) {
 882                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 883                 return r;
 884         }
 885
 886         r = gmc_v6_0_mc_init(adev);
 887         if (r)
 888                 return r;
 889
 890         adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
 891
 892         r = amdgpu_bo_init(adev);
 893         if (r)
 894                 return r;
 895
 896         r = gmc_v6_0_gart_init(adev);
 897         if (r)
 898                 return r;
 899
 900         /*
 901          * number of VMs
 902          * VMID 0 is reserved for System
 903          * amdgpu graphics/compute will use VMIDs 1-7
 904          * amdkfd will use VMIDs 8-15
 905          */
 906         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 907         amdgpu_vm_manager_init(adev);
 908
 909         /* base offset of vram pages */
 910         if (adev->flags & AMD_IS_APU) {
 911                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 912
 913                 tmp <<= 22;
 914                 adev->vm_manager.vram_base_offset = tmp;
 915         } else {
 916                 adev->vm_manager.vram_base_offset = 0;
 917         }
 918
 919         return 0;
 920 }
 921
 922 static int gmc_v6_0_sw_fini(void *handle)
 923 {
 924         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 925
 926         amdgpu_gem_force_release(adev);
 927         amdgpu_vm_manager_fini(adev);
 928         amdgpu_gart_table_vram_free(adev);
 929         amdgpu_bo_fini(adev);
 930         amdgpu_gart_fini(adev);
 931         release_firmware(adev->gmc.fw);
 932         adev->gmc.fw = NULL;
 933
 934         return 0;
 935 }
 936
 937 static int gmc_v6_0_hw_init(void *handle)
 938 {
 939         int r;
 940         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 941
 942         gmc_v6_0_mc_program(adev);
 943
 944         if (!(adev->flags & AMD_IS_APU)) {
 945                 r = gmc_v6_0_mc_load_microcode(adev);
 946                 if (r) {
 947                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 948                         return r;
 949                 }
 950         }
 951
 952         r = gmc_v6_0_gart_enable(adev);
 953         if (r)
 954                 return r;
 955
 956         return r;
 957 }
 958
 959 static int gmc_v6_0_hw_fini(void *handle)
 960 {
 961         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 962
 963         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 964         gmc_v6_0_gart_disable(adev);
 965
 966         return 0;
 967 }
 968
 969 static int gmc_v6_0_suspend(void *handle)
 970 {
 971         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 972
 973         gmc_v6_0_hw_fini(adev);
 974
 975         return 0;
 976 }
 977
 978 static int gmc_v6_0_resume(void *handle)
 979 {
 980         int r;
 981         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 982
 983         r = gmc_v6_0_hw_init(adev);
 984         if (r)
 985                 return r;
 986
 987         amdgpu_vmid_reset_all(adev);
 988
 989         return 0;
 990 }
 991
 992 static bool gmc_v6_0_is_idle(void *handle)
 993 {
 994         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 995         u32 tmp = RREG32(mmSRBM_STATUS);
 996
 997         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 998                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 999                 return false;
1000
1001         return true;
1002 }
1003
1004 static int gmc_v6_0_wait_for_idle(void *handle)
1005 {
1006         unsigned i;
1007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008
1009         for (i = 0; i < adev->usec_timeout; i++) {
1010                 if (gmc_v6_0_is_idle(handle))
1011                         return 0;
1012                 udelay(1);
1013         }
1014         return -ETIMEDOUT;
1015
1016 }
1017
1018 static int gmc_v6_0_soft_reset(void *handle)
1019 {
1020         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1021         u32 srbm_soft_reset = 0;
1022         u32 tmp = RREG32(mmSRBM_STATUS);
1023
1024         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1025                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1026                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1027
1028         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1029                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1030                 if (!(adev->flags & AMD_IS_APU))
1031                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1032                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1033         }
1034
1035         if (srbm_soft_reset) {
1036                 gmc_v6_0_mc_stop(adev);
1037                 if (gmc_v6_0_wait_for_idle(adev)) {
1038                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1039                 }
1040
1041
1042                 tmp = RREG32(mmSRBM_SOFT_RESET);
1043                 tmp |= srbm_soft_reset;
1044                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1045                 WREG32(mmSRBM_SOFT_RESET, tmp);
1046                 tmp = RREG32(mmSRBM_SOFT_RESET);
1047
1048                 udelay(50);
1049
1050                 tmp &= ~srbm_soft_reset;
1051                 WREG32(mmSRBM_SOFT_RESET, tmp);
1052                 tmp = RREG32(mmSRBM_SOFT_RESET);
1053
1054                 udelay(50);
1055
1056                 gmc_v6_0_mc_resume(adev);
1057                 udelay(50);
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1064                                              struct amdgpu_irq_src *src,
1065                                              unsigned type,
1066                                              enum amdgpu_interrupt_state state)
1067 {
1068         u32 tmp;
1069         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1070                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1071                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1072                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1073                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1074                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1075
1076         switch (state) {
1077         case AMDGPU_IRQ_STATE_DISABLE:
1078                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1079                 tmp &= ~bits;
1080                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1081                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1082                 tmp &= ~bits;
1083                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1084                 break;
1085         case AMDGPU_IRQ_STATE_ENABLE:
1086                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1087                 tmp |= bits;
1088                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1089                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1090                 tmp |= bits;
1091                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1092                 break;
1093         default:
1094                 break;
1095         }
1096
1097         return 0;
1098 }
1099
1100 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1101                                       struct amdgpu_irq_src *source,
1102                                       struct amdgpu_iv_entry *entry)
1103 {
1104         u32 addr, status;
1105
1106         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1107         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1108         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1109
1110         if (!addr && !status)
1111                 return 0;
1112
1113         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1114                 gmc_v6_0_set_fault_enable_default(adev, false);
1115
1116         if (printk_ratelimit()) {
1117                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1118                         entry->src_id, entry->src_data[0]);
1119                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1120                         addr);
1121                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1122                         status);
1123                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1124         }
1125
1126         return 0;
1127 }
1128
1129 static int gmc_v6_0_set_clockgating_state(void *handle,
1130                                           enum amd_clockgating_state state)
1131 {
1132         return 0;
1133 }
1134
1135 static int gmc_v6_0_set_powergating_state(void *handle,
1136                                           enum amd_powergating_state state)
1137 {
1138         return 0;
1139 }
1140
1141 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1142         .name = "gmc_v6_0",
1143         .early_init = gmc_v6_0_early_init,
1144         .late_init = gmc_v6_0_late_init,
1145         .sw_init = gmc_v6_0_sw_init,
1146         .sw_fini = gmc_v6_0_sw_fini,
1147         .hw_init = gmc_v6_0_hw_init,
1148         .hw_fini = gmc_v6_0_hw_fini,
1149         .suspend = gmc_v6_0_suspend,
1150         .resume = gmc_v6_0_resume,
1151         .is_idle = gmc_v6_0_is_idle,
1152         .wait_for_idle = gmc_v6_0_wait_for_idle,
1153         .soft_reset = gmc_v6_0_soft_reset,
1154         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1155         .set_powergating_state = gmc_v6_0_set_powergating_state,
1156 };
1157
1158 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1159         .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1160         .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1161         .set_prt = gmc_v6_0_set_prt,
1162         .get_vm_pde = gmc_v6_0_get_vm_pde,
1163         .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1164 };
1165
1166 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1167         .set = gmc_v6_0_vm_fault_interrupt_state,
1168         .process = gmc_v6_0_process_interrupt,
1169 };
1170
1171 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1172 {
1173         adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1174 }
1175
1176 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1177 {
1178         adev->gmc.vm_fault.num_types = 1;
1179         adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1180 }
1181
1182 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1183 {
1184         .type = AMD_IP_BLOCK_TYPE_GMC,
1185         .major = 6,
1186         .minor = 0,
1187         .rev = 0,
1188         .funcs = &gmc_v6_0_ip_funcs,
1189 };