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Merge tag 'dm-3.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/device...
[linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <[email protected]>
af36d7f0
JG		 5 * Please ALWAYS copy [email protected]
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1 55 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 56 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 57 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 58};
59
60enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
cb85696d
JL		 86static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 88static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
438ac6d5 90#ifdef CONFIG_PM
c1332875
TH		 91static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 93#endif
ad616ffb 94
fad16e7a
TH		 95static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97};
98
029cfd6b
TH		 99static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
a1efdaba 101 .hardreset = ahci_vt8251_hardreset,
029cfd6b 102};
edc93052 103
029cfd6b
TH		 104static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
a1efdaba 106 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 107};
108
98ac62de 109static const struct ata_port_info ahci_port_info[] = {
441577ef 110 /* by features */
facb8fa6 111 [board_ahci] = {
1188c0d8 112 .flags = AHCI_FLAG_COMMON,
14bdef98 113 .pio_mask = ATA_PIO4,
469248ab 114 .udma_mask = ATA_UDMA6,
1da177e4
LT		 115 .port_ops = &ahci_ops,
116 },
facb8fa6 117 [board_ahci_ign_iferr] = {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
facb8fa6 124 [board_ahci_nosntf] = {
441577ef 125 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 126 .flags = AHCI_FLAG_COMMON,
14bdef98 127 .pio_mask = ATA_PIO4,
469248ab 128 .udma_mask = ATA_UDMA6,
41669553
TH		 129 .port_ops = &ahci_ops,
130 },
facb8fa6 131 [board_ahci_yes_fbs] = {
5f173107
TH		 132 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
441577ef 138 /* by chipsets */
facb8fa6 139 [board_ahci_mcp65] = {
83f2b963
TH		 140 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
141 AHCI_HFLAG_YES_NCQ),
ae01b249 142 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
146 },
facb8fa6 147 [board_ahci_mcp77] = {
83f2b963
TH		 148 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
facb8fa6 154 [board_ahci_mcp89] = {
83f2b963 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 156 .flags = AHCI_FLAG_COMMON,
14bdef98 157 .pio_mask = ATA_PIO4,
469248ab 158 .udma_mask = ATA_UDMA6,
441577ef 159 .port_ops = &ahci_ops,
55a61604 160 },
facb8fa6 161 [board_ahci_mv] = {
417a1a6d 162 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 163 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 164 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 165 .pio_mask = ATA_PIO4,
cd70c266
JG		 166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
facb8fa6 169 [board_ahci_sb600] = {
441577ef
TH		 170 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
171 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
172 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 173 .flags = AHCI_FLAG_COMMON,
14bdef98 174 .pio_mask = ATA_PIO4,
e39fc8c9 175 .udma_mask = ATA_UDMA6,
345347c5 176 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 177 },
facb8fa6 178 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 179 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 184 },
facb8fa6 185 [board_ahci_vt8251] = {
441577ef 186 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
441577ef 190 .port_ops = &ahci_vt8251_ops,
1b677afd 191 },
1da177e4
LT		 192};
193
3b7d697d 194static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 195 /* Intel */
54bb3a94
JG		 196 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
197 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
198 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
199 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
200 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 201 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 202 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
204 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
205 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 206 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 207 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 208 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
209 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
210 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
211 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
215 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
216 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
221 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 223 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
224 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 225 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 226 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 227 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 228 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
229 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 230 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 231 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 232 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 233 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 234 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 235 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 236 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
237 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
238 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
240 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
241 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 242 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
243 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
244 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 245 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 246 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 247 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
248 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
249 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
252 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 253 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 254 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
261 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 262 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
263 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
264 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
268 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
269 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 270 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
271 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
272 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
277 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
278 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
280 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 286 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
287 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 288 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
289 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
291 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
293 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 296 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 297 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
298 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
300 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
fe7fa31a 301
e34bb370
TH		 302 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
303 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
304 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 305 /* JMicron 362B and 362C have an AHCI function with IDE class code */
306 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
307 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 308
309 /* ATI */
c65ec1c2 310 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 311 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
312 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
313 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
314 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
315 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
316 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 317
e2dd90b1 318 /* AMD */
5deab536 319 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 320 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 321 /* AMD is using RAID class only for ahci controllers */
322 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
323 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
324
fe7fa31a 325 /* VIA */
54bb3a94 326 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 327 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 328
329 /* NVIDIA */
e297d99e
TH		 330 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
331 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
332 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
333 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 338 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 414
95916edd 415 /* SiS */
20e2de4a
TH		 416 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
417 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
418 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 419
318893e1
AR		 420 /* ST Microelectronics */
421 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
422
cd70c266
JG		 423 /* Marvell */
424 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 425 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 426 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 427 .class = PCI_CLASS_STORAGE_SATA_AHCI,
428 .class_mask = 0xffffff,
5f173107 429 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 430 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 431 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 432 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
433 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
434 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 435 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 436 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35
GS		 437 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
438 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 439 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 440 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
69fd3157 441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 442 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
444 .driver_data = board_ahci_yes_fbs },
cd70c266 445
c77a036b
MN		 446 /* Promise */
447 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
448
c9703765 449 /* Asmedia */
7b4f6eca
AC		 450 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
451 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
452 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
453 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 454
7f9c9f8e
HD		 455 /* Enmotus */
456 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
457
415ae2b5
JG		 458 /* Generic, PCI class code for AHCI */
459 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 460 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 461
1da177e4
LT		 462 { } /* terminate list */
463};
464
465
466static struct pci_driver ahci_pci_driver = {
467 .name = DRV_NAME,
468 .id_table = ahci_pci_tbl,
469 .probe = ahci_init_one,
24dc5f33 470 .remove = ata_pci_remove_one,
438ac6d5 471#ifdef CONFIG_PM
c1332875 472 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 473 .resume = ahci_pci_device_resume,
474#endif
475};
1da177e4 476
365cfa1e
AV		 477#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
478static int marvell_enable;
479#else
480static int marvell_enable = 1;
481#endif
482module_param(marvell_enable, int, 0644);
483MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 484
1da177e4 485
365cfa1e
AV		 486static void ahci_pci_save_initial_config(struct pci_dev *pdev,
487 struct ahci_host_priv *hpriv)
488{
489 unsigned int force_port_map = 0;
490 unsigned int mask_port_map = 0;
67846b30 491
365cfa1e
AV		 492 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
493 dev_info(&pdev->dev, "JMB361 has only one port\n");
494 force_port_map = 1;
1da177e4
LT		 495 }
496
365cfa1e
AV		 497 /*
498 * Temporary Marvell 6145 hack: PATA port presence
499 * is asserted through the standard AHCI port
500 * presence register, as bit 4 (counting from 0)
d28f87aa 501 */
365cfa1e
AV		 502 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
503 if (pdev->device == 0x6121)
504 mask_port_map = 0x3;
505 else
506 mask_port_map = 0xf;
507 dev_info(&pdev->dev,
508 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
509 }
1da177e4 510
365cfa1e
AV		 511 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
512 mask_port_map);
1da177e4
LT		 513}
514
365cfa1e 515static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 516{
365cfa1e 517 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 518
365cfa1e 519 ahci_reset_controller(host);
1da177e4 520
365cfa1e
AV		 521 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
522 struct ahci_host_priv *hpriv = host->private_data;
523 u16 tmp16;
d6ef3153 524
365cfa1e
AV		 525 /* configure PCS */
526 pci_read_config_word(pdev, 0x92, &tmp16);
527 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
528 tmp16 |= hpriv->port_map;
529 pci_write_config_word(pdev, 0x92, tmp16);
530 }
d6ef3153
SH		 531 }
532
1da177e4
LT		 533 return 0;
534}
535
365cfa1e 536static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 537{
365cfa1e
AV		 538 struct ahci_host_priv *hpriv = host->private_data;
539 struct pci_dev *pdev = to_pci_dev(host->dev);
540 void __iomem *port_mmio;
78cd52d0 541 u32 tmp;
365cfa1e 542 int mv;
78cd52d0 543
365cfa1e
AV		 544 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
545 if (pdev->device == 0x6121)
546 mv = 2;
547 else
548 mv = 4;
549 port_mmio = __ahci_port_base(host, mv);
78cd52d0 550
365cfa1e 551 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 552
365cfa1e
AV		 553 /* clear port IRQ */
554 tmp = readl(port_mmio + PORT_IRQ_STAT);
555 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
556 if (tmp)
557 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 558 }
559
365cfa1e 560 ahci_init_controller(host);
edc93052
TH		 561}
562
365cfa1e
AV		 563static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
564 unsigned long deadline)
d6ef3153 565{
365cfa1e
AV		 566 struct ata_port *ap = link->ap;
567 bool online;
d6ef3153
SH		 568 int rc;
569
365cfa1e 570 DPRINTK("ENTER\n");
d6ef3153 571
365cfa1e 572 ahci_stop_engine(ap);
d6ef3153 573
365cfa1e
AV		 574 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
575 deadline, &online, NULL);
d6ef3153
SH		 576
577 ahci_start_engine(ap);
d6ef3153 578
365cfa1e 579 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 580
365cfa1e
AV		 581 /* vt8251 doesn't clear BSY on signature FIS reception,
582 * request follow-up softreset.
583 */
584 return online ? -EAGAIN : rc;
7d50b60b
TH		 585}
586
365cfa1e
AV		 587static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
588 unsigned long deadline)
7d50b60b 589{
365cfa1e 590 struct ata_port *ap = link->ap;
1c954a4d 591 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 592 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
593 struct ata_taskfile tf;
594 bool online;
595 int rc;
7d50b60b 596
365cfa1e 597 ahci_stop_engine(ap);
028a2596 598
365cfa1e
AV		 599 /* clear D2H reception area to properly wait for D2H FIS */
600 ata_tf_init(link->device, &tf);
9bbb1b0e 601 tf.command = ATA_BUSY;
365cfa1e 602 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 603
365cfa1e
AV		 604 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
605 deadline, &online, NULL);
028a2596 606
365cfa1e 607 ahci_start_engine(ap);
c1332875 608
365cfa1e
AV		 609 /* The pseudo configuration device on SIMG4726 attached to
610 * ASUS P5W-DH Deluxe doesn't send signature FIS after
611 * hardreset if no device is attached to the first downstream
612 * port && the pseudo device locks up on SRST w/ PMP==0. To
613 * work around this, wait for !BSY only briefly. If BSY isn't
614 * cleared, perform CLO and proceed to IDENTIFY (achieved by
615 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
616 *
617 * Wait for two seconds. Devices attached to downstream port
618 * which can't process the following IDENTIFY after this will
619 * have to be reset again. For most cases, this should
620 * suffice while making probing snappish enough.
621 */
622 if (online) {
623 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
624 ahci_check_ready);
625 if (rc)
626 ahci_kick_engine(ap);
c1332875 627 }
c1332875
TH		 628 return rc;
629}
630
365cfa1e 631#ifdef CONFIG_PM
c1332875
TH		 632static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
633{
0a86e1c8 634 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 635 struct ahci_host_priv *hpriv = host->private_data;
d8993349 636 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 637 u32 ctl;
638
9b10ae86
TH		 639 if (mesg.event & PM_EVENT_SUSPEND &&
640 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 641 dev_err(&pdev->dev,
642 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 643 return -EIO;
644 }
645
3a2d5b70 646 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 647 /* AHCI spec rev1.1 section 8.3.3:
648 * Software must disable interrupts prior to requesting a
649 * transition of the HBA to D3 state.
650 */
651 ctl = readl(mmio + HOST_CTL);
652 ctl &= ~HOST_IRQ_EN;
653 writel(ctl, mmio + HOST_CTL);
654 readl(mmio + HOST_CTL); /* flush */
655 }
656
657 return ata_pci_device_suspend(pdev, mesg);
658}
659
660static int ahci_pci_device_resume(struct pci_dev *pdev)
661{
0a86e1c8 662 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 663 int rc;
664
553c4aa6
TH		 665 rc = ata_pci_device_do_resume(pdev);
666 if (rc)
667 return rc;
c1332875 668
cb85696d
JL		 669 /* Apple BIOS helpfully mangles the registers on resume */
670 if (is_mcp89_apple(pdev))
671 ahci_mcp89_apple_enable(pdev);
672
c1332875 673 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 674 rc = ahci_pci_reset_controller(host);
c1332875
TH		 675 if (rc)
676 return rc;
677
781d6550 678 ahci_pci_init_controller(host);
c1332875
TH		 679 }
680
cca3974e 681 ata_host_resume(host);
c1332875
TH		 682
683 return 0;
684}
438ac6d5 685#endif
c1332875 686
4447d351 687static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 688{
1da177e4 689 int rc;
1da177e4 690
318893e1
AR		 691 /*
692 * If the device fixup already set the dma_mask to some non-standard
693 * value, don't extend it here. This happens on STA2X11, for example.
694 */
695 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
696 return 0;
697
1da177e4 698 if (using_dac &&
6a35528a
YH		 699 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
700 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 701 if (rc) {
284901a9 702 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 703 if (rc) {
a44fec1f
JP		 704 dev_err(&pdev->dev,
705 "64-bit DMA enable failed\n");
1da177e4
LT		 706 return rc;
707 }
708 }
1da177e4 709 } else {
284901a9 710 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 711 if (rc) {
a44fec1f 712 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 713 return rc;
714 }
284901a9 715 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 716 if (rc) {
a44fec1f
JP		 717 dev_err(&pdev->dev,
718 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 719 return rc;
720 }
721 }
1da177e4
LT		 722 return 0;
723}
724
439fcaec
AV		 725static void ahci_pci_print_info(struct ata_host *host)
726{
727 struct pci_dev *pdev = to_pci_dev(host->dev);
728 u16 cc;
729 const char *scc_s;
730
731 pci_read_config_word(pdev, 0x0a, &cc);
732 if (cc == PCI_CLASS_STORAGE_IDE)
733 scc_s = "IDE";
734 else if (cc == PCI_CLASS_STORAGE_SATA)
735 scc_s = "SATA";
736 else if (cc == PCI_CLASS_STORAGE_RAID)
737 scc_s = "RAID";
738 else
739 scc_s = "unknown";
740
741 ahci_print_info(host, scc_s);
742}
743
edc93052
TH		 744/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
745 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
746 * support PMP and the 4726 either directly exports the device
747 * attached to the first downstream port or acts as a hardware storage
748 * controller and emulate a single ATA device (can be RAID 0/1 or some
749 * other configuration).
750 *
751 * When there's no device attached to the first downstream port of the
752 * 4726, "Config Disk" appears, which is a pseudo ATA device to
753 * configure the 4726. However, ATA emulation of the device is very
754 * lame. It doesn't send signature D2H Reg FIS after the initial
755 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
756 *
757 * The following function works around the problem by always using
758 * hardreset on the port and not depending on receiving signature FIS
759 * afterward. If signature FIS isn't received soon, ATA class is
760 * assumed without follow-up softreset.
761 */
762static void ahci_p5wdh_workaround(struct ata_host *host)
763{
764 static struct dmi_system_id sysids[] = {
765 {
766 .ident = "P5W DH Deluxe",
767 .matches = {
768 DMI_MATCH(DMI_SYS_VENDOR,
769 "ASUSTEK COMPUTER INC"),
770 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
771 },
772 },
773 { }
774 };
775 struct pci_dev *pdev = to_pci_dev(host->dev);
776
777 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
778 dmi_check_system(sysids)) {
779 struct ata_port *ap = host->ports[1];
780
a44fec1f
JP		 781 dev_info(&pdev->dev,
782 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 783
784 ap->ops = &ahci_p5wdh_ops;
785 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
786 }
787}
788
cb85696d
JL		 789/*
790 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
791 * booting in BIOS compatibility mode. We restore the registers but not ID.
792 */
793static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
794{
795 u32 val;
796
797 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
798
799 pci_read_config_dword(pdev, 0xf8, &val);
800 val |= 1 << 0x1b;
801 /* the following changes the device ID, but appears not to affect function */
802 /* val = (val & ~0xf0000000) | 0x80000000; */
803 pci_write_config_dword(pdev, 0xf8, val);
804
805 pci_read_config_dword(pdev, 0x54c, &val);
806 val |= 1 << 0xc;
807 pci_write_config_dword(pdev, 0x54c, val);
808
809 pci_read_config_dword(pdev, 0x4a4, &val);
810 val &= 0xff;
811 val |= 0x01060100;
812 pci_write_config_dword(pdev, 0x4a4, val);
813
814 pci_read_config_dword(pdev, 0x54c, &val);
815 val &= ~(1 << 0xc);
816 pci_write_config_dword(pdev, 0x54c, val);
817
818 pci_read_config_dword(pdev, 0xf8, &val);
819 val &= ~(1 << 0x1b);
820 pci_write_config_dword(pdev, 0xf8, val);
821}
822
823static bool is_mcp89_apple(struct pci_dev *pdev)
824{
825 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
826 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
827 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
828 pdev->subsystem_device == 0xcb89;
829}
830
2fcad9d2
TH		 831/* only some SB600 ahci controllers can do 64bit DMA */
832static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 833{
834 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 835 /*
836 * The oldest version known to be broken is 0901 and
837 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 838 * Enable 64bit DMA on 1501 and anything newer.
839 *
03d783bf
TH		 840 * Please read bko#9412 for more info.
841 */
58a09b38
SH		 842 {
843 .ident = "ASUS M2A-VM",
844 .matches = {
845 DMI_MATCH(DMI_BOARD_VENDOR,
846 "ASUSTeK Computer INC."),
847 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
848 },
03d783bf 849 .driver_data = "20071026", /* yyyymmdd */
58a09b38 850 },
e65cc194
MN		 851 /*
852 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
853 * support 64bit DMA.
854 *
855 * BIOS versions earlier than 1.5 had the Manufacturer DMI
856 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
857 * This spelling mistake was fixed in BIOS version 1.5, so
858 * 1.5 and later have the Manufacturer as
859 * "MICRO-STAR INTERNATIONAL CO.,LTD".
860 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
861 *
862 * BIOS versions earlier than 1.9 had a Board Product Name
863 * DMI field of "MS-7376". This was changed to be
864 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
865 * match on DMI_BOARD_NAME of "MS-7376".
866 */
867 {
868 .ident = "MSI K9A2 Platinum",
869 .matches = {
870 DMI_MATCH(DMI_BOARD_VENDOR,
871 "MICRO-STAR INTER"),
872 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
873 },
874 },
ff0173c1
MN		 875 /*
876 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
877 * 64bit DMA.
878 *
879 * This board also had the typo mentioned above in the
880 * Manufacturer DMI field (fixed in BIOS version 1.5), so
881 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
882 */
883 {
884 .ident = "MSI K9AGM2",
885 .matches = {
886 DMI_MATCH(DMI_BOARD_VENDOR,
887 "MICRO-STAR INTER"),
888 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
889 },
890 },
3c4aa91f
MN		 891 /*
892 * All BIOS versions for the Asus M3A support 64bit DMA.
893 * (all release versions from 0301 to 1206 were tested)
894 */
895 {
896 .ident = "ASUS M3A",
897 .matches = {
898 DMI_MATCH(DMI_BOARD_VENDOR,
899 "ASUSTeK Computer INC."),
900 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
901 },
902 },
58a09b38
SH		 903 { }
904 };
03d783bf 905 const struct dmi_system_id *match;
2fcad9d2
TH		 906 int year, month, date;
907 char buf[9];
58a09b38 908
03d783bf 909 match = dmi_first_match(sysids);
58a09b38 910 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 911 !match)
58a09b38
SH		 912 return false;
913
e65cc194
MN		 914 if (!match->driver_data)
915 goto enable_64bit;
916
2fcad9d2
TH		 917 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
918 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 919
e65cc194
MN		 920 if (strcmp(buf, match->driver_data) >= 0)
921 goto enable_64bit;
922 else {
a44fec1f
JP		 923 dev_warn(&pdev->dev,
924 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
925 match->ident);
2fcad9d2
TH		 926 return false;
927 }
e65cc194
MN		 928
929enable_64bit:
a44fec1f 930 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 931 return true;
58a09b38
SH		 932}
933
1fd68434
RW		 934static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
935{
936 static const struct dmi_system_id broken_systems[] = {
937 {
938 .ident = "HP Compaq nx6310",
939 .matches = {
940 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
941 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
942 },
943 /* PCI slot number of the controller */
944 .driver_data = (void *)0x1FUL,
945 },
d2f9c061
MR		 946 {
947 .ident = "HP Compaq 6720s",
948 .matches = {
949 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
950 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
951 },
952 /* PCI slot number of the controller */
953 .driver_data = (void *)0x1FUL,
954 },
1fd68434
RW		 955
956 { } /* terminate list */
957 };
958 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
959
960 if (dmi) {
961 unsigned long slot = (unsigned long)dmi->driver_data;
962 /* apply the quirk only to on-board controllers */
963 return slot == PCI_SLOT(pdev->devfn);
964 }
965
966 return false;
967}
968
9b10ae86
TH		 969static bool ahci_broken_suspend(struct pci_dev *pdev)
970{
971 static const struct dmi_system_id sysids[] = {
972 /*
973 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
974 * to the harddisk doesn't become online after
975 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 976 *
977 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
978 *
979 * Use dates instead of versions to match as HP is
980 * apparently recycling both product and version
981 * strings.
982 *
983 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 984 */
985 {
986 .ident = "dv4",
987 .matches = {
988 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
989 DMI_MATCH(DMI_PRODUCT_NAME,
990 "HP Pavilion dv4 Notebook PC"),
991 },
9deb3431 992 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 993 },
994 {
995 .ident = "dv5",
996 .matches = {
997 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
998 DMI_MATCH(DMI_PRODUCT_NAME,
999 "HP Pavilion dv5 Notebook PC"),
1000 },
9deb3431 1001 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1002 },
1003 {
1004 .ident = "dv6",
1005 .matches = {
1006 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1007 DMI_MATCH(DMI_PRODUCT_NAME,
1008 "HP Pavilion dv6 Notebook PC"),
1009 },
9deb3431 1010 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1011 },
1012 {
1013 .ident = "HDX18",
1014 .matches = {
1015 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1016 DMI_MATCH(DMI_PRODUCT_NAME,
1017 "HP HDX18 Notebook PC"),
1018 },
9deb3431 1019 .driver_data = "20090430", /* F.23 */
9b10ae86 1020 },
cedc9bf9
TH		 1021 /*
1022 * Acer eMachines G725 has the same problem. BIOS
1023 * V1.03 is known to be broken. V3.04 is known to
25985edc 1024 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1025 * that we don't have much idea about. For now,
1026 * blacklist anything older than V3.04.
9deb3431
TH		 1027 *
1028 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1029 */
1030 {
1031 .ident = "G725",
1032 .matches = {
1033 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1034 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1035 },
9deb3431 1036 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1037 },
9b10ae86
TH		 1038 { } /* terminate list */
1039 };
1040 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1041 int year, month, date;
1042 char buf[9];
9b10ae86
TH		 1043
1044 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1045 return false;
1046
9deb3431
TH		 1047 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1048 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1049
9deb3431 1050 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1051}
1052
5594639a
TH		 1053static bool ahci_broken_online(struct pci_dev *pdev)
1054{
1055#define ENCODE_BUSDEVFN(bus, slot, func) \
1056 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1057 static const struct dmi_system_id sysids[] = {
1058 /*
1059 * There are several gigabyte boards which use
1060 * SIMG5723s configured as hardware RAID. Certain
1061 * 5723 firmware revisions shipped there keep the link
1062 * online but fail to answer properly to SRST or
1063 * IDENTIFY when no device is attached downstream
1064 * causing libata to retry quite a few times leading
1065 * to excessive detection delay.
1066 *
1067 * As these firmwares respond to the second reset try
1068 * with invalid device signature, considering unknown
1069 * sig as offline works around the problem acceptably.
1070 */
1071 {
1072 .ident = "EP45-DQ6",
1073 .matches = {
1074 DMI_MATCH(DMI_BOARD_VENDOR,
1075 "Gigabyte Technology Co., Ltd."),
1076 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1077 },
1078 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1079 },
1080 {
1081 .ident = "EP45-DS5",
1082 .matches = {
1083 DMI_MATCH(DMI_BOARD_VENDOR,
1084 "Gigabyte Technology Co., Ltd."),
1085 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1086 },
1087 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1088 },
1089 { } /* terminate list */
1090 };
1091#undef ENCODE_BUSDEVFN
1092 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1093 unsigned int val;
1094
1095 if (!dmi)
1096 return false;
1097
1098 val = (unsigned long)dmi->driver_data;
1099
1100 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1101}
1102
8e513217 1103#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1104static void ahci_gtf_filter_workaround(struct ata_host *host)
1105{
1106 static const struct dmi_system_id sysids[] = {
1107 /*
1108 * Aspire 3810T issues a bunch of SATA enable commands
1109 * via _GTF including an invalid one and one which is
1110 * rejected by the device. Among the successful ones
1111 * is FPDMA non-zero offset enable which when enabled
1112 * only on the drive side leads to NCQ command
1113 * failures. Filter it out.
1114 */
1115 {
1116 .ident = "Aspire 3810T",
1117 .matches = {
1118 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1119 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1120 },
1121 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1122 },
1123 { }
1124 };
1125 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1126 unsigned int filter;
1127 int i;
1128
1129 if (!dmi)
1130 return;
1131
1132 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1133 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1134 filter, dmi->ident);
f80ae7e4
TH		 1135
1136 for (i = 0; i < host->n_ports; i++) {
1137 struct ata_port *ap = host->ports[i];
1138 struct ata_link *link;
1139 struct ata_device *dev;
1140
1141 ata_for_each_link(link, ap, EDGE)
1142 ata_for_each_dev(dev, link, ALL)
1143 dev->gtf_filter |= filter;
1144 }
1145}
8e513217
MT		 1146#else
1147static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1148{}
1149#endif
f80ae7e4 1150
e1ba8459 1151static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
7b92b4f6 1152 struct ahci_host_priv *hpriv)
5ca72c4f 1153{
7b92b4f6 1154 int rc, nvec;
5ca72c4f 1155
7b92b4f6
AG		 1156 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1157 goto intx;
1158
1159 rc = pci_msi_vec_count(pdev);
1160 if (rc < 0)
1161 goto intx;
1162
1163 /*
1164 * If number of MSIs is less than number of ports then Sharing Last
1165 * Message mode could be enforced. In this case assume that advantage
1166 * of multipe MSIs is negated and use single MSI mode instead.
1167 */
1168 if (rc < n_ports)
1169 goto single_msi;
1170
1171 nvec = rc;
1172 rc = pci_enable_msi_block(pdev, nvec);
1173 if (rc)
1174 goto intx;
5ca72c4f 1175
7b92b4f6
AG		 1176 return nvec;
1177
1178single_msi:
1179 rc = pci_enable_msi(pdev);
1180 if (rc)
1181 goto intx;
1182 return 1;
1183
1184intx:
5ca72c4f
AG		 1185 pci_intx(pdev, 1);
1186 return 0;
1187}
1188
1189/**
1190 * ahci_host_activate - start AHCI host, request IRQs and register it
1191 * @host: target ATA host
1192 * @irq: base IRQ number to request
1193 * @n_msis: number of MSIs allocated for this host
1194 * @irq_handler: irq_handler used when requesting IRQs
1195 * @irq_flags: irq_flags used when requesting IRQs
1196 *
1197 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1198 * when multiple MSIs were allocated. That is one MSI per port, starting
1199 * from @irq.
1200 *
1201 * LOCKING:
1202 * Inherited from calling layer (may sleep).
1203 *
1204 * RETURNS:
1205 * 0 on success, -errno otherwise.
1206 */
1207int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1208{
1209 int i, rc;
1210
1211 /* Sharing Last Message among several ports is not supported */
1212 if (n_msis < host->n_ports)
1213 return -EINVAL;
1214
1215 rc = ata_host_start(host);
1216 if (rc)
1217 return rc;
1218
1219 for (i = 0; i < host->n_ports; i++) {
c91bc6cc 1220 const char* desc;
b29900e6
AG		 1221 struct ahci_port_priv *pp = host->ports[i]->private_data;
1222
c91bc6cc
XF		 1223 /* pp is NULL for dummy ports */
1224 if (pp)
1225 desc = pp->irq_desc;
1226 else
1227 desc = dev_driver_string(host->dev);
1228
5ca72c4f
AG		 1229 rc = devm_request_threaded_irq(host->dev,
1230 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
c91bc6cc 1231 desc, host->ports[i]);
5ca72c4f
AG		 1232 if (rc)
1233 goto out_free_irqs;
1234 }
1235
1236 for (i = 0; i < host->n_ports; i++)
1237 ata_port_desc(host->ports[i], "irq %d", irq + i);
1238
1239 rc = ata_host_register(host, &ahci_sht);
1240 if (rc)
1241 goto out_free_all_irqs;
1242
1243 return 0;
1244
1245out_free_all_irqs:
1246 i = host->n_ports;
1247out_free_irqs:
1248 for (i--; i >= 0; i--)
1249 devm_free_irq(host->dev, irq + i, host->ports[i]);
1250
1251 return rc;
1252}
1253
24dc5f33 1254static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1255{
e297d99e
TH		 1256 unsigned int board_id = ent->driver_data;
1257 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1258 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1259 struct device *dev = &pdev->dev;
1da177e4 1260 struct ahci_host_priv *hpriv;
4447d351 1261 struct ata_host *host;
5ca72c4f 1262 int n_ports, n_msis, i, rc;
318893e1 1263 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1264
1265 VPRINTK("ENTER\n");
1266
b429dd59 1267 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1268
06296a1e 1269 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1270
5b66c829
AC		 1271 /* The AHCI driver can only drive the SATA ports, the PATA driver
1272 can drive them all so if both drivers are selected make sure
1273 AHCI stays out of the way */
1274 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1275 return -ENODEV;
1276
cb85696d
JL		 1277 /* Apple BIOS on MCP89 prevents us using AHCI */
1278 if (is_mcp89_apple(pdev))
1279 ahci_mcp89_apple_enable(pdev);
c6353b45 1280
7a02267e
MN		 1281 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1282 * At the moment, we can only use the AHCI mode. Let the users know
1283 * that for SAS drives they're out of luck.
1284 */
1285 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1286 dev_info(&pdev->dev,
1287 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1288
7f9c9f8e 1289 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1290 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1291 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1292 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1293 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1294
4447d351 1295 /* acquire resources */
24dc5f33 1296 rc = pcim_enable_device(pdev);
1da177e4
LT		 1297 if (rc)
1298 return rc;
1299
c4f7792c
TH		 1300 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1301 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1302 u8 map;
1303
1304 /* ICH6s share the same PCI ID for both piix and ahci
1305 * modes. Enabling ahci mode while MAP indicates
1306 * combined mode is a bad idea. Yield to ata_piix.
1307 */
1308 pci_read_config_byte(pdev, ICH_MAP, &map);
1309 if (map & 0x3) {
a44fec1f
JP		 1310 dev_info(&pdev->dev,
1311 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1312 return -ENODEV;
1313 }
1314 }
1315
6fec8871
PB		 1316 /* AHCI controllers often implement SFF compatible interface.
1317 * Grab all PCI BARs just in case.
1318 */
1319 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1320 if (rc == -EBUSY)
1321 pcim_pin_device(pdev);
1322 if (rc)
1323 return rc;
1324
24dc5f33
TH		 1325 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1326 if (!hpriv)
1327 return -ENOMEM;
417a1a6d
TH		 1328 hpriv->flags |= (unsigned long)pi.private_data;
1329
e297d99e
TH		 1330 /* MCP65 revision A1 and A2 can't do MSI */
1331 if (board_id == board_ahci_mcp65 &&
1332 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1333 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1334
e427fe04
SH		 1335 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1336 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1337 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1338
2fcad9d2
TH		 1339 /* only some SB600s can do 64bit DMA */
1340 if (ahci_sb600_enable_64bit(pdev))
1341 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1342
318893e1 1343 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1344
4447d351 1345 /* save initial config */
394d6e53 1346 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1347
4447d351 1348 /* prepare host */
453d3131
RH		 1349 if (hpriv->cap & HOST_CAP_NCQ) {
1350 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1351 /*
1352 * Auto-activate optimization is supposed to be
1353 * supported on all AHCI controllers indicating NCQ
1354 * capability, but it seems to be broken on some
1355 * chipsets including NVIDIAs.
1356 */
1357 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1358 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1359
1360 /*
1361 * All AHCI controllers should be forward-compatible
1362 * with the new auxiliary field. This code should be
1363 * conditionalized if any buggy AHCI controllers are
1364 * encountered.
1365 */
1366 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1367 }
1da177e4 1368
7d50b60b
TH		 1369 if (hpriv->cap & HOST_CAP_PMP)
1370 pi.flags |= ATA_FLAG_PMP;
1371
0cbb0e77 1372 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1373
1fd68434
RW		 1374 if (ahci_broken_system_poweroff(pdev)) {
1375 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1376 dev_info(&pdev->dev,
1377 "quirky BIOS, skipping spindown on poweroff\n");
1378 }
1379
9b10ae86
TH		 1380 if (ahci_broken_suspend(pdev)) {
1381 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1382 dev_warn(&pdev->dev,
1383 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1384 }
1385
5594639a
TH		 1386 if (ahci_broken_online(pdev)) {
1387 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1388 dev_info(&pdev->dev,
1389 "online status unreliable, applying workaround\n");
1390 }
1391
837f5f8f
TH		 1392 /* CAP.NP sometimes indicate the index of the last enabled
1393 * port, at other times, that of the last possible port, so
1394 * determining the maximum port number requires looking at
1395 * both CAP.NP and port_map.
1396 */
1397 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1398
7b92b4f6
AG		 1399 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1400 if (n_msis > 1)
1401 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1402
837f5f8f 1403 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1404 if (!host)
1405 return -ENOMEM;
4447d351
TH		 1406 host->private_data = hpriv;
1407
f3d7f23f 1408 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1409 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1410 else
d2782d96 1411 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1412
18f7ba4c
KCA		 1413 if (pi.flags & ATA_FLAG_EM)
1414 ahci_reset_em(host);
1415
4447d351 1416 for (i = 0; i < host->n_ports; i++) {
dab632e8 1417 struct ata_port *ap = host->ports[i];
4447d351 1418
318893e1
AR		 1419 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1420 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1421 0x100 + ap->port_no * 0x80, "port");
1422
18f7ba4c
KCA		 1423 /* set enclosure management message type */
1424 if (ap->flags & ATA_FLAG_EM)
008dbd61 1425 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1426
1427
dab632e8 1428 /* disabled/not-implemented port */
350756f6 1429 if (!(hpriv->port_map & (1 << i)))
dab632e8 1430 ap->ops = &ata_dummy_port_ops;
4447d351 1431 }
d447df14 1432
edc93052
TH		 1433 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1434 ahci_p5wdh_workaround(host);
1435
f80ae7e4
TH		 1436 /* apply gtf filter quirk */
1437 ahci_gtf_filter_workaround(host);
1438
4447d351
TH		 1439 /* initialize adapter */
1440 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1441 if (rc)
24dc5f33 1442 return rc;
1da177e4 1443
3303040d 1444 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1445 if (rc)
1446 return rc;
1da177e4 1447
781d6550 1448 ahci_pci_init_controller(host);
439fcaec 1449 ahci_pci_print_info(host);
1da177e4 1450
4447d351 1451 pci_set_master(pdev);
5ca72c4f
AG		 1452
1453 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1454 return ahci_host_activate(host, pdev->irq, n_msis);
1455
4447d351
TH		 1456 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1457 &ahci_sht);
907f4678 1458}
1da177e4 1459
2fc75da0 1460module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1461
1462MODULE_AUTHOR("Jeff Garzik");
1463MODULE_DESCRIPTION("AHCI SATA low-level driver");
1464MODULE_LICENSE("GPL");
1465MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1466MODULE_VERSION(DRV_VERSION);
Empty description
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